JP2008160661A - Amplifier protection circuit - Google Patents

Abstract

It is difficult to set conditions for a protection circuit of a BTL amplifier.
A based on the BTL amplifier 2 of the non-inverting output terminal _{N OUT +} of the potential _{V OUT +} and the inverted output terminal _{N OUT-} potential _{V OUT-, N OUT +} or _{N OUT-} is connected incorrectly shorted to a power supply _{V CC,} etc. Detect state. A resistance is divided between V _{OUT +} and V _OUT− to generate a potential V ₁ at the midpoint thereof. In a normal state, V ₁ is kept at the reference bias potential V _b0 of V _{OUT +} and V _OUT− . Balance determination circuit 14, V ₁ outputs the L level when it is in the vicinity of V _b0, V ₁ outputs an H level when off the said vicinity. The out-of-range state detection circuit 6 outputs an H level when V _{OUT +} or V _OUT− is out of the allowable bias range including V _b0 . When the AND circuit 8 detects that both the balance determination circuit 14 and the out-of-range state detection circuit 6 are in the H output state, the control circuit 10 turns off the bias circuit 12 to protect the BTL amplifier 2.
[Selection] Figure 1

Description

  The present invention relates to a protection circuit for protecting a BTL (Balanced Transformer Less) amplifier.

  The BTL amplifier includes two anti-phase SEPP (Single Ended Push-Pull) circuits, and outputs an output signal having the same DC potential and opposite phase from the output terminals of these two SEPP circuits. The BTL amplifier does not require a coupling capacitor for cutting the direct current flowing through the load by connecting the load between the two output terminals in which the direct current potential is balanced. In an amplifier that requires a coupling capacitor, the lower the frequency of the signal, the larger the coupling capacitor required, which makes design difficult. On the other hand, since the BTL amplifier does not require a coupling capacitor, it is used for an output stage of an ultra-low frequency amplifier or a DC amplifier.

Here, when each output terminal of the BTL amplifier is short-circuited with the positive power supply _VCC , the ground potential GND, or the like, inconveniences such as excessive current flowing in the output transistor constituting the SEPP circuit occur. Therefore, a protection circuit that protects the BTL amplifier from such a short circuit is required.

FIG. 4 is a circuit diagram for explaining a conventional protection circuit, and shows a configuration of an output stage of one SEPP circuit constituting a BTL amplifier. SEPP circuit shown in FIG. 4, an output transistor Q01 and Q02, Q01 are connected the collector and the emitter to _{V CC} and the output terminal _{N OUT,} respectively, Q02 are connected the collector and emitter _{N OUT} and GND, respectively. Voltage between the base and N _OUT of Q01 is inputted to the resistor divided based detection transistor Q03 with R01 and R02. Further, the voltage between the base of Q02 and GND is resistance-divided by R03 and R04 and input to the base of the detection transistor Q04. For example, when N _OUT and V _CC are short-circuited (this case is hereinafter referred to as a power fault), a large collector current I _C2 flows in Q02, and the base-emitter voltage V _BE of Q02 is V _BE -I. It increases based on the _C characteristic. This increase in V _BE changes the conduction state of Q04. On the other hand, when N _OUT and GND are short-circuited (this case is hereinafter referred to as a ground fault), V _BE changes in response to the collector current I _{C1 of} Q01 becoming a large current, and the conduction state of Q03 is changed. Change.

Conventionally, an SEPP circuit having the configuration shown in FIG. 4 is provided at each of the inverting output terminal N _OUT− and the non-inverting output terminal N _{OUT +} of the BTL amplifier. A control circuit that controls the operation of the protection circuit detects a large current when the output transistors Q01 and Q02 in the SEPP circuit are short-circuited based on changes in the collector currents I _C3 and I _C4 of the detection transistors Q03 and Q04. It is determined that there is an erroneous connection state called a ground fault. When the control circuit determines that the connection is incorrect, the control circuit turns off the bias circuit that supplies bias power to the BTL amplifier, and stops the operation of the BTL amplifier.
Japanese Patent Laid-Open No. 2005-006464

The conventional configuration for detecting the change in V _BE of the output transistors Q01 and Q02 using I _C3 and I _C4 flowing through the detection transistors Q03 and Q04 as detection currents is a resistance ratio between R01 and R02 and a resistance ratio between R03 and R04. Must be set so that the erroneous connection state and the normal state can be accurately distinguished. This setting requires a relatively fine adjustment and may require an operation for finding an appropriate condition. Therefore, there is a problem that a man-hour and a period of time are required for the design.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a configuration in which conditions can be easily set in a protection circuit for a BTL amplifier.

  The amplifier protection circuit according to the present invention includes a BTL amplifier that outputs an inverted output signal and a non-inverted output signal at a predetermined reference bias potential from the inverted output terminal and the non-inverted output terminal, respectively, the inverted output terminal or the non-inverted output. A circuit that protects against a potential outside the allowable bias range applied to the terminal, and based on the potential of the inverting output terminal and the potential of the non-inverting output terminal, obtains a midpoint potential that is the midpoint thereof, A midpoint determination circuit for determining whether the midpoint potential is in an equilibrium state or an unbalanced state with respect to the reference bias potential; and the inverted output signal or the non-inverted output signal is a potential outside the allowable bias range. An out-of-range state detection circuit that detects an out-of-range state, and a protection that performs a protection operation on the BLT amplifier based on the unbalanced state and the out-of-range state Has a line circuit, the.

  The protection execution circuit is configured to stop the bias circuit as the protection operation when the BTL amplifier has a configuration of operating at the reference bias potential based on power supplied from the bias circuit. can do.

  According to the present invention, based on the potentials of the inverting output terminal and the non-inverting output terminal, for example, an abnormal state such as a power fault or a ground fault is detected more directly, so that the condition setting of the amplifier protection circuit can be performed. It becomes easy.

  Hereinafter, embodiments of the present invention (hereinafter referred to as embodiments) will be described with reference to the drawings. The present embodiment is a low-frequency signal amplifying device configured using a BTL amplifier. The amplifying apparatus includes an amplifier protection circuit that protects the BTL amplifier, and is configured as an IC.

FIG. 1 is a schematic diagram illustrating a schematic circuit configuration of a low-frequency signal amplifier according to an embodiment. BTL amplifier 2 amplifies the input from the input terminal _{N IN} signal, and outputs an inverted output signal _{V OUT-} from the inverted output terminal _{N OUT-,} while non-inverting output terminal _{N OUT +} non-inverted output signal from the _{V OUT +} Is output. V _{OUT +} and V _OUT− are signals in which AC signal components are superimposed in opposite phases on a reference bias potential V _b0 that is the same DC bias. For _example, if the _{V OUT +} AC signal component of the representative and _{V sig, V OUT +} and _{V OUT-} is expressed by the following equation. In the present embodiment, V _b0 is set to V _CC / 2 as an example.

V _{OUT +} = V _b0 + V _sig (1)

V _OUT− = V _b0 −V _sig (2)

  The amplifier protection circuit includes a midpoint determination circuit 4, an out-of-range state detection circuit 6, an AND circuit 8, a control circuit 10, and a bias circuit 12.

Midpoint determination circuit _4, and _{N OUT +} and _N resistors R1 connected in series between the _OUT-, R2, consisting balance determination circuit 14 that is input to the potential _{V 1} of the connection point _{P 1} of the R1 and R2. Resistance ratio between R1 and R2 is basically 1: set to 1, by which, _{V 1} is the midpoint potential between _{V OUT +} and _{V OUT-.} (1) During normal operation in which V _{OUT +} and V _OUT− represented by the expression (2) are output, the signal components V _sig that are in opposite phases to each other at V _{OUT +} and V _OUT− are canceled at the point P ₁ . In principle, V ₁ is held at a constant potential expressed by the following equation.

V ₁ = V _b0 (3)

On the other hand, when N _{OUT +} or N _OUT− is in an erroneous connection state, V ₁ basically deviates from the potential represented by the expression (3). For example, when N _{OUT +} or N _OUT− becomes a power fault state, the DC bias potential becomes V _CC , and the bias potential at the point P ₁ rises to (V _b0 + V _CC ) / 2. Further, when N _{OUT +} or N _OUT− is in a ground fault state, the DC bias potential becomes GND (0 V), and the bias potential at the point P ₁ drops to V _b0 / 2.

The balance determination circuit 14 determines the difference in V ₁ between the normal state and the erroneous connection state, and outputs a low voltage L (Low) representing a logical value “0” in the normal state. A high voltage H (High) representing a logical value “1” is output.

FIG. 2 is a schematic circuit diagram showing an example of the configuration of the balance determination circuit 14. _{V 1} input to the input terminal IN is applied to the pnp transistor Q1 and npn transistor Q2 respective bases. The emitter of Q1 and the emitter of Q2 are connected to a reference voltage source _Vref . V _ref is set to a voltage between V _CC and GND. The collector of Q1 is connected to GND via a resistor R3. R3 has one end connected to the collector of Q1 connected to the output terminal OUT of the balance determination circuit 14, and the other end connected to GND.

The collector of Q2 is connected to V _CC through transistor Q3 which is diode-connected. Transistor Q3 forms a current mirror circuit together with transistor Q4. Q4 of the output side path of this current mirror circuit is connected to one end of R3 as with Q1 described above. With this configuration, the collector current of Q1 and the collector current of Q2 can be supplied to R3 in the same direction.

When V ₁ is in the vicinity of V _ref , this balance determination circuit 14 is in the off state of Q 1 and Q 2, and no current flows through R 3. Therefore, the balance determination circuit 14 outputs the GND potential as an L level potential from OUT. Meanwhile, _{V 1} is Q1 is turned on when about 0.6V lower than _{V ref,} Q1 of the current flows in R3, the potential of OUT becomes the voltage drop higher by H level at from L level R3. Further, Q2 is turned on when _{V 1} is made about 0.6V higher than _{V ref,} by Q2 of current flows in R3 is folded by the current mirror circuit, the potential of OUT becomes also higher than the L level H level .

V _ref is set in the vicinity of V _b0 so that the balance determination circuit 14 outputs an L level when the reference bias potential V _b0 is input. For example, V _ref can be set equal to V _b0 . By setting V _ref in the vicinity of V _b0 , the balance determination circuit 14 causes V ₁ maintained at the reference bias potential V _b0 in the normal state and V greatly deviated from the reference bias potential V _{b0 in the} erroneous connection state. ₁ is output from OUT in the normal state and H level in the erroneous connection state.

Next, the out-of-range state detection circuit 6 monitors the potentials of N _{OUT +} and N _OUT− , and outputs an H level when either of these potentials deviates from a predetermined allowable range (allowable bias range). When the potential is within the allowable bias range, the L level is output.

FIG. 3 is a schematic circuit diagram showing an example of the configuration of the out-of-range state detection circuit 6. Range state detection circuit 6, and the non-inverting side of the detection block 20 to monitor the input terminal IN _{+ N OUT} is connected to the _{+ V OUT +,} the input terminal IN _- the monitoring a is connected to the _{N OUT- V OUT-} inversion Side detection block 22 and a detection signal output unit 24 that combines the output signals of both detection blocks 20 and 22.

  FIG. 3 shows a specific circuit configuration example of the detection block 20 on the non-inversion side, and this configuration will be described below. Note that the inversion-side detection block 22 can basically have the same circuit configuration as the non-inversion-side detection block 20, and illustration and description thereof are omitted here.

The detection block 20 has resistors R4, R5, and R6 connected in series between VCC and GND. The potential V ₂ at the connection point P ₂ between R4 and R5, are set according to the upper limit of the allowable bias range, the potential V ₃ of the connection point P ₃ and R5 and R6, set according to the lower limit of the allowable bias range Is done.

The connection point _{P 2} is connected to the base of the pnp transistors Q5, the connection point _{P 3} the base of the npn transistor Q6 is connected. IN ₊ to which V _{OUT +} is input is connected to the emitter of Q5 through the diode D1, and is connected to the emitter of Q6 through the diode D2. D1 _{is, V OUT +} is forward biased at a potential greater than the potential _{V 2} of _{P 2,} D2 _{is, V OUT +} is provided in the direction which becomes forward biased at a potential below the potential _{V 3} of the _{P 3.}

Q5 is turned on when V _{OUT +} exceeds the upper limit of the allowable bias range, and the collector current flows from the output terminal to the detection signal output unit 24. The detection signal output unit 24 converts the current output from the detection block 20 into a positive voltage by the resistor R7 and outputs the positive voltage.

Q6 turns on when V _{OUT +} falls below the lower limit of the allowable bias range. The collector current of Q6 is turned back by a current mirror circuit composed of a diode D3 and a transistor Q8, and the current is in the same direction as the collector current when Q5 is on, and is output from the output terminal to the detection signal output unit 24. In this case as well, the detection signal output unit 24 outputs the H level in the same manner as when Q5 is on.

An inversion side detection block 22 is connected to the detection signal output unit 24 in parallel with the non-inversion side detection block 20 described above. The detection block 22 outputs a current in the same manner as the detection block 20 when V _OUT− exceeds the upper limit of the allowable bias range and falls below the lower limit, and the detection signal output unit 24 accordingly outputs H. Output level.

On the other hand, when both V _{OUT +} and V _OUT− are within the allowable bias range, Q 5 and Q 6 of the detection blocks 20 and 22 are in an off state, and basically no current flows through R 7, and the terminal of R 7 The inter-voltage is maintained at 0V, and the detection signal output unit 24 outputs L level.

V _{OUT +} and _{V OUT-} becomes a potential corresponding to _{V CC} is in heaven fault occurs, the potential corresponding to GND to ground fault. In response to this, the out-of-range state detection circuit 6 basically outputs the H level continuously while the power supply state and the ground fault state continue. On the other hand, in the normal state, the amplitude of V _sig becomes H level only during the period when it exceeds the allowable bias range, and becomes L level during the other periods. That is, the out-of-range state detection circuit 6 basically does not continuously output the H level in the normal state. This low-frequency signal amplifying apparatus uses the output of the out-of-range state detection circuit 6 showing different characteristics between the erroneous connection state and the normal state, together with the output of the midpoint determination circuit 4, for detection of the erroneous connection state.

  The AND circuit 8 receives the output signal from the midpoint determination circuit 4 and the output signal from the out-of-range state detection circuit 6 and outputs a signal corresponding to the logical product of them.

Based on the output signal of the AND circuit 8, the control circuit 10 determines the presence or absence of the occurrence of a ground fault or a ground fault at N _{OUT +} or N _OUT− and controls on / off of the bias circuit 12.

The bias circuit 12 is a circuit that supplies bias power to the BTL amplifier 2. The output transistor of the BTL amplifier 2 is driven by the bias power supply supplied from the bias circuit 12, and the DC bias potentials of V _{OUT +} and V _OUT− are set to the reference bias potential _Vb0 .

  When the AND circuit 8 detects a state in which both the midpoint determination circuit 4 and the out-of-range state detection circuit 6 are at the H level, the control circuit 10 receives the output at the set input unit S and turns off the bias circuit 12. Since the bias circuit 12 is turned off, it is possible to prevent an excessive current from flowing through the BTL amplifier 2 and to protect the BTL amplifier 2. Further, when the control circuit 10 receives a signal indicating that the out-of-range state detection circuit 6 has become L level at the reset input portion R, the control circuit 10 turns on the bias circuit 12 to return to normal operation.

In the above configuration, V ₁ in the normal state is in principle the midpoint potential of V _{OUT +} and V _OUT− , and is maintained at the reference bias potential V _b0 which is a DC signal with the AC signal component canceled. Therefore, in principle, the output of the midpoint determination circuit 4 is maintained at the L level in a normal state, and it seems as if the out-of-range state detection circuit 6 is unnecessary. However, in reality, V ₁ may fluctuate in the vicinity of V _b0 due to various factors. Width of the input signal potential midpoint determination circuit 4 outputs an L level is relatively small, the midpoint determination circuit 4, there may be also outputs the H-level by variations in V ₁ of the normal state. That is, it is conceivable that only the midpoint determination circuit 4 erroneously detects an erroneous connection state such as a power fault or a ground fault.

  On the other hand, in this low frequency signal amplifying device, an out-of-range state detection circuit 6 that operates differently from the midpoint determination circuit 4 is provided, and an erroneous detection is detected based on the logical product of both. This prevents the protection circuit from malfunctioning. That is, the out-of-range state detection circuit 6 basically outputs the H level only temporarily in the normal state, so that the outputs of both the midpoint determination circuit 4 and the out-of-range state detection circuit 6 are at the H level in the normal state. Therefore, the possibility of erroneous detection is suppressed from the possibility of erroneous detection of the configuration of only the midpoint determination circuit 4.

In addition, a configuration is possible in which only the out-of-range state detection circuit 6 is used and the protection circuit is operated with the H level output continuing for a certain grace period or more as an erroneous connection state. It takes a certain amount of time to make a quick decision. As a result, the time until the protection circuit operates becomes longer, and the possibility that the BTL amplifier 2 is adversely affected during that time increases. In particular, as the signal V _sig to be amplified by the BTL amplifier 2 has a lower frequency, the grace time needs to be set longer, and the BTL amplifier 2 may not be effectively protected by the protection circuit.

  On the other hand, the above-described protection circuit used in the present low-frequency signal amplifying device can effectively protect the BTL amplifier 2 by detecting the erroneous connection state quickly and with high reliability as described above. It is.

1 is a schematic diagram illustrating a schematic circuit configuration of a low-frequency signal amplification device according to an embodiment of the present invention. It is a schematic circuit diagram which shows an example of a structure of a balance determination circuit. It is a schematic circuit diagram which shows an example of a structure of an out-of-range state detection circuit. It is a circuit diagram for demonstrating the conventional protection circuit.

Explanation of symbols

  2 BTL amplifier, 4 midpoint determination circuit, 6 out-of-range state detection circuit, 8 AND circuit, 10 control circuit, 12 bias circuit, 14 balance determination circuit, 20, 22 detection block, 24 detection signal output unit.

Claims (2)

A BTL amplifier that outputs an inverted output signal and a non-inverted output signal at a predetermined reference bias potential from each of the inverted output terminal and the non-inverted output terminal is outside the allowable bias range applied to the inverted output terminal or the non-inverted output terminal. A protection circuit that protects against the potential of
Based on the potential of the inverting output terminal and the potential of the non-inverting output terminal, a midpoint potential that is the midpoint between them is obtained, and whether the midpoint potential is in an equilibrium state with respect to the reference bias potential. A midpoint determination circuit for determining whether or not
An out-of-range state detection circuit that detects an out-of-range state in which the inverted output signal or the non-inverted output signal is at a potential outside the allowable bias range;
A protection execution circuit that performs a protection operation on the BLT amplifier based on the unbalanced state and the out-of-range state;
An amplifier protection circuit comprising: The amplifier protection circuit of claim 1.
The BTL amplifier operates at the reference bias potential based on a power source supplied by a bias circuit,
The protection execution circuit stops the bias circuit as the protection operation;
An amplifier protection circuit.

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