JP2008159924A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method, by which residues, scum or the like on a substrate obtained by carrying out a patterning of a film by using a hard mask are further reduced, in a method of manufacturing semiconductor devices such as FeRAM or the like including a process of carrying out the patterning of films such as a metal film, an insulating film or the like by using the hard mask. <P>SOLUTION: The method of manufacturing the semiconductor device is provided with a prevention process, comprising the steps of:forming a hard mask 17a of nitride such as TiN through a sacrificial film 16 of alumina film on a first conductive film 15 consisting of IrO<SB>2</SB>which is set as a patterning object; carrying out a patterning of the first conductive film 15 in a region which is not covered with the hard mask 17a; removing the sacrificial film 16 by a wet processing using mixed liquor of ammonium fluoride, amide, organic acid, organic acid salts and water; and lifting the hard mask 17a from an upper part of the first conductive film 15 and sticking again the residues, the scums or the like which are stuck on a front surface of the hard mask 17a. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device including a step of patterning a film such as a metal film or an insulating film using a hard mask.

  The FeRAM is an element that has a ferroelectric capacitor, and writes and reads information using a hysteresis characteristic in the relationship between the polarization charge amount and voltage of the ferroelectric material.

  The lower electrode, the ferroelectric film, and the upper electrode constituting the ferroelectric capacitor are, for example, a first conductive layer on an interlayer insulating film that covers a transistor formed on a semiconductor substrate, as described in Patent Document 1 below, for example. The film, the ferroelectric film, and the second conductive film are formed in this order, and then the films are patterned.

  Patent Document 1 describes a planar ferroelectric capacitor having a structure in which conductive plugs are connected to the upper surface of the upper electrode and the upper surface of the lower electrode, respectively. ) To (e).

  First, as shown in FIG. 14A, an adhesion layer 102 made of alumina and a first conductive film 103 made of platinum or iridium are formed on an interlayer insulating film 101 formed on a silicon substrate (not shown). Then, a ferroelectric film 104 made of PZT and a second conductive film 105 made of iridium oxide are sequentially formed. Thereafter, a first mask 106 is formed on the capacitor upper electrode region in the second conductive film 105.

  Next, as shown in FIG. 14B, the second conductive film 105 in the region not covered with the first mask 106 is etched, whereby the second conductive layer 105 left under the first mask 106 is etched. The conductive film 105 is used as the upper electrode 105a.

  After the first mask 106 is removed, a second mask 107 is formed on the capacitor dielectric formation region including the upper electrode 105a in the ferroelectric film 104. Then, as shown in FIG. 14C, the ferroelectric film 104 in the region not covered with the second mask 107 is etched, and the remaining ferroelectric film 104 is used as the capacitor dielectric film 104a. .

  Further, after removing the second mask 107, a third mask 108 is formed in the capacitor lower electrode formation region including the plurality of upper electrodes 105a in the first conductive film 103. Subsequently, as shown in FIG. 14D, the first conductive film 103 in the region not covered with the third mask 108 is etched, and the remaining first conductive film 103 is used as the lower electrode 103a. use.

  The upper electrode 105a, the capacitor dielectric film 104a, and the lower electrode 103a formed by patterning as described above constitute a ferroelectric capacitor Q as shown in FIG.

  As the masks 106 to 108 used for patterning the film, Patent Document 1 describes that a photoresist is applied, but titanium nitride (TiN) and aluminum (Al) as described in Patent Documents 2 and 3 are described. It is also possible to use a hard mask made of such a hard film.

  In particular, a contact hole (not shown) is formed on the upper electrode 105a, and a tungsten plug (not shown) is embedded in the upper electrode 105a by a CVD method, so that the reduction of the ferroelectric film that is likely to occur during plug formation is prevented. Therefore, the upper electrode 105a is preferably formed thick, and a hard mask can be used for patterning the upper electrode 105a. Moreover, if a mask made of titanium nitride, that is, a hard mask is used, titanium nitride is a conductor and unlike aluminum, it is difficult to oxidize, so that it can be left as it is.

  The patterning process using the hard mask is not limited to the formation of the ferroelectric capacitor, but for example, it is described in Patent Document 4 that it is adopted for the formation of a copper wiring having a dual damascene structure.

  The copper wiring of the dual damascene structure is formed by embedding a copper wiring in a recess formed in the insulating film, and the recess is formed by a process as shown in FIGS. 15 and 16 using a hard mask, for example. The

  First, as shown in FIG. 15A, a first wiring 122 is formed in a second interlayer insulating film 121 covering the first interlayer insulating film 120, and the first wiring 122 is a thin silicon nitride film 123. Covered by. On the silicon nitride film 123, a third interlayer insulating film 124, an SOG (spin on glass) film 125, a silicon oxide film 126, a silicon nitride film 127, and a first antireflection film 128 are formed.

  A silicon oxide film is formed as the interlayer insulating films 120, 121, and 124, and an organic BARC (Bottom anti-reflection coating) film is formed as the first antireflection film 128, for example. A first photoresist 129 is applied on the first antireflection film 128, and is further exposed and developed to form an opening 130 having a wiring shape.

  Next, as shown in FIG. 15B, the first antireflection film 128 and the silicon nitride film 127 are etched through the opening 130 of the first photoresist 129. The patterned silicon nitride film 127 is used as a hard mask 127a in which the wiring pattern region 130a is opened.

  The first photoresist 129 and the first antireflection film 128 are removed with a solvent. Thereafter, as shown in FIG. 15C, a second antireflection film 131 made of organic BARC is formed on the hard mask 127 a and the silicon oxide film 126, and further, the second antireflection film 131 is formed on the second antireflection film 131. Second photoresist 132 is applied.

  Then, by exposing and developing the second photoresist 132, a via hole opening 133 is formed in a part of the wiring pattern region 130 a that is not covered with the hard mask 127.

  Further, as shown in FIG. 16A, the second antireflection film 131, the silicon oxide film 126, the SOG film 125, and the third interlayer insulating film 124 are etched through the via hole opening 133 to form a via hole 134. Form.

  Then, after removing the second photoresist 132 and the second antireflection film 131, as shown in FIG. 16B, the silicon oxide film 126 and the SOG film are used using the hard mask 127a as an etching prevention mask. 125, the wiring pattern region 130a is deepened to form a wiring recess 135.

  Thereafter, as shown in FIG. 16C, the upper surface of the first wiring 122 is exposed by etching the silicon nitride film 123 at the bottom of the via hole 134 using the third interlayer insulating film 124 as a mask.

Thereafter, the wiring recess 135 and the via hole 134 are filled with copper or the like to form a dual damascene structure wiring, but details thereof are omitted.
JP 2004-153019 A Japanese Patent Laid-Open No. 2004-23078 JP 2003-257842 A JP 2001-338978 A

  By the way, as shown in FIGS. 14A and 14B, after the second conductive film 105 is partially etched to form the upper electrode 105a of the ferroelectric capacitor Q, residues generated by the etching, Removal of the scum 100 or the like by wet cleaning is performed. Also in the formation of the dual damascene, as shown in FIG. 16C, the residue, scum, etc. 100 generated by etching after the formation of the wiring recess 135 is also removed by wet processing.

  However, if a TiN hard mask is used as the mask 106 of the second conductive film 103 in the capacitor formation process, residues, scum, etc. adhering to the TiN film cannot be easily removed by the wet cleaning process and should be left as they are. It becomes a source of contamination in subsequent processes. Although it is conceivable to etch the TiN film by wet processing, the generation of contamination sources is unavoidable even by the etching.

  If the TiN film is wet-etched, a mixed solution of ammonium hydroxide, hydrogen peroxide, pure water (DIW), and isopropyl alcohol (IPA) is used as the chemical solution.

  Although it is possible to change the chemical used in the wet cleaning process in order to remove residues, scum, etc. adhering to the TiN film, the PZT ferroelectric film 104 and the second conductive film 105 are reduced in film thickness. It is not easy to make no chemicals.

  On the other hand, in the formation of the dual damascene, the hard mask 127a made of a silicon nitride film is used. However, removal of residues, scum, etc. 100 attached to the surface is also difficult.

  An object of the present invention is to provide a method of manufacturing a semiconductor device that can further reduce residues, scum, etc. on a substrate after patterning a film using a hard mask.

  According to the semiconductor device of the present invention for solving the above-described problem, a hard mask is formed on the first film to be patterned via a sacrificial film, and then not covered with the hard mask. The first film in the region is etched and patterned, and then the sacrificial film is wet-etched to peel off the hard mask from the first film.

  The first film is an upper conductive film constituting the upper electrode of the capacitor, an insulating film in which a dual damascene wiring trench is formed, or the like. When the hard mask is made of nitride, the nitride is, for example, either a silicon nitride film or a titanium nitride film. Further, the sacrificial film interposed between the hard mask and the first film is selected from any one of an alumina film, an aluminum nitrogen oxide film, a tantalum oxide film, and a titanium oxide film, for example.

  According to the present invention, a hard mask is formed on a first film to be patterned via a sacrificial film, and the first film in a region not covered with the hard mask is etched and patterned. Further, when removing the hard mask, the sacrificial film is removed by wet processing.

  Accordingly, when a hard mask used for patterning the first film is formed of a nitride hard film, for example, residues, scum, and the like can be easily removed from the first film. In addition, it is possible to prevent a residue such as nitride, scum, and the like from reattaching during etching of the hard mask.

  Therefore, it is possible to suppress the remaining of contaminants when manufacturing the semiconductor device.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
(First embodiment)
1 to 5 are cross-sectional views showing a process for forming a semiconductor device according to the first embodiment of the present invention.
First, steps required until a sectional structure shown in FIG.

  In FIG. 1A, an element isolation insulating film 2 having a LOCOS structure is formed on the surface of a p-type or n-type silicon (semiconductor) substrate 1 by a selective oxidation method. The element isolation insulating film 2 may employ a shallow trench isolation (STI) structure.

  Subsequently, by selectively introducing p-type impurities and n-type impurities into predetermined active regions (transistor forming regions) in the memory cell region A and the peripheral circuit region B of the silicon substrate 1, the active region of the memory cell region A The first well 3a is formed in the first step, and the second well 3b is formed in the active region of the peripheral circuit region B.

  Thereafter, the surface of the silicon substrate 1 is thermally oxidized to form silicon oxide films used as the gate insulating films 4a, 4b, and 4c on the surfaces of the first and second wells 3a and 3b.

  Next, a polycrystalline or amorphous silicon film and a tungsten silicide film are sequentially formed as a conductive film on the element isolation insulating film 2 and the gate insulating films 4a, 4b, and 4c. Further, an insulating film 6 made of either a silicon oxide film, a silicon nitride film, or a two-layer structure thereof is formed on the conductive film. Then, by patterning the insulating film 6 to the silicon film into a predetermined shape by photolithography, two gate electrodes 5a and 5b are formed on the first well 3a at intervals, and the second well is formed. A gate electrode 5c is formed on 3b. The upper surfaces of the gate electrodes 5a, 5b, and 5c are covered with the insulating film 6.

  Note that a part of one gate electrode 5a on the first well 3a is omitted.

  In the memory cell region A, the two gate electrodes 5a and 5b formed above the first well 3a are formed at a substantially parallel interval, and these gate electrodes 5a and 5b are formed on the element isolation insulating film 2. It extends to become a word line.

The silicon substrate 1 on both sides of the two gate electrodes 5a and 5b formed on the first well 3a in the memory cell region A via the gate insulating films 4a and 4b is oppositely conductive to the first well 3a. The first and second impurity diffusion regions 7a and 7b and the third n-type impurity diffusion region (non-impurity) which are the source / drain of the first and _second MOS transistors T ₁ and T ₂ are implanted by ion implantation of a type impurity. Are formed).

  In these impurity diffusion regions 7a and 7b, after insulating sidewalls 9 are formed on the side surfaces of the gate electrodes 5a and 5b, impurities of the same conductivity type are ion-implanted again to form an LDD structure.

  The first impurity diffusion region 7a located in the center of the first well 3a is electrically connected to the bit line above the first impurity diffusion region 7a, and the second impurity diffusion region located near both sides of the first well 3a. 7b and a third impurity diffusion region (not shown) are electrically connected to a ferroelectric capacitor described later.

Subsequently, of the second well 3b in the peripheral circuit region B, the silicon substrate 1 on both sides of the gate electrode 5c is ion-implanted with an impurity having a conductivity type opposite to that of the second well 3b, so that the third MOS 4 serving as the source / drain of the transistor T _3, the fifth impurity diffusion regions 8a, 8b are formed. These impurity diffusion regions 8 a and 8 b have an LDD structure by impurity ion implantation again after the formation of the sidewall insulating film 9.

The sidewall insulating film 9 is formed by forming an insulating film such as silicon oxide (SiO ₂ ) on the silicon substrate 1, the element isolation insulating film 2 and the gate electrodes 5a, 5b, and 5c, and then etching back the insulating film. It is formed.

Thereafter, a cover film 10 of, for example, silicon oxynitride (SiON) covering the first, second, and third MOS transistors T ₁ , T ₂ , T ₃ is formed on the silicon substrate 1 by plasma CVD.

Next, a silicon oxide (SiO ₂ ) film is grown on the cover film 10 by plasma CVD using TEOS (tetraethoxysilane) gas, and this silicon oxide film is used as the first interlayer insulating film 11.

  Subsequently, as the densification treatment of the first interlayer insulating film 11, the first interlayer insulating film 11 is heat-treated at a temperature of 650 ° C. for 10 minutes in an atmospheric pressure oxygen atmosphere. Thereafter, the upper surface of the first interlayer insulating film 11 is polished and planarized by a chemical mechanical polishing (CMP) method.

Next, as shown in FIG. 1B, an alumina (Al ₂ O ₃ ) film is formed as the adhesion film 12 on the first interlayer insulating film 11 by sputtering. Thereafter, the alumina film is oxidized in an oxygen atmosphere at 650 ° C. by rapid heat treatment. The adhesion film 12 is formed in order to improve adhesion with a capacitor lower electrode described later.

Subsequently, a first conductive film 13, a ferroelectric film 14, a second conductive film 15, and an alumina film 16 are sequentially formed on the adhesion film 12.
As the first conductive film 13, platinum (Pt), iridium (Ir), or the like is formed to a thickness of 50 to 300 nm.

Further, as the ferroelectric film 14, PZT (PbZrTiO ₃ ) is formed in an amorphous state by a sputtering method. Subsequently, the ferroelectric film 17 is subjected to a rapid heat treatment for crystallization, for example, a heat treatment for 90 seconds in an O ₂ atmosphere at 575 ° C. and 1.25%.

Other methods for forming the ferroelectric layer 14 include a spin-on method using a MOD (metal organic deposition) solution, a MOCVD (organometallic CVD) method, and a spin-on method using a sol-gel solution. In addition, as the material of the ferroelectric layer 17, other PZT materials containing at least one element of lanthanum (La), strontium (Sr), calcium (Ca) in PZT, SrBi ₂ Ta ₂ O ₉ , bismuth layered structure compounds such as SrBi ₂ (Ta, Nb) ₂ O ₉ , and other metal oxide ferroelectrics may be employed.

The second conductive film 15 is composed of an iridium oxide (IrO ₂ ) film. The IrO ₂ film is formed by, for example, a two-step film formation method, and the first IrO ₂ film is formed as a lower layer portion by a sputtering method so as to have a thickness of, for example, 100 to 300 nm. Then, in order to recover the damage of the ferroelectric film 14 received by the formation of the first IrO ₂ film to the original state, a rapid heat treatment, for example, a heat treatment for 20 seconds in a 700 ° C., 1% O ₂ atmosphere. Is done. Thereafter, the second IrO ₂ film is formed on the first IrO ₂ film as an upper layer portion of the second conductive film 15.

  The alumina film 16 is formed to a thickness of 20 nm to 50 nm, for example, by sputtering. As film formation conditions, for example, alumina is used as a target, the substrate temperature is room temperature (for example, 20 ° C.), the pressure of the sputtering atmosphere is 1.0 Pa, the flow rate of argon (Ar) gas flowing in the sputtering atmosphere is 20 sccm, and the high frequency (RF) Bias power is set to 2 kW, respectively. As will be described later, the alumina film 16 is used as a sacrificial film when removing the hard mask.

The TiN film 17 is formed to a thickness of about 20 nm by sputtering, for example. As the film forming conditions, for example, titanium is used as a target, argon (Ar) gas and nitrogen (N ₂ ) gas are introduced into the sputtering atmosphere, and the substrate temperature is set to 200 ° C., for example.

After applying a photoresist 18 on the TiN film 17, as shown in FIG. 1C, this is exposed and developed to form a planar pattern of the capacitor upper electrode to form a resist pattern 18a. Subsequently, as shown in FIG. 2A, the TiN film 17 is etched by sputtering using the resist pattern 18a as a mask, whereby the TiN film 17 left under the resist pattern 18a is used as the hard mask 17a. To do.
An antireflection film such as an organic BARC film may be formed between the photoresist 18 and the TiN film 17.

  The resist pattern 18a is removed during the etching of the TiN film 17, and residues, scum, etc. 17b generated by the etching of the TiN film 17 are removed by a wet cleaning process. The residues, scum, etc. 17b are removed from the surface of the TiN hard mask 17a. It will be in the state which adhered to. The resist pattern 18a may be formed to a thickness that can be removed by a solvent before or after the patterning of the alumina film 16.

  Next, as shown in FIGS. 2B and 2C, the alumina film 16 and the second conductive film 15 in a region not covered with the hard mask 17a are continuously etched by sputtering, and below the hard mask 17a. The remaining second conductive film 15 is used as the capacitor upper electrode 15a.

  Thereafter, in order to remove residues, scum, etc. 17b adhering to the surface of the hard mask 17a from the capacitor upper electrode 15a, as shown in FIG. 3A, the alumina film 16 is used as a sacrificial film by wet processing. Etch.

As a chemical solution used for the wet treatment, a mixed solution of ammonium fluoride, amide, organic acid, organic acid salt, and water is used. As the mixed solution, for example, a chemical solution containing ammonium fluoride, glycol ether, dimethylacetamide, water, more specifically, a trade name of Air Products and Chemicals, Inc. of the United States. There is ACTNE98 or the product name KEC2xx or 6xx (2xx or 6xx series) of EKC Technology KK in the United States.
The concentration of ammonium fluoride contained in the chemical solution is preferably 0.05 to 4.50% by volume. The temperature of the chemical solution is preferably about 25 to 50 ° C. for etching alumina.

  Under such conditions, the etching rate of the alumina film 16 is fast, and residues, scum, etc. 17b generated by etching of the TiN film 17 are removed from the upper electrode 15a of the capacitor as the hard mask 17a is peeled off by etching of the alumina film 16. Removed. Further, the chemical solution used here does not cause film loss in the ferroelectric film 14 and the capacitor upper electrode 15a.

  6A and 6B show a wet processing apparatus 31 for removing the alumina film 16, and a suction chuck 32 for mounting the silicon substrate (silicon wafer) 1 on its upper surface and a rotation for rotating the suction chuck 32. A mechanism 33 is provided. A cylindrical shutter 34 is disposed on the outer periphery of the suction chuck 32. The cylindrical shutter 34 is opened upward during chemical solution processing, and closed downward during washing and drying.

  In the state where the shutter 34 is opened as shown in FIG. 6A, the liquid radiated from above by the centrifugal force due to the rotation of the silicon wafer 1 passes under the shutter 34. On the other hand, in the closed state as shown in FIG. 6B, the liquid radiated by the centrifugal force due to the rotation of the silicon wafer 1 hits the inner wall of the shutter 34.

  A liquid recovery bowl 35 is disposed below the shutter 34 to recover the liquid that has hit the inner wall of the closed shutter 34. The upper opening end of the liquid recovery bowl 35 is positioned below the suction chuck 32, and the bottom surface of the liquid recovery bowl 35 has a waste liquid port 36.

  On the further outer periphery of the liquid recovery bowl 35, a cylinder 36 is disposed on which the chemical liquid that has passed under the opened shutter 34 hits. Further, a flange 36 a is provided at the lower end of the outer periphery of the cylinder 36, and a liquid flow path is formed with the flange 35 a provided on the outer periphery of the liquid recovery bowl 35.

  In such a wet processing apparatus, the silicon substrate 1 having a structure as shown in FIG. Then, as shown in FIG. 6A, the shutter 34 is opened, the suction chuck 32 is rotated at, for example, 120 rpm by the rotation mechanism 33, and the chemical solution is supplied from the chemical solution nozzle 37 to the silicon substrate 1 to etch the alumina film 16. To do. The treatment time is appropriately changed depending on the type and concentration of the chemical solution.

Thereby, as shown in FIG. 3A, the hard mask 17a made of TiN is peeled off from the capacitor upper electrode 15a.
After that, as shown in FIG. 6B, the shutter 34 is closed, the suction chuck 32 is rotated at a speed of, for example, 300 rpm by the rotation mechanism 33, and pure water is supplied from the DIW nozzle 38 to the silicon substrate 1 to The electrode 15a, the ferroelectric film 14 and the like are cleaned, for example, for about 60 seconds.

  By these wet treatments, the residue / scum 27b is removed from the silicon substrate 2 together with the chemical solution, the cleaning solution, and the like. Further, the suction chuck 32 is rotated by the rotation mechanism 33 at a speed of, for example, 4000 rpm for 20 seconds to dry the capacitor upper electrode 15a, the ferroelectric film 14, and the like.

  Next, as shown in FIG. 3B, a resist is applied onto the ferroelectric film 14 and the capacitor upper electrode 15a, and this is exposed and developed to cover the region including the capacitor upper electrode 15a. A pattern 19 is formed.

  Subsequently, as shown in FIG. 3C, the ferroelectric film 14 is etched using the resist pattern 19 as a mask. As a result, a capacitor dielectric film 14 a is formed from the ferroelectric film 14. The patterned ferroelectric film 14 has a shape expanded around the capacitor upper electrode 15a, and has a shape that is long in the extending direction of the word line, for example.

  After the resist pattern 19 is removed, another resist pattern 20 having the shape of the capacitor lower electrode is newly formed as shown in FIG. 4A, and the first conductive film 13 is formed using the resist pattern 20 as a mask. Etch. As shown in FIG. 4B, the patterned first conductive film 13 becomes a capacitor lower electrode 13a, protrudes from the bottom of the capacitor dielectric film 14a, and extends in a stripe shape in the word line extending direction. It has a contact region that is not covered by the dielectric film 14a and the capacitor upper electrode 15a.

By the patterning as described above, by one of the underlying capacitor upper electrode 18 a capacitor dielectric film 14a and the capacitor lower electrode 13a, one ferroelectric capacitor Q ₁ is constructed.

Next, an alumina film is formed as a capacitor protection insulating film 21 on the ferroelectric capacitor Q ₁ and the adhesion film 12 by sputtering so as to have a thickness of about 20 to 50 nm. As the capacitor protection insulating film 21, an aluminum nitride oxide film, a tantalum oxide film, a titanium oxide film, or the like may be used in addition to the alumina film.

Subsequently, as shown in FIG. 4C, the capacitor protection insulating film 21 and the adhesion film 12 are patterned using a resist mask (not shown), so that the _first region is formed in a region other than the plurality of ferroelectric capacitors Q1. The surface of one interlayer insulating film 14 is exposed.

Next, as shown in FIG. 5A, a silicon oxide film having a thickness of about 1 μm is formed as a second interlayer insulating film 22 on the capacitor protection insulating film 21 and the first interlayer insulating film 11. . This silicon oxide film is formed by CVD using TEOS, for example. Subsequently, the upper surface of the second interlayer insulating film 22 is planarized by the CMP method. In this example, the remaining film thickness of the second interlayer insulating film 22 after CMP is set to about 300 nm on the ferroelectric capacitor Q _{1 in} the memory cell region A.

Further, an alumina film 23 and a base insulating film 24 are sequentially formed on the second interlayer insulating film 22. The alumina film 23 is formed in order to protect the ferroelectric capacitor Q ₁ from hydrogen and water in the subsequent process. Further, the base insulating film 24 is made of silicon oxide in order to improve the adhesion with the wiring formed thereon, and is formed by a CVD method using TEOS as a source gas.

  Next, a via formation resist pattern (not shown) is formed on the second interlayer insulating film 22, and the base insulating film 24, the alumina film 23, the second interlayer insulating film 22, the first interlayer insulating film 11, By etching the cover film 10, as shown in FIG. 5B, on the capacitor upper electrode 15a, on the contact region of the capacitor lower electrode 13a, and on the impurity diffusion regions 7a, 7b, 8a and 8b. The contact holes 22a to 22f are formed respectively.

Further, a titanium (Ti) film and a titanium nitride (TiN) film are sequentially formed as a glue film on the inner surfaces of the contact holes 22a to 22f and the upper surface of the base insulating film 24 by a sputtering method. Further, a tungsten (W) film is grown on the TiN film by CVD using tungsten hexafluoride (WF ₆ ) as a source gas to completely fill the contact holes 22a to 22f.

  Thereafter, the W film, the TiN film, and the TiN film are removed from the upper surface of the base insulating film 24 by the CMP method. Thereby, the W film, the TiN film, and the TiN film left in the contact holes 22a to 22f are applied as the conductive plugs 25a to 25f.

  Thereafter, a metal film is formed on the base insulating film 24 and the conductive plugs 25a to 25f. As the metal film, for example, a TiN film having a thickness of 150 nm, an aluminum film having a thickness of 500 nm, a Ti film having a thickness of 5 nm, and a TiN film having a thickness of 100 nm are sequentially formed on the base insulating film 24.

  Subsequently, by patterning the metal film by photolithography, as shown in FIG. 5C, the conductive plug 21a is disconnected and connected on the impurity diffusion region 7a at the center of the first well 3a. The conductive pads 23 are formed, and further, the wirings 23 to 27 connected to the second to sixth conductive plugs 21b to 21f are formed.

  After forming the conductive pad 23 and the wirings 24 to 27, a third interlayer insulating film is further formed, a conductive plug is formed, and a bit line and the like are further formed on the third interlayer insulating film. Details thereof are omitted.

  As described above, the alumina film 16 formed between the hard mask 17a and the lower electrode 15a is removed by an optimal wet process, so that the hard mask 17a is peeled off from the capacitor upper electrode 15a and removed. Therefore, it is possible to prevent the residue, scum, and the like attached to the surface of the hard mask 17a from attaching again.

  For example, when the hard mask 17a is left as it is, residues are attached to the surface as shown in FIG. 7, but when the underlying alumina film 16 is removed by wet processing, the residues 17b are not removed from the hard mask 17a. At the same time, it was poured into the chemical.

(Second Embodiment)
8 and 9 are cross-sectional views showing the steps of forming a semiconductor device according to the second embodiment of the present invention. 8 and 9, the same reference numerals as those in FIGS. 1 to 5 denote the same elements.

First, steps required until a structure shown in FIG.
According to the same manner as the first embodiment, the first well 3a in the memory cell region A of the silicon substrate 1, first, to form a second MOS transistors T _1, T _2, those of the MOS transistors T _1, A cover film 10 and a first interlayer insulating film 11 covering T ₂ are formed. The element isolation insulating film 2 formed around the first well 3a has an STI structure.

On both sides of the gate electrodes 5a and 5b of the first and second MOS transistors T ₁ and T ₂ , there are first, second and third impurity diffusion regions 7a, 7b, 7c is formed.

  A first contact hole 11a is formed by photolithography on the first impurity diffusion region 7a between the two gate electrodes 5a and 5b, and a titanium (Ti) film and a glue film are formed therein. A TiN film is grown, and further a tungsten film is grown by a CVD method, whereby the first conductive plug 41 is configured. Note that the glue film and the tungsten film on the first interlayer insulating film 11 are removed by CMP.

  Next, an antioxidant film 42 made of a silicon nitride film and a base insulating film 43 made of a silicon oxide film are sequentially formed on the first interlayer insulating film 11 and the first conductive plug 41 by a plasma CVD method to 100 nm. Grows to a degree of thickness.

  Further, the base insulating film 43 to the cover film 10 are patterned by photolithography to form second and third contact holes 11b and 11c on the second and third impurity diffusion regions 7b and 7c. Then, the second and third conductive plugs 44 and 45 are formed in the second and third contact holes 11 b and 11 c by the same method as the formation of the first conductive plug 41.

Next, as shown in FIG. 8B, a first conductive film 46 is formed on the second and third conductive plugs 44 and 45 and the base insulating film 43. As the first conductive film 46, for example, an Ir film having a thickness of 200 nm and an IrO ₂ film having a thickness of about 100 nm are formed by sputtering.

  Note that the base insulating film 43 is annealed before or after the first conductive film 46 is formed, for example, to prevent film peeling. As an annealing method, for example, RTA heated at 600 to 750 ° C. in an argon atmosphere is employed.

Next, a PZT film of, eg, a 100 nm-thickness is formed as a ferroelectric film 47 on the first conductive film 46 by sputtering. Other methods for forming the ferroelectric film 47 include the MOD method, the MOCVD method, and the sol-gel method. As the material of the ferroelectric film 47, in addition to PZT, other PZT materials such as PLCSZT and PLZT, and bismuth (Bi) material SrBi ₂ (Ta _x Nb _1-x ) ₂ O ₉ (However, 0 <x ≦ 1), Bi ₄ Ti ₂ O ₁₂ or the like may be used.

  Subsequently, the ferroelectric film 47 is crystallized by annealing in an oxygen atmosphere. As the annealing, for example, the first step is a substrate temperature of 600 ° C. for 90 seconds in a mixed gas atmosphere of argon and oxygen, and the second step is a substrate temperature of 750 ° C. for 60 seconds in an oxygen atmosphere. RTA processing is adopted.

  Further, on the ferroelectric film 47, for example, iridium oxide having a film thickness of 300 nm is formed as the second conductive film 48 by sputtering. As growth conditions for the iridium oxide film, an iridium target is used, the sputtering power is 1 kW, and argon and oxygen are allowed to flow in the growth atmosphere.

  Thereafter, an alumina film 49 serving as a sacrificial oxide film is formed on the second conductive film 48 to a thickness of, for example, 20 nm to 50 nm by sputtering. As film formation conditions, for example, alumina is used as a target, the substrate temperature is room temperature (for example, 20 ° C.), the pressure of the sputtering atmosphere is 1.0 Pa, the flow rate of argon (Ar) gas flowing in the sputtering atmosphere is 20 sccm, and the high frequency (RF) Bias power is set to 2 kW, respectively.

  Further, a TiN film 50 and a silicon oxide film 51 are sequentially formed on the alumina film 49 so as to have thicknesses of about 20 nm and about 70 nm, respectively. The TiN film 50 is formed by a sputtering method. As a film forming condition, for example, titanium is used as a target, and nitrogen gas is allowed to flow in the film forming atmosphere.

The silicon oxide film 51 is grown by a high density plasma (HDP) CVD method. The growth conditions are, for example, that the bias power of the silicon substrate 1 is 0 W, the high frequency power of the electrode facing the silicon substrate 1 is 3500 W, the substrate temperature is about 250 ° C., the growth pressure is 15 mTorr, and silane (SiH ₄ ) The gas flow rate is 70 sccm, the oxygen (O ₂ ) gas flow rate is 525 sccm, and the argon (Ar) gas flow rate is 420 sccm.

The silicon oxide film 51 is not limited to adopting the HDPCVD method, but other growth methods for reducing damage to the ferroelectric film 47, for example, TEOS, nitrogen oxide (N ₂ O), oxygen (O ₂ ) may be used, and growth may be performed with low moisture and low stress by a plasma enhanced CVD method using a reaction during plasma discharge.

  Thereafter, a photoresist 52 is applied on the silicon oxide film 51, and this is exposed and developed to form a capacitor planar shape above the second and third conductive plugs 44 and 45. An antireflection film such as an organic BARC film may be formed between the photoresist 52 and the silicon oxide film 51.

  Next, as shown in FIG. 8C, using the photoresist 52 as a mask, the silicon oxide film 51 and the TiN film 50 are etched by sputtering, whereby the silicon oxide film 51 left under the photoresist 52 is etched. The TiN film 50 is used as the hard mask 53.

  Then, after removing the photoresist 52 with a solvent, residues, scum, and the like generated by etching of the TiN film 50 are removed by a wet cleaning process. The residues, scum, etc. are removed from the surface of the hard mask 52, particularly the TiN film 50. It will be in the state which cannot be easily removed by adhering to the side surface.

Next, as shown in FIG. 9A, the alumina film 49, the second conductive film 48, the ferroelectric film 47, and the first conductive film 46 in a region not covered with the hard mask 53 are sequentially etched and patterned. . In this case, the ferroelectric film 47 is etched by sputtering in an atmosphere containing chlorine and argon. The second conductive film 48 and the first conductive film 46 are etched by a sputtering reaction in a bromine (Br ₂ ) -introduced atmosphere.

Thus, on the oxidation-preventing insulating film 43, a lower electrode 46a of the capacitor Q ₂ to which consists of the first conductive film 46, the capacitor Q ₂ to which made of a ferroelectric film 47 and the dielectric film 47a, the second upper electrode 48a of the capacitor Q ₂ to which consisting the conductive film 48 is formed.

  On the first well 3a, one lower electrode 46a is electrically connected to the second impurity diffusion region 7b through the second conductive plug 44, and another lower electrode 46a is connected to the third well 46a. It is electrically connected to the third impurity diffusion region 7 c through the conductive plug 45.

  Thereafter, as shown in FIG. 9B, the hard mask 53 is removed. The removal of the hard mask 53 is performed, for example, by etching the alumina film 49 with the wet processing apparatus shown in FIG. 6 under the same conditions as in the first embodiment.

  As the chemical solution used for the wet treatment, for example, a chemical solution similar to that of the first embodiment, for example, a mixed solution of ammonium fluoride, amide, organic acid, organic acid salt, and water is used. As the mixed solution, for example, a chemical solution containing ammonium fluoride, glycol ether, dimethylacetamide, and water is used. The concentration of ammonium fluoride contained in the chemical solution is preferably 0.05 to 4.50% by volume. The temperature of the chemical solution is preferably about 25 to 50 ° C. for etching the alumina film 49.

  According to this condition, the etching rate of the silicon oxide film 51 formed at an unbias and temperature of about 250 ° C. constituting the hard mask 53 is 0.2 to 0.4 nm / min, while the etching rate of the alumina film 49 is Is 5 to 6 nm / min. Therefore, the etching rate of the alumina film 49 is fast, and the residue on the surface of the hard mask 53 is peeled off from the upper electrode 48 a together with the hard mask 53 by the etching of the alumina film 49.

  Subsequently, recovery annealing is performed to recover damage to the ferroelectric film 47 due to etching. In this case, the recovery annealing is performed, for example, in an oxygen atmosphere at a substrate temperature of 650 ° C. for 60 minutes.

Next, steps required until a structure shown in FIG.
After forming alumina having a film thickness of 50 nm as the capacitor protective insulating film 54 covering the capacitor Q ₂ by sputtering, the capacitor Q ₂ is annealed in an oxygen atmosphere at 650 ° C. for 60 minutes. This capacitor protection insulating film 54 protects the capacitor Q ₂ from process damage.

  Subsequently, a silicon oxide film is formed as a second interlayer insulating film 55 on the capacitor protection insulating film 54. This silicon oxide film is formed by the CVD method using TEOS, and is flattened by CMP after the growth.

Further, a contact hole is formed on the upper electrode 48a and the first conductive plug 41 of the capacitors Q _2, further embedding the fourth, fifth conductive plugs 56, 57 therein. The method for forming the conductive plugs 56 and 57 is the same as the process for forming the first conductive plug 41.

  Thereafter, a bit line conductive pad 58 connected to the conductive plug 56 above the first impurity diffusion region 7a and a wiring 59 connected to the conductive plug 57 on the upper electrode 48a are connected to the third interlayer insulating film. 55 is formed.

  Thereafter, although not described in detail, an interlayer insulating film, a conductive plug, a wiring, and the like are formed on the second interlayer insulating film 55, the wiring 59, and the conductive pad 58.

As described above, in the present embodiment, the hard mask 53 is composed of the two-layer structure of the TiN film 50 and the silicon oxide film 51, and the alumina film 49 is interposed between the hard mask 53 and the first conductive film 48 as a sacrificial film. After the hard mask 53 is used, the hard mask 53 is removed by removing the alumina film 49 by wet processing.
Therefore, residues, scum, etc. adhering to the hard mask 53 are easily removed together with the chemical solution and the cleaning solution and do not become a contamination source in the subsequent steps.

(Third embodiment)
10 to 13 are sectional views showing a method for forming a semiconductor device according to the third embodiment of the present invention.
First, steps required until a structure shown in FIG.

A first interlayer insulating film 62 is formed on a silicon (semiconductor) substrate 61. Further, a first SOG film 63 having a thickness of about 150 nm and a second interlayer insulating film having a thickness of about 100 nm are formed thereon. 64 is formed. As the first and second interlayer insulating films 62 and 64, for example, silicon oxide films are grown by plasma CVD.
The first SOG film 63 and the second interlayer insulating film 64 have a first groove 65 with a width of about 200 nm, and the first groove 65 has a refractory metal along the inner peripheral surface thereof. For example, a barrier metal film made of TiN or tantalum nitride (TaN) is formed.

  In the first groove 65, a copper film is formed on the barrier metal film by sputtering, and the first wiring 66 is constituted by the copper film and the barrier metal film in the first groove 65. Note that the barrier metal film and the copper film formed on the second interlayer insulating film 64 are removed by CMP.

  Next, on the first wiring 66 and the second interlayer insulating film 64, for example, a first antioxidant film 70 made of a silicon nitride film having a thickness of about 70 nm and a silicon oxide film having a thickness of about 280 nm are formed. A third interlayer insulating film 71 is formed by plasma CVD.

  Further, a second SOG film 72 having a thickness of about 150 nm is formed on the third interlayer insulating film 71. Subsequently, a fourth SOG film made of a silicon oxide film having a thickness of about 100 nm is formed on the second SOG film 72. An interlayer insulating film 73 is grown by plasma CVD.

  A low dielectric constant organic insulating film may be applied as the first to fourth interlayer insulating films 62, 64, 71, 73. The first and second SOG films 63 and 72 are not limited in their constituent materials. For example, any of the first and fourth interlayer insulating films 62, 64, 71 and 73 is selected. A material that can be etched is selected.

  Next, an alumina film 74 having a thickness of about 50 nm is formed as a sacrificial film on the fourth interlayer insulating film 73 by sputtering, and a second silicon nitride film 75 thicker than the first silicon nitride film 70 is formed thereon. Growing by plasma CVD method. An antireflection film 76 made of organic BARC is formed on the second silicon nitride film 75, and a photoresist 77 is applied thereon. Then, the photoresist 77 is exposed and developed to form an opening 77a in the wiring region C.

  Next, as shown in FIG. 10B, the wiring groove 78 is formed by etching, for example, reactive ion etching (RIE) from the antireflection film 76 to the alumina film 74 exposed from the opening 77a of the photoresist 77. Next, as shown in FIG. To do.

  Further, as shown in FIG. 10C, the photoresist 77 and the antireflection film 76 are removed. The photoresist 77 may be removed either before, during, or after the etching of the alumina film 74. The patterned second silicon nitride film 75 is used as a hard mask 75a. Residues, scum, and the like are generated during the etching of the silicon nitride film 75 for forming the hard mask 75a, and a part thereof is attached to the surface of the hard mask 75a without being removed by the subsequent wet cleaning process. .

  Subsequently, as shown in FIG. 11A, a second antireflection film 79 made of organic BARC is formed in the wiring trench 78 and on the hard mask 75a, and further, a second photoresist 80 is formed thereon. Apply. Then, the second photoresist 80 is exposed and developed to form a via forming opening 80a.

  Next, as shown in FIG. 11B, via holes 81 are formed by dry etching, for example, by the RIE method, from the alumina film 74 exposed through the via forming opening 80a to the third interlayer insulating film 71. In this case, the first antioxidant film 70 serves as an etching stopper. Subsequently, as shown in FIG. 11C, the second photoresist 80 and the second antireflection film 79 are removed.

  Further, as shown in FIGS. 12A and 12B, the fourth interlayer insulating film 73 and the second SOG film 72 exposed from the wiring groove 78 are etched to deepen the wiring groove 78. . In this case, the fourth interlayer insulating film 73 and the second SOG film 72 are etched by dry etching using a gas containing fluorine, while the hard mask 75a and the first silicon nitride film 64 are used as etching stoppers.

Further, as shown in FIG. 12C, the first antioxidant film 64 made of a silicon nitride film is etched by the RIE method through the via hole 81, thereby exposing a part of the first wiring 66 and exposing the via hole. Make 81 deeper. For example, a mixed gas of CHF ₃ , Ar, and O ₂ is used as an etching gas, and the fourth interlayer insulating film 73 is not etched. In this case, the hard mask 75a made of a silicon nitride film is etched and thinned, and residues, scum, and the like resulting from etching adhere to the surface.

  Next, as shown in FIG. 13A, the hard mask 75a is removed. The removal of the hard mask 75a is performed, for example, by etching the alumina film 74 using the wet processing apparatus shown in FIG. 6 under the same conditions as in the first embodiment.

  As a chemical solution used for the wet treatment, a mixed solution of ammonium fluoride, amide, organic acid, organic acid salt, and water is used. As the mixed solution, the same chemical solution as exemplified in the first embodiment is used, and for example, a chemical solution containing ammonium fluoride, glycol ether, dimethylacetamide, and water is used. The concentration of ammonium fluoride contained in the chemical solution is preferably 0.05 to 4.50% by volume. The temperature of the chemical solution is preferably about 25 to 50 ° C.

  The etching rate of the alumina film 74 is fast, and residues, scum, etc. on the surface of the hard mask 75a made of a silicon nitride film are peeled off from the fourth interlayer insulating film 74 together with the hard mask 75a by the etching of the alumina film 74. As a result, the upper surface of the clean fourth interlayer insulating film 73 is exposed.

  Next, as shown in FIG. 13B, a barrier film made of TiN or TaN is grown along the inner surfaces of the wiring trench 78 and the via hole 81, and the copper film is embedded in the barrier film, and the via hole 81 is filled with copper. In addition, a second wiring 83 made of copper is formed in the wiring groove 78. Note that the barrier metal film and the copper film on the fourth interlayer insulating film 73 are removed by CMP.

  Then, a second antioxidant film 84 made of a silicon nitride film is formed on the second wiring 83. Thereafter, a third-layer wiring and a second-layer via are formed by a similar process.

  In the above embodiment, even if residues, scum, etc. generated when patterning the silicon nitride film 75 constituting the hard mask 75a adhere to the hard mask 75a, the underlying alumina film 74 is then wet-processed. The hard mask 75a is removed together with the residue, scum, etc. by removing.

  Accordingly, the removal of the hard mask 75a is facilitated, and the residue, scum and the like attached to the surface of the hard mask 57a are flowed to the outside together with the chemical solution and the cleaning solution, and recontamination due to the residue, scum and the like is prevented.

  By the way, in said 1st-3rd embodiment, an alumina film | membrane is formed as a sacrificial film under a hard mask, and the hard mask on it is peeled by carrying out wet etching of this.

  However, the sacrificial film used for removing the hard mask is not limited to the alumina film, and a film capable of increasing the etching rate as compared with the hard mask, such as an aluminum nitrogen oxide film (AlNO film). ), A tantalum oxide film (TaO film), or a titanium oxide film (TiO film). In this case, the sacrificial film is formed to a thickness of about 20 nm or more, for example. The TaO film is preferably 80 nm or less.

  Further, when a nitride such as titanium nitride or silicon nitride is used as the hard mask, the effect of removing residues, scum, etc. by wet processing of the sacrificial film is particularly high. On the other hand, even when the hard mask is composed of a hard film of another material, a sacrificial film may be formed under the hard mask and the hard mask may be peeled off by wet treatment.

Next, features of the present invention will be added.
(Appendix 1) Forming a first film on a semiconductor substrate through an insulating film, forming a sacrificial film on the first film, and forming a hard film on the sacrificial film A step of forming a photoresist pattern on the hard film, a step of forming a hard mask by etching the hard film in a region not covered by the photoresist pattern, and not covered by the hard mask Etching the sacrificial film in a region; removing the photoresist pattern either during, before or after etching the sacrificial film; and the first in a region not covered by the hard mask. Etching and patterning the film, and removing the sacrificial film by wet processing to peel the hard mask from the first film. The method of manufacturing a semiconductor device, characterized in that.
(Additional remark 2) The said 1st film | membrane is an upper conductive film which comprises the upper electrode of a capacitor, The manufacturing method of the semiconductor device of Additional remark 1 characterized by the above-mentioned.
(Supplementary Note 3) Before the upper conductive film is formed, the lower conductive film and the dielectric film are sequentially formed on the insulating film, and the upper conductive film is patterned and then covered with the hard mask. Etching the dielectric film and the lower conductive film in a non-existing region to form the capacitor dielectric film and the lower electrode between the insulating film and the upper electrode. The manufacturing method of the semiconductor device according to attachment 2.
(Appendix 4) A step of forming a silicon oxide film between the photoresist pattern and the hard film, and etching the silicon oxide film in a region exposed from the photoresist pattern to form an upper layer portion of the hard mask The method for manufacturing a semiconductor device according to any one of appendix 1 to appendix 3, further comprising a step.
(Supplementary note 5) The semiconductor according to supplementary note 4, wherein the silicon oxide film is formed by a plasma enhanced vapor deposition method using TEOS or a vapor deposition method that puts the semiconductor substrate into an unbiased state. Device manufacturing method.
(Appendix 6) The method according to appendix 1, further comprising a step of forming a wiring groove by patterning the first film and a step of forming a wiring by filling the wiring groove with a conductive material. A method for manufacturing a semiconductor device.
(Supplementary Note 7) Before or after forming the wiring groove, forming another photoresist pattern having a via contact opening at a position overlapping the wiring groove, and the insulating film immediately below the via contact opening The method further includes: a step of forming a via hole by etching up to a step; and a step of forming a via by filling the conductive material filled in the wiring groove into the via hole. Semiconductor device manufacturing method.
(Supplementary Note 8) The hard film is any one of a silicon nitride film and a titanium nitride film, and the sacrificial film is selected from any one of an alumina film, an aluminum nitrogen oxide film, a tantalum oxide film, and a titanium oxide film. The method for manufacturing a semiconductor device according to any one of Appendix 1 to Appendix 7.
(Additional remark 9) The said silicon nitride film is formed by the plasma CVD method, The manufacturing method of the semiconductor device of Additional remark 8 characterized by the above-mentioned.
(Additional remark 10) The said wet process of the said sacrificial film is performed by use of the chemical | medical solution containing ammonium fluoride, The manufacturing method of the semiconductor device as described in any one of additional remark 1 thru | or appendix 9.
(Additional remark 11) The said chemical | medical solution contains an amide, organic acid, organic acid salt, and water further, The manufacturing method of the semiconductor device of Additional remark 10 characterized by the above-mentioned.
(Additional remark 12) The manufacturing method of the semiconductor device of Additional remark 10 characterized by further including glycol ether, dimethylacetamide, and water in the said chemical | medical solution.
(Additional remark 13) The said ammonium fluoride in the said chemical | medical solution is 0.05 volume%-4.5 volume%, The manufacturing method of the semiconductor device as described in any one of Additional marks 10 thru | or Additional note 12 characterized by the above-mentioned. .
(Supplementary note 14) The method for manufacturing a semiconductor device according to any one of supplementary notes 1 to 13, wherein an antireflection film is formed between the resist pattern and the hard film.

FIG. 1 is a cross-sectional view (No. 1) showing a step of forming a semiconductor device according to the first embodiment of the present invention. FIG. 2 is a sectional view (No. 2) showing a step of forming the semiconductor device according to the first embodiment of the invention. FIG. 3 is a sectional view (No. 3) showing the step of forming the semiconductor device according to the first embodiment of the invention. FIG. 4 is a sectional view (No. 4) showing a step of forming the semiconductor device according to the first embodiment of the invention. FIG. 5 is a sectional view (No. 5) showing the step of forming the semiconductor device according to the first embodiment of the invention. FIG. 6 is a schematic configuration diagram of a wet processing apparatus used for forming a semiconductor device according to an embodiment of the present invention. FIG. 7 is a plan view showing residues, scum, and the like attached to the film patterned in the process of forming the semiconductor device according to the first embodiment of the present invention. FIG. 8 is a cross-sectional view (No. 1) showing a step of forming a semiconductor device according to the second embodiment of the invention. FIG. 9 is a sectional view (No. 2) showing the step of forming the semiconductor device according to the second embodiment of the invention. FIG. 10 is a sectional view (No. 1) showing a step of forming a semiconductor device according to the third embodiment of the invention. FIG. 11 is a sectional view (No. 2) showing a step of forming a semiconductor device according to the third embodiment of the invention. FIG. 12 is a sectional view (No. 3) showing a step of forming a semiconductor device according to the third embodiment of the invention. FIG. 13 is a sectional view (No. 4) showing a step of forming a semiconductor device according to the third embodiment of the invention. FIG. 14 is a cross-sectional view showing a process for forming a semiconductor device according to the first prior art. FIG. 15 is a sectional view (No. 1) showing a step of forming a semiconductor device according to the second prior art. FIG. 16 is a cross-sectional view (No. 2) showing the step of forming the semiconductor device according to the second prior art.

Explanation of symbols

1 silicon substrate (semiconductor substrate),
2 element isolation insulating film,
3a, 3b, 3c well,
4a, 4b gate insulating film,
5a, 5b, 5c gate electrode,
7a, 7b, 7c, 8a, 8b impurity diffusion regions,
9 Side wall insulating film,
10 Cover membrane,
11 interlayer insulation film,
12 Adhesive film,
13 first conductive film,
14 Ferroelectric film,
14a: capacitor dielectric film,
15 second conductive film,
15a capacitor upper electrode,
16 Aluminum film (sacrificial film),
17 TiN film (hard film),
17a hard mask,
17b Residue, scum, etc.
18 photoresist,
18a resist pattern,
19, 20 resist pattern,
21 Capacitor protective film,
22 interlayer insulation film,
41, 44, 45 conductive plugs,
42 antioxidant film,
43 Underlying insulating film,
46 first conductive film,
46a capacitor lower electrode,
47 Ferroelectric film,
47a capacitor dielectric film,
48 second conductive film,
48a capacitor upper electrode,
49 Aluminum film (sacrificial film),
50 TiN film (hard film),
51 silicon oxide film,
52 photoresist,
53 Hard mask,
54 Capacitor protective film,
55 ... interlayer insulating film,
61 silicon substrate (semiconductor substrate),
62, 64, 71, 73 interlayer insulation film,
66 Wiring,
70, 84 Antioxidation film,
63, 72 SOG film,
74 Alumina film (sacrificial film),
75 Silicon nitride film (hard film),
75a hard mask,
76 antireflection film,
77 photoresist,
77a opening,
78 Wiring groove,
79 Anti-reflective coating,
80 photoresist,
80a opening,
81 via hole,
82 beer,
83 Wiring.

Claims (6)

Forming a first film on the semiconductor substrate via an insulating film;
Forming a sacrificial film on the first film;
Forming a hard film on the sacrificial film;
Forming a photoresist pattern on the hard film;
Etching the hard film in a region not covered with the photoresist pattern to form a hard mask;
Etching the sacrificial film in a region not covered by the hard mask;
Removing the photoresist pattern either before or after etching the sacrificial layer;
Etching and patterning the first film in a region not covered by the hard mask;
And a step of removing the sacrificial film by a wet process to peel the hard mask from the first film.   The method of manufacturing a semiconductor device according to claim 1, wherein the first film is an upper conductive film constituting an upper electrode of a capacitor.   Before the upper conductive film is formed, the lower conductive film and the dielectric film are sequentially formed on the insulating film, and in a region not covered with the hard mask, following the patterning of the upper conductive film. 3. The method according to claim 2, further comprising: forming a dielectric film and a lower electrode of the capacitor between the insulating film and the upper electrode by etching the dielectric film and the lower conductive film. The manufacturing method of the semiconductor device of description. Forming a wiring trench by patterning the first film;
The method of manufacturing a semiconductor device according to claim 1, further comprising a step of forming a wiring by filling the wiring groove with a conductive material.   Before or after forming the wiring groove, a step of forming another photoresist pattern having a via contact opening at a position overlapping the wiring groove, and etching up to the insulating film immediately below the via contact opening. 5. The semiconductor device according to claim 4, further comprising a step of forming a via hole and a step of filling the conductive material filled in the wiring groove into the via hole to form a via. Manufacturing method.   The hard film is a silicon nitride film or a titanium nitride film, and the sacrificial film is selected from an alumina film, an aluminum nitrogen oxide film, a tantalum oxide film, and a titanium oxide film. The method for manufacturing a semiconductor device according to claim 1.