JP2008159722A - Transistor, method of manufacturing transistor, electronic device, and electronic apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a transistor wherein an organic semiconductor layer can be formed in a desired thickness in a desired region relatively easily at a low cost, to provide a method of manufacturing the transistor, and to provide an electronic device and an electronic apparatus which are equipped with the transistor. <P>SOLUTION: The method of manufacturing the transistor 1 comprises a first process and a second process. In the first process, a source electrode 3 and a drain electrode 4 are formed in such a manner that the contour of a region between the source electrode 3 and the drain electrode 4 and the contour of a composite region 2 of the source electrode 3 and the drain electrode 4 combined may be constructed by a curved line substantially containing no angular portions having a right angle or an acute angle in planar view. In the second process, a liquid material 9 containing an organic semiconductor material or its precursor is dropped in the composite region 2 and then is solidified or hardened after being wet-expanded until it nearly overlaps the composite region 2 in planar view to form the organic semiconductor layer. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a transistor, a transistor manufacturing method, an electronic device, and an electronic apparatus.

In recent years, the development of transistors using organic materials (organic semiconductor materials) that exhibit semiconducting electrical conduction has been promoted. This transistor has advantages such as being suitable for reduction in thickness and weight, flexibility, and low material cost, and is expected as a switching element for flexible displays and the like.
Such a transistor includes a top gate structure in which a source electrode and a drain electrode and an organic semiconductor layer are formed on a substrate, and a gate insulating layer and a gate electrode are stacked in this order on each portion. A bottom gate structure is proposed in which a gate electrode and a gate insulating layer are stacked in this order, and a source electrode and a drain electrode and an organic semiconductor layer are formed on these portions (see, for example, Patent Document 1). .)

In patent document 1, when forming an organic-semiconductor layer on a board | substrate, the method (coating method) of apply | coating the liquid containing an organic-semiconductor material on a board | substrate, and solidifying and hardening is used. Since this method can be used in the air, the organic semiconductor layer forming process can be simplified and the cost of the transistor can be reduced.
In particular, in Patent Document 1, an ink jet method is used, and liquid droplets as described above are applied onto a substrate and solidified and cured. The ink jet method has an advantage that the organic semiconductor layer can be formed in a non-contact manner with respect to the substrate.

  By the way, in order to prevent interference between transistors and formation of a parasitic transistor, or to reduce leakage current and off-current, the formation region of the organic semiconductor layer is a region between the source electrode and the drain electrode and its vicinity. It is desirable to be limited to In addition, in order to obtain desired transistor characteristics, it is necessary to form the organic semiconductor layer with a desired region and thickness.

  In the coating method as described above, since the liquid applied to the substrate surface tends to aggregate due to the surface tension, it is difficult to form the organic semiconductor layer with a desired region and thickness by simply applying the liquid on the substrate. There is a problem. In particular, in the ink jet method, a liquid having a relatively low viscosity is used in order to more stably discharge droplets from a nozzle. For this reason, the behavior of the liquid applied to the substrate surface is strongly influenced by the surface tension and the wettability of the substrate surface, and the problems described above become significant.

In order to solve such a problem, in Patent Document 1, the substrate surface is controlled by controlling the wettability of the substrate surface or by providing a barrier structure (so-called bank structure) along the contour of a desired pattern. Controls the behavior of the liquid on the surface.
However, in these methods, it is necessary to form a region for controlling the wettability of the substrate or to form a partition wall structure separately from the formation of each part constituting the transistor. In particular, since it is necessary to use a photolithography method for forming these, the manufacturing process of the transistor becomes complicated, and the productivity is lowered.

Japanese Patent Laid-Open No. 2004-6682

  An object of the present invention is to provide a transistor capable of forming an organic semiconductor layer with a desired region and thickness at a relatively simple and low cost, a method for manufacturing the transistor, an electronic device and an electronic apparatus including the transistor. It is in.

Such an object is achieved by the present invention described below.
The transistor according to the present invention includes a source electrode, a drain electrode, a gate electrode, an organic semiconductor layer positioned between the source electrode and the drain electrode, and a gate positioned between the gate electrode and the organic semiconductor layer. A part of the outline of the organic semiconductor layer and a part of the outline of the source electrode coincide with each other, and a part of the outline overlaps with the source electrode of the organic semiconductor layer. Includes a curve, and a part of the contour overlapping with the organic semiconductor layer of the source electrode includes a curve. In this transistor, it is preferable that the organic semiconductor layer is formed at a position overlapping a composite region including the source electrode, the drain electrode, and a region between the source electrode and the drain electrode.

  Thus, since the organic semiconductor layer is formed up to the outline of the source electrode, even if the gate electrode is formed so as to cover the source electrode, the gate insulating layer and the organic semiconductor layer are provided between the source electrode and the gate electrode. Therefore, the occurrence of a short circuit between the source electrode and the gate electrode can be suppressed. Further, for example, when the contour of the source electrode is a stepped portion and the gate insulating layer is formed over the stepped portion, if the shape of the stepped portion in plan view is curved, the gate insulating film in the stepped portion Therefore, the occurrence of defects such as cracks can be suppressed.

A transistor according to the present invention includes a source electrode and a drain electrode provided on a substrate so as to be separated from each other,
An organic semiconductor layer located between the source electrode and the drain electrode;
A gate electrode, and a gate insulating layer that insulates the gate electrode from the source electrode and the drain electrode,
The source electrode and the drain electrode are configured so that a contour of a combined region including a region between the source electrode and the drain electrode and a combination of the source electrode and the drain electrode includes a curve in a plan view. Formed as
The organic semiconductor layer is formed by dropping an organic semiconductor material or a liquid material containing a precursor thereof into the composite region and solidifying or curing the organic semiconductor layer, and substantially matches the composite region in plan view. It is formed over a range.
Thus, a transistor having excellent characteristics can be provided by forming the organic semiconductor layer with a desired region and thickness at a relatively simple and low cost. In particular, when a plurality of transistors are provided over the same substrate, variation in characteristics among transistors can be suppressed.

In the transistor of the present invention, it is preferable that the outline of the composite region is formed so as not to substantially include a right angle or an acute corner.
As a result, when the transistor is manufactured, the dropped liquid material spreads over almost the entire circumference of the contour of the composite region when it spreads concentrically from the dropping position. Therefore, the organic semiconductor layer can be formed over a range substantially coincident with the composite region in plan view more reliably and easily.

In the transistor of the present invention, it is preferable that the composite region has a substantially circular shape or a substantially oval shape in plan view.
Thereby, when manufacturing the transistor, the variation in the distance from the center of the dropped liquid material to the edge of the composite region can be reduced. Therefore, when the dropped liquid material spreads concentrically from the dropping position, it spreads over almost the entire circumference of the contour of the composite region. Therefore, the organic semiconductor layer can be formed over a range substantially coincident with the composite region in plan view more reliably and easily.

In the transistor of the present invention, the region between the source electrode and the drain electrode has a longitudinal shape in plan view, and the composite region extends in the longitudinal direction of the region between the source electrode and the drain electrode. It is preferable that it is substantially oval so that it exists.
Thereby, when the planar view shape of the composite region is an ellipse, the organic semiconductor layer can be formed over a range that substantially coincides with the composite region in plan view more easily and reliably.

In the transistor of the present invention, a region between the source electrode and the drain electrode has a longitudinal shape in plan view, and the composite region has a plurality of substantially circular shapes or substantially oval shapes in the source electrode and the drain. It is preferable to have a shape in which the regions between the electrodes are connected side by side in the longitudinal direction.
As a result, even when the shape of the composite region in plan view is an elongated shape, the organic semiconductor layer can be seen in plan view more easily and reliably by dropping the liquid material into each substantially circular or substantially oval region. It can be formed over a range substantially coincident with the composite region.

In the transistor of the present invention, it is preferable that the source electrode and the drain electrode each have a comb-like portion in plan view, and are provided so as to mesh with each other with a space therebetween.
Thereby, even when the area of the composite region is large, the organic semiconductor layer can be formed over a range that substantially coincides with the composite region in plan view more easily and reliably.

A method of manufacturing a transistor according to the present invention includes a source electrode and a drain electrode provided on a substrate so as to be spaced apart from each other, an organic semiconductor layer positioned between the source electrode and the drain electrode, a gate electrode, A method of manufacturing a transistor having a gate insulating layer that insulates the gate electrode from a source electrode and a drain electrode,
In the plan view, the source electrode and the drain electrode are substantially perpendicular to each other or have a sharp corner portion of a composite region including the region between the source electrode and the drain electrode and the source electrode and the drain electrode. A first step of forming a curve so as not to include the curve;
A liquid material containing an organic semiconductor material or a precursor thereof is dropped into the composite region, spreads until it substantially coincides with the composite region in plan view, and then solidifies or cures, thereby forming the organic semiconductor layer. And a second step of forming.
Thus, a transistor having excellent characteristics can be provided by forming the organic semiconductor layer with a desired region and thickness at a relatively simple and low cost. In particular, when a plurality of transistors are provided over the same substrate, variation in characteristics among transistors can be suppressed.

In the transistor manufacturing method of the present invention, in the first step, the source electrode and the drain electrode are preferably formed so that the composite region has a substantially circular shape or a substantially oval shape in plan view. .
Thereby, when manufacturing the transistor, the variation in the distance from the center of the dropped liquid material to the edge of the composite region can be reduced. Therefore, when the dropped liquid material spreads concentrically from the dropping position, it spreads over almost the entire circumference of the contour of the composite region. Therefore, the organic semiconductor layer can be formed over a range substantially coincident with the composite region in plan view more reliably and easily.

In the transistor manufacturing method of the present invention, in the first step, a region between the source electrode and the drain electrode has a longitudinal shape in plan view, and the composite region has the source in plan view. It is preferable that the source electrode and the drain electrode are formed so as to form a substantially oval shape extending in the longitudinal direction of the region between the electrode and the drain electrode.
Thereby, when the planar view shape of the composite region is an ellipse, the organic semiconductor layer can be formed over a range that substantially coincides with the composite region in plan view more easily and reliably.

In the transistor manufacturing method of the present invention, in the first step, a region between the source electrode and the drain electrode has a longitudinal shape in plan view, and the composite region has a plurality of shapes in plan view. It is preferable that the source electrode and the drain electrode are formed so as to form a shape in which a substantially circular shape or a substantially oval shape is arranged and connected in the longitudinal direction of the region between the source electrode and the drain electrode.
As a result, even when the shape of the composite region in plan view is an elongated shape, the organic semiconductor layer can be seen in plan view more easily and reliably by dropping the liquid material into each substantially circular or substantially oval region. It can be formed over a range substantially coincident with the composite region.

In the method for manufacturing a transistor of the present invention, in the first step, the source electrode and the drain electrode have comb-shaped portions in plan view, and are engaged with each other with a gap therebetween. It is preferable to form a source electrode and the drain electrode.
Thereby, even when the area of the composite region is large, the organic semiconductor layer can be formed over a range substantially coincident with the composite region in a plan view more easily and reliably.

In the transistor manufacturing method of the present invention, in the second step, it is preferable to use an inkjet method as a method of dropping the liquid material.
As a result, a desired amount of the liquid material can be dropped at a desired position relatively easily and with high accuracy to obtain an organic semiconductor layer having a desired region and thickness.
In the transistor manufacturing method of the present invention, before or after the second step, the gate insulating layer defining layer that defines the formation region of the gate insulating layer is curved without substantially including a right-angled or acute corner. Forming a contour configured to include, and in a plan view, surrounding the composite region or its formation site with an interval, and
After the second step, a liquid material containing an organic insulating material or a precursor thereof is dropped into a region where the gate insulating layer defining layer and its inner region are combined, and substantially coincides with the region in plan view. It is preferable to have a step of forming the gate insulating layer by solidifying or hardening after wetting and spreading until it is done.
Thus, a transistor having excellent characteristics can be provided by forming the gate insulating layer with a desired region and thickness at a relatively simple and low cost.

In the method for manufacturing a transistor of the present invention, the step of forming the gate insulating layer defining layer is performed before the second step, and the gate insulating layer defining layer is formed in the first step. It is preferable to form together with the source electrode and the drain electrode.
Accordingly, it is possible to provide a transistor having excellent characteristics by forming a gate insulating layer with a desired region and thickness at a relatively simple and low cost while preventing the manufacturing process of the transistor from being complicated. .

An electronic device according to the present invention includes a transistor manufactured by the method for manufacturing a transistor of the present invention.
Thereby, an electronic device having excellent reliability can be provided.
An electronic apparatus according to the present invention includes the electronic device according to the present invention.
Thereby, an electronic device having excellent reliability can be provided.

DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, preferred embodiments of a transistor, a transistor manufacturing method, an electronic device, and an electronic apparatus according to the invention will be described with reference to the accompanying drawings.
<First Embodiment>
First, a first embodiment of the present invention will be described. An example in which the transistor of the present invention is applied to an active matrix device will be described below with reference to FIGS.
1 is a plan view showing an active matrix device including a transistor according to a first embodiment of the present invention, FIG. 2 is a sectional view taken along line XX in FIG. 1, and FIG. 3 is an active matrix device shown in FIG. It is a top view which shows the source electrode and drain electrode with which it was equipped. In the following description, the upper side in FIG. 2 is referred to as “upper” and the lower side is referred to as “lower”.

The active matrix device 130 shown in FIG. 1 has a plurality of data lines 131 orthogonal to each other, a plurality of scanning lines 132, and a transistor 1 provided near each intersection of the data lines 131 and the scanning lines 132. is doing. That is, the plurality of transistors 1 are arranged in a square lattice shape (matrix shape).
As shown in FIG. 2, each transistor 1 includes a source electrode 3 and a drain electrode 4, an organic semiconductor layer 5, a gate insulating layer 6, and a gate electrode 7.
In the present embodiment, among the plurality of transistors 1, the plurality of transistors 1 arranged in parallel in the left-right direction (row direction) in FIG. 1 have their gate electrodes 7 formed integrally with each other to form a scanning line 132. ing. One end of the scanning line 132 is connected to a connection electrode 133 provided on the substrate 50. The connection electrode 133 is a connection terminal for connecting to an external electrode.

The source electrode 3 included in each transistor 1 is connected to the data line 131, and the drain electrode 4 is connected to the pixel electrode (individual electrode) 141.
Each pixel electrode 141 is arranged in a matrix corresponding to each transistor 1.

Hereinafter, the configuration of the transistor 1 will be described in detail.
The transistor 1 is a top gate type transistor. In the transistor 1, the source electrode 3 and the drain electrode 4 are provided on the substrate 50 so as to be separated from each other, and the organic semiconductor layer 5 is provided so as to be in contact with the source electrode 3 and the drain electrode 4. A gate insulating layer 6 is provided so as to be in contact with the upper surface of the organic semiconductor layer 5 (the surface opposite to the substrate 50). Further, the source electrode 3 and the drain are formed on the upper surface of the gate insulating layer 6. A gate electrode 7 is provided so as to correspond to a region between the electrodes 4, and a protective film 8 is provided so as to cover the gate electrode 7 and the gate insulating layer 6.

In the transistor 1, a region between the source electrode 3 and the drain electrode 4 in the organic semiconductor layer 5 is a channel region 51 in which carriers move, and most carriers induced in the channel region 51. Moves along the interface between the organic semiconductor layer 5 and the gate insulating layer 6.
Hereinafter, in this channel region 51, the length in the carrier moving direction, that is, the distance between the source electrode 3 and the drain electrode 4 is the channel length L, and the length in the direction orthogonal to the channel length L direction is the channel width W. To tell.

The substrate 50 supports each layer (each part) constituting the transistor 1. As the substrate 50, for example, a glass substrate, a plastic substrate (resin substrate), a quartz substrate, a silicon substrate, a gallium arsenide substrate, or the like can be used. In the case where flexibility is given to the transistor 1, a resin substrate is selected as the substrate 50.
An underlayer may be provided on the substrate 50. The underlayer is provided, for example, for the purpose of preventing diffusion of ions from the surface of the substrate 50, or for improving the adhesion (bondability) between the source electrode 3 and drain electrode 4 and the substrate 50.
This underlayer can be made of, for example, silicon oxide (SiO ₂ ), silicon nitride (SiN), polyimide, polyamide, a polymer insolubilized by crosslinking, or the like.

As shown in FIG. 3, the source electrode 3 and the drain electrode 4 are arranged side by side on the substrate 50 so as to be separated from each other by a predetermined distance (channel length L). Hereinafter, a region between the source electrode 3 and the drain electrode 4 on the substrate 50 is referred to as a channel formation region 52, and a combined region of the channel formation region 52, the source electrode 3, and the drain electrode 4 in a plan view is combined. This is called region 2.
Each of the source electrode 3 and the drain electrode 4 is formed such that a part of the contour includes a curve. For this reason, the outline (outer peripheral edge) of the composite region 2 is configured to include a curved line without a substantially right angle and an acute corner (that is, a corner having an inner angle of 90 ° or less) (rounded). )

Here, in the transistor 1 of this embodiment, the organic semiconductor layer 5 described later is formed by dropping a liquid material containing an organic semiconductor material or a precursor thereof into the composite region 2 and curing or solidifying it. And formed over a range substantially coincident with the source / drain / channel region 2.
As described above, when the contour of the composite region 2 includes a curved line, the organic semiconductor layer 5 is formed in a desired range and thickness at a relatively simple and low cost in a manufacturing process described in detail later. be able to.

In the present embodiment, the outline (edge 23) of the composite region 2 does not have a right angle and an acute angle as described above, and a pair of curved (arc) portions 21 and 1 connecting them. It is composed of a pair of linear portions 22.
More specifically, each of the source electrode 3 and the drain electrode 4 has a semi-oval shape obtained by dividing an ellipse along its major axis in plan view, and is provided so as to face each other with a space therebetween. It has been. Thereby, the outline of the composite region 2 has a substantially oval shape in plan view. Further, the channel forming region 52 has a longitudinal shape, and the outline of the composite region 2 is substantially oval so as to extend in the longitudinal direction of the channel forming region 52.

Examples of the constituent material of the source electrode 3 and the drain electrode 4 include metal materials such as Pd, Pt, Au, W, Ta, Mo, Al, Cr, Ti, Cu, and alloys containing these, and channels. It is preferable to select appropriately according to the type of carrier moving in the region.
For example, in the case of a p-channel transistor in which holes move in the channel region as carriers, it is preferable to use Pd, Pt, Au, Ni, Cu or an alloy containing these metals having a relatively high work function.

Moreover, as each constituent material of the source electrode 3 and the drain electrode 4, in addition to the above metal materials, conductive materials such as ITO, FTO, ATO, SnO ₂ , carbon materials such as carbon black, carbon nanotubes, fullerenes, etc. , Polyacetylene, polypyrrole, polythiophene such as PEDOT (poly-ethylenedioxythiophene), polyaniline, poly (p-phenylene), poly (p-phenylenevinylene), polyfluorene, polycarbazole, polysilane or derivatives thereof A material etc. are mentioned, Among these, it can use combining 1 type (s) or 2 or more types.
The conductive polymer material is usually used in a state where it is doped with a polymer such as iron chloride, iodine, an inorganic acid, an organic acid, or polystyrene sulfonic acid, and imparted with conductivity.

The average thickness of the source electrode 3 and the drain electrode 4 is not particularly limited, but is preferably about 30 to 300 nm, and more preferably about 50 to 150 nm.
The distance (separation distance) between the source electrode 3 and the drain electrode 4, that is, the channel length L is preferably 100 μm or less, more preferably about 2 to 30 μm, and about 5 to 20 μm. Is more preferable. If the channel length L is smaller than the lower limit value, the channel length varies among the plurality of transistors 1, and the characteristics (transistor characteristics) may vary. On the other hand, when the channel length L is made larger than the upper limit value, the absolute value of the threshold voltage is increased, the drain current value is decreased, and the characteristics of the transistor 1 may be insufficient. In particular, when the channel length L is too large (specifically, greater than 100 μm), in the manufacturing process of the transistor 1 as described later, a liquid material containing an organic semiconductor material or a precursor thereof is added to the composite region 2. When dropped into the interior, depending on the type of dropped liquid material, the liquid material may flow out from both ends of the channel formation region 52 and the organic semiconductor layers 5 of the adjacent transistors 1 may be formed in contact with each other. When the organic semiconductor layers 5 of the adjacent transistors 1 are formed in contact with each other as described above, there is a risk of increasing the leakage current or inducing crosstalk between the elements.

  The channel width W is preferably about 0.1 to 5 mm, and more preferably about 0.5 to 3 mm. If the channel width W is made smaller than the lower limit value, the drain current value becomes small, and the characteristics of the transistor 1 may be insufficient. On the other hand, when the channel width W is larger than the upper limit value, the transistor 1 is increased in size, and there is a risk that parasitic capacitance increases and leakage current to the gate electrode 7 via the gate insulating layer 6 increases.

  In addition, an organic semiconductor layer 5 formed over a range substantially coincident with the region 2 is provided on the composite region 2. That is, a part of the contour of the organic semiconductor layer 5 includes a curve, and the curved part coincides with a part of the contour of the source electrode 3, for example. Thus, by providing the organic semiconductor layer 5 only in the composite region 2, interference between transistors and formation of a parasitic transistor can be prevented, and leakage current and off-current can be reduced.

The organic semiconductor layer 5 is composed mainly of an organic semiconductor material (an organic material that exhibits semiconducting electrical conduction).
As will be described later in detail, the organic semiconductor layer 5 is formed by dropping a liquid material containing an organic semiconductor material or a precursor thereof into the composite region 2 and solidifying or curing it.

In the present embodiment, as described above, the composite region 2 has a substantially oval shape. Thus, since the outline of the composite region 2 does not have corners, the liquid material dropped onto the composite region 2 does not overflow from the composite region 2 to the outside in the manufacturing process of the transistor 1 as described later. Surely spread to the edge of this area. Therefore, the organic semiconductor layer 5 having a planar shape substantially coinciding with the composite region 2 and having a thickness within a predetermined range is obtained. The transistor having such an organic semiconductor layer 5 has the predetermined planar shape and thickness of the organic semiconductor layer 5, so that the purpose and transistor characteristics can be reliably obtained. In addition, variation in characteristics can be prevented in each of the plurality of transistors 1, and the reliability of an electronic device (such as a display device described later) incorporating the transistor 1 can be improved.
The organic semiconductor layer 5 is preferably oriented so as to be substantially parallel to the channel length L direction at least in the channel region 51. As a result, the carrier mobility in the channel region 51 is high, and as a result, the transistor 1 has a higher operating speed.

  Examples of the organic semiconductor material include naphthalene, anthracene, tetracene, pentacene, hexacene, phthalocyanine, perylene, hydrazone, triphenylmethane, diphenylmethane, stilbene, arylvinyl, pyrazoline, triphenylamine, triarylamine, oligothiophene, phthalocyanine or Low molecular organic semiconductor materials such as these derivatives, poly-N-vinylcarbazole, polyvinylpyrene, polyvinylanthracene, polythiophene, polyalkylthiophene, polyhexylthiophene, poly (p-phenylene vinylene), polytinylene vinylene, Polyarylamine, pyrene formaldehyde resin, ethylcarbazole formaldehyde resin, fluorene-bithiophene copolymer, fluorene-ary Examples thereof include high molecular organic semiconductor materials (conjugated polymer materials) such as amine copolymers or derivatives thereof, and one or more of these can be used in combination. It is preferable to use a material mainly composed of a molecular organic semiconductor material (conjugated polymer material). The conjugated polymer material has a particularly high carrier mobility due to its unique electron cloud spread.

A polymer organic semiconductor material can be formed by a simple method and can be oriented relatively easily. Of these, fluorene-bithiophene copolymer, fluorene-arylamine copolymer are used as high-molecular organic semiconductor materials (conjugated polymer materials) because they are not easily oxidized in the air and are stable. It is particularly preferable to use a compound, a polyarylamine or a derivative containing at least one of these derivatives as a main component.
In addition, the organic semiconductor layer 5 composed mainly of a polymer organic semiconductor material can be reduced in thickness and weight, and is excellent in flexibility. Therefore, the transistor can be used as a switching element of a flexible display. Suitable for applications.

The average thickness of the organic semiconductor layer 5 is preferably about 1 to 200 nm, and more preferably about 10 to 100 nm.
A gate insulating layer 6 is provided on the organic semiconductor layer 5 so as to cover the source electrode 3, the drain electrode 4, and the organic semiconductor layer 5.
This gate insulating layer 6 insulates the gate electrode 7 from the source electrode 3 and the drain electrode 4.
The material of the gate insulating layer 6 is not particularly limited as long as it is a known gate insulator material, and either an organic material or an inorganic material can be used.

Examples of the organic material include polymethyl methacrylate, polyvinyl phenol, polyimide, polystyrene, polyvinyl alcohol, polyvinyl acetate, and the like, and one or more of these can be used in combination.
On the other hand, examples of the inorganic material include metal oxides such as silica, silicon nitride, aluminum oxide, and tantalum oxide, and metal composite oxides such as barium strontium titanate and lead zirconium titanate. A combination of more than one species can be used.

The thickness (average) of the gate insulating layer 6 is not particularly limited, but is preferably about 10 to 5000 nm, and more preferably about 50 to 1000 nm. By setting the thickness of the gate insulating layer 6 within the above range, the operating voltage of the transistor 1 can be lowered while reliably insulating the source electrode 3, the drain electrode 4, and the gate electrode 7.
Note that the gate insulating layer 6 is not limited to a single layer structure, and may have a multilayer structure.

A gate electrode 7 is provided on the gate insulating layer 6.
As the constituent material of the gate electrode 7, the same materials as those mentioned for the source electrode 3 and the drain electrode 4 can be used.
The average thickness of the gate electrode 7 is not particularly limited, but is preferably about 0.1 to 5000 nm, more preferably about 1 to 5000 nm, and still more preferably about 10 to 5000 nm.

The gate electrode 7 may be porous. Thereby, the gate electrode 7 has high air permeability. As a result, even if the transistor 1 is temporarily exposed to a high temperature and humidity environment, when the transistor 1 is returned to a low temperature and low humidity environment, oxygen and moisture that have entered the transistor 1 quickly enter the outside of the transistor 1. It will be discharged. Therefore, oxygen and moisture are prevented from being stored inside the transistor 1, and the characteristics can be preferably maintained.
Such a configuration can also be applied to the source electrode 3 and the drain electrode 4.

Further, a protective film 8 is provided on the gate insulating layer 6 so as to cover almost the entire surface thereof.
This protective film 8 mechanically protects each transistor 1 and, for example, when the active matrix device 130 is applied to an electrophoretic display device as described later, an electrophoretic dispersion liquid (parent material) enclosed in microcapsules. Even when oily liquid) flows out to the outside for some reason, it has a function of preventing diffusion to the transistor 1 side.
Examples of the constituent material of the protective film 8 include organic materials such as polyvinyl alcohol, ethylene-vinyl alcohol copolymer, vinyl chloride-vinyl alcohol copolymer and vinyl acetate-vinyl alcohol copolymer, SiO 2 An inorganic material such as ₂ can be used.
The average thickness of the protective film 8 is not particularly limited, but is preferably about 100 to 5000 nm, and more preferably 300 to 3000 nm. Thereby, the protective film 8 can fully exhibit its function.

In such a transistor 1, the amount of current flowing between the source electrode 3 and the drain electrode 4 is controlled by changing the voltage applied to the gate electrode 7.
That is, in the OFF state in which no voltage is applied to the gate electrode 7, even if a voltage is applied between the source electrode 3 and the drain electrode 4, almost no carriers are present in the organic semiconductor layer 5, so that a very small current Only flows. On the other hand, in the ON state in which a voltage is applied to the gate electrode 7, movable charges (carriers) are induced in the portion of the organic semiconductor layer 5 facing the gate insulating layer 6, and a flow path is formed in the channel region 51. When a voltage is applied between the source electrode 3 and the drain electrode 4 in this state, a current flows through the channel region 51.

Next, a method for manufacturing the transistor 1 of the first embodiment will be described with reference to FIGS.
4 to 11 are diagrams for explaining a method of manufacturing the active matrix device shown in FIGS. 1 and 2 (a method of manufacturing each transistor). FIG. 12 shows the outline of the composite region as a reference example. It is a figure for demonstrating the wet spreading state of the liquid material in the case of having a right-angle corner | angular part. 4 to 12, FIGS. 5 (a), 7, 9 (b), and 12 are plan views, and the other drawings are longitudinal sectional views. In the following description, the upper side is referred to as “upper” and the lower side is referred to as “lower” in FIGS.
The manufacturing method of the active matrix device 130 (each transistor 1) includes [1] electrode (excluding gate electrode) and wiring formation process (first process), and [2] organic semiconductor layer formation process (second process). And [3] a gate insulating layer forming step, [4] a gate electrode forming step, and [5] a protective film forming step. Hereinafter, each of these steps will be described sequentially.

[1] Electrode and wiring formation process (first process)
A substrate 50 is prepared as shown in FIG. Then, the source electrode 3 and the drain electrode 4 are formed on the substrate 50 as shown in FIG. At this time, together with the source electrode 3 and the drain electrode 4, the pixel electrode 141, the data line 131, and the connection electrode 133 are also formed. Hereinafter, the source electrode 3, the drain electrode 4, the pixel electrode 141, the data line 131, and the connection electrode 133 are also referred to as “source electrode 3 and drain electrode 4”.

In this manufacturing method, the source electrode 3 and the drain electrode 4 are formed in the shape as described above, that is, the outline of the composite region 2 is mainly composed of a curve without substantially including an acute angle or a right angle corner. To form. Thereby, in process [2] mentioned below, a liquid material can be spread and spread over the range which substantially corresponds with compound field 2. Therefore, the organic semiconductor layer 5 having a desired range and thickness can be formed simply by defining the amount of the liquid material to be dropped in the step [2] to be described later.
For example, when the source electrode 3 and the drain electrode 4 are made of metal as a main material, when forming the source electrode 3 and the drain electrode 4 as described above, first, a metal film ( Metal layer).

This metal film can be formed by, for example, chemical vapor deposition (CVD) such as plasma CVD, thermal CVD, laser CVD, vacuum deposition, sputtering (low temperature sputtering), dry plating methods such as ion plating, electrolytic plating, immersion plating, It can be formed by wet plating methods such as electrolytic plating, thermal spraying methods, sol-gel methods, MOD methods, metal foil bonding, and the like.
On this metal film, a resist layer having a shape corresponding to the shape of the source electrode 3 and the drain electrode 4 is formed by photolithography. Using this resist layer as a mask, unnecessary portions of the metal film are removed.

For the removal of the metal film, for example, one or more of physical etching methods such as plasma etching, reactive ion etching, beam etching, and optical assist etching, and chemical etching methods such as wet etching are used. They can be used in combination.
Thereafter, by removing the resist layer, the source electrode 3 and the drain electrode 4 are obtained as shown in FIG.

  For example, the source electrode 3 and the drain electrode 4 are made of a liquid material such as a colloid liquid (dispersion) containing conductive particles or a liquid (solution or dispersion) containing a conductive polymer on the substrate 50. After forming the film by supplying to the film, the film can be formed by subjecting the film to post-treatment (for example, heating, irradiation with infrared rays, application of ultrasonic waves, etc.) as necessary.

In addition, it is preferable that the source electrode 3 and the drain electrode 4 are subjected to post-treatment before the next step [2].
For example, when the source electrode 3 and the drain electrode 4 are made of a metal material as a main material, it is preferable to perform plasma treatment (for example, argon plasma treatment or oxygen plasma treatment). Thereby, organic substances adhering to the surfaces of the source electrode 3 and the drain electrode 4 can be removed, and as a result, the characteristics of the obtained transistor 1 can be further improved. In addition, in the step [2] to be described later, the unintended behavior of the dropped liquid material can be suppressed.

  In particular, when the source electrode 3 and the drain electrode 4 are made of Ni and Cu as main materials, it is preferable to perform oxygen plasma treatment. As a result, organic substances adhering to the surface of the source electrode 3 and the drain electrode 4 can be removed, the vicinity of the surface can be oxidized, and the work function can be increased. As a result, when the p-channel transistor 1 is constructed, the characteristics are particularly excellent.

[2] Organic semiconductor layer forming step (second step)
Next, the organic semiconductor layer 5 is formed on the composite region 2 over a range that substantially matches the region 2 (that is, at a position and shape that substantially match in plan view).
As shown in FIGS. 6 and 7, the organic semiconductor layer 5 has a film formed by dropping a liquid material 9 containing an organic semiconductor material or a precursor thereof into the composite region 2 and spreading it. Thereafter, the film is formed by subjecting this film to post-treatment (for example, heating, irradiation with infrared rays, application of ultrasonic waves, etc.) to solidify or cure as necessary.
More specifically, when the liquid material 9 is dropped into the composite region 2, the dropped liquid material 9 spreads in a substantially concentric manner starting from the dropping position (center position).

  As shown in FIG. 8A, the liquid material 9 has a forward wetting angle θ on the upper surface of the source electrode 3 and the drain electrode 4 while the vicinity of the contact line A, which is the outer periphery of the liquid material 9, is maintained. It proceeds toward the edge of each electrode 3, 4. Then, as shown in FIG. 8B, when the contact line A reaches the edges of the source electrode 3 and the drain electrode 4 which are the boundary portions of the unevenness, the edges of the electrodes 3 and 4 are affected by the action of surface tension. When the contact line A swells until the angle θ ′ formed between the imaginary line B passing through the portion and extending in a direction perpendicular to the surfaces of the electrodes 3 and 4 and the contact line A becomes substantially equal to the wetting angle θ Stops.

  In this way, the liquid material 9 dropped into the composite region 2 does not overflow from the edge 23 of the composite region 2 due to the action of the surface tension generated at the uneven boundary, and reaches the edge 23 of this region 2. Wetting and spreading form a film as shown in FIG. Then, post-treatment (for example, heating, infrared irradiation, application of ultrasonic waves, etc.) is performed on this film as necessary, so that it substantially matches the composite region 2 as shown in FIG. The organic semiconductor layer 5 formed over the range is obtained. Thus, since the organic semiconductor layer 5 can be formed only in a desired region, the thickness of the obtained organic semiconductor layer 5 can be set to a desired one only by defining the amount and concentration of the liquid material to be dropped. can do. In addition, by equalizing the amount and concentration of the liquid material to be dropped between the transistors 1, the thickness distribution of the organic semiconductor layer 5 can be made uniform between the transistors 1.

Here, as described above, the contour of the composite region 2 is mainly composed of a curved line (curved curve that is convex toward the outside of the region 2), so that the liquid material 9 extends over the entire circumference of the composite region 2. Can be distributed to the edge 23.
In particular, in the present embodiment, the source electrode 3 and the drain electrode 4 are formed so that the composite region 2 has a substantially oval shape in plan view. The variation in the distance to the edge can be reduced. Therefore, the dropped liquid material 9 spreads over substantially the entire circumference of the contour of the composite region 2 when it spreads concentrically from the dropping position. Therefore, the organic semiconductor layer 5 can be formed over a range substantially coincident with the composite region 2 in plan view more reliably and easily.

  Furthermore, in the present embodiment, the source electrode 3 and the drain electrode 4 are formed so that the composite region 2 has a substantially oval shape extending in the longitudinal direction of the channel formation region 52 in plan view. Even if the shape of the region 2 in plan view is an oval shape, the organic semiconductor layer 5 can be formed over a range that substantially coincides with the composite region 2 in plan view more easily and reliably. This is because the dropped liquid material 9 tends to spread in the longitudinal direction of the channel forming region 52.

  On the other hand, as shown in FIG. 12A, if the composite region 2 has a corner, the contact line A of the liquid material 9 that proceeds toward the corner is before the corner reaches the corner. In addition, since the vicinity of the contact line first reaches the edge 23 of the source electrode 3 and the drain electrode 4 and the progress is stopped by the action of the surface tension, the progress is stopped so as to be dragged by this. For this reason, a phenomenon that the liquid material does not spread to the corners occurs. The vicinity of the contact line A stopped before this corner is likely to be different in thickness from the other parts, and the organic semiconductor layer 5 is formed with a part having a thickness outside the desired range. It becomes. The thickness of the organic semiconductor layer 5 affects transistor characteristics such as the on-current, off-current, and threshold value Vth of the transistor 1. Therefore, if the organic semiconductor layer 5 has a portion having a thickness outside the desired range, the target transistor characteristics cannot be obtained, and the transistor characteristics vary among the plurality of transistors 1. As a result, it is difficult to perform sufficient gradation display particularly when the active matrix device 130 is used as a display apparatus that performs gradation display.

  In addition, it is conceivable that the amount of the liquid material 9 to be dropped is increased to spread the liquid material 9 to the corners. However, in this case, the liquid material 9 covers the edges at the edges other than the corners of the composite region 2. It overflows beyond. As a result, the organic semiconductor layer 5 is formed in contact with the electrode of the adjacent transistor 1, which may increase the leakage current or induce crosstalk between the elements.

  In the present embodiment, the curvature radius of the curved portion 21 in the composite region 2 is preferably 10 to 100 μm, and more preferably 50 to 80 μm. By setting the curvature radius in such a range, the liquid material 9 is dropped in an appropriate amount (0.1 to 40 pL / 1 drop, more preferably 1 to 30 pL / 1 drop), and the edge of the composite region 2 When wetting and spreading to (curved portion 21), the radius of curvature of the liquid material 9 that has spread out and the radius of curvature of the curved portion 21 of the composite region 2 can be made substantially coincident. Thereby, the state of the liquid material in the vicinity of the edge 23 becomes stable, and the organic semiconductor layer 5 is formed with a more uniform thickness. As a result, excellent transistor characteristics can be obtained in the manufactured transistor 1. In addition, variations in characteristics can be reliably prevented in each manufactured transistor 1, and the reliability of an electronic device (such as a display device described later) incorporating the transistor 1 can be improved. .

As a method of dropping the liquid material 9, it is preferable to use an ink jet method (droplet discharge method). According to the ink jet method, a predetermined amount of droplets can be easily and accurately dropped.
In the ink jet method, a liquid material 9 containing an organic semiconductor material or a precursor thereof is discharged as fine droplets from a nozzle of a droplet discharge head. In particular, when a plurality (many) of transistors 1 are formed, a plurality of (many) droplets of the liquid material 9 are ejected from the nozzles of the droplet discharge head onto the substrate 50 corresponding to each composite region 2 and patterned. .
Here, as the liquid material 9, a material obtained by dissolving the organic semiconductor material or a precursor thereof as described above in a solvent or dispersing in a dispersion medium can be used.

  The solvent or dispersion medium is determined according to the type of organic semiconductive material used and the dropping conditions, and is not particularly limited. For example, nitric acid, sulfuric acid, ammonia, hydrogen peroxide, water, carbon disulfide, four Inorganic solvents such as carbon chloride and ethylene carbonate, ketone solvents such as methyl ethyl ketone (MEK), acetone, diethyl ketone, methyl isobutyl ketone (MIBK), methyl isopropyl ketone (MIPK), cyclohexanone, methanol, ethanol, isopropanol, ethylene glycol , Alcohol solvents such as diethylene glycol (DEG) and glycerin, diethyl ether, diisopropyl ether, 1,2-dimethoxyethane (DME), 1,4-dioxane, tetrahydrofuran (THF), tetrahydropyran (THP), aniso , Ether solvents such as diethylene glycol dimethyl ether (diglyme), diethylene glycol ethyl ether (carbitol), cellosolv solvents such as methyl cellosolve, ethyl cellosolve, phenyl cellosolve, aliphatic hydrocarbon solvents such as hexane, pentane, heptane, cyclohexane, Aromatic hydrocarbon solvents such as toluene, xylene and benzene, aromatic heterocyclic solvents such as pyridine, pyrazine, furan, pyrrole, thiophene and methylpyrrolidone, N, N-dimethylformamide (DMF), N, N- Amide solvents such as dimethylacetamide (DMA), halogen compound solvents such as dichloromethane, chloroform and 1,2-dichloroethane, ester solvents such as ethyl acetate, methyl acetate and ethyl formate, dimethylsulfoxy (DMSO), sulfur compound solvents such as sulfolane, nitrile solvents such as acetonitrile, propionitrile, acrylonitrile, various organic solvents such as organic acid solvents such as formic acid, acetic acid, trichloroacetic acid, trifluoroacetic acid, or Examples thereof include mixed solvents containing these.

The viscosity (normal temperature) of the liquid material 9 is not particularly limited, but is usually preferably about 2 to 20 cps, more preferably about 4 to 8 cps. By setting the viscosity of the liquid material 9 in such a range, it is possible to more stably discharge droplets from the nozzle. When the viscosity of the liquid material 9 is smaller than the above range, the vibration of the piezo element that is displaced at the time of discharge is difficult to attenuate, so that the discharge tends to become unstable. In addition, when the viscosity of the liquid material 9 is larger than the above range, the flow resistance of the liquid material 9 is large, so when printing at high speed, the supply of the liquid material 9 may not catch up and may become unstable. .
The viscosity of the liquid material 9 can be adjusted, for example, by appropriately setting the concentration of the organic semiconductor material or its precursor, the type or composition of the solvent or dispersion medium, and the like.

Further, the particle size (average) of one drop of the liquid material 9 is determined according to the shape and area of the composite region 2 and is not particularly limited, but it is usually preferably about 0.1 to 40 pL. More preferably, it is about 30 pL. Further, by setting the amount (average) of one droplet of the liquid material 9 within such a range, a more precise shape can be formed. If the volume of the droplet is too small, depending on the type of the liquid material 9 and the like, it becomes difficult to wet and spread the dropped liquid material 9 or to stably discharge the liquid material 9 from the nozzle. If the volume of the droplet is too large, depending on the area and shape of the composite region 2, it becomes difficult to drop the liquid material 9 so as to fit in the composite region 2.
The number of droplets may be one or a plurality of droplets.
The static contact angle (θ shown in FIG. 8) of the liquid material 9 with respect to the source electrode 3 or the drain electrode 4 immediately after dropping the liquid material 9 on the substrate 50 is preferably 20 to 50 °, and preferably 25 to 45 °. It is more preferable that

[3] Gate Insulating Layer Formation Step Next, as shown in FIG. 10B, the gate insulating layer 6 is formed so as to cover the organic semiconductor layer 5.
For example, when the gate insulating layer 6 is composed of an organic insulating material, the gate insulating layer 6 is applied (supplied) so as to cover the organic semiconductor layer 5 with a solution containing the organic insulating material or its precursor, and then necessary. Accordingly, it can be formed by subjecting this coating film to post-treatment (for example, heating, infrared irradiation, application of ultrasonic waves, etc.).

As a method for applying (supplying) a solution containing an organic insulator material or a precursor thereof onto the organic semiconductor layer 5, the application method, the printing method, and the like mentioned in the above-mentioned step [1] can be used.
When the gate insulating layer 6 is made of an inorganic material, the gate insulating layer 6 can be formed by, for example, a thermal oxidation method, a CVD method, an SOG method, or the like. Further, by using polysilazane as a raw material, a silica film and a silicon nitride film can be formed as a gate insulating layer 6 by a wet process.

[4] Scanning Line (Gate Electrode) Formation Step Next, as shown in FIG. 11A, the scanning line 132 (gate electrode 7) is formed on the gate insulating layer 6.
The scanning line 132 can be formed using a method similar to the above-described step [1].
[5] Protective Film Formation Step Next, as shown in FIG. 11B, the protective film 8 is formed so as to cover almost the entire surface of the gate insulating layer 6.
The protective film 8 can be formed using a method similar to the above-described step [3].

Through the steps as described above, the active matrix device 130 (transistor 1) shown in FIGS. 1 and 2 is obtained.
According to the manufacturing method of the transistor 1 as described above, the process [1] (first process) and the process [2] (second process) as described above are included. The transistor 1 having excellent characteristics can be obtained by forming the organic semiconductor layer 5 in a desired region and thickness easily and at low cost. In particular, when a plurality of transistors 1 are provided on the same substrate 50 as in this embodiment, variation in characteristics among the transistors 1 can be suppressed.

<Second Embodiment>
Next, a second embodiment of the present invention will be described.
FIG. 13 is a longitudinal sectional view showing a transistor according to the second embodiment of the present invention. In the following description, the upper side in FIG. 13 is referred to as “upper” and the lower side is referred to as “lower”.
Hereinafter, although the transistor of 2nd Embodiment is demonstrated, it demonstrates centering around difference with the transistor of 1st Embodiment mentioned above, The description is abbreviate | omitted about the same matter.
The transistor 1A of the second embodiment is the same as the transistor 1 of the first embodiment described above except that the stacking order of each part constituting the transistor is different.

A transistor 1A shown in FIG. 13 includes a gate electrode 7, a gate insulating layer 6, a source electrode 3 and a drain electrode 4, an organic semiconductor layer 5, and a protective film 8 stacked in this order from the substrate 50 side. It is configured.
That is, the transistor 1A is a transistor having a configuration in which the gate electrode 7 is provided on the substrate 50 side of the source electrode 3 and the drain electrode 4, that is, a bottom-gate transistor.

  Specifically, in the transistor 1A, the gate electrode 7 is provided on the substrate 50, and the gate insulating layer 6 is provided so as to cover the gate electrode 7. A source electrode 3 and a drain electrode 4 are provided on the gate insulating layer 6 so as to be separated from each other via a gate electrode 7 in plan view. An organic semiconductor layer 5 is provided on the composite region 2 in which the region between the source electrode 3 and the drain electrode and the source electrode 3 and the drain electrode 4 are combined. Further, a protective film 8 is provided so as to cover the organic semiconductor layer 5 and the gate insulating layer 6.

In the present embodiment, as in the first embodiment described above, the source electrode 3 and the drain electrode 4 have a semi-oval shape obtained by dividing an ellipse along the major axis in plan view, and are spaced from each other. It is provided so as to face each other. As a result, the outline of the composite region 2 has an approximately oval shape in plan view.
Although not shown, the organic semiconductor layer is formed on the composite region 2 over a range substantially coincident with the region 2.

Such a transistor 1A includes a [4] gate electrode forming step, [3] gate insulating layer forming step, [1] electrode and wiring forming step, and [2] organic in the method for manufacturing the transistor 1 of the first embodiment described above. The semiconductor layer forming step and [5] protective film forming step can be sequentially performed in this order.
Even in the transistor 1A according to the second embodiment, the same operation and effect as those of the first embodiment described above can be obtained. That is, the present invention can be applied to a top-gate transistor or a bottom-gate transistor.

<Third Embodiment>
Next, a third embodiment of the present invention will be described.
FIG. 14 is a plan view showing a source electrode and a drain electrode provided in the transistor of the third embodiment.
Hereinafter, although the transistor of 3rd Embodiment is demonstrated, it demonstrates centering around difference with the transistor of 1st Embodiment mentioned above, The description is abbreviate | omitted about the same matter.
The transistor of the third embodiment is the same as the transistor 1 of the first embodiment described above except that the source electrode 3, the drain electrode 4, and the organic semiconductor layer 5 are different from each other in plan view.

  As shown in FIG. 14, each of the source electrode 3 and the drain electrode 4 provided in the transistor of this embodiment has a shape in which a corner of one long side of a rectangle is rounded. Other long sides facing the long side are provided so as to face each other with a space therebetween. Thereby, the outline of the source / drain / channel region 2 has a shape in which four corners of a rectangle are rounded in a plan view.

Although not shown, the organic semiconductor layer is formed on the composite region 2 over a range substantially coincident with the region 2.
Such a transistor can be manufactured in the same manner as the transistor of the first embodiment described above.
Even in the transistor according to the third embodiment, the same operation and effect as those of the transistor 1 according to the first embodiment described above can be obtained.

<Fourth embodiment>
Next, a fourth embodiment of the present invention will be described.
FIG. 15 is a plan view showing a source electrode and a drain electrode provided in the transistor of the fourth embodiment of the present invention.
Hereinafter, although the transistor of 4th Embodiment is demonstrated, it demonstrates centering around difference with the transistor of 1st Embodiment mentioned above, The description is abbreviate | omitted about the same matter.
The transistor of the fourth embodiment is the same as the transistor 1 of the first embodiment described above, except that the planar shapes of the source electrode 3, the drain electrode 4, and the organic semiconductor layer 5 are different.

As shown in FIG. 15, the source electrode 3 and the drain electrode 4 provided in the transistor of the present embodiment have a semi-elliptical shape obtained by dividing the ellipse along the major axis in plan view, and are spaced apart from each other. It is provided so as to face each other. Thereby, the outline of the source / drain / channel region 2 is substantially elliptical (substantially oval).
Although not shown, the organic semiconductor layer is formed on the composite region 2 over a range substantially coincident with the region 2.
Such a transistor can be manufactured in the same manner as the transistor of the first embodiment described above.
Even in the transistor according to the fourth embodiment, the same operation and effect as those of the transistor 1 according to the first embodiment described above can be obtained.

<Fifth Embodiment>
Next, a fifth embodiment of the present invention will be described.
FIG. 16 is a plan view showing a source electrode and a drain electrode provided in the transistor of the fifth embodiment of the present invention.
Hereinafter, although the transistor of 5th Embodiment is demonstrated, it demonstrates centering around difference with the transistor 1 of 1st Embodiment mentioned above, The description is abbreviate | omitted about the same matter.
The transistor of the fifth embodiment is the same as the transistor 1 of the first embodiment described above except that the source electrode 3, the drain electrode 4, and the organic semiconductor layer have different planar shapes.

As shown in FIG. 16, each of the source electrode 3 and the drain electrode 4 provided in the transistor of this embodiment has a substantially semicircular shape obtained by dividing a circle along its diameter, and the linear portions are spaced from each other. So as to face each other. Thereby, the outline of the source / drain / channel region 2 has a substantially circular shape in plan view.
Although not shown, the organic semiconductor layer is formed on the composite region 2 over a range substantially coincident with the region 2.
Such a transistor can be manufactured in the same manner as the transistor of the first embodiment described above.

Even in the transistor of the fifth embodiment, the same operation and effect as the transistor 1 of the first embodiment described above can be obtained.
In particular, in this embodiment, since the outline of the composite region 2 is substantially circular in a plan view, when the liquid material is dropped into the composite region 2 when the transistor is manufactured, the dropped liquid The outer peripheral edge (contact line) of the material spreads concentrically and reaches the edge of the region 2 almost simultaneously over the entire circumference.

<Sixth Embodiment>
Next, a sixth embodiment of the present invention will be described.
FIG. 17 is a plan view showing a source electrode and a drain electrode provided in the transistor according to the sixth embodiment of the present invention.
Hereinafter, although the transistor of 6th Embodiment is demonstrated, it demonstrates centering around difference with the transistor 1 of 1st Embodiment mentioned above, The description is abbreviate | omitted about the same matter.
The transistor of the sixth embodiment is the same as the transistor 1 of the first embodiment described above, except that the planar shape of the source electrode 3, the drain electrode 4, and the organic semiconductor layer is different.

As shown in FIG. 17, the source electrode 3 and the drain electrode 4 provided in the transistor of the present embodiment have three semicircles in the same posture with each straight line portion on the same line as shown in FIG. 17. It is shaped so as to be connected side by side in the direction, and is provided so that the straight portions of each other face each other with an interval. Thus, the outline of the source / drain / channel region 2 has a shape in which three circles are arranged in one direction and connected. That is, the composite region 2 has a shape in which a plurality of substantially circular shapes are arranged and connected in the longitudinal direction of the channel forming region 52 in plan view.
Although not shown, the organic semiconductor layer is formed on the composite region 2 over a range substantially coincident with the region 2.

Such a transistor can be manufactured in the same manner as the transistor of the first embodiment described above, but it is preferable to drop the liquid material for each of the substantially circular regions of the composite region 2. Thereby, even if the planar view shape of the composite region 2 is an elongated shape, the liquid material can be spread over the entire region of the composite region 2 without being excessive or insufficient. Therefore, the organic semiconductor layer can be formed over a range substantially coincident with the composite region 2 in plan view more easily and reliably.
Even in the transistor of the sixth embodiment, the same operation and effect as the transistor 1 of the first embodiment described above can be obtained.

<Seventh embodiment>
Next, a seventh embodiment of the present invention will be described.
18 is a schematic diagram illustrating a transistor according to a seventh embodiment of the present invention. FIG. 19 is a schematic diagram illustrating a source electrode, a drain electrode, and a gate insulating layer defining layer included in the transistor illustrated in FIG. FIG. 21 and FIG. 21 are diagrams for explaining a method of manufacturing the transistor shown in FIG. 18 to 21, (a) is a plan view and (b) is a cross-sectional view taken along line YY of (a).
Hereinafter, the transistor of the seventh embodiment will be described, but the description will focus on the differences from the transistor 1 of the first embodiment described above, and description of similar matters will be omitted.

In the transistor of the seventh embodiment, the source electrode 3, the drain electrode 4, the organic semiconductor layer 5, and the gate insulating layer 6 are different from each other in plan view, and the gate insulating layer defining that defines the region where the gate insulating layer 6 is formed. Except for providing the layer 11 on the substrate 50, it is the same as the active matrix device 130 of the first embodiment described above.
In the transistor of this embodiment, as shown in FIG. 19, a source electrode 3, a drain electrode 4, and a gate insulating layer defining layer 11 are provided on a substrate 50.

The drain electrode 4 is composed of a plurality of linear portions 42 extending radially. That is, the drain electrode 4 has a substantially comb-like shape in which a plurality of linear portions 42 are arranged in parallel in the circumferential direction at intervals. A wiring 13 extending in the radial direction is connected to such a drain electrode 4.
On the other hand, the source electrode 3 is formed to surround the outer peripheral edge of the drain electrode 4 as described above with a substantially constant interval. That is, the source electrode 3 is provided so as to mesh with the drain electrode 4 having a substantially comb-like shape as described above at an interval. Such a source electrode 3 includes an annular part 32 having a shape in which a part of the annular part is missing in the circumferential direction, and an inner part extending from the annular part 32 and spaced apart from each other in the circumferential direction. And a plurality of wedge-shaped portions 33 arranged side by side. A wiring 12 extending in the radial direction is connected to such a source electrode.
In such a source electrode 3 and drain electrode 4, the outline of the source / drain / channel region 2 is substantially circular in plan view.

The gate insulating layer defining layer 11 defines a formation region of the gate insulating layer 6 formed in the process [3A] described later. Such a gate insulating layer defining layer 11 is formed such that a portion of the annular ring surrounding the outer periphery of the source electrode 3 with a space therebetween is missing. In other words, the gate insulating layer defining layer 11 has a contour configured to include a curve without substantially including a right-angled or acute corner, and surrounds the composite region 2 with a space in plan view. It is formed as follows.
The contour of such a region (hereinafter referred to as “gate insulating layer forming region 14”) that is a combination of the gate insulating layer defining layer 11 and the region inside the gate insulating layer defining layer 11 is the contour of the composite region 2. It is almost circular shape that is one size larger than.
The constituent material of the gate insulating layer defining layer 11 is not particularly limited, but it is preferable to use the same material as that of the source electrode 3 and the drain electrode 4. Thereby, the gate insulating layer defining layer 11 can be formed simultaneously with each electrode and data line in the electrode and wiring forming step, and the gate insulating layer defining layer 11 can be formed without complicating the manufacturing process. .

The organic semiconductor layer 5 is formed on the composite region 2 over a range substantially coincident with the region 2.
The gate insulating layer 6 is formed on the gate insulating layer forming region 14 over a range substantially coincident with the region 14 and is disposed so as to cover the organic semiconductor layer 5.

Further, as shown in FIG. 18, the gate electrode 7 is provided on the gate insulating layer 6 so as to overlap the channel formation region 52.
The transistor of this embodiment is the same as that of the transistor manufacturing method of the first embodiment described above except that the steps [1] and [3] are changed to the following [1A] and [3A]. The transistor can be manufactured in the same manner as the transistor manufacturing method in the first embodiment.

[1A] Electrode and wiring and gate insulating layer defining layer forming step A substrate 50 is prepared, and on this substrate 50, the source electrode 3, the drain electrode 4, the pixel electrode 141, the data line 131, the connection electrode 133, and the gate insulation The layer defining layer 11 is formed. As a method for forming each of these parts, the same method as in step [1] in the first embodiment described above can be used.

[3A] Gate Insulating Layer Formation Step Next, as shown in FIG. 21, the gate insulating layer 6 is formed so as to cover the organic semiconductor layer 5.
The gate insulating layer 6 can be formed using a method similar to the method for forming the organic semiconductor layer 5 described above.
That is, the gate insulating layer 6 forms a film by dropping droplets of a liquid material containing an organic polymer material or a precursor thereof into the gate insulating layer forming region 14 and spreading it, and then as necessary. The film can be formed by post-treatment (for example, heating, infrared irradiation, application of ultrasonic waves, etc.).

By forming the gate insulating layer 6 in this manner, the obtained gate insulating layer 6 is formed over a range substantially coincident with the gate insulating layer forming region 14. That is, the gate insulating layer 6 can be formed in a desired region and thickness only by defining the amount of liquid material to be dropped.
Even in the transistor of the seventh embodiment, the same operation and effect as those of the transistor 1 of the first embodiment described above can be obtained.

  In particular, in the present embodiment, the source electrode 3 and the drain electrode 4 have comb-shaped portions in plan view, and are formed so as to mesh with each other with a gap therebetween, so that the organic semiconductor layer is formed. In this case, even when the area of the composite region 2 is large or a liquid material that does not easily spread out is used, the dropped liquid material can be spread over the entire composite region 2 without excess or deficiency. Therefore, the organic semiconductor layer can be formed over a range substantially coincident with the composite region 2 in plan view more easily and reliably. This is because the dropped liquid material easily spreads along the channel forming region 52.

In addition, since the transistor manufacturing method of this embodiment includes the steps [1A] and [3A] as described above, the gate insulating layer 6 can be formed in a desired region and thickness relatively easily and at low cost. Thus, a transistor having excellent characteristics can be provided.
Further, the step of forming the gate insulating layer defining layer 11 is performed before the step [2] which is the second step, and the gate insulating layer defining layer is performed in the step [1A] which is the first step. 11 is formed together with the source electrode 3 and the drain electrode 4, so that the manufacturing process of the transistor 1 is prevented from being complicated, and the gate insulating layer 6 is formed in a desired region and thickness relatively easily and at low cost. Thus, a transistor having excellent characteristics can be provided.
The formation of the gate insulating layer defining layer 11 can be performed in a step separate from the step [1A] as the first step, and the step [2] as the second step. It can also be done later.

<Eighth Embodiment>
Next, an eighth embodiment of the present invention will be described.
FIG. 22 is a plan view showing a transistor according to the eighth embodiment of the present invention, and FIG. 23 is a plan view showing electrodes and wirings provided in the transistor shown in FIG.
Hereinafter, the transistor of the eighth embodiment will be described, but the description will focus on differences from the transistor 1 of the first embodiment described above, and description of similar matters will be omitted.
The transistor of the eighth embodiment is the same as the transistor of the first embodiment described above, except that the planar shape of the source electrode 3, the drain electrode 4, and the organic semiconductor layer 5 is different.

As shown in FIG. 24, the source electrode 3 and the drain electrode 4 provided in the transistor of the present embodiment have comb-shaped portions, and are provided so as to mesh with each other.
More specifically, the source electrode 3 includes a base portion 3b extending in an arc shape and a plurality of electrode fingers 3a extending from the inside of the base portion 3b and arranged in parallel at intervals to form a comb shape. And have. Here, the plurality of electrode fingers 3a are set to such a length that the ends of the electrode fingers 3a opposite to the base 3b are on the same straight line.

The drain electrode 4 has a semi-oval base 4b having an arc substantially equal to the arc of the base 3b of the source electrode 3, and extends from the side opposite to the arc of the base 4b, and is spaced from each other so as to form a comb-teeth shape. And a plurality of electrode fingers 4a arranged side by side.
The source electrode 3 and the drain electrode 4 are provided so that the electrode fingers 3a and 4a are alternately arranged and mesh with each other.

In such a source electrode 3 and drain electrode 4, the outline of the composite region 2 has a substantially oval shape in plan view.
The organic semiconductor layer 5 is formed on the composite region 2 over a range substantially coincident with the region 2.
As shown in FIG. 23, the gate electrode 7 (scanning line 132) is provided so as to overlap with a region where the source electrode 3 and the drain electrode 4 are engaged, that is, a region where the electrode fingers 3a and 4a are alternately arranged. ing. Note that although a gate insulating layer is not illustrated in FIG. 23, the gate electrode 7 (scanning line 132) is provided over the gate insulating layer.

Such a transistor can be manufactured in the same manner as the transistor of the first embodiment described above.
Even in the transistor according to the third embodiment, the same operation and effect as those of the transistor 1 according to the first embodiment described above can be obtained.
In particular, in the present embodiment, the source electrode 3 and the drain electrode 4 have comb-shaped portions in plan view, and are formed so as to mesh with each other with a gap therebetween, so that the organic semiconductor layer is formed. In this case, even when the area of the composite region 2 is large or a liquid material that does not easily spread out is used, the dropped liquid material can be spread over the entire composite region 2 without excess or deficiency. Therefore, the organic semiconductor layer can be formed over a range substantially coincident with the composite region 2 in plan view more easily and reliably. This is because the dropped liquid material easily spreads along the channel forming region 52.

  Here, in the transistor 1 of this embodiment, the size of the portion where the source electrode 3 and the drain electrode 4 overlap the gate electrode 7 is determined by the width of the electrode fingers 3a and 4a. Can be formed using a resist layer formed by photolithography as a mask. In this case, the width of the electrode fingers 3a and 4a depends on the accuracy of the photolithography method, but can be narrowed because the accuracy of the photolithography method is extremely high.

For this reason, even when the width of the gate electrode 7 (scanning line 132) is formed relatively large, it is possible to prevent the area of the portion where the gate electrode 7 overlaps with the source electrode 3 and the drain electrode 4 from increasing. it can. Thereby, in the transistor 1, the capacity | capacitance of a gate can be restrained small, As a result, a favorable characteristic (switching characteristic) is exhibited.
Therefore, in this embodiment, since it is not required to form the gate electrode 7 in a fine shape, the range of selection of the formation method is widened, and even when various coating methods are used for forming the gate electrode 7, it is satisfactory. A transistor 1 having excellent characteristics can be obtained.

<Ninth Embodiment>
Next, a ninth embodiment of the present invention will be described.
FIG. 24 is a plan view showing an example in which the transistor according to the ninth embodiment of the present invention is applied to an inverter circuit.
Hereinafter, the transistor of the ninth embodiment will be described, but the description will focus on differences from the transistors of the first embodiment and the second embodiment described above, and description of similar matters will be omitted.

The inverter circuit 10 illustrated in FIG. 24 includes a p-type transistor 1A1 that constitutes a p-channel transistor and an n-type transistor 1A2 that constitutes an n-channel transistor.
The configurations of the p-type transistor 1A1 and the n-type transistor 1A2 are the same as those of the transistor 1A in the second embodiment described above except that a p-type organic semiconductor material and an n-type organic semiconductor material are used as the constituent materials of the organic semiconductor layer 5, respectively. It is the same.

The gate electrodes 7 of the p-type transistor 1A1 and the n-type transistor 1A2 are integrally formed, and one end thereof is connected to a connection electrode (not shown). This connection electrode is an input terminal for inputting a signal voltage.
Further, wirings 15 are connected to the drain electrodes 4 of the p-type transistor 1A1 and the n-type transistor 1A2, respectively, and both of these wirings 15 are connected to a connection electrode (not shown). The connection electrode is an output terminal that outputs a signal voltage.

The source electrode 3 of the p-type transistor 1A1 is connected to the power supply (Vdd) via the wiring 17, and the source electrode 3 of the n-type transistor 1A2 is grounded (Vss) via the wiring 17.
In such an inverter circuit 10, when an H level voltage is applied from the input terminal, almost no current flows in the organic semiconductor layer 5 of the p-type transistor 1A1, and in the organic semiconductor layer 5 of the n-type transistor 1A2 , Carriers are induced, and a current flows in the channel region. Therefore, an L level (Vss) voltage is output from the output terminal.

On the other hand, when an L level voltage is applied from the input terminal, carriers are induced in the organic semiconductor layer 5 of the p-type transistor 1A1, and a current flows in the channel region. In addition, almost no current flows in the organic semiconductor layer 5 of the n-type transistor 1A2. Therefore, an H level (Vdd) voltage is output from the output terminal.
Thus, the inverter circuit 10 functions as an inverting circuit that inverts and outputs an input signal.

Each transistor of the inverter circuit 10 can be manufactured in the same manner as the transistor of the second embodiment described above.
Even in the transistor of the ninth embodiment, the same operation and effect as the transistor 1 of the first embodiment described above can be obtained.
In particular, in the present embodiment, in the inverter circuit 10, the p-type transistor 1A1 and the n-type transistor 1A2 have different conductive organic semiconductor layers 5, so that the organic semiconductor layer 5 of the p-type transistor 1A1 and the n-type transistor It is necessary that the organic semiconductor layer 5 of the transistor 1A2 is reliably separated. Therefore, it is extremely useful to apply the present invention to such an inverter circuit 10.

<Electronic device>
Next, a liquid crystal panel including the above-described active matrix device 130 will be described as an example of the electronic device of the present invention.
FIG. 25 is a longitudinal sectional view showing an embodiment in which the electronic device of the present invention is applied to a liquid crystal panel.

  As shown in FIG. 25, a liquid crystal panel (TFT liquid crystal panel) 100 includes an active matrix device 130 which is a TFT substrate, an alignment film 60 bonded to the active matrix device 130, a counter substrate 20 for a liquid crystal panel, and a liquid crystal panel. An alignment film 40 bonded to the counter substrate 20, a liquid crystal layer 90 made of liquid crystal sealed in a gap between the alignment film 60 and the alignment film 40, and an outer surface (upper surface) of the active matrix device (liquid crystal driving substrate) 130. The polarizing film 70 is bonded to the side, and the polarizing film 80 is bonded to the outer surface (lower surface) side of the counter substrate 20 for the liquid crystal panel.

The counter substrate 20 for the liquid crystal panel is provided on the microlens substrate 201, the surface layer 202 of the microlens substrate 201, the black matrix 204 in which the opening 203 is formed, and the black matrix 204 on the surface layer 202 so as to cover the black matrix 204. A transparent conductive film (common electrode) 209.
The microlens substrate 201 includes a substrate (first substrate) 206 having concave portions for microlenses (a first substrate) 206 provided with a plurality of (many) concave portions (concave portions for microlenses) 205 having a concave curved surface, and the substrate 206 having concave portions for microlenses. And a surface layer 202 joined via a resin layer (adhesive layer) 207 to the surface provided with the recess 205, and in the resin layer 207, the microlens is formed by the resin filled in the recess 205. 208 is formed.

The active matrix device 130 is a substrate that drives the liquid crystal of the liquid crystal layer 90.
The transistor 1 of the active matrix device 130 is connected to a control circuit (not shown) and controls a current supplied to the pixel electrode 141. Thereby, charging / discharging of the pixel electrode 141 is controlled.
The inorganic alignment film 60 is bonded to the pixel electrode 141 of the active matrix device 130, and the inorganic alignment film 60 is bonded to the liquid crystal layer 90 of the counter substrate 20 for the liquid crystal panel.
The liquid crystal layer 90 contains liquid crystal molecules, and the alignment of the liquid crystal molecules, that is, the liquid crystal changes corresponding to the charge / discharge of the pixel electrode 141.
In such a liquid crystal panel 100, normally, one micro lens 208, one opening 203 of the black matrix 204 corresponding to the optical axis Q of the micro lens 208, one pixel electrode 141, and such a pixel. One transistor 1 connected to the electrode 141 corresponds to one pixel.

  Incident light L incident from the liquid crystal panel counter substrate 20 side passes through the microlens recessed substrate 206 and is condensed when passing through the microlens 208, while opening the resin layer 207, the surface layer 202, and the black matrix 204. 203, the transparent conductive film 209, the liquid crystal layer 90, the pixel electrode 141, and the substrate 50 are transmitted. At this time, since the polarizing film 80 is provided on the incident side of the microlens substrate 201, when the incident light L passes through the liquid crystal layer 90, the incident light L is linearly polarized. At this time, the polarization direction of the incident light L is controlled in accordance with the alignment state of the liquid crystal molecules in the liquid crystal layer 90. Therefore, by transmitting the incident light L transmitted through the liquid crystal panel 100 to the polarizing film 70, the luminance of the emitted light can be controlled.

As described above, the liquid crystal panel 100 includes the microlens 208, and the incident light L that has passed through the microlens 208 is collected and passes through the openings 203 of the black matrix 204. On the other hand, the incident light L is shielded in a portion where the opening 203 of the black matrix 204 is not formed. Therefore, in the liquid crystal panel 100, unnecessary light is prevented from leaking from portions other than the pixels, and attenuation of the incident light L at the pixel portions is suppressed. For this reason, the liquid crystal panel 100 has high light transmittance in the pixel portion.
The electronic device of the present invention is not limited to application to such a liquid crystal panel, and can also be applied to an electrophoretic display device, an organic or inorganic EL display device, and the like.

<Electronic equipment>
Next, as an example of the electronic apparatus of the present invention, a liquid crystal display device including the above-described liquid crystal panel 100 will be described based on first to fourth examples shown in FIGS.
(First example)
FIG. 26 is a perspective view showing a configuration of a mobile type (or notebook type) personal computer which is a first example of the electronic apparatus of the present invention.
In this figure, a personal computer 1100 includes a main body 1104 having a keyboard 1102 and a display unit 1106. The display unit 1106 is supported by the main body 1104 via a hinge structure so as to be rotatable. Yes.
In the personal computer 1100, the display unit 1106 includes the liquid crystal panel 100 described above and a backlight (not shown). An image (information) can be displayed by transmitting light from the backlight to the liquid crystal panel 100.

(Second example)
FIG. 27 is a perspective view showing a configuration of a mobile phone (including PHS) as a second example of the electronic apparatus of the invention.
In this figure, a cellular phone 1200 includes the above-described liquid crystal panel 100 and a backlight (not shown) as well as a plurality of operation buttons 1202, an earpiece 1204 and a mouthpiece 1206.

(Third example)
FIG. 28 is a perspective view showing the configuration of a digital still camera which is a third example of the electronic apparatus of the present invention. In this figure, connection with an external device is also simply shown.
Here, an ordinary camera sensitizes a silver halide photographic film with a light image of a subject, whereas a digital still camera 1300 photoelectrically converts a light image of a subject with an imaging device such as a CCD (Charge Coupled Device). An imaging signal (image signal) is generated.

The above-described liquid crystal panel 100 and a backlight (not shown) are provided on the back of a case (body) 1302 in the digital still camera 1300. The liquid crystal panel 100 is configured to perform display based on an imaging signal from the CCD. Functions as a finder that displays the subject as an electronic image.
A circuit board 1308 is installed inside the case. The circuit board 1308 is provided with a memory that can store (store) an imaging signal.
A light receiving unit 1304 including an optical lens (imaging optical system), a CCD, and the like is provided on the front side of the case 1302 (on the back side in the illustrated configuration).
When the photographer confirms the subject image displayed on the liquid crystal panel 100 and presses the shutter button 1306, the image pickup signal of the CCD at that time is transferred and stored in the memory of the circuit board 1308.

  In the digital still camera 1300, a video signal output terminal 1312 and an input / output terminal 1314 for data communication are provided on the side surface of the case 1302. As shown in the figure, a television monitor 1430 is connected to the video signal output terminal 1312 and a personal computer 1440 is connected to the input / output terminal 1314 for data communication as necessary. Further, the imaging signal stored in the memory of the circuit board 1308 is output to the television monitor 1430 or the personal computer 1440 by a predetermined operation.

(Fourth example)
FIG. 29 is a diagram schematically showing an optical system of a projection display device (liquid crystal projector) which is a fourth example of the electronic apparatus of the invention.
As shown in the figure, the projection display apparatus 300 includes a light source 301, an illumination optical system including a plurality of integrator lenses, a color separation optical system (light guide optical system) including a plurality of dichroic mirrors, and the like. Liquid crystal light valve (liquid crystal optical shutter array) 240 corresponding to red (liquid crystal optical shutter array) 240 corresponding to red, liquid crystal light valve (liquid crystal optical shutter array) 250 corresponding to green (liquid crystal optical shutter array) 250, and blue corresponding to blue (for blue) ) A liquid crystal light valve (liquid crystal light shutter array) 260, a dichroic prism (color combining optical system) 210 on which a dichroic mirror surface 211 reflecting only red light and a dichroic mirror surface 212 reflecting only blue light are formed, and projection A lens (projection optical system) 220.

  The illumination optical system includes integrator lenses 302 and 303. The color separation optical system includes mirrors 304, 306, and 309, a dichroic mirror 305 that reflects blue light and green light (transmits only red light), a dichroic mirror 307 that reflects only green light, and a dichroic that reflects only blue light. A mirror (or a mirror that reflects blue light) 308 and condenser lenses 310, 311, 312, 313, and 314 are included.

The liquid crystal light valve 250 includes the liquid crystal panel 100 described above. The liquid crystal light valves 240 and 260 have the same configuration as the liquid crystal light valve 250. The liquid crystal panels 100 included in the liquid crystal light valves 240, 250, and 260 are connected to driving circuits (not shown).
In the projection display device 300, the dichroic prism 210 and the projection lens 220 constitute the optical block 200. The optical block 200 and liquid crystal light valves 240, 250 and 260 fixedly installed with respect to the dichroic prism 210 constitute a display unit 230.

Hereinafter, the operation of the projection display apparatus 300 will be described.
White light (white light beam) emitted from the light source 301 passes through the integrator lenses 302 and 303. The light intensity (luminance distribution) of the white light is made uniform by the integrator lenses 302 and 303. The white light emitted from the light source 301 preferably has a relatively high light intensity. Thereby, the image formed on the screen 320 can be made clearer. In addition, since the projection display device 300 uses the liquid crystal panel 100 having excellent light resistance, excellent long-term stability can be obtained even when the intensity of light emitted from the light source 301 is large.

The white light transmitted through the integrator lenses 302 and 303 is reflected to the left side in FIG. 7 by the mirror 304, and blue light (B) and green light (G) of the reflected light are respectively reflected by the dichroic mirror 305 in FIG. The red light (R) is reflected downward and passes through the dichroic mirror 305.
The red light transmitted through the dichroic mirror 305 is reflected downward in FIG. 29 by the mirror 306, and the reflected light is shaped by the condenser lens 310 and enters the liquid crystal light valve 240 for red.

Green light out of blue light and green light reflected by the dichroic mirror 305 is reflected to the left in FIG. 29 by the dichroic mirror 307, and the blue light passes through the dichroic mirror 307.
The green light reflected by the dichroic mirror 307 is shaped by the condenser lens 311 and enters the green liquid crystal light valve 250.
Further, the blue light transmitted through the dichroic mirror 307 is reflected on the left side in FIG. 29 by the dichroic mirror (or mirror) 308, and the reflected light is reflected on the upper side in FIG. 30 by the mirror 309. The blue light is shaped by the condenser lenses 312, 313 and 314 and enters the blue liquid crystal light valve 260.

As described above, the white light emitted from the light source 301 is separated into the three primary colors of red, green, and blue by the color separation optical system, and is guided to the corresponding liquid crystal light valve and enters.
At this time, each pixel (transistor 1 and pixel electrode 141 connected thereto) of the liquid crystal panel 100 included in the liquid crystal light valve 240 is subjected to switching control by a driving circuit (driving means) that operates based on a red image signal. (On / off), ie modulated.

Similarly, green light and blue light enter the liquid crystal light valves 250 and 260, respectively, and are modulated by the respective liquid crystal panels 100, thereby forming a green image and a blue image. At this time, each pixel of the liquid crystal panel 100 included in the liquid crystal light valve 250 is subjected to switching control by a drive circuit that operates based on an image signal for green, and each pixel of the liquid crystal panel 100 included in the liquid crystal light valve 260 is used for blue color. Switching control is performed by a drive circuit that operates based on the image signal.
As a result, the red light, the green light, and the blue light are modulated by the liquid crystal light valves 240, 250, and 260, respectively, so that a red image, a green image, and a blue image are formed.

The red image formed by the liquid crystal light valve 240, that is, the red light from the liquid crystal light valve 240, enters the dichroic prism 210 from the surface 213, and is reflected by the dichroic mirror surface 211 to the left in FIG. The light passes through the surface 212 and exits from the exit surface 216.
Further, the green image formed by the liquid crystal light valve 250, that is, the green light from the liquid crystal light valve 250, enters the dichroic prism 210 from the surface 214, passes through the dichroic mirror surfaces 211 and 212, and exits. The light exits from the surface 216.
In addition, the blue image formed by the liquid crystal light valve 260, that is, the blue light from the liquid crystal light valve 260, is incident on the dichroic prism 210 from the surface 215, and is reflected by the dichroic mirror surface 212 to the left in FIG. The light passes through the dichroic mirror surface 211 and exits from the exit surface 216.

  Thus, the light of each color from the liquid crystal light valves 240, 250 and 260, that is, the images formed by the liquid crystal light valves 240, 250 and 260 are synthesized by the dichroic prism 210, thereby forming a color image. Is done. This image is projected (enlarged projection) onto the screen 320 installed at a predetermined position by the projection lens 220.

In addition to the personal computer (mobile personal computer) shown in FIG. 26, the mobile phone shown in FIG. 27, the digital still camera shown in FIG. 28, and the projection display device shown in FIG. , Video camera, viewfinder type, monitor direct-view video tape recorder, car navigation device, pager, electronic notebook (including communication function), electronic dictionary, calculator, electronic game device, word processor, workstation, video phone, crime prevention TV monitors, electronic binoculars, POS terminals, devices equipped with touch panels (for example, cash dispensers of financial institutions, automatic ticket vending machines), medical devices (for example, electronic thermometers, blood pressure monitors, blood glucose meters, electrocardiographs, ultrasonic diagnostic devices) , Endoscope display devices), fish detectors, various measuring instruments, instruments ( In example, vehicle, aircraft, gauges of a ship), such as flight simulators, and the like. And it cannot be overemphasized that the liquid crystal panel of this invention mentioned above is applicable as a display part of these various electronic devices, and a monitor part.
As described above, the electronic device and electronic equipment included in the transistor 1 have excellent reliability.

Although the transistor, the transistor manufacturing method, the electronic device, and the electronic apparatus of the present invention have been described based on the illustrated embodiments, the present invention is not limited to this.
For example, in the method for manufacturing a transistor of the present invention, one or two or more optional steps may be added. In addition, for example, in the transistor, the electronic device, and the electronic device of the present invention, the configuration of each part can be replaced with any configuration that exhibits the same function, and any configuration can be added. .
Moreover, in the said embodiment, although the projection type display apparatus (electronic device) has three liquid crystal panels and demonstrated the thing which applied the liquid crystal panel of this invention to all of these, At least among these One may be the liquid crystal panel of the present invention. In this case, it is preferable to apply the present invention to at least a liquid crystal panel used for a liquid crystal light valve for blue.

1 is a plan view showing an active matrix device including a transistor according to a first embodiment of the present invention. FIG. 2 is a longitudinal sectional view of the transistor shown in FIG. 1. FIG. 2 is a plan view showing a source electrode and a drain electrode provided in the transistor shown in FIG. 1. It is a figure for demonstrating the manufacturing method of the transistor shown in FIG. It is a figure for demonstrating the manufacturing method of the transistor shown in FIG. It is a figure for demonstrating the manufacturing method of the transistor shown in FIG. It is a figure for demonstrating the manufacturing method of the transistor shown in FIG. It is a figure for demonstrating the manufacturing method of the transistor shown in FIG. It is a figure for demonstrating the manufacturing method of the transistor shown in FIG. It is a figure for demonstrating the manufacturing method of the transistor shown in FIG. It is a figure for demonstrating the manufacturing method of the transistor shown in FIG. It is a figure for demonstrating the wet spreading state of a liquid material in case the outline of a composite area | region has a right-angled corner | angular part as a reference example. It is a longitudinal cross-sectional view which shows the transistor of 2nd Embodiment of this invention. It is a top view which shows the source electrode and drain electrode which were provided in the transistor of 3rd Embodiment of this invention. It is a top view which shows the source electrode and drain electrode which were provided in the transistor of 4th Embodiment of this invention. It is a top view which shows the source electrode and drain electrode which were provided in the transistor of 5th Embodiment of this invention. It is a top view which shows the source electrode and drain electrode which were provided in the transistor of 6th Embodiment of this invention. It is a schematic diagram which shows the transistor of 7th Embodiment of this invention. FIG. 19 is a schematic plan view showing a source electrode, a drain electrode, and a gate insulating layer defining layer provided in the transistor shown in FIG. 18. It is a figure for demonstrating the manufacturing method of the transistor shown in FIG. It is a figure for demonstrating the manufacturing method of the transistor shown in FIG. It is a typical top view showing a transistor of an 8th embodiment of the present invention. FIG. 23 is a plan view showing electrodes and wirings provided in the transistor shown in FIG. 22. It is a top view which shows the example which applied the transistor concerning 9th Embodiment of this invention to the inverter circuit. It is a longitudinal cross-sectional view which shows the structure of the liquid crystal panel which is an example of the electronic device of this invention. 1 is a perspective view illustrating a configuration of a mobile (or notebook) personal computer that is a first example of an electronic apparatus according to the present invention. It is a perspective view which shows the structure of the mobile telephone (PHS is also included) which is the 2nd example of the electronic device of this invention. It is a perspective view which shows the structure of the digital still camera which is the 3rd example of the electronic device of this invention. It is a figure which shows typically the optical system of the projection type display apparatus which is the 4th example of the electronic device of this invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Transistor 2 ... Composite area 21 ... Curve part 22 ... Straight line part 23 ... Edge 3, 3A ... Source electrode 31 ... Top surface 32 ... Ring part 33 ... Wedge-like part 3a ... Electrode finger 3b ··· Base 4, 4A ··· Drain electrode 41 ··· Upper surface 42 ··· Linear portion 4a ··· Electrode finger 4b ··· Base 5 ··· Organic semiconductor layer 50 ··· Substrate 51 ··· Channel region 52 ··· Channel formation region 6 ... Gate insulation layer 7, 7A, 7B ... Gate electrode 8 ... Protective film 9 ... Liquid material 11 ... Gate insulation layer defining layer 12, 13 ... Wiring 14 ... Gate insulation layer formation region 15, 17 ... wiring 10 ... inverter circuit 1A1 ... p-type transistor 1A2 ... n-type transistor 5A ... p-type organic semiconductor layer 5B ... n-type organic semiconductor layer 100 ... liquid crystal panel DESCRIPTION OF SYMBOLS 90 ... Liquid crystal layer 60 ... Inorganic alignment film 40 ... Inorganic alignment film 209 ... Transparent electrically conductive film 70 ... Polarizing film 80 ... Polarizing film 201 ... Microlens substrate 206 ... Substrate with a concave part for microlenses 205 ... ... Concavity 208 ... Micro lens 202 ... Surface layer 207 ... Resin layer 20 ... Counter substrate for liquid crystal panel 204 ... Black matrix 203 ... Opening 130 ... Active matrix device 131 ... Data line 132 ... Scanning line 133 ...... Connecting electrode 141 ...... Pixel electrode 1100 ... Personal computer 1102 ... Keyboard 1104 ... Main unit 1106 ... Display unit 1200 ... Mobile phone 1202 ... Operation buttons 1204 ... Earpiece 1206 ... Mouthpiece 1300 Digital still camera 13 2 ... Case (body) 1304 ... Light receiving unit 1306 ... Shutter button 1308 ... Circuit board 1312 ... Video signal output terminal 1314 ... Input / output terminal for data communication 1430 ... Television monitor 1440 ... Personal computer 300 …… Projection type display device 301 …… Light source 302, 303 …… Integrator lenses 304, 306, 309 …… Mirrors 305, 307, 308… Dichroic mirrors 310-314 …… Condensing lens 320 …… Screen 200 …… Optical Block 210 ... Dichroic prism 211, 212 ... Dichroic mirror surface 213 to 215 ... Surface 216 ... Outgoing surface 220 ... Projection lens 230 ... Display unit 240 to 260 ... Liquid crystal light valve

Claims (18)

A source electrode;
A drain electrode;
A gate electrode;
An organic semiconductor layer located between the source electrode and the drain electrode;
A gate insulating layer located between the gate electrode and the organic semiconductor layer;
A part of the outline of the organic semiconductor layer and a part of the outline of the source electrode coincide and overlap, a part of the outline that coincides and overlaps with the source electrode of the organic semiconductor layer includes a curve, and the source electrode A part of the contour that overlaps with the organic semiconductor layer includes a curve.   2. The transistor according to claim 1, wherein the organic semiconductor layer is formed at a position overlapping a composite region including the source electrode, the drain electrode, and a region between the source electrode and the drain electrode. A source electrode and a drain electrode provided on the substrate at a distance from each other;
An organic semiconductor layer located between the source electrode and the drain electrode;
A gate electrode, and a gate insulating layer that insulates the gate electrode from the source electrode and the drain electrode,
The source electrode and the drain electrode are configured so that a contour of a combined region including a region between the source electrode and the drain electrode and a combination of the source electrode and the drain electrode includes a curve in a plan view. Formed as
The organic semiconductor layer is formed by dropping an organic semiconductor material or a liquid material containing a precursor thereof into the composite region and solidifying or curing the organic semiconductor layer, and substantially matches the composite region in plan view. A transistor formed over a range.   4. The transistor according to claim 2, wherein a contour of the composite region is formed so as not to substantially include a right angle or an acute corner.   The transistor according to claim 1, wherein the composite region has a substantially circular shape or a substantially oval shape in plan view.   In a plan view, the region between the source electrode and the drain electrode has a longitudinal shape, and the composite region is substantially long so as to extend in the longitudinal direction of the region between the source electrode and the drain electrode. 6. The transistor according to claim 5, wherein the transistor is circular.   In a plan view, the region between the source electrode and the drain electrode has a longitudinal shape, and the composite region has a plurality of substantially circular shapes or substantially elliptical regions between the source electrode and the drain electrode. 7. The transistor according to claim 1, wherein the transistor is shaped so as to be connected in the longitudinal direction.   The source electrode and the drain electrode each have a comb-like portion in a plan view, and are provided so as to mesh with each other with a space therebetween. Transistor. A source electrode and a drain electrode provided on a substrate spaced apart from each other; an organic semiconductor layer positioned between the source electrode and the drain electrode; a gate electrode; and the gate with respect to the source electrode and the drain electrode A method of manufacturing a transistor having a gate insulating layer for insulating an electrode,
In the plan view, the source electrode and the drain electrode are substantially perpendicular to each other or have a sharp corner portion of a composite region including the region between the source electrode and the drain electrode and the source electrode and the drain electrode. A first step of forming a curve so as not to include the curve;
A liquid material containing an organic semiconductor material or a precursor thereof is dropped into the composite region, spreads until it substantially coincides with the composite region in plan view, and then solidifies or cures, thereby forming the organic semiconductor layer. And a second step of forming the transistor.   The method for manufacturing a transistor according to claim 9, wherein in the first step, the source electrode and the drain electrode are formed so that the composite region has a substantially circular shape or a substantially oval shape in plan view.   In the first step, a region between the source electrode and the drain electrode has a longitudinal shape in plan view, and the composite region is between the source electrode and the drain electrode in plan view. The method for manufacturing a transistor according to claim 10, wherein the source electrode and the drain electrode are formed so as to form a substantially oval shape extending in a longitudinal direction of the region.   In the first step, a region between the source electrode and the drain electrode has a longitudinal shape in plan view, and the composite region has a plurality of substantially circular shapes or substantially oval shapes in plan view. The method for manufacturing a transistor according to claim 9, wherein the source electrode and the drain electrode are formed so as to form a shape in which the regions between the source electrode and the drain electrode are connected side by side in the longitudinal direction.   In the first step, the source electrode and the drain electrode are formed so that each of the source electrode and the drain electrode has a comb-like portion in plan view and meshes with each other with a space therebetween. A method for manufacturing the transistor according to claim 9.   The method for manufacturing a transistor according to claim 9, wherein, in the second step, an inkjet method is used as a method for dropping the liquid material. Before or after the second step, the gate insulating layer defining layer that defines the formation region of the gate insulating layer has a contour that includes a curve without substantially including a right angle or an acute corner. A step of forming the composite region or its formation site in a plan view so as to surround the space with a space therebetween;
After the second step, a liquid material containing an organic insulating material or a precursor thereof is dropped into a region where the gate insulating layer defining layer and its inner region are combined, and substantially coincides with the region in plan view. The method for manufacturing a transistor according to claim 9, further comprising a step of forming the gate insulating layer by solidifying or hardening after being wet-spread until it is done.   The step of forming the gate insulating layer defining layer is performed before the second step, and the gate insulating layer defining layer is bundled together with the source electrode and the drain electrode in the first step. The method for manufacturing a transistor according to claim 15, which is formed by:   An electronic device comprising the transistor manufactured by the method for manufacturing a transistor according to claim 9.   An electronic apparatus comprising the electronic device according to claim 17.

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