JP2008158184A - Method of driving plasma display panel - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a driving method of a plasma display panel which attains higher resolution of a screen and can perform gradation display for every scanning line. <P>SOLUTION: The method of driving the plasma display panel includes a front substrate and a back substrate which face each other via a discharge space, a plurality of row electrodes which are juxtaposed on the inner surface of the front substrate and constitute scanning lines for every adjacent opposite line, and a plurality of column electrodes which are juxtaposed in a direction intersecting in the row electrodes on the inner surface of the back substrate and constitute cell respectively in the intersection positions with the scanning lines. The row discharge step for performing sustain discharge by applying two or more sustain pulses for every scanning line is line sequentially changed over and performed. The sustain step of applying an address potential based on the display data for every row discharge step is included. The gradation display step to apply a suppression pulse of the row discharge step in synchronization with the sustain pulse of the row discharge step to a column electrode is included. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a method for driving a surface discharge AC plasma display panel.

  FIG. 1 shows a panel structure of a conventional plasma display panel, and is a front view schematically showing the relationship between row electrode pairs X and Y and barrier ribs 6. (See Patent Document 1).

  The plasma display panel of FIG. 1 is formed by laminating a back substrate and a front substrate facing each other through a discharge space in parallel. On the front side of the rear substrate, a plurality of column electrodes (indicated by broken lines) each extending in the column direction and arranged in the row direction are provided, and a column electrode protection layer is formed thereon. A plurality of row electrode pairs X and Y, each extending in the row direction and arranged in parallel in the column direction, are provided on the back side of the front substrate.

  As shown in FIG. 1, on the column electrode protection layer of the back substrate, a vertical barrier rib extending in the column direction and a horizontal barrier rib extending in the row direction are coupled to each other at positions between the column electrodes arranged in the row direction. A partition wall 6 formed in a substantially lattice shape (well shape) is formed.

A cell D is defined as a rectangular chamber by the substantially lattice-shaped partition 6 so that a unit light-emitting portion is formed at the intersection of the column electrode and the row electrode pair. A T-shaped transparent electrode portion Ka protrudes in the column direction from each of the row electrode pairs X and Y.
JP2002-197981

  The plasma display panel has excellent performance as a large thin display. Currently, large panels of 30 inches or more are manufactured in the market.

  In recent years, it has been studied to use a plasma display panel not only for a conventional large panel but also for a medium-sized, full HD class high definition display of about 26 inches.

  However, when the size of the cell is reduced, for example, when the size (passage) becomes 100 μm or less, the cell D becomes too narrow, the discharge space is reduced, and the light emission efficiency is significantly reduced. was there. This is because if the size of the unit cell is reduced, the positive column of the plasma (plasma in the space between the cathode and the anode) cannot be taken sufficiently large. As a result, the luminance and the luminous efficiency are reduced.

  The present invention has been made to solve the problems in the conventional surface discharge type AC plasma display panel as described above. Problems to be solved by the present invention include reduction in luminance and error in cells. An example is to provide a method for driving a plasma display panel that can prevent discharge and realize high definition of the screen.

  Further, in the plasma display panel, the image display is not performed by the address display separation (ADS) subframe method, but in the unit display period (one field, one frame) of the input image signal, the sustain between the row electrode pairs constituting the scanning line is maintained. An example is to provide a driving method in which an address potential is applied to each column electrode in accordance with display data and gradation display is performed for each scanning line at the same time as the discharge is line-sequentially scanned.

  In order to achieve such an object, a plasma display panel according to the present invention has the following configuration, and features thereof are as follows.

The driving method of the plasma display panel according to claim 1, wherein a front substrate and a rear substrate facing each other through a discharge space, and a plurality of scanning lines that are arranged in parallel on the inner surface of the front substrate and constitute adjacent pairs. Driving a plasma display panel comprising: a row electrode; and a plurality of column electrodes arranged in parallel in a direction intersecting the row electrode on the inner surface of the rear substrate and each constituting a cell at the intersection with the scanning line A method,
A row discharge step in which sustain discharge is performed by applying two or more sustain pulses to each scanning line is switched in line sequence, and an address potential is applied to the column electrode based on display data at each row discharge step. Including a sustain step to
The method includes a gradation display step in which a suppression pulse for suppressing the sustain discharge is applied to the column electrode in synchronization with the sustain pulse of the row discharge step.

BEST MODE FOR CARRYING OUT THE INVENTION

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 2 is an exploded perspective view disassembled into a front substrate and a rear substrate for explaining the configuration of the main body 120 of the plasma display panel.

  As shown in FIG. 2, a front substrate in which a plurality of row electrodes X and Y are made of glass on the rear surface of the front substrate 1 made of glass as a display surface (the inner surface facing the rear substrate 4 spaced apart in parallel). 1 are arranged in parallel so as to extend in the row direction (left-right direction in FIG. 2).

  The row electrode X has a strip-like common bus electrode portion Kb made of a metal film extending in the row direction of the front substrate 1, and is arranged in parallel at equal intervals along the common bus electrode portion Kb. With a T-shaped transparent electrode portion Ka (a discharge electrode that protrudes in the column direction from the bus electrode portion) made of a transparent conductive film such as ITO (indium tin oxide) connected to the common bus electrode portion Kb. It is configured.

  Similarly, the row electrode Y has a strip-like common bus electrode portion Kb made of a metal film extending in the row direction of the front substrate 1, and a narrow base end arranged in parallel at equal intervals along the common bus electrode portion Kb. The portion is constituted by a T-shaped transparent electrode portion Ka (discharge electrode) made of a transparent conductive film such as ITO connected to the common bus electrode portion Kb.

  The row electrodes X and Y are alternately arranged in the column direction of the front substrate 1 (vertical direction in FIG. 2), and transparent electrode portions Ka arranged in parallel along the two common bus electrode portions Kb are paired with each other. The wide apexes of the transparent electrode portions Ka are opposed to each other via a discharge gap having a required width. In the row electrode Y, the transparent electrode portions Ka are arranged in high density so that the row electrode adjacent to the opposite side of the row electrode X also forms a row electrode pair. That is, the transparent electrode portions Ka are provided on both sides in the column direction of the row electrodes.

  As shown in FIG. 2, a dielectric layer 2 is formed on the row electrode pairs X and Y on the back side of the front substrate 1 so as to cover them.

  On the back side of the dielectric layer 2, a strip-like raised dielectric layer 2 </ b> A that protrudes from the dielectric layer 2 to the discharge space on the back side is formed in parallel on the bus electrode portion Kb. A protective layer 3 made of MgO is formed on the back side of the dielectric layer 2 and the raised dielectric layer 2A.

  On the other hand, on the lower side of the surface (inner surface) facing the front substrate 1 of the rear substrate 4 arranged in parallel with the front substrate 1 through the discharge space, column electrodes C (address electrodes) are respectively connected to the row electrode pairs X. , Y are arranged in parallel at equal intervals so as to extend in the column direction at positions facing the paired transparent electrode portions Ka.

  A column electrode protective layer 5 (dielectric layer) is further formed on the inner surface of the rear substrate 4 on the display side to cover the column electrode C. A partition wall 6 formed in a lattice shape (well shape) is formed on the protective layer 5. In other words, the discharge space is partitioned by the barrier ribs 6, and a plurality of cells D that are aligned in the row and column directions are defined.

  On each inner surface of the partition wall 6 facing each cell D and on the surface of the column electrode protective layer 5, a phosphor layer 7 that is excited by discharge and emits light is formed so as to cover these surfaces. For example, in a full color display panel, each cell D on the back substrate is divided into phosphor layers of three primary colors of red (R), green (G), and blue (B), and the discharge area of the cell for each color is divided. .

  A discharge gas containing xenon gas Xe is sealed in the discharge space of each cell D between the front substrate 1 and the back substrate 4.

  FIG. 3 is a schematic block diagram showing a configuration example of the plasma display panel device according to the present embodiment. The display device includes various drive devices that drive the panel body 120 of the plasma display panel, a column electrode drive circuit 212, a row electrode drive circuit 210, and the like.

  The panel body 120 includes odd-numbered row electrodes X1 to Xn and even-numbered row electrodes Y1 to Yn and column electrodes C1 to Cm arranged in a matrix. The column electrodes C1 to Cm are connected to the column electrode drive circuit 212, and the row electrodes X1 to Xn and Y1 to Yn are connected to the row electrode drive circuit 210. A cell Dij (unit light emitting portion) is formed at the intersection of one of the column electrodes C1 to Cm and a pair of adjacent odd and even row electrodes. For each cell, a row electrode pair is provided with the above-described opposed discharge electrodes, although not shown. That is, each of a pair of adjacent row electrode pairs X and Y constitutes a scanning line.

  The row electrode drive circuit 210 applies a drive pulse such as a sustain pulse to the adjacent row electrode pair X and Y, scans the row electrode pair X and Y sequentially in line display, and in synchronization with this line display scan, The electrode drive circuit 212 generates pixel data pulses (pulses having address potentials such as a discharge suppression potential, a reference potential, and a discharge promotion potential) corresponding to each pixel data supplied from the output processing circuit 206 to Applied to the column electrodes C1 to Cm. Although not shown, the row electrode drive circuit 210 sends an X driver that generates a first sustain pulse to the row electrodes X1 to Xn, and a second sustain pulse that has an opposite phase to the first sustain pulse to the row electrodes Y1 to Yn. Y driver to be generated is included. The column electrode drive circuit 212 changes the potential of the column electrode from a reference potential, for example, the ground potential (0 V), to a large potential in the negative polarity direction (discharge suppression potential) or a large potential in the positive polarity direction (discharge promotion potential). A pixel data pulse (address potential) is generated.

  Thus, in the plasma display panel, display driving is performed by supplying an address potential to the column electrodes C1 to Cm on the back substrate side in synchronization with the line sequential scanning of the row electrode pairs X and Y on the front substrate side. The discharge current of the light emitting unit is adjusted for each group of cells in one row of row electrode pairs. When an address potential corresponding to an image signal is applied to each column electrode while the sustain pulse is applied to the row electrode, sampling is performed and the gradation (brightness level of light and dark) of the light emitting unit can be controlled. For example, in a full color display panel, RGB image signals are sequentially supplied to the corresponding cells, and an image is displayed according to the image signal by applying a discharge suppression potential to a column electrode of a color that is not displayed.

  In the plasma display panel apparatus of FIG. 3, the sync separation circuit 201 extracts horizontal and vertical sync signals from the supplied input video signal and supplies them to the timing pulse generation circuit 202. The timing pulse generation circuit 202 generates an extracted synchronization signal timing pulse based on the extracted horizontal and vertical synchronization signals, and outputs the extracted synchronization signal timing pulse to each of the A / D converter 203, the memory control circuit 205, and the read timing signal generation circuit 207. To supply. The A / D converter 203 converts the input video signal into digital pixel data corresponding to each pixel in synchronization with the extraction synchronization signal timing pulse, and supplies this to the frame memory 204. The memory control circuit 205 supplies the frame memory 204 with a write signal and a read signal synchronized with the extraction synchronization signal timing pulse. The frame memory 204 sequentially captures each pixel data supplied from the A / D converter 203 according to the write signal. Further, the frame memory 204 sequentially reads out the pixel data stored in the frame memory 204 according to the read signal and supplies it to the output processing circuit 206 at the next stage. The read timing signal generation circuit 207 generates various timing signals for controlling the discharge light emission operation and supplies them to the row electrode drive circuit 210 and the output processing circuit 206, respectively. The output processing circuit 206 supplies the pixel data supplied from the frame memory 204 to the column electrode drive circuit 212 in synchronization with the timing signal from the readout timing signal generation circuit 207.

  Further, the row electrode drive circuit 210 is used to regenerate a pre-discharge pulse for performing pre-discharge and charged particles in addition to a sustain pulse for maintaining discharge between all the row electrode pairs of the panel body 120. It is possible to generate a priming pulse, a reset pulse for stabilizing the discharge at the time of data writing, and an erasing pulse for stopping the sustain light emission discharge. The row electrode drive circuit 210 applies these pulses to the row electrodes X1 to Xn and Y1 to Yn of the panel body 120 at timings according to various timing signals supplied from the read timing signal generation circuit 207.

  Here, it should be noted that the row electrode driving circuit 210 applies a sustain pulse train having an antiphase of about 1 to 30 pulses to each pair of adjacent row electrodes X and Y to maintain discharge, and performs line sequential. That is, it has a function of performing scanning, and the column electrode driving circuit 212 has a function of controlling discharge by selectively applying an address potential to the column electrodes.

  Next, a method for driving the plasma display panel of this embodiment will be described.

  FIG. 4 shows a timing chart of drive pulse waveforms applied to the electrodes in one frame period displayed periodically and repeatedly in the surface discharge AC type plasma display panel device of this embodiment. The row electrodes are labeled X1, Y1, X2, Y2,... Xn, Yn in order from the top. The column electrodes are sequentially labeled C1... Cm below the row electrodes.

  Each frame that is repeatedly displayed periodically includes a reset discharge period (reset step), a sustain discharge period (sustain step), and an erase discharge period (erase discharge step). The sustain discharge period (sustain step) is composed of a predetermined number (row electrode number-1) of row discharge periods (row discharge steps).

  First, a sustain discharge period (sustain step) in which a sustain pulse is generated by line sequential scanning by applying a sustain pulse to a pair of row electrodes which is a main part of line sequential display will be described. As shown in the figure, the sustain pulse waveforms are applied to the row electrode pairs so that the phases thereof are shifted from each other by 180 degrees.

  In a set of row electrode pairs (scanning lines), when a pulse is applied only to one of the row electrodes, no discharge occurs. When anti-phase pulses are applied to both synchronously, discharge occurs only during that period. For example, focusing on the row electrode pair X1, Y1, that is, the first and second row electrodes, when a positive / negative pulse is applied to the row electrode X1, a negative / positive pulse is applied to the row electrode Y1 almost simultaneously. As a result, the first discharge is generated at the timing when the negative polarity pulse of the row electrode Y falls to a predetermined value. In accordance with this, by applying a predetermined image signal to each of the column electrodes C1 to Cm, the cells of the first scanning line emit light with a predetermined luminance distribution (first row discharge period).

  After that, since the row electrode X1 becomes the ground potential (0 V), the light is extinguished in the cell of the first scanning line, but 2 in the row electrode pair of the row electrode Y1 and the next row electrode X2 to which the positive / negative pulse is applied. A second discharge potential is generated, and by applying a predetermined image signal to each of the column electrodes C1 to Cm, the cells of the second scanning line emit light with a predetermined luminance distribution (second row discharge). period). Next, similarly, the cells of the third scanning line of the row electrode pair X2, Y2 emit light (third row discharge period). Similarly, light is emitted sequentially to the cells of the nth scanning line of the row electrode pair Xn, Yn (nth row discharge period). Note that both the row electrode X and the row electrode Y straddle (shared) between adjacent row electrode pairs. However, only one side of the row electrode is actually discharged by this driving, and scanning can be sequentially performed. It becomes. Accordingly, since a pair of row electrode pairs corresponds to one scanning line, for example, in the case of an input image signal having a frame size of 1920 × 1080 dots in the case of monochrome display, 1920 column electrodes and 1081 A plasma display panel can be constituted by the row electrodes.

  In other words, the sustain operation is replaced with the scan operation in the conventional ADS driving method of the plasma display panel. In the conventional driving method of the plasma display panel, the scan pulse is only once. However, the sustain pulse of the present embodiment has a pulse number of 1 or more and continues sequentially for each display period of one scan line. Discharging is performed line-sequentially and line-sequential display is performed.

  Further, the brightness adjustment is controlled by the magnitude of the column electrode potential (address potential) during the sustain discharge period. If the column electrode potential is large in the negative direction, even if the sustain potential is the same, the electron intrusion region is suppressed, the discharge current and the light emission efficiency are reduced, and even if the column electrode potential is large in the positive direction, this time the ions enter. The region is suppressed, and the discharge current and the light emission efficiency are reduced. By adjusting the luminance for each RGB, the hue can be adjusted.

  Further embodiments are shown in FIG. Here, the description of the row electrodes is expressed as the odd-numbered row electrodes X1 to Xn and the even-numbered row electrodes Y1 to Yn in the above description. Further, description will be made based on the plasma display panel PDP shown in FIG. This panel PDP is composed of nine cells (L1C1, L1C2, L1C3, L2C1, L2C2, L2C3, L3C1, L3C2, L3C3) in three rows (L1, L2, L3) * 3 columns (C1, C2, C3). These three rows are between the row electrodes of (L1-L2, L2-L3, L3-L4), but are simply represented as (L1, L2, L3). Further, the number of sustain pulses applied for the sustain discharge of the cells in each row is 8 per row. The odd-numbered electrodes L1 and L3 have columns of positive and negative (+ -95V) sustain pulses So1 to So8, and the even-numbered electrodes L2 and L4 have columns of positive and negative polarity (+ -95V) sustain pulses Se1 to Se8. Applied in reverse phase. Now, the L1C2, L2C1, L2C3, and L3C2 cells on the four sides in the PDP shown in FIG. 5A are caused to emit light, and the other four corners and the center cell are displayed in black (that is, non-luminous with zero luminance). In this case, a sustain pulse is applied to the row electrode at the timing shown in FIG. The pulse width (suppression pulse) includes the columns of sustain pulses So1 to So8 and Se1 to Se8 applied to the row electrode pairs, and the discharge suppression potential (second potential = −) is applied to the C1 and C3 column electrodes in the first row discharge period. 190V), -190V is applied to the C2 column electrode during the second row discharge period, and -190V is applied to the C1 and C3 column electrodes during the third row discharge period. A change in the discharge current flowing through each cell during the sustain discharge is shown by oblique hatching pulses in FIG. It can be seen that a discharge current for a total of 8 pulses flows in the cell to emit light. Of course, no discharge current flows through the black cell.

  On the other hand, as shown in FIG. 7, the sustain pulse application to the row electrode pair is the same, and the first So1-Se1, the third So3-Se3, the fifth So5-Se5, and the seventh So7-Se7 are odd numbers. Only when a discharge suppression potential (second potential = -190 V) is applied in a pulsed manner (suppression pulse) to the C1 and C3 column electrodes in synchronization with only the sustain discharge, a discharge current similar to that in FIG. 6 flows. It is clear from That is, when the first sustain pulse is applied, a small amount of wall charges having opposite polarities are accumulated on the discharge electrodes. If the discharge is suppressed by applying the suppression pulse, the second sustain pulse is applied. When a pulse is applied, the small amount of wall charges described above interferes with the next discharge, and a phenomenon in which a sustain discharge does not occur even if a suppression pulse is not applied occurs.

  In the above, the distinction between the case where the luminance for each cell is 0 and the case where the luminance is not 0 is performed based on the timing of applying the suppression pulse. The amplitude can also be achieved.

  In the plasma display panel PDP shown in FIG. 8A, when a pattern such as a checkered pattern is drawn with three kinds of gradations of black, white, and gray (cross hatching), the sustain pulse and the suppression pulse at the timing shown in FIG. Apply. When the sustain pulse is applied, the second potential (discharge suppression potential = -190 V) is applied to the cell (L2C2) corresponding to the black gradation. Further, an intermediate potential (discharge suppression potential = −170 V) is applied to cells (L1C1, L1C3, L3C1, and L3C3) corresponding to gray gradations as a suppression pulse having a pulse amplitude smaller than the above when a sustain pulse is applied. The state of the discharge current at this time is shown by the oblique hatching pulses in FIG. It can be seen that a discharge current flows through all the sustain pulses during the sustain discharge period in the gray level cell corresponding to gray, and this discharge current is controlled by the potential of the suppression pulse. However, in this case, there is a high possibility that the luminance near black will become bright because of the characteristic that even the luminance of the low gradation cell is expressed by eight sustain discharges.

  Therefore, if the luminance near this black can be expressed by a small number of sustain discharges, it is possible to more faithfully express the luminance of this portion in a form closer to the ideal.

  FIG. 10 shows a checkered pattern with three types of gradations of black, white, and gray (cross-hatching) in the panel PDP as in the panel PDP shown in FIG. 8A, which is the first embodiment. The timing chart of the sustain pulse and the suppression pulse in the case of drawing is shown.

  The pulse width (suppression pulse) including the columns of sustain pulses So1 to So5 and Se1 to Se5 applied to the row electrode pair, and the discharge suppression potential (second) in the C1 and C3 column electrodes in the first and third row discharge periods. (Potential = -190V) is applied, but in the second row discharge period, -190V is applied to the C2 column electrode with a pulse width including the columns of the sustain pulses So1 to So8 and Se1 to Se8. The change of the discharge current flowing through each cell during the sustain discharge is shown by oblique hatching pulses in FIG. As is clear from FIG. 11, in the cells (L1C1, L1C3, L3C1, L3C3) in which dark gray gradation is set, the suppression pulse (-190V) is used until the fifth So5-Se5 of the sustain pulse. Although the discharge is completely suppressed, it can be seen that the fifth and subsequent sustain pulses So6-Se6 to So8-Se8 remove the suppression by the suppression pulse, and the discharge current gradually rises. That is, by controlling the number of sustain pulses effective for the discharge among the sustain discharges, it is possible to obtain the luminance gradation of each cell. In this case, it can be seen that up to four gradations can be controlled. As a result of further detailed examination, it has been found that the suppression by the suppression pulse is effective at the initial stage of the sustain pulse application, that is, from the first stage.

  Therefore, generally speaking, in the first embodiment of FIGS. 10 and 11, when the number of sustain pulses in the row discharge step is M, during the sustain pulse application up to the mth (2 ≦ m <M). A discharge suppression potential (second potential = -190V) is applied, and a first potential (for example, ground potential = 0V) that does not stop the sustain discharge is applied every time the (m + 1) th and subsequent sustain pulses are applied. In other words, gradation control is possible by controlling the pulse width of the suppression pulse. After applying the suppression pulse to the first m sustain pulses in the row discharge step to completely suppress the sustain discharge, do not apply this suppression pulse to the remaining (M−m) sustain pulses. Thus, cell gradation can be obtained.

  FIG. 12 shows a timing chart of the sustain pulse and the suppression pulse of the second embodiment. This is because the second suppression pulse (intermediate potential = discharge suppression potential = −170 V) is added to the fifth and subsequent sustain pulses So6-Se6˜ in addition to the suppression pulses up to the fifth So5-Se5 in the embodiment of FIG. Same as above except that it is applied to So8-Se8. The state of the discharge current at this time is shown by the oblique hatching pulses in FIG. As shown in FIG. 13, by controlling the potential of the second suppression pulse from the sustain discharge of the fifth So5-Se5 (pulse amplitude control), the fifth and subsequent sustain pulses So6-Se6 to So8-Se8 Although the suppression pulse is present, it can be seen that the discharge current gradually rises. By controlling the pulse amplitude of the suppression pulse, it is possible to control the luminance corresponding to the total size from zero luminance to three sustain discharges. Therefore, it can be seen that the gradation of the PDP pattern of the cells (L1C1, L1C3) in which the light gray gradation is set in addition to the dark gray gradation is obtained as shown in FIG.

  Therefore, generally speaking, in the second embodiment of FIGS. 12 and 13, when the number of sustain pulses in the row discharge step is M, the discharge suppression potential (second potential = second potential) is applied during the application of the mth sustain pulse. −190V), and when applying the (m + 1) th and subsequent sustain pulses, an intermediate potential (a predetermined intermediate potential between the second potential and the ground potential, for example, −170V) is applied. Key display is possible.

  In the gradation display step of the above embodiment, it can be seen that it is preferable that the suppression pulse for suppressing the sustain discharge is applied to the column electrode in synchronization with the sustain pulse of the row discharge step.

  In the gradation display step, it is preferable that the suppression pulse is selected to have a pulse width including the first sustain pulse of the row discharge step, and the sustain discharge corresponding to the gradation is adjusted by the pulse width of the suppression pulse. It is.

  In the gradation display step, the suppression pulse is selected to have the number of pulses corresponding to the number of pulses from the first sustain pulse in the row discharge step, and the sustain discharge can be adjusted according to the gradation according to the number of suppression pulses. Is preferred.

  In the gradation display step, it is preferable to select one of a plurality of pulse amplitudes of the suppression pulse and adjust the sustain discharge corresponding to the gradation by the pulse amplitude of the suppression pulse.

By the way, when attention is paid to the brightness (discharge current) of the sustain discharge, it can be seen that the change shown in FIG. This shows the case where there is no control by the suppression pulse. In the first sustain pulse, a relatively small discharge starts and a small luminance is obtained, but the discharge grows in the second So2. The discharge grows to a considerable size around the third So3, and the discharge current and the luminance are almost saturated to constant values from the fourth So4. If this saturated luminance is BU, an arbitrary luminance B can be expressed by the following equation.
B = N * BU + s * BU
Here, B represents the luminance of an arbitrary cell, N represents the number of sustain discharges during discharge light emission in each row, and satisfies the expression of 0 ≦ N ≦ Nmax. Here, Nmax is the maximum number of sustain discharges defined in common for each row, and Nmax = 8 in this example. Further, s satisfies the equation of 0 ≦ s ≦ 1 as a continuous variable.

  In order to realize the luminance corresponding to s * BU, in the example of the panel PDP shown in FIGS. 12 and 13, the L1C1 cell has the first three sustain pulses So6-Se6 to So8-Se8. 2 Suppression pulse (-170V) is applied. From the above discussion, it is apparent that when the luminance corresponding to s * BU is applied to the last r sustain pulses, it is appropriate to satisfy the range of the expression 1 <r ≦ 3. It is.

  The absolute value of the discharge suppressing intermediate potential (−170 V) in the example of the panel PDP in FIGS. 12 and 13 is the second potential (discharge suppressing potential = −190 V) applied to the first sustain discharge five times. The absolute value is small. As a result of these and detailed studies, when there are M sustain pulses in the row discharge period (row discharge step) of the sustain discharge period (sustain step), the first to mth (however, 2 ≦ m <M) When the suppression pulse voltage applied to the sustain discharge is Vadr, m and the suppression pulse voltage applied to the remaining (m + 1) th to last sustain pulses is Vadr, z, | Vadr, m | ≧ It has become clear that it is appropriate to satisfy the range of | Vadr, z |.

  Further, as shown in FIG. 15, the suppression pulse voltage applied to the first to m-th sustain discharge is Vadr, m, and the (m + 1) th to (m + x) th (where (m + x) <M) It has also been found that it is appropriate to satisfy the range of | Vadr, m | ≧ | Vadr, x | when the suppression pulse voltage applied to the sustain pulse up to is Vadr, x.

  Furthermore, as shown in FIG. 16, the suppression pulse voltage applied to the first to m-th sustain discharge is Vadr, m, and (m + 1) th to (m + x) th (where (m + x) <M The suppression pulse voltage to be applied to the sustain pulse up to) is Vadr, x, and is applied to the sustain pulse from the (m + x + 1) th to the (m + x + y) th (where (m + x + y) <M). It has also been found that it is appropriate to satisfy the range of | Vadr, m | ≧ | Vadr, x | ≧ | Vadr, y | when the suppression pulse voltage is Vadr, y.

  As described above, according to the present embodiment, a predetermined number (two or more, 20-30) of row electrode pairs constituting a scanning line is line-sequentially in a unit display period (one field, one frame) of an input image signal. Low gray scale display can be realized in a driving method in which display is performed by applying a second sustain pulse and applying a second potential (discharge suppression potential) to the column electrodes in accordance with display data.

It is a front view which shows typically the relationship between the row electrode pair and partition for demonstrating the conventional surface discharge alternating current type plasma display panel. 1 is an exploded perspective view of a front substrate and a rear substrate in order to explain a surface discharge AC type plasma display panel according to an embodiment of the present invention. It is a block diagram which shows the structure of the display apparatus of the surface discharge alternating current type plasma display panel of embodiment by this invention. FIG. 3 is a timing chart of applied pulses showing an outline of a method for driving a surface discharge AC type plasma display panel according to an embodiment of the present invention. FIG. 3 is a timing diagram illustrating applied pulse timings illustrating an embodiment of a surface discharge AC plasma display panel driving method according to an embodiment of the present invention. FIG. 10 is a timing diagram illustrating applied pulse timing illustrating an embodiment of a method for driving a surface discharge AC type plasma display panel according to another embodiment of the present invention. FIG. 10 is a timing diagram illustrating applied pulse timing illustrating an embodiment of a method for driving a surface discharge AC type plasma display panel according to another embodiment of the present invention. FIG. 10 is a timing diagram illustrating applied pulse timing illustrating an embodiment of a method for driving a surface discharge AC type plasma display panel according to another embodiment of the present invention. FIG. 10 is a timing diagram illustrating applied pulse timing illustrating an embodiment of a method for driving a surface discharge AC type plasma display panel according to another embodiment of the present invention. FIG. 10 is a timing diagram illustrating applied pulse timing illustrating an embodiment of a method for driving a surface discharge AC type plasma display panel according to another embodiment of the present invention. FIG. 10 is a timing diagram illustrating applied pulse timing illustrating an embodiment of a method for driving a surface discharge AC type plasma display panel according to another embodiment of the present invention. FIG. 10 is a timing diagram illustrating applied pulse timing illustrating an embodiment of a method for driving a surface discharge AC type plasma display panel according to another embodiment of the present invention. FIG. 10 is a timing diagram illustrating applied pulse timing illustrating an embodiment of a method for driving a surface discharge AC type plasma display panel according to another embodiment of the present invention. FIG. 10 is a timing diagram illustrating applied pulse timing illustrating an embodiment of a method for driving a surface discharge AC type plasma display panel according to another embodiment of the present invention. FIG. 10 is a timing diagram illustrating applied pulse timing illustrating an embodiment of a method for driving a surface discharge AC type plasma display panel according to another embodiment of the present invention. FIG. 10 is a timing diagram illustrating applied pulse timing illustrating an embodiment of a method for driving a surface discharge AC type plasma display panel according to another embodiment of the present invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Front substrate 2 Dielectric layer 2A Raised dielectric layer 3 Protective layer 4 Back substrate 5 Column electrode protective layer 7 Phosphor layer 120 Panel body 201 Synchronous separation circuit 202 Timing pulse generation circuit 203 A / D converter 204 Frame memory 205 Memory Control circuit 206 Output processing circuit 207 Read timing signal generation circuit 210 Row electrode drive circuit 212 Column electrode drive circuit C Column electrode D Cell X, Y Row electrode Kb Common bus electrode part Ka Transparent electrode part

Claims (12)

A front substrate and a rear substrate facing each other through a discharge space; a plurality of row electrodes arranged in parallel on the inner surface of the front substrate and constituting scanning lines in pairs; and the row on the inner surface of the rear substrate. A plurality of column electrodes arranged in parallel in a direction intersecting with the electrodes and constituting cells at intersections with the scanning lines, respectively,
A row discharge step in which sustain discharge is performed by applying two or more sustain pulses to each scanning line is switched in line sequence, and an address potential is applied to the column electrode based on display data at each row discharge step. Including a sustain step to
A method for driving a plasma display panel, comprising: a gradation display step in which a suppression pulse for suppressing the sustain discharge is applied to the column electrode in synchronization with the sustain pulse of the row discharge step.   In the gradation display step, the suppression pulse is selected to have a pulse width including the first sustain pulse of the row discharge step, and the sustain discharge corresponding to the gradation is adjusted according to the pulse width of the suppression pulse. The method of driving a plasma display panel according to claim 1.   In the gradation display step, the suppression pulse is selected to have a pulse number corresponding to the number of pulses from the first sustain pulse of the row discharge step, and the sustain discharge corresponding to the gradation is adjusted according to the pulse number of the suppression pulse. The method of driving a plasma display panel according to claim 1.   4. The gradation display step, wherein one of a plurality of pulse amplitudes of the suppression pulse is selected, and sustain discharge corresponding to the gradation is adjusted according to the pulse amplitude of the suppression pulse. A method for driving a plasma display panel according to claim 1.   In the gradation display step, when the number of sustain pulses in the row discharge step is M, the suppression pulse is applied only during the first to m-th (2 ≦ m <M) sustain pulse application period. 2. The method of driving a plasma display panel according to claim 1, wherein:   In the gradation display step, when the number of sustain pulses in the row discharge step is M, a first potential that does not stop the sustain discharge is applied only during the first (m + 1) th to Mth application periods. 6. The method of driving a plasma display panel according to claim 5, further comprising a gradation display step.   7. The method according to claim 1, further comprising a reset step of setting the cell to a lighting state by applying a reset pulse between the row electrodes constituting the row electrode pair prior to the sustain step. A driving method of the plasma display panel as described.   8. The method of driving a plasma display panel according to claim 7, wherein an address potential is kept constant during the reset step and an address potential corresponding to luminance is applied during the sustain step.   9. The method of driving a plasma display panel according to claim 1, wherein the sustain step is executed once during a unit display period of the input image signal.   6. The method of driving a plasma display panel according to claim 5, wherein the sustain pulse is a pulse having positive and negative polarities, and the first potential is a ground potential.   6. The plasma display panel according to claim 5, wherein the sustain pulse is a pulse having positive and negative polarities, and the first potential is a predetermined potential between the ground potential and a discharge suppression potential of the suppression pulse. Driving method.   6. The method of driving a plasma display panel according to claim 5, wherein the absolute value of the discharge suppression potential of the suppression pulse is larger than the absolute value of the first potential.

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