JP2008154078A - Receiver - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To estimate phase rotation per symbol by frequency deviation with sufficient precision by a receiver which decodes a received modulation signal. <P>SOLUTION: A delay detection means 1 performs delay detection of the modulation signal, phase rotation means A1-An provide predetermined phase rotation to delay detection results, decoding means B1-Bn decodes a signals after the phase rotation, verification means C1-Cn, D1-Dn verify decoding results with a synchronization pattern, a modulation component elimination means E1-En eliminate modulation components of the signals after the phase rotation based on the decoding results, an angle acquisition means F1-Fn, G1-Gn acquire angles based on the signals after eliminating the modulation components, angle adjustment means H1-Hn add angles equivalent to phase rotation opposite to the predetermined phase rotation to the angles and an initial phase decision means 2 decides angles acquired by the angle adjustment means as an initial phase when the synchronization pattern is detected by the verification results. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a receiver that delay-detects a received signal by, for example, a π / 4 shift QPSK method, and more particularly to a receiver that accurately estimates a phase rotation per symbol due to a frequency deviation.

  For example, in a receiver in a radio of a mobile communication system that performs radio communication, delay detection is generally used when demodulating a digital modulation signal. In the reception method using delay detection, if there is a frequency deviation, for example, the error rate deteriorates and the received signal cannot be accurately demodulated, so that the reception frequency is automatically adjusted to the transmission frequency. Automatic frequency control (AFC: Automatic Frequency Control) is required.

However, when synchronization (for example, word synchronization) is lost, the AFC cannot be controlled because the frequency deviation is unknown. For example, when the modulation method is QPSK (Quadrature Phase Shift Keying) or π / 4 shift QPSK, the difference in phase between adjacent points of the constellation is ± π / 4, and thus, per symbol due to frequency deviation. If the phase rotation is not within ± π / 4, the synchronization word cannot be detected using bit correlation.
Therefore, a configuration is generally adopted in which a synchronization phase can be detected even when a predetermined phase rotation is applied to the signal after delay detection and the frequency deviation is large.

FIG. 3 shows a configuration example of the initial phase detection circuit.
In FIG. 3, for convenience of explanation, the same reference numerals are given to components that are substantially the same as those shown in FIG. 1 that is referred to in an embodiment according to the present invention described later. There is no intention to limit the invention unnecessarily.
The initial phase detection circuit shown in FIG. 3 includes a delay detection unit 1, a plurality of n processing units W1 to Wn, and a phase detection unit 11.
Each of the processing units W1 to Wn includes one multiplier (in this example, a complex multiplier) A1 to An, one determination decoding unit B1 to Bn, one shift register C1 to Cn, One synchronization word collating unit D1 to Dn is provided.

An example of the operation performed in the initial phase detection circuit of this example is shown.
A complex baseband signal (received complex baseband signal) obtained from the received signal is input to the delay detection unit 1.
The delay detection unit 1 performs delay detection on the input reception complex baseband signal, and outputs the result (signal after delay detection) to each of the multipliers A1 to An. In this delay detection, for example, a reception complex baseband signal is multiplied by a complex conjugate signal obtained by delaying the reception complex baseband signal by one symbol (in this example, complex multiplication).

Each multiplier A1~An (in this example, complex multiplication) the predetermined value ^e jθ1 ~e jθn multiplying the signal on the input signal from delay detection section 1 ₁ a predetermined phase rotation θ by ~ giving theta _n, and outputs the multiplication result to the judgment decryption unit Bl to Bn.
For example, when n = 3, θ ₁ = −π / 4, θ ₂ = 0, and θ ₃ = + π / 4 are set.

Each determination decoding unit B1 to Bn performs threshold determination on a signal (a signal after delayed detection to which each phase rotation is given) input from each multiplier A1 to An, and decodes it to a bit signal (bit sequence signal). Then, the result is output to each of the shift registers C1 to Cn.
For example, when the modulation method is π / 4 shift QPSK, as shown in FIG. 2, the x-axis and the y-axis serve as determination threshold values, and one symbol is decoded into 2 bits.

Each shift register C1 to Cn stores the decoded bit signal input from each of the determination decoding units B1 to Bn.
Each synchronization word collation unit D1 to Dn collates the bit signal stored in each shift register C1 to Cn with the signal of the bit pattern of a predetermined synchronization word, and outputs a signal indicating the collation result to the phase detection unit 11 To do. As an example, it can be determined that a synchronization word has been detected when the degree of bit pattern correlation (coincidence) is equal to or greater than a threshold (or exceeds the threshold).

The phase detection unit 11 monitors each collation result by signals input from the n synchronization word collation units D1 to Dn, and a synchronization word is detected by any one of the synchronization word collation units Di (i = 1 to n). In this case, a negative value (−θ _i ) of the phase rotation, which is a rotation amount for pulling back the phase rotation corresponding to the synchronous word collating unit Di, is obtained and output as an initial phase.
For example, when n = 3, θ ₁ = −π / 4, θ ₂ = 0, and θ ₃ = + π / 4, when the phase rotation of θ ₁ is given, the synchronous word collation unit D1 of the system that gave the phase rotation of θ ₁ When a synchronization word is detected in ( ₁₎ , the output initial phase value is −θ ₁ = + π / 4.

As described above, the initial phase detection circuit shown in FIG. 3 can detect a synchronization word even when the frequency deviation is large, and further, n phase rotations per symbol due to the frequency deviation can be detected. Since it can be estimated from among the phase rotations θ _{1 to} θ _n, the AFC can be controlled from the detection time of the synchronization word.

Japanese Patent Laid-Open No. 2003-234791

  However, in the initial phase detection circuit as shown in FIG. 3, if the value of n, which is the number of phase rotations, is small, the initial phase is roughly estimated, and conversely if the value of n is increased, synchronization is performed with a plurality of phase rotations. Words are likely to be detected, and in any case, the estimation accuracy of the initial phase is lowered, and the AFC follow-up time is increased.

  The present invention has been made in view of such a conventional situation. For example, when performing delay detection, the present invention provides a receiver capable of accurately estimating a phase rotation per symbol due to a frequency deviation. Objective.

In order to achieve the above object, in the present invention, a receiver configured to decode a received modulated signal has the following configuration.
That is, the delay detection means delay-detects the received modulation signal. The phase rotation means gives a predetermined phase rotation to the signal of the delay detection result acquired by the delay detection means. The decoding means decodes the signal given the phase rotation by the phase rotation means. A collation unit collates the decoding result acquired by the decoding unit with a predetermined synchronization pattern. The modulation component removal means removes the modulation component contained in the signal given the phase rotation by the phase rotation means based on the decoding result acquired by the decoding means. An angle acquisition unit acquires a signal representing an angle based on the signal from which the modulation component has been removed by the modulation component removal unit. As a result of the angle adjustment means adding an angle corresponding to a phase rotation opposite to the predetermined phase rotation given by the phase rotation means to the angle represented by the signal acquired by the angle acquisition means. Obtain a signal representing the angle. The initial phase determining means determines the angle represented by the signal acquired by the angle adjusting means as the initial phase when the predetermined synchronization pattern is detected from the collation result by the collating means.
Therefore, for example, when performing delay detection, it is possible to accurately estimate the phase rotation (initial phase) per symbol due to the frequency deviation, thereby making it possible to follow the AFC at high speed.

Here, as a modulation method, for example, a π / 4 shift QPSK method is used, but other methods may be used.
Further, as the predetermined phase rotation, various phase rotation values may be used.
In addition, various patterns may be used as the predetermined synchronization pattern. As an example, a bit pattern of a synchronization word is used.
Further, in the collation between the decoding result and the synchronization pattern, for example, it is determined that a predetermined synchronization pattern has been detected when the degree of coincidence is equal to or greater than a predetermined threshold (or exceeds a predetermined threshold).
In addition, the angle acquisition unit acquires, for example, a signal (complex signal) from which the modulation component has been removed by converting it into a signal representing the angle. In this case, for example, a time corresponding to a predetermined number of symbols, etc. Averaging may be performed over a predetermined period of time.

The receiver according to the present invention has the following configuration as one configuration example.
That is, a plurality of processing units including the phase rotation unit, the decoding unit, the collating unit, the modulation component removing unit, the angle obtaining unit, and the angle adjusting unit are provided.
In the plurality of processing units, the predetermined phase rotation values given by the phase rotation means are different from each other.
The initial phase determination unit monitors the collation result by the collation unit of the plurality of processing units, and when the predetermined synchronization pattern is detected by the collation result by the collation unit of any of the processing units, The angle represented by the signal acquired by the angle adjusting means of the processing unit is determined as the initial phase.
Therefore, for example, even when the frequency deviation is large, it is possible to detect a synchronization pattern (for example, a synchronization word), and further, the phase rotation (initial phase) per symbol due to the frequency deviation at the time of detection of the synchronization pattern. Since it is possible to estimate with high accuracy, it is possible to follow AFC at high speed.

Here, various numbers may be used as the number of the plurality of processing units.
Various values may be used as the phase rotation values given by the phase rotation means of each processing unit.

  As described above, according to the receiver according to the present invention, for example, when performing delay detection, it is possible to accurately estimate the phase rotation (initial phase) per symbol due to the frequency deviation. It is possible to follow at high speed.

  Embodiments according to the present invention will be described with reference to the drawings.

A first embodiment of the present invention will be described.
FIG. 1 shows a configuration example of an initial phase detection circuit provided in a receiver according to an embodiment of the present invention.
The initial phase detection circuit of this example includes a delay detection unit 1, a plurality of n processing units V1 to Vn, and a selector 2.
Each processing unit V1 to Vn includes one multiplier (in this example, a complex multiplier) A1 to An, one determination decoding unit B1 to Bn, one shift register C1 to Cn, One synchronization word collation unit D1 to Dn, one modulation component removal unit E1 to En, one angle conversion unit F1 to Fn, one average unit G1 to Gn, and one addition The devices H1 to Hn are provided.

In the receiver of this example, a signal modulated by the π / 4 shift QPSK method on the transmission side and wirelessly transmitted from the antenna is received by the antenna, and the received signal is demodulated.
FIG. 2 shows an example of the determination decoding result of π / 4 shift QPSK.
In this example, on the xy coordinates representing the complex plane (IQ plane), the symbol point with the bit value “11” is at the position of + π / 4, and the symbol point with the bit value “01” is at the position of + 3π / 4. The symbol point with the bit value “10” is at the position −π / 4, and the symbol point with the bit value “00” is at the position −3π / 4.

An example of the operation performed in the initial phase detection circuit of this example is shown.
A complex baseband signal (received complex baseband signal) obtained from the received signal is input to the delay detection unit 1.
The delay detection unit 1 performs delay detection on the input reception complex baseband signal, and outputs the result (signal after delay detection) to each of the multipliers A1 to An. In this delay detection, for example, a reception complex baseband signal is multiplied by a complex conjugate signal obtained by delaying the reception complex baseband signal by one symbol (in this example, complex multiplication).

Each multiplier A1~An (in this example, complex multiplication) the predetermined value ^e jθ1 ~e jθn multiplying the signal on the input signal from delay detection section 1 ₁ a predetermined phase rotation θ by ~ giving theta _n, and outputs the multiplication result to the judgment decryption unit B1~Bn and each modulation component removing unit E1 to En.
For example, when n = 3, θ ₁ = −π / 4, θ ₂ = 0, and θ ₃ = + π / 4 are set.

Each determination decoding unit B1 to Bn performs threshold determination on a signal (a signal after delayed detection to which each phase rotation is given) input from each multiplier A1 to An, and decodes it to a bit signal (bit sequence signal). Then, the result is output to each of the shift registers C1 to Cn and each of the modulation component removing units E1 to En.
For example, when the modulation method is π / 4 shift QPSK, as shown in FIG. 2, the x-axis and the y-axis serve as determination threshold values, and one symbol is decoded into 2 bits.

Each shift register C1 to Cn stores the decoded bit signal input from each of the determination decoding units B1 to Bn.
Each synchronization word collation unit D1 to Dn collates the bit signal stored in each shift register C1 to Cn with the signal of the bit pattern of a predetermined synchronization word, and outputs a signal indicating the collation result to selector 2. As an example, it can be determined that a synchronization word has been detected when the degree of bit pattern correlation (coincidence) is equal to or greater than a threshold (or exceeds the threshold).

Each modulation component removal unit E1 to En uses the determination decoding result input from each determination decoding unit B1 to Bn to apply a phase rotation to the signal input from each multiplier A1 to An, thereby modulating the modulation. The component is removed, and the resulting signal is output to each angle converter F1 to Fn.
For example, when the modulation method is π / 4 shift QPSK as shown in FIG. 2, when the determination decoding result is “11”, the input signals from the multipliers A1 to An are rotated by −π / 4. When the determination decoding result is “01”, the input signal from the multipliers A1 to An is rotated by −3π / 4, and when the determination decoding result is “10”, the input signals from the multipliers A1 to An are increased by + π / 4. The input signal is rotated, and when the determination decoding result is “00”, the input signal from the multipliers A1 to An is rotated by + 3π / 4.
As a result, in an ideal reception state with no frequency deviation or noise, the signal after modulation component removal moves on the positive x-axis, and when there is a frequency deviation, the signal after modulation component removal according to the frequency deviation. Is away from the x-axis.

Each angle conversion unit F1 to Fn converts the signal (complex signal and vector) input from each modulation component removal unit E1 to En into a signal representing the angle (for example, radians), and each average unit G1 to Gn. Output to. Here, for example, tan ⁻¹ (y / x) can be used as the angle conversion formula.
Each averaging unit G1 to Gn averages the angle represented by the signal input from each angle converting unit F1 to Fn over a plurality of symbol periods to remove a noise component, and the averaging result is added to each adder. Output to H1 to Hn.

Each of the adders H1 to Hn has a negative value −θ _{1 to} −− of the rotation angle given by the multipliers A1 to An corresponding to the signals (angle averaging results) input from the averaging units G1 to Gn. θ _n is added, that is, the rotation angles θ _{1 to} θ _n given by the corresponding multipliers A _{1 to} An are subtracted from the angle averaging result, and the result is output to the selector 2. The signals output from the adders H1 to Hn represent the phase rotation angle per symbol due to the frequency deviation.

The selector 2 monitors each collation result by a signal input from the n synchronization word collation units D1 to Dn, and a sync word is detected by any one of the synchronization word collation units Di (i = 1 to n). For this, a signal (phase rotation angle) input from the adder Hi corresponding to the synchronous word collating unit Di is selected and output as an initial phase.
Through the above processing, in the initial phase detection circuit of this example, for example, even when the frequency deviation is large, one of the synchronization word collating units D1 to Dn detects the synchronization word, and at the same time, one symbol based on the frequency deviation. The hit phase rotation can be accurately estimated.

Here, the signal of a predetermined value ^e jθ1 ~e jθn for providing each phase rotation theta ₁ through? _N is input to each multiplier A1~An, for example, each multiplier being output from the rotator by unit vectors It is input to A1 to An, or preset and stored in a memory, output from the memory, and input to each multiplier A1 to An.
Further, the negative values −θ ₁ to −θ _n of the respective rotation angles input to the adders H1 to Hn are generated based on, for example, the output signal from the rotator and input to the adders H1 to Hn. Alternatively, it is preset according to the phase rotation values θ _{1 to} θ _n set in the rotator and stored in the memory, and is output from the memory and input to the adders H 1 to Hn. .

  As described above, in this example, in the initial phase detection circuit provided in the receiver using the digital modulation method, a plurality of predetermined phase rotations are given to the signal obtained by delay detection of the reception complex baseband signal, The signal to which the phase rotation is applied is individually decoded into a bit sequence and then collated with the synchronization word pattern in bit units, and together with this, the modulation component is removed from the signal to which the predetermined phase rotation is applied based on the decoding result Then, the phase rotation per symbol is detected, and the phase rotation corresponding to the predetermined phase rotation is further removed to detect the phase rotation due to the frequency deviation per symbol. When a synchronous word pattern is detected from a signal given any of the phase rotations, the phase rotation based on the frequency deviation per symbol detected from the signal given the phase rotation is set as the initial phase.

  Specifically, in the initial phase detection circuit provided in the receiver of this example, a delay detection unit 1 that multiplies a reception complex baseband signal by a complex conjugate signal obtained by delaying the reception complex baseband signal by one symbol; The n multipliers A1 to An that give a predetermined phase rotation to the delayed detection output from the delay detection unit 1 and the n multipliers A1 to An are installed in correspondence with the multipliers A1 to An. N determination decoding units B1 to Bn that determine the output as a threshold value and decode it into bit signals, and bits that are installed corresponding to the n determination decoding units B1 to Bn and output from each of the determination decoding units B1 to Bn Bit shift signals C1 to Cn that hold signals, bit signals that are installed in correspondence with the n shift registers C1 to Cn and held in the shift registers C1 to Cn, and a predetermined synchronization word pattern Illuminate by unit The n synchronized word collating units D1 to Dn for outputting the collation results and n multipliers A1 to An are installed corresponding to the determination decoding results from the respective determination decoding units B1 to Bn. N modulation component removal units E1 to En that remove modulation components from the outputs from the multipliers A1 to An, and n modulation component removal units E1 to En are installed corresponding to the n modulation component removal units E1 to En. N angle converters F1 to Fn for converting complex outputs from En into angles, and a plurality of angle outputs from the angle converters F1 to Fn installed corresponding to the n angle converters F1 to Fn. N multipliers A1 to Gn that are installed in correspondence with the n average parts G1 to Gn that are averaged over the symbol time and the average angle outputs from the average parts G1 to Gn. By subtracting the phase rotation angle given by An, 1 by frequency deviation Monitor the collation results from the n adders H1 to Hn that output the phase rotation angle per symbol and the n sync word collation units D1 to Dn, and a sync word is detected by any sync word collation unit Di. In this case, a selector 2 is provided that selects a phase rotation angle output from an adder Hi installed corresponding to the synchronous word collating unit Di and outputs it as an initial phase.

  Therefore, in the initial phase detection circuit provided in the receiver of this example, when the AFC is controlled during the synchronization acquisition in the demodulation process of the digital modulation signal, for example, the synchronization word is detected even when the frequency deviation is large. Furthermore, since the phase rotation (initial phase) per symbol due to the frequency deviation can be accurately estimated at the time of detection of the synchronization word, it is possible to follow the AFC at high speed.

  In the initial phase detection circuit provided in the receiver of this example, the delay detection means is configured by the function of the delay detection unit 1, and the phase rotation means is configured by the functions of the multipliers A1 to An. The decoding means is configured by the functions of the respective determination decoding units B1 to Bn, and the verification unit is configured by the functions of the respective shift registers C1 to Cn and the respective synchronization word verification units D1 to Dn. Modulation component removal means is configured by the functions of E1 to En, angle acquisition means is configured by the functions of the angle conversion units F1 to Fn and the average units G1 to Gn, and the functions of the adders H1 to Hn. Thus, an angle adjusting means is configured, and an initial phase determining means is configured by the function of the selector 2.

A second embodiment of the present invention will be described.
In this example, an application example of a receiver provided with an initial phase detection circuit as shown in the first embodiment is shown.
As an example, in a wireless mobile communication system having at least one base station apparatus and a plurality of mobile terminal apparatuses (or at least one mobile terminal apparatus), the mobile terminal apparatus described above is shown in the first embodiment. The receiver is provided with the initial phase detection circuit, thereby performing the initial phase control and compensating for the phase (frequency compensation). In the mobile communication system of this example, for example, wireless communication is performed between the base station apparatus and the mobile terminal apparatus using the SCPC (Single Channel Per Carrier) system using the π / 4 shift QPSK system. Done.

FIG. 4 shows a configuration example of a receiver provided in the mobile terminal apparatus of this example.
Note that the mobile terminal apparatus of this example is provided with other functions such as a transmitter, for example, but detailed description thereof is omitted in this example.
The receiver of the mobile terminal apparatus of this example includes an antenna 31, a receiving unit 32, a delay detecting unit 1 similar to that shown in FIG. 1, a decision decoding unit 33, and the same as shown in FIG. A frequency error detection unit 34 having n processing units V1 to Vn and a selector 2 and a local frequency generator 35 are provided.

An example of the operation performed in the receiver of this example is shown.
The antenna 31 receives a signal transmitted wirelessly from the communication device on the transmission side and outputs the signal to the reception unit 32.
The local frequency generator 35 is configured using, for example, a frequency synthesizer, generates a signal having a frequency (reception frequency) that is variably controlled by an external control signal, and outputs the signal to the receiving unit 32. To do.
The receiving unit 32 converts the received signal input from the antenna 31 using the signal input from the local frequency generator 35 into, for example, a baseband (BB: Base Band) signal or an intermediate frequency (IF: Interim Frequency) signal. Processing is performed, and the result is output to the delay detection unit 1.

The delay detection unit 1 delay-detects the signal input from the reception unit 32 and outputs the result to the determination decoding unit 33 and the frequency error detection unit 34.
The determination decoding unit 33 decodes the signal input from the delay detection unit 1 and acquires received data. As another configuration example, the reception data is decoded using the functions of the determination decoding units B1 to Bn included in the processing units V1 to Vn included in the frequency error detection unit 34 without including the determination decoding unit 33. It may be configured as such.

  The frequency error detection unit 34 acquires frequency error information or frequency error information (for example, initial phase information) based on the signal input from the delay detection unit 1, and the local frequency generator based on the acquired information. A control signal for controlling the frequency of the signal generated by 35 is generated, and the control signal is output to the local frequency generator 35. In this example, control is performed so that the reception frequency matches the transmission frequency (the frequency of the transmission signal used in the communication device on the transmission side).

  The frequency error detection unit 34 may have various functions for detecting frequency error information or frequency error information. As an example, the frequency error detection unit 34 uses n processing units V1 to Vn and a selector 2 as an initial stage. Phase information can be detected. In addition, the frequency error detection unit 34 has both the function of detecting the information of the initial phase and the function of detecting the information of the frequency error or the information about the frequency error by another method. It may be configured to be used by switching.

Here, the configuration of the system and apparatus according to the present invention is not necessarily limited to the configuration described above, and various configurations may be used. The present invention can also be provided as, for example, a method or method for executing the processing according to the present invention, a program for realizing such a method or method, or a recording medium for recording the program. It is also possible to provide various systems and devices.
The application field of the present invention is not necessarily limited to the above-described fields, and the present invention can be applied to various fields.
In addition, as various processes performed in the system and apparatus according to the present invention, for example, the processor executes a control program stored in a ROM (Read Only Memory) in hardware resources including a processor and a memory. A controlled configuration may be used, and for example, each functional unit for executing the processing may be configured as an independent hardware circuit.
The present invention can also be understood as a computer-readable recording medium such as a floppy (registered trademark) disk or a CD (Compact Disc) -ROM storing the control program, and the program (itself). The processing according to the present invention can be performed by inputting the program from the recording medium to the computer and causing the processor to execute the program.

It is a figure which shows the structural example of the initial phase detection circuit provided in the receiver which concerns on one Example of this invention. It is a figure which shows an example of the determination decoding result of (pi) / 4 shift QPSK. It is a figure which shows the structural example of an initial phase detection circuit. It is a figure which shows the structural example of the receiver of a mobile terminal device.

Explanation of symbols

  1 ·· Delay detection unit 2 ·· Selector 11 ·· Phase detection unit 21 ·· Mobile terminal device 31 ·· Antenna 32 ·· Reception unit 33 ·· Decoding decoding unit 34 ·· Frequency error detection 35, local frequency generator, A1 to An, multiplier, B1 to Bn, decision decoding unit, C1 to Cn, shift register, D1 to Dn, synchronous word collating unit, E1 to En, Modulation component removal unit, F1 to Fn, angle conversion unit, G1 to Gn, average unit, H1 to Hn, adder, V1 to Vn, W1 to Wn, processing unit,

Claims (2)

In a receiver that decodes a received modulated signal,
Delay detection means for delay detection of the received modulated signal;
Phase rotation means for applying a predetermined phase rotation to the signal of the delay detection result acquired by the delay detection means;
Decoding means for decoding a signal given phase rotation by the phase rotation means;
Collation means for collating the decoding result acquired by the decoding means with a predetermined synchronization pattern;
A modulation component removing unit that removes a modulation component included in the signal to which the phase rotation is given by the phase rotation unit based on the decoding result acquired by the decoding unit;
An angle acquisition means for acquiring a signal representing an angle based on the signal from which the modulation component has been removed by the modulation component removal means;
A signal representing an angle obtained as a result of adding an angle corresponding to a phase rotation opposite to the predetermined phase rotation given by the phase rotation unit to an angle represented by the signal acquired by the angle acquisition unit. An angle adjustment means to obtain;
An initial phase determination unit that determines an angle represented by a signal acquired by the angle adjustment unit as an initial phase when the predetermined synchronization pattern is detected by a verification result by the verification unit;
A receiver comprising: The receiver of claim 1,
A plurality of processing units including the phase rotation unit, the decoding unit, the collating unit, the modulation component removing unit, the angle obtaining unit, and the angle adjusting unit;
In each of the plurality of processing units, the value of the predetermined phase rotation given by the phase rotation unit is different,
The initial phase determination unit monitors the collation result by the collation unit of the plurality of processing units, and when the predetermined synchronization pattern is detected by the collation result by the collation unit of any of the processing units, Determining an angle represented by a signal acquired by the angle adjusting means of the processing unit as an initial phase;
A receiver characterized by that.

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