JP2008154052A - Load drive circuit - Google Patents

Load drive circuit Download PDF

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JP2008154052A
JP2008154052A JP2006341141A JP2006341141A JP2008154052A JP 2008154052 A JP2008154052 A JP 2008154052A JP 2006341141 A JP2006341141 A JP 2006341141A JP 2006341141 A JP2006341141 A JP 2006341141A JP 2008154052 A JP2008154052 A JP 2008154052A
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load
power supply
stabilized power
control signal
output voltage
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JP4891050B2 (en
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Takeaki Yokota
猛昭 横田
Haruhiko Yoshida
晴彦 吉田
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New Japan Radio Co Ltd
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    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

<P>PROBLEM TO BE SOLVED: To apply stable supply voltage without influencing an operation of the load to the load in starting of a DC stabilization power source, etc. <P>SOLUTION: This load drive circuit is constituted so that a P channel MOS FET 1 is connected in series between the DC stabilization power source 102 and the load, the FET 1 performs an on/off operation according to a first control signal SW1 with a first N channel MOS FET 2 connected to its gate, on the other hand, a sub-constant current source 5 and a second N channel MOS FET 2 which operates according to a second control signal SW2 from the outside are connected in series between a source and a ground of the MOS FET 1, the sub-constant current source 5 is connected to the DC stabilization power source 102 by the second control signal SW2 prior to applying of the DC stabilization power source 102 to the load of output voltage, the MOS FET 1 is turned on by the first control signal SW1 after stabilization of the output voltage to apply voltage to the load. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は、直流安定化電源と負荷との間に設けられ、負荷へ対する電源電圧の印加の制御を行う負荷駆動回路に係り、特に、出力電圧特性の向上等を図ったものに関する。   The present invention relates to a load drive circuit that is provided between a direct current stabilized power supply and a load and controls the application of a power supply voltage to the load, and particularly relates to an output voltage characteristic that is improved.

従来、この種の回路としては、例えば、図４に示されたような構成のものが良く知られている。
以下、同図を参照しつつ、この従来回路について説明する。
この従来回路は、直流安定化電源（図４においては「ＤＣ−ＲＥＧ」と表記）１０２Ａの出力電圧を、負荷駆動回路１０１Ａを介して、負荷としてのＬＥＤへ印加できるようにしたものである。
直流安定化電源１０２Ａは、スイッチングレギュレータやＬＤＯ等による公知・周知の構成を有してなる直流安定化電源である。 Conventionally, as this type of circuit, for example, one having a configuration as shown in FIG. 4 is well known.
The conventional circuit will be described below with reference to FIG.
In this conventional circuit, the output voltage of a DC stabilized power supply (denoted as “DC-REG” in FIG. 4) 102A can be applied to an LED as a load via a load driving circuit 101A.
The stabilized DC power supply 102A is a stabilized DC power supply having a known and well-known configuration such as a switching regulator or LDO.

負荷駆動回路１０１Ａは、直流安定化電源１０２Ａと負荷との間に直列に設けられたＰチャンネルＭＯＳ ＦＥＴ（以下、「ＰＭＯＳトランジスタ」と称する）ＭＰと、このＰＭＯＳトランジスタＭＰのゲートとグランドとの間に直列接続されて設けられたＮチャンネルＭＯＳ ＦＥＴ（以下、「ＮＭＯＳトランジスタ」と称する）ＭＮ１とを主たる構成要素として構成されてなるものである。
そして、負荷駆動回路１０１Ａには、複数のＬＥＤと、このＬＥＤに直列接続された定電流源Ｉrefとが負荷として接続されたものとなっている。 The load drive circuit 101A includes a P-channel MOS FET (hereinafter referred to as “PMOS transistor”) MP provided in series between the DC stabilized power supply 102A and a load, and the gate of the PMOS transistor MP and the ground. The main component is an N-channel MOS FET (hereinafter referred to as “NMOS transistor”) MN1 provided in series.
A plurality of LEDs and a constant current source Iref connected in series to the LEDs are connected to the load drive circuit 101A as a load.

かかる構成において、ＮＭＯＳトランジスタＭＮ１のゲートに、負荷駆動信号として論理値Ｈｉｇｈに相当するゲート電圧が印加されることにより、ＮＭＯＳトランジスタＭＮ１及びＰＭＯＳトランジスタＭＰが共にオン状態となり、直流安定化電源１０２Ａの出力電圧ＶoutがＰＭＯＳトランジスタＭＰを介して負荷へ印加されることとなる。
一方、ＮＭＯＳトランジスタＭＮ１のゲートに、負荷駆動信号として論理値Ｌｏｗに相当するゲート電圧が印加されることにより、上述の場合とは逆に、負荷への電源電圧の印加は遮断されることとなる。
なお、このような直流安定化電源の出力電圧の負荷への安定した印加を目的としたものとしては、この他に、例えば、特許文献１等に開示されたようなものもある。
特開平１１−１７８３４３号公報（第３−４頁、図１） In such a configuration, when a gate voltage corresponding to the logical value High is applied as a load drive signal to the gate of the NMOS transistor MN1, both the NMOS transistor MN1 and the PMOS transistor MP are turned on, and the output of the DC stabilized power supply 102A. The voltage Vout is applied to the load via the PMOS transistor MP.
On the other hand, by applying a gate voltage corresponding to the logical value Low as a load driving signal to the gate of the NMOS transistor MN1, contrary to the above case, the application of the power supply voltage to the load is cut off. .
In addition to the above, the purpose of the stable application of the output voltage of the DC stabilized power supply to the load is disclosed in, for example, Patent Document 1 and the like.
JP-A-11-178343 (page 3-4, FIG. 1)

ところで、スイッチングレギュレータやＬＤＯ等の直流安定化電源は、負荷が無負荷状態から重負荷状態に切り替わった際、出力電圧変動が最小となるよう動作する構成となっている。
しかし、かかる直流安定化電源は、一般には、負荷変動時の出力電圧変動分を、誤差増幅器へ帰還し、出力電圧を制御する構成となっているため、出力電圧の変動が生じてから規定電圧へ復帰するまでに遅延を生ずる。この誤差増幅器による制御遅れにより、負荷変動時の出力電圧は、一定ではなく、制御遅れの期間中には電圧変動が生ずることとなる。 By the way, DC stabilized power supplies such as switching regulators and LDOs are configured to operate such that output voltage fluctuation is minimized when the load is switched from a no-load state to a heavy load state.
However, such a stabilized DC power supply generally has a configuration in which the output voltage fluctuation at the time of load fluctuation is fed back to the error amplifier to control the output voltage. There is a delay before returning. Due to the control delay caused by the error amplifier, the output voltage at the time of load fluctuation is not constant, and voltage fluctuation occurs during the control delay period.

図５には、かかる従来回路における負荷駆動信号に対する出力電圧の変動の様子を説明する概略波形図が示されており、以下、同図を参照しつつ、上述の制御遅れに起因する出力電圧変動について説明する。
図４に示された回路において、負荷駆動信号としてＰＷＭ信号が入力されて、そのＰＷＭ信号が論理値Ｌｏｗに相当する所定の電圧から論理値Ｈｉｇｈに相当する電圧となると（図５（Ａ）参照）、直流安定化電源１０２Ａの出力電圧がＬＥＤに印加され、ＬＥＤは点灯状態となるが、上述したように、この出力電圧の立ち上がりの際に、制御遅れに起因して負荷電圧ＶLOADが低下する期間が生ずる（図５（Ｂ）及び図５（Ｃ）の符号Ｂの部分参照）。 FIG. 5 is a schematic waveform diagram for explaining how the output voltage fluctuates with respect to the load drive signal in the conventional circuit. Hereinafter, referring to FIG. 5, the output voltage fluctuation caused by the control delay described above is shown. Will be described.
In the circuit shown in FIG. 4, when a PWM signal is input as a load drive signal, the PWM signal changes from a predetermined voltage corresponding to the logical value Low to a voltage corresponding to the logical value High (see FIG. 5A). ) The output voltage of the DC stabilized power supply 102A is applied to the LED, and the LED is turned on. As described above, the load voltage VLOAD is reduced due to the control delay when the output voltage rises. A period occurs (refer to the portion denoted by reference character B in FIGS. 5B and 5C).

この負荷電圧の降下により、ＬＥＤが点灯しない期間が生じ、ＰＷＭ信号のデューティ比に応じた輝度が得られないという問題を生ずる。
かかる問題の解決策として、例えば、直流安定化電源１０２Ａの出力とグランドとの間に、出力キャパシタを接続し、電圧降下を抑圧する方法が考えられるが、出力電圧の降下を完全に零とすることはできず、負荷に大きな負荷電流が必要とされる場合には、それに応じて大容量のキャパシタが必要となり、コストの増大を招くだけでなく、回路が大型化する等の欠点を生ずる。 Due to the drop in the load voltage, a period in which the LED is not turned on occurs, and there arises a problem that luminance corresponding to the duty ratio of the PWM signal cannot be obtained.
As a solution to such a problem, for example, a method is conceivable in which an output capacitor is connected between the output of the DC stabilized power supply 102A and the ground to suppress the voltage drop. When a large load current is required for the load, a large-capacitance capacitor is required accordingly, which not only increases the cost but also increases the size of the circuit.

一方、スイッチングレギュレータやＬＤＯなどの直流安定化電源は、その回路構成上、基本的に、その起動時には出力電圧は徐々に立ち上がり、急峻な立ち上がりの出力電圧を発生することはできないものとなっている。
仮に、負荷駆動回路１０１Ａの動作を制御して負荷に出力電圧を供給しない状態で、直流安定化電源１０２Ａを起動し、その出力電圧が安定した状態となった後に、負荷駆動回路１０１Ａを介して負荷へ出力電圧を印加するようにしても、直流安定化電源１０２Ａの負荷変動に対する制御遅れによって、やはり負荷電圧ＶLOADは急峻な立ち上がりとはならない。 On the other hand, DC stabilized power supplies such as switching regulators and LDOs basically have an output voltage that gradually rises at the start-up and cannot generate a steeply rising output voltage due to its circuit configuration. .
If the operation of the load drive circuit 101A is controlled and no output voltage is supplied to the load, the DC stabilized power supply 102A is activated, and after the output voltage becomes stable, the load drive circuit 101A is connected via the load drive circuit 101A. Even when the output voltage is applied to the load, the load voltage VLOAD does not rise sharply due to the control delay with respect to the load fluctuation of the DC stabilized power supply 102A.

本発明は、上記実状に鑑みてなされたもので、直流安定化電源の起動時、負荷の接続や切断時などにおいて、負荷の動作に影響を与えることのない安定した負荷電圧を出力することのできる負荷駆動回路を提供するものである。   The present invention has been made in view of the above circumstances, and outputs a stable load voltage that does not affect the operation of the load when the DC stabilized power supply is started or when the load is connected or disconnected. Provided is a load drive circuit that can be used.

上記本発明の目的を達成するため、本発明に係る負荷駆動回路は、
外部からの第１の制御信号に応じて動作が制御される負荷駆動用スイッチ素子を直流安定化電源とグランドとの間に負荷と直列接続して前記直流安定化電源の出力電圧の負荷への印加を制御可能にするように構成されてなる負荷駆動回路であって、
前記直流安定化電源が接続される接続点とグランドとの間に、外部からの第２の制御信号によりオン・オフ制御可能な副スイッチ素子と、副負荷手段とを直列接続して設け、
前記直流安定化電源に接続される負荷の所望する駆動状態に対応して外部において生成される負荷駆動信号の論理値Ｈｉｇｈに相当するレベルへの立ち上がりから、前記直流安定化電源の負荷変動に対する制御遅れ以上の長さに設定された所定の遅延時間経過後に論理値Ｈｉｇｈに相当するレベルに立ち上がり、所定のパルス幅を有してなる前記第１の制御信号と、
前記負荷駆動信号の論理値Ｈｉｇｈに相当するレベルへの立ち上がりに同期して論理値Ｈｉｇｈに相当するレベルに立ち上がり、前記遅延時間に等しいパルス幅を有してなる前記第２の制御信号とを印加し、前記直流安定化電源の出力電圧の安定化後に当該出力電圧の前記負荷への印加を可能としてなるものである。
また、本発明の目的を達成するため、外部からの第１の制御信号に応じて動作が制御される負荷駆動用スイッチ素子を直流安定化電源とグランドとの間に負荷と直列接続して前記直流安定化電源の出力電圧の負荷への印加を制御可能にするように構成されてなる負荷駆動回路であって、
前記直流安定化電源が接続される接続点とグランドとの間に、外部からの第２の制御信号によりオン・オフ制御可能な副スイッチ素子と、副負荷手段とを直列接続して設け、
前記直流安定化電源への入力電圧の立ち上がりから、前記直流安定化電源の起動時に出力電圧が安定するまでの時間以上の長さに設定された所定の遅延時間経過後に論理値Ｈｉｇｈに相当するレベルに立ち上がり、所定のパルス幅を有してなる前記第１の制御信号と、
少なくとも前記直流安定化電源への入力電圧の立ち上がりに論理値Ｈｉｇｈに相当するレベルにあり、前記所定の遅延時間経過後に論理値Ｌｏｗに相当するレベルとなる前記第２の制御信号を印加し、前記直流安定化電源の出力電圧の安定化後に当該出力電圧の前記負荷への印加を可能としてなるものも好適である。 In order to achieve the above object of the present invention, a load driving circuit according to the present invention includes:
A load driving switch element whose operation is controlled in accordance with a first control signal from the outside is connected in series with the load between the DC stabilized power supply and the ground, and the output voltage of the DC stabilized power supply is applied to the load. A load driving circuit configured to be able to control application,
A sub-switch element that can be controlled to be turned on / off by a second control signal from the outside, and a sub-load means are connected in series between a connection point to which the DC stabilized power source is connected and the ground,
Control of load fluctuation of the DC stabilized power supply from the rise to the level corresponding to the logical value High of the load drive signal generated externally corresponding to the desired drive state of the load connected to the DC stabilized power supply The first control signal rising to a level corresponding to the logical value High after a predetermined delay time set to a length equal to or longer than the delay and having a predetermined pulse width;
Synchronously with the rise of the load driving signal to the level corresponding to the logical value High, the second control signal having the pulse width equal to the delay time is applied to rise to the level corresponding to the logical value High. Then, after the output voltage of the DC stabilized power supply is stabilized, the output voltage can be applied to the load.
In order to achieve the object of the present invention, a load driving switch element whose operation is controlled in response to a first control signal from the outside is connected in series with a load between a DC stabilized power source and a ground. A load driving circuit configured to be able to control application of an output voltage of a direct current stabilized power supply to a load,
A sub-switch element that can be controlled to be turned on / off by a second control signal from the outside, and a sub-load means are connected in series between a connection point to which the DC stabilized power source is connected and the ground,
A level corresponding to the logical value High after a lapse of a predetermined delay time set to a time longer than the time from the rising of the input voltage to the DC stabilized power supply until the output voltage is stabilized when the DC stabilized power supply is started. And the first control signal having a predetermined pulse width,
Applying the second control signal which is at a level corresponding to the logical value High at least at the rise of the input voltage to the DC stabilized power supply and becomes a level corresponding to the logical value Low after the predetermined delay time has elapsed, It is also preferable to make it possible to apply the output voltage to the load after stabilizing the output voltage of the DC stabilized power supply.

本発明によれば、直流安定化電源における制御遅れに起因する出力電圧変動の影響を負荷に与えることがなく、安定した電源電圧の印加が可能となるという効果を奏するものである。
また、負荷駆動回路の動作を考慮して、直流安定化電源が無負荷となる場合には、直流安定化電源を待機モードとすることができ、それによって、装置全体の消費電力の削減を行うことができる。 According to the present invention, there is an effect that it is possible to apply a stable power supply voltage without giving an influence of an output voltage fluctuation caused by a control delay in a DC stabilized power supply to a load.
In addition, in consideration of the operation of the load driving circuit, when the DC stabilized power supply becomes no load, the DC stabilized power supply can be set to the standby mode, thereby reducing the power consumption of the entire apparatus. be able to.

以下、本発明の実施の形態について、図１乃至図３を参照しつつ説明する。
なお、以下に説明する部材、配置等は本発明を限定するものではなく、本発明の趣旨の範囲内で種々改変することができるものである。
最初に、本発明の実施の形態における負荷駆動回路の回路構成例について、図１を参照しつつ説明する。
本発明の実施の形態における負荷駆動回路１０１は、直流電圧出力端子１５と負荷駆動端子１６との間に、負荷駆動用スイッチ素子としてのＰチャンネルＭＯＳ ＦＥＴ（図１においては「ＭＰ」と表記）１が直列接続されて設けられている。すなわち、ＰチャンネルＭＯＳ ＦＥＴ（以下「ＰＭＯＳ」と称する）１のソースは、直流電圧出力端子１５に、ドレインは負荷駆動端子１６に、それぞれ接続される一方、ゲートには、第１のＮチャンネルＭＯＳ ＦＥＴ（図１においては「ＭＮ１」と表記）２のドレインが接続されたものとなっている。
また、ＰＭＯＳ１のゲートとソースの間には、ゲート・ソース間抵抗器４が接続されている。 Hereinafter, embodiments of the present invention will be described with reference to FIGS. 1 to 3.
The members and arrangements described below do not limit the present invention and can be variously modified within the scope of the gist of the present invention.
First, an example of the circuit configuration of the load driving circuit according to the embodiment of the present invention will be described with reference to FIG.
The load drive circuit 101 according to the embodiment of the present invention includes a P-channel MOS FET (denoted as “MP” in FIG. 1) as a load drive switch element between the DC voltage output terminal 15 and the load drive terminal 16. 1 are connected in series. That is, the source of a P-channel MOS FET (hereinafter referred to as “PMOS”) 1 is connected to the DC voltage output terminal 15, the drain is connected to the load drive terminal 16, and the gate is connected to the first N-channel MOS FET. The drain of the FET (denoted as “MN1” in FIG. 1) 2 is connected.
A gate-source resistor 4 is connected between the gate and source of the PMOS 1.

第１のＮチャンネルＭＯＳ ＦＥＴ（以下「第１のＮＭＯＳ」と称する）２のソースは、グランドに接続される一方、ゲートには、後述するように外部から第１の制御信号ＳＷ１が印加されるようになっている。
また、ＰＭＯＳ１のソースとグランドとの間には、ソース側から順に、副負荷手段（以下「副負荷」と称する）としての副定電流源５と、副スイッチ素子としての第２のＮチャンネルＭＯＳ ＦＥＴ（図１においては「ＭＮ２」と表記）３とが直列接続されている。
すなわち、第２のＮチャンネルＭＯＳ ＦＥＴ（以下「第２のＮＭＯＳ」と称する）３のドレインは、副定電流源５に接続される一方、ソースは、グランドに接続されている。また、第２のＮＭＯＳ３のゲートには、後述するよう外部から第２の制御信号ＳＷ２が印加されるようになっている。 The source of the first N-channel MOS FET (hereinafter referred to as “first NMOS”) 2 is connected to the ground, while the gate is supplied with a first control signal SW1 from the outside as will be described later. It is like that.
Further, between the source of the PMOS 1 and the ground, in order from the source side, a sub constant current source 5 as sub load means (hereinafter referred to as “sub load”) and a second N channel MOS as a sub switch element. An FET 3 (denoted as “MN2” in FIG. 1) 3 is connected in series.
That is, the drain of the second N-channel MOS FET (hereinafter referred to as “second NMOS”) 3 is connected to the sub-constant current source 5, while the source is connected to the ground. A second control signal SW2 is applied to the gate of the second NMOS 3 from the outside as will be described later.

この負荷駆動回路１０１に接続される直流安定化電源（図１においては「ＤＣ−ＲＥＧ」と表記）１０２は、スイッチングレギュレータやＬＤＯ等の公知・周知の構成を有してなるもので、外部からの印加電圧ＶINを安定化し、直流電圧として出力可能に構成されたものである。
この直流安定化電源１０２の出力電圧は、直流電圧出力端子１５を介して負荷駆動回路１０１へ入力されるようになっている。
また、直流安定化電源１０２の出力電圧は、直流電圧出力端子１５とグランドとの間に直列接続されて設けられた分圧用第１及び第２の抵抗器７，８により分圧され、この抵抗器７，８の接続点における分圧電圧が直流安定化電源１０２へフィードバックされるよう構成されている。すなわち、直流安定化電源１０２において、上述のフィードバック電圧は、通常、直流安定化電源１０２内に設けられている誤差増幅器（図示せず）へ入力されて、出力電圧が一定電圧に保持されるよう制御されるものとなっている。 The stabilized DC power supply (denoted as “DC-REG” in FIG. 1) 102 connected to the load drive circuit 101 has a known and well-known configuration such as a switching regulator and LDO. The applied voltage VIN is stabilized so that it can be output as a DC voltage.
The output voltage of the DC stabilized power supply 102 is input to the load driving circuit 101 via the DC voltage output terminal 15.
Further, the output voltage of the DC stabilized power source 102 is divided by the first and second resistors 7 and 8 for voltage division provided in series between the DC voltage output terminal 15 and the ground. The divided voltage at the connection point of the devices 7 and 8 is fed back to the DC stabilized power supply 102. That is, in the DC stabilized power supply 102, the above feedback voltage is normally input to an error amplifier (not shown) provided in the DC stabilized power supply 102 so that the output voltage is maintained at a constant voltage. It is to be controlled.

一方、負荷駆動端子１６には、負荷が接続されるが、本発明の実施の形態においては、負荷駆動端子１６とグランドとの間に、負荷として、複数のＬＥＤ１１−１〜１１−ｎと、主定電流源１２が直列接続されて設けられている。
なお、複数のＬＥＤ１１−１〜１１−ｎは、各々のアノードが負荷駆動端子１６側に、各々のカソードがグランド側に、それぞれ位置するように直列接続されたものとなっている。 On the other hand, a load is connected to the load drive terminal 16, but in the embodiment of the present invention, a plurality of LEDs 11-1 to 11-n as loads between the load drive terminal 16 and the ground, A main constant current source 12 is provided in series.
The plurality of LEDs 11-1 to 11-n are connected in series so that each anode is located on the load drive terminal 16 side and each cathode is located on the ground side.

次に、かかる構成における基本的な動作について説明すれば、まず、ＰＭＯＳ１は、第１のＮＭＯＳ２のゲートに外部から印加される第１の制御信号ＳＷ１が論理値Ｈｉｇｈに相当するレベルとなると、第１のＮＭＯＳ２と共にオン状態となり、直流安定化電源１０２の出力電圧が負荷に印加されることとなる。
一方、第１の制御信号ＳＷ１が論理値Ｌｏｗに相当するレベルとされると、第１のＮＭＯＳ２がオフ状態になると共にＰＭＯＳ１もオフ状態となり、直流安定化電源１０１の出力電圧の負荷への印加が遮断されることとなる。 Next, the basic operation in such a configuration will be described. First, when the first control signal SW1 applied from the outside to the gate of the first NMOS2 becomes a level corresponding to the logical value High, 1 is turned on together with the NMOS 2 and the output voltage of the DC stabilized power supply 102 is applied to the load.
On the other hand, when the first control signal SW1 is set to a level corresponding to the logic value Low, the first NMOS 2 is turned off and the PMOS 1 is also turned off, so that the output voltage of the DC stabilized power supply 101 is applied to the load. Will be blocked.

次に、第２のＮＭＯＳ３のゲートに外部から印加される第２の制御信号ＳＷ２が論理値Ｈｉｇｈに相当するレベルとなると、第２のＮＭＯＳ３がオン状態となり、副負荷としての副定電流源５が直流安定化電源１０２の負荷となる。
ここで、副負荷としての副定電流源５の電流値ＩＤは、主負荷である複数のＬＥＤ１１−１〜１１−ｎに流れる電流を決定する主定電流源１２の電流値ＩREFと同一に設定されたものとなっている。
なお、副負荷である副定電流源５は、主負荷、すなわち、複数のＬＥＤ１１−１〜１１−ｎに流れる電流と同一電流が流れる抵抗器などに置換しても好適である。 Next, when the second control signal SW2 applied from the outside to the gate of the second NMOS 3 becomes a level corresponding to the logical value High, the second NMOS 3 is turned on, and the sub constant current source 5 as a sub load is turned on. Becomes a load of the DC stabilized power supply 102.
Here, the current value ID of the sub constant current source 5 as the sub load is set to be the same as the current value IREF of the main constant current source 12 that determines the current flowing through the plurality of LEDs 11-1 to 11-n as the main load. It has been made.
The sub-constant current source 5 that is a sub-load is also preferably replaced with a main load, that is, a resistor through which the same current as the current flowing through the plurality of LEDs 11-1 to 11-n flows.

次に、より具体的な動作形態の第１の実施例について、図２を参照しつつ説明する。
まず、第１の制御信号ＳＷ１と第２の制御信号ＳＷ２は、外部の回路で発生される所定のデューティ比を有した繰り返しパルス信号である負荷駆動信号（図２（Ａ））に対して、それぞれ次述するようなタイミングで生成されるものとされている。
ここで、負荷駆動信号は、主負荷であるＬＥＤ１１−１〜１１−ｎの所望する駆動状態に対応して外部において生成されるパルス信号である。 Next, a first example of a more specific operation mode will be described with reference to FIG.
First, the first control signal SW1 and the second control signal SW2 are in response to a load drive signal (FIG. 2A) that is a repetitive pulse signal having a predetermined duty ratio generated by an external circuit. Each is generated at the timing described below.
Here, the load drive signal is a pulse signal generated externally corresponding to a desired drive state of the LEDs 11-1 to 11-n as the main loads.

すなわち、第１の制御信号ＳＷ１は、負荷駆動信号の立ち上がりに対して所定遅延時間ｔD遅れて論理値Ｈｉｇｈに相当するレベルに立ち上がる信号となっており、そのパルス幅は、負荷駆動信号に一致したものとなっている（図２（Ｃ）参照）。
ここで、遅延時間ｔＤは、従来技術で説明したように直流安定化電源１０２における誤差増幅器の制御遅れ時間以上の長さに設定されたものである。 That is, the first control signal SW1 is a signal that rises to a level corresponding to the logical value High after a predetermined delay time tD with respect to the rise of the load drive signal, and its pulse width coincides with the load drive signal. (See FIG. 2C).
Here, the delay time tD is set to a length equal to or longer than the control delay time of the error amplifier in the DC stabilized power supply 102 as described in the prior art.

一方、第２の制御信号ＳＷ２は、負荷駆動信号の論理値Ｈｉｇｈへの立ち上がりに同期して、同じく論理値Ｈｉｇｈに相当するレベルに立ち上がるものとなっており、そのパルス幅は、上述の遅延時間ｔDに相当するものとなっている（図２（Ｂ）参照）。   On the other hand, the second control signal SW2 rises to a level corresponding to the logical value High in synchronization with the rise of the load drive signal to the logical value High, and its pulse width is equal to the delay time described above. This corresponds to tD (see FIG. 2B).

しかし、負荷駆動信号が論理値Ｌｏｗから論理値Ｈｉｇｈへ切り換わると、最初に第２の制御信号ＳＷ２が負荷駆動信号と同様に論理値Ｌｏｗから論理値Ｈｉｇｈへ切り換わり、それによって、第２のＮＭＯＳ３がオン状態となり、直流安定化電源１０２に対して、副負荷としての副定電流源５が接続されることとなる。この時点において、第１のＮＭＯＳ２のゲート信号となる第１の制御信号ＳＷ１は、論理値Ｌｏｗに相当するレベルであるので（図２（Ａ）〜図２（Ｃ）参照）、第１のＮＭＯＳ２はオフ状態となっている。   However, when the load drive signal is switched from the logic value Low to the logic value High, the second control signal SW2 is first switched from the logic value Low to the logic value High in the same manner as the load drive signal. The NMOS 3 is turned on, and the sub constant current source 5 as a sub load is connected to the DC stabilized power source 102. At this time, since the first control signal SW1 that is the gate signal of the first NMOS 2 is at a level corresponding to the logic value Low (see FIGS. 2A to 2C), the first NMOS 2 Is off.

直流安定化電源１０２は、副定電流源５が接続される以前の無負荷状態から、副定電流源５が接続された負荷状態に切り換わったことにより、出力電圧変動を最小とするよう動作するが、その内部に設けられている誤差増幅器（図示せず）の制御遅れにより出力電圧の低下が生ずる（図２（Ｄ）の符号Ａの部分参照）。
そして、直流安定化電源１０２の誤差増幅器の制御遅れ期間を過ぎると、出力電圧は規定電圧に復帰し（図２（Ｄ）参照）、第２の制御信号ＳＷ２は、論理値Ｈｉｇｈから論理値Ｌｏｗに相当するレベルとなる（図２（Ｂ）参照）。これによって、第２のＮＭＯＳ３は、オフ状態となり副負荷としての副定電流源５の直流安定化電源１０２の接続が断たれることとなる。 The stabilized DC power supply 102 operates so as to minimize fluctuations in output voltage by switching from a no-load state before the auxiliary constant current source 5 is connected to a load state to which the auxiliary constant current source 5 is connected. However, the output voltage is lowered due to the control delay of an error amplifier (not shown) provided therein (see the portion A in FIG. 2D).
When the control delay period of the error amplifier of the DC stabilized power supply 102 has passed, the output voltage returns to the specified voltage (see FIG. 2D), and the second control signal SW2 is changed from the logical value High to the logical value Low. (See FIG. 2B). As a result, the second NMOS 3 is turned off, and the connection of the DC stabilized power source 102 of the sub constant current source 5 as a sub load is disconnected.

一方、第１の制御信号ＳＷ１は、直流安定化電源１０２の出力電圧が規定電圧になった後に、第２の制御信号ＳＷ２が論理値Ｈｉｇｈから論理値Ｌｏｗへ切り換わると同時に、それとは逆に論理値Ｌｏｗから論理値Ｈｉｇｈに相当するレベルとなり（図２（Ｂ）及び図２（Ｃ）参照）、ＰＭＯＳ１が第１のＮＭＯＳ２と共にオン状態となる。その結果、直流安定化電源１０２の出力電圧が規定電圧の状態で、主負荷である複数のＬＥＤ１１−１〜１１−ｎ及び主定電流源１２に印加されることとなる（図２（Ｂ）、図２（Ｃ）及び図２(Ｅ）参照。）   On the other hand, the first control signal SW1 is opposite to the second control signal SW2 that switches from the logical value High to the logical value Low after the output voltage of the DC stabilized power supply 102 reaches the specified voltage. The level corresponding to the logic value High is changed from the logic value Low (see FIGS. 2B and 2C), and the PMOS1 is turned on together with the first NMOS2. As a result, the output voltage of the DC stabilized power supply 102 is applied to the plurality of LEDs 11-1 to 11-n and the main constant current source 12 as the main load in a state where the output voltage is a specified voltage (FIG. 2B). (Refer to FIG. 2C and FIG. 2E.)

このように、第１の実施例においては、ＰＭＯＳ１をオン状態とする前に、第２のＮＭＯＳ３をオン状態とすることにより、直流安定化電源１０２の誤差増幅器の制御遅れによる出力電圧降下の影響を主負荷としての複数のＬＥＤ１１−１〜１１−ｎへ与えずに、負荷へ印加される出力電圧の波形が改善される。
例えば、ＬＥＤ１１−１〜１１−ｎをＰＷＭ信号によって輝度制御する場合などには、第１の制御信号ＳＷ１を、負荷駆動信号の立ち上がり及び立ち下がりの双方に対して、それぞれ先の遅延時間ｔDを有する信号として第１のＮＭＯＳ２のゲートに印加することで、ＬＥＤ１１−１〜１１−ｎに加わるる負荷電圧（負荷駆動端子１６における電圧）のデューティ比は、負荷駆動信号と同一とすることができる。これにより、負荷駆動信号であるＰＷＭ信号のデューティ比とＬＥＤ１１−１〜１１−ｎの輝度のリニアリティーを保つことができ、高精度の起動制御が可能となる。 As described above, in the first embodiment, the second NMOS 3 is turned on before the PMOS 1 is turned on, whereby the influence of the output voltage drop due to the control delay of the error amplifier of the DC stabilized power supply 102 is affected. Is applied to the plurality of LEDs 11-1 to 11-n as the main load, and the waveform of the output voltage applied to the load is improved.
For example, when controlling the luminance of the LEDs 11-1 to 11-n with a PWM signal, the first control signal SW1 is set to the previous delay time tD with respect to both the rise and fall of the load drive signal. The duty ratio of the load voltage (voltage at the load drive terminal 16) applied to the LEDs 11-1 to 11-n can be made the same as that of the load drive signal by applying it to the gate of the first NMOS 2 as a signal having it. . As a result, the linearity of the duty ratio of the PWM signal, which is the load drive signal, and the luminance of the LEDs 11-1 to 11-n can be maintained, and high-accuracy start-up control is possible.

次に、第２の実施例について、図３を参照しつつ説明する。
この第２の実施例は、直流安定化電源１０２の起動時における動作制御例である。
まず、直流安定化電源１０２への入力電圧ＶIN が図３（Ａ）に示されたように、ある時点で零から所定電圧へ立ち上がったとする。
これに対して、直流安定化電源１０２の出力電圧は、既に述べたように内部の誤差増幅器の制御遅れに起因して入力電圧印加後から徐々に上昇してゆき、所定の遅延時間ｔD経過後に規定電圧に達する（図３（Ｄ）参照）。 Next, a second embodiment will be described with reference to FIG.
The second embodiment is an example of operation control when the DC stabilized power supply 102 is started up.
First, it is assumed that the input voltage VIN to the DC stabilized power supply 102 rises from zero to a predetermined voltage at a certain time as shown in FIG.
On the other hand, the output voltage of the DC stabilized power supply 102 gradually increases after application of the input voltage due to the control delay of the internal error amplifier as described above, and after a predetermined delay time tD has elapsed. The specified voltage is reached (see FIG. 3D).

そこで、直流安定化電源１０２の起動時、すなわち、入力電圧ＶINの印加時において、第１の制御信号ＳＷ１として論理値Ｌｏｗに相当するレベルの信号を第１のＮＭＯＳ２のゲートに、第２の制御信号ＳＷ２として論理値Ｈｉｇｈに相当するレベルの信号を第２のＮＭＯＳ３のゲートに、それぞれ印加する（図３（Ａ）〜図３（Ｃ）参照）。
なお、直流安定化電源１０２の起動時以前から第１の制御信号ＳＷ１を論理値Ｌｏｗに相当するレベルとし、第２の制御信号ＳＷ２を論理値Ｈｉｇｈに相当するレベルに設定しておくことが動作の安定性等の観点から好ましい。 Therefore, when the DC stabilized power supply 102 is started, that is, when the input voltage VIN is applied, a signal corresponding to the logical value Low is supplied to the gate of the first NMOS 2 as the first control signal SW1, and the second control is performed. A signal having a level corresponding to the logical value High is applied to the gate of the second NMOS 3 as the signal SW2 (see FIGS. 3A to 3C).
Note that the first control signal SW1 is set to a level corresponding to the logical value Low and the second control signal SW2 is set to a level corresponding to the logical value High before the DC stabilized power supply 102 is activated. It is preferable from the viewpoint of stability.

これによって、直流安定化電源１０２の起動時には、副負荷としての副定電流源５のみが接続された状態となる。
そして、直流安定化電源１０２の起動時から遅延時間ｔD経過した時点、すなわち、直流安定化電源１０２の出力電圧が安定した時点において、第１の制御信号ＳＷ１を論理値Ｌｏｗから論理値Ｈｉｇｈに相当するレベルとする一方、第２の制御信号ＳＷ２を論理値Ｈｉｇｈから論理値Ｌｏｗに相当するレベルとする（図３（Ａ）〜図３（Ｄ）参照）。 As a result, when the DC stabilized power supply 102 is started, only the sub constant current source 5 as a sub load is connected.
Then, when the delay time tD has elapsed since the start of the DC stabilized power supply 102, that is, when the output voltage of the DC stabilized power supply 102 is stabilized, the first control signal SW1 corresponds to the logic value High from the logic value Low. On the other hand, the second control signal SW2 is set to a level corresponding to the logical value Low from the logical value High (see FIGS. 3A to 3D).

その結果、第２のＮＭＯＳ３がオフ状態となり、副定電流源５と直流安定化電源１０２の接続状態が遮断される一方、主負荷であるＬＥＤ１１−１〜１１−ｎ及び主定電流源１２が直列安定化電源１０２に接続されて、安定した負荷電圧が印加されることとなる（図３（Ｂ）、図３（Ｃ）及び図３（Ｅ）参照）。
この場合、直流安定化電源１０２の負荷電流は、副定電流源５から主定電流源１２へ切り換えられて流れるため、変化を生ずることがなく、安定した出力電圧となる。
なお、遅延時間ｔDは、直流安定化電源起動時から出力電圧が安定するまでの時間より大きな値に設定されたものである。 As a result, the second NMOS 3 is turned off, and the connection state between the auxiliary constant current source 5 and the DC stabilized power source 102 is cut off, while the LEDs 11-1 to 11-n and the main constant current source 12 which are main loads are disconnected. A stable load voltage is applied to the series stabilized power supply 102 (see FIGS. 3B, 3C, and 3E).
In this case, the load current of the DC stabilized power supply 102 is switched from the sub constant current source 5 to the main constant current source 12 and flows, so that no change occurs and a stable output voltage is obtained.
The delay time tD is set to a value larger than the time from when the DC stabilized power supply is started until the output voltage is stabilized.

このように、第２の実施例においては、負荷駆動スイッチ素子としてのＰＭＯＳ１をオン状態とする前に、副スイッチ素子としての第２のＮＭＯＳ３をオン状態とすることにより、直流安定化電源１０２の起動時における不安定な出力電圧を負荷へ与えることなく、負荷電圧の波形改善が可能となっている。   Thus, in the second embodiment, before the PMOS 1 as the load driving switch element is turned on, the second NMOS 3 as the sub switch element is turned on, so that the DC stabilized power supply 102 The load voltage waveform can be improved without giving an unstable output voltage to the load at the time of startup.

次に、第３の実施例について説明する。
この第３の実施例は、直流安定化電源１０２の起動の仕方の例である。
まず、第１及び第２の制御信号ＳＷ１，ＳＷ２は、図２に示されたものとする。そして、直流安定化電源１０２に、副定電流源５又は主定電流源１２のいずれかが接続されている（換言すれば、第１又は第２の制御信号ＳＷ１、ＳＷ２のいずれかが論理値Ｈｉｇｈに相当するレベルにある）ときにのみ、直流安定化電源１０２を動作させる一方、第１及び第２の制御信号ＳＷ１，ＳＷ２が共に論理値Ｌｏｗに相当するレベルにある場合には、直流安定化電源１０２をスタンバイ（待機）等の消費電流を減ずることのできる動作モード、換言すれば、出力電圧が出力されていない状態とする。 Next, a third embodiment will be described.
The third embodiment is an example of how to start the DC stabilized power supply 102.
First, it is assumed that the first and second control signals SW1 and SW2 are shown in FIG. Then, either the secondary constant current source 5 or the main constant current source 12 is connected to the DC stabilized power supply 102 (in other words, any of the first or second control signals SW1 and SW2 is a logical value). The DC stabilized power supply 102 is operated only when it is at a level corresponding to High, while the first and second control signals SW1 and SW2 are both at a level corresponding to the logical value Low. The operating power source 102 is set to an operation mode that can reduce current consumption, such as standby (standby), in other words, the output voltage is not output.

このような直流安定化電源１０２の動作制御を行うことによって、上述した実施例同様、負荷電圧波形の改善がなされると共に、直流安定化電源１０２が無負荷状態にある間は、直流安定化電源１０２の動作が低消費電流となる動作モードへ切り換えることにより、装置全体の消費電力が削減されることとなる。   By controlling the operation of the DC stabilized power supply 102 as described above, the load voltage waveform is improved and the DC stabilized power supply 102 is in a no-load state as in the above-described embodiment. By switching to the operation mode in which the operation of 102 is a low current consumption, the power consumption of the entire apparatus is reduced.

本発明の実施の形態における負荷駆動回路の回路構成例を示す回路図である。It is a circuit diagram which shows the circuit structural example of the load drive circuit in embodiment of this invention. 図１に示された負荷駆動回路の動作制御の第１の実施例における回路主要部の波形図であって、図２（Ａ）は負荷駆動信号の変化を示す波形図、図２（Ｂ）は第２の制御信号ＳＷ２の変化を示す波形図、図２（Ｃ）は第１の制御信号ＳＷ１の変化を示す波形図、図２（Ｄ）は、直流安定化電源の出力電圧の変化を示す波形図、図２（Ｅ）は負荷駆動回路を介して負荷に印加される負荷電圧の変化を示す波形図である。FIG. 2A is a waveform diagram of the main part of the circuit in the first embodiment of the operation control of the load drive circuit shown in FIG. 1, and FIG. 2A is a waveform diagram showing changes in the load drive signal, and FIG. Is a waveform diagram showing a change in the second control signal SW2, FIG. 2C is a waveform diagram showing a change in the first control signal SW1, and FIG. 2D is a graph showing a change in the output voltage of the DC stabilized power supply. FIG. 2E is a waveform diagram showing changes in load voltage applied to the load via the load driving circuit. 図１に示された負荷駆動回路の動作制御の第２の実施例における回路主要部の波形図であって、図３（Ａ）は直流安定化電源への入力電圧の変化を示す波形図、図３（Ｂ）は第２の制御信号ＳＷ２の変化を示す波形図、図３（Ｃ）は第１の制御信号ＳＷ１の変化を示す波形図、図３（Ｄ）は、直流安定化電源の出力電圧の変化を示す波形図、図３（Ｅ）は負荷駆動回路を介して負荷に印加される負荷電圧の変化を示す波形図である。FIG. 3 is a waveform diagram of the main part of the circuit in the second embodiment of the operation control of the load driving circuit shown in FIG. 1, and FIG. 3A is a waveform diagram showing a change in the input voltage to the DC stabilized power supply; FIG. 3B is a waveform diagram showing the change of the second control signal SW2, FIG. 3C is a waveform diagram showing the change of the first control signal SW1, and FIG. 3D is a diagram of the DC stabilized power supply. FIG. 3E is a waveform diagram showing a change in the load voltage applied to the load via the load drive circuit. 従来回路の回路構成例を示す回路図である。It is a circuit diagram which shows the circuit structural example of a conventional circuit. 図４に示された従来回路の主要部の波形図であって、図５（Ａ）は負荷駆動信号の変化を示す波形図、図５（Ｂ）は直流安定化電源の出力電圧の変化を示す波形図、図５（Ｃ）は負荷駆動回路を介して負荷に印加される負荷電圧の変化を示す波形図である。FIG. 5A is a waveform diagram showing a change in the load drive signal, and FIG. 5B is a waveform diagram showing a change in the output voltage of the DC stabilized power supply. FIG. 5C is a waveform diagram showing changes in the load voltage applied to the load via the load drive circuit.

符号の説明Explanation of symbols

１…ＰチャンネルＭＯＳ ＦＥＴ
２…第１のＮチャンネルＭＯＳ ＦＥＴ
３…第２のＮチャンネルＭＯＳ ＦＥＴ
５…副定電流源
１２…主定電流源
１０１…負荷駆動回路
１０２…直流安定化電源 1 ... P-channel MOS FET
2 ... First N-channel MOS FET
3 ... Second N-channel MOS FET
5 ... Sub-constant current source 12 ... Main constant current source 101 ... Load drive circuit 102 ... DC stabilized power supply

Claims (2)

外部からの第１の制御信号に応じて動作が制御される負荷駆動用スイッチ素子を直流安定化電源とグランドとの間に負荷と直列接続して前記直流安定化電源の出力電圧の負荷への印加を制御可能にするように構成されてなる負荷駆動回路であって、
前記直流安定化電源が接続される接続点とグランドとの間に、外部からの第２の制御信号によりオン・オフ制御可能な副スイッチ素子と、副負荷手段とを直列接続して設け、
前記直流安定化電源に接続される負荷の所望する駆動状態に対応して外部において生成される負荷駆動信号の論理値Ｈｉｇｈに相当するレベルへの立ち上がりから、前記直流安定化電源の負荷変動に対する制御遅れ以上の長さに設定された所定の遅延時間経過後に論理値Ｈｉｇｈに相当するレベルに立ち上がり、所定のパルス幅を有してなる前記第１の制御信号と、
前記負荷駆動信号の論理値Ｈｉｇｈに相当するレベルへの立ち上がりに同期して論理値Ｈｉｇｈに相当するレベルに立ち上がり、前記遅延時間に等しいパルス幅を有してなる前記第２の制御信号とを印加し、前記直流安定化電源の出力電圧の安定化後に当該出力電圧の前記負荷への印加を可能としてなることを特徴とする負荷駆動回路。 A load driving switch element whose operation is controlled in accordance with a first control signal from the outside is connected in series with the load between the DC stabilized power supply and the ground, and the output voltage of the DC stabilized power supply is applied to the load. A load driving circuit configured to be able to control application,
A sub-switch element that can be controlled to be turned on / off by a second control signal from the outside, and a sub-load means are connected in series between a connection point to which the DC stabilized power source is connected and the ground,
Control of load fluctuation of the DC stabilized power supply from the rise to the level corresponding to the logical value High of the load drive signal generated externally corresponding to the desired drive state of the load connected to the DC stabilized power supply The first control signal rising to a level corresponding to the logical value High after a predetermined delay time set to a length equal to or longer than the delay and having a predetermined pulse width;
Synchronously with the rise of the load driving signal to the level corresponding to the logical value High, the second control signal having the pulse width equal to the delay time is applied to rise to the level corresponding to the logical value High. And a load driving circuit that enables application of the output voltage to the load after stabilization of the output voltage of the DC stabilized power supply. 外部からの第１の制御信号に応じて動作が制御される負荷駆動用スイッチ素子を直流安定化電源とグランドとの間に負荷と直列接続して前記直流安定化電源の出力電圧の負荷への印加を制御可能にするように構成されてなる負荷駆動回路であって、
前記直流安定化電源が接続される接続点とグランドとの間に、外部からの第２の制御信号によりオン・オフ制御可能な副スイッチ素子と、副負荷手段とを直列接続して設け、
前記直流安定化電源への入力電圧の立ち上がりから、前記直流安定化電源の起動時に出力電圧が安定するまでの時間以上の長さに設定された所定の遅延時間経過後に論理値Ｈｉｇｈに相当するレベルに立ち上がり、所定のパルス幅を有してなる前記第１の制御信号と、
少なくとも前記直流安定化電源への入力電圧の立ち上がりに論理値Ｈｉｇｈに相当するレベルにあり、前記所定の遅延時間経過後に論理値Ｌｏｗに相当するレベルとなる前記第２の制御信号を印加し、前記直流安定化電源の出力電圧の安定化後に当該出力電圧の前記負荷への印加を可能としてなることを特徴とする負荷駆動回路。 A load driving switch element whose operation is controlled in accordance with a first control signal from the outside is connected in series with the load between the DC stabilized power supply and the ground, and the output voltage of the DC stabilized power supply is applied to the load. A load driving circuit configured to be able to control application,
A sub-switch element that can be controlled to be turned on / off by a second control signal from the outside, and a sub-load means are connected in series between a connection point to which the DC stabilized power source is connected and the ground,
A level corresponding to the logical value High after a lapse of a predetermined delay time set to a time longer than the time from the rising of the input voltage to the DC stabilized power supply until the output voltage is stabilized when the DC stabilized power supply is started. And the first control signal having a predetermined pulse width,
Applying the second control signal which is at a level corresponding to the logical value High at least at the rise of the input voltage to the DC stabilized power supply and becomes a level corresponding to the logical value Low after the predetermined delay time has elapsed, A load driving circuit, wherein the output voltage can be applied to the load after stabilization of the output voltage of the DC stabilized power supply.
JP2006341141A 2006-12-19 2006-12-19 Load drive circuit Expired - Fee Related JP4891050B2 (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010051068A (en) * 2008-08-20 2010-03-04 Rohm Co Ltd Load driver, lighting device, and display
JP2011249328A (en) * 2010-05-25 2011-12-08 National Semiconductor Corp Driving system with inductor pre-charging for led systems with pwm dimming control or other loads
JP2014179944A (en) * 2013-03-15 2014-09-25 Omron Corp Sensor
US11032880B2 (en) 2019-03-22 2021-06-08 Seiko Epson Corporation Light emission control device, light source device, and projection-type video display apparatus

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JP2002111786A (en) * 2000-10-03 2002-04-12 Rohm Co Ltd Light emitting device for portable telephone set and drive ic therefor
JP2003208993A (en) * 2002-01-11 2003-07-25 Toyoda Gosei Co Ltd Led illumination equipment
JP2003332623A (en) * 2002-05-07 2003-11-21 Rohm Co Ltd Light emitting element drive device and electronic apparatus having light emitting element
JP2006140438A (en) * 2004-10-14 2006-06-01 Sony Corp Drive device for light emitting device and display device

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Publication number Priority date Publication date Assignee Title
JP2000299499A (en) * 1999-04-16 2000-10-24 Nippon Seiki Co Ltd Drive circuit
JP2002111786A (en) * 2000-10-03 2002-04-12 Rohm Co Ltd Light emitting device for portable telephone set and drive ic therefor
JP2003208993A (en) * 2002-01-11 2003-07-25 Toyoda Gosei Co Ltd Led illumination equipment
JP2003332623A (en) * 2002-05-07 2003-11-21 Rohm Co Ltd Light emitting element drive device and electronic apparatus having light emitting element
JP2006140438A (en) * 2004-10-14 2006-06-01 Sony Corp Drive device for light emitting device and display device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010051068A (en) * 2008-08-20 2010-03-04 Rohm Co Ltd Load driver, lighting device, and display
JP2011249328A (en) * 2010-05-25 2011-12-08 National Semiconductor Corp Driving system with inductor pre-charging for led systems with pwm dimming control or other loads
JP2014179944A (en) * 2013-03-15 2014-09-25 Omron Corp Sensor
US11032880B2 (en) 2019-03-22 2021-06-08 Seiko Epson Corporation Light emission control device, light source device, and projection-type video display apparatus

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