JP2008153630A - Method of manufacturing semiconductor device - Google Patents

Method of manufacturing semiconductor device Download PDF

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JP2008153630A
JP2008153630A JP2007289516A JP2007289516A JP2008153630A JP 2008153630 A JP2008153630 A JP 2008153630A JP 2007289516 A JP2007289516 A JP 2007289516A JP 2007289516 A JP2007289516 A JP 2007289516A JP 2008153630 A JP2008153630 A JP 2008153630A
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layer
semiconductor device
resin precursor
manufacturing
forming
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JP4873180B2 (en
JP2008153630A5 (en
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Yasunori Kurosawa
康則 黒澤
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Seiko Epson Corp
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Seiko Epson Corp
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Priority to US11/942,809 priority patent/US8143173B2/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys

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Abstract

<P>PROBLEM TO BE SOLVED: To prevent flaws to a metal layer formed on the active surface of a semiconductor substrate. <P>SOLUTION: A stress relief layer 20 is formed on a first surface 16 having an electrode 12 electrically connected to the integrated circuit of the semiconductor substrate 10 on which the integrated circuit is formed. A conductive film 22 is formed while covering the stress relief layer 20 and the electrode 12. A plating resist layer 26 is formed on the conductive film 22 so that it has an opening 24, where the conductive film 22 is exposed partially. A metal layer 28 is formed on an exposed portion from the plating resist layer 26 of the conductive film 22 by electrolytic plating performed by allowing current to flow to the conductive film 22. Then, the plating resist layer 26 is removed. The exposed portion from the metal layer 28 of the conductive film 22 is etched for removal with the metal layer 28 as a mask. A solder resist layer 30 is formed on the metal layer 28. Then, a protective layer 34 is formed on a second surface 32 opposite to the first surface 16 of the semiconductor substrate 10. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明のいくつかの態様は、半導体装置の製造方法に関する。   Some embodiments of the present invention relate to a method for manufacturing a semiconductor device.

近年、半導体装置の小型化の要求に伴い、半導体ウエハの能動面に配線やバンプとなる金属層を形成するプロセスが開発されており、半導体装置を薄型化するため、薄い半導体ウエハが使用される場合がある。その場合、薄い半導体ウエハを補強するためにその裏面に樹脂層を形成することが知られている（特許文献１）。しかし、従来の技術では、半導体ウエハの裏面に樹脂層を形成するときに、能動面の金属層に傷を付けるおそれがあり、その対策が必要であった。
特開２０００−３３２０３４号公報 In recent years, with the demand for miniaturization of semiconductor devices, a process for forming a metal layer for wiring and bumps on the active surface of a semiconductor wafer has been developed, and a thin semiconductor wafer is used to make the semiconductor device thinner. There is a case. In that case, in order to reinforce a thin semiconductor wafer, it is known to form a resin layer on the back surface (Patent Document 1). However, in the prior art, when the resin layer is formed on the back surface of the semiconductor wafer, there is a risk of scratching the metal layer on the active surface, and countermeasures have to be taken.
JP 2000-332034 A

本発明は、半導体基板の能動面に形成された金属層に傷が付かないようにすることを目的とする。   An object of the present invention is to prevent a metal layer formed on an active surface of a semiconductor substrate from being damaged.

（１）本発明係る半導体装置の製造方法は、
（ａ）半導体基板の電極を有する第１の面に応力緩和層を形成する工程と、
（ｂ）前記（ａ）工程後に、前記電極上及び前記応力緩和層上に配線を形成する工程と、
（ｃ）前記（ｂ）工程後に、前記配線上にソルダレジスト層を形成する工程と、
（ｄ）前記（ｃ）工程後に、前記半導体基板の前記第１の面とは反対の第２の面に保護層を形成する工程と、
を含む。本発明によれば、金属層がソルダレジスト層で覆われた状態で保護層を形成するので、ソルダレジスト層によって保護されて金属層に傷が付かないようになる。
（２）この半導体装置の製造方法において、
前記（ｂ）工程は、
（ｂ−１）前記応力緩和層及び前記電極を覆うように導電膜を形成する工程と、
（ｂ−２）前記導電膜上に前記導電膜の一部が露出する開口を有するようにメッキレジスト層を形成する工程と、
（ｂ−３）前記導電膜に電流を流して行う電解メッキによって前記導電膜の前記メッキレジスト層からの露出部上に金属層を形成する工程と、
（ｂ−４）前記メッキレジスト層を除去する工程と、
（ｂ−５）前記金属層をマスクとして、前記導電膜の前記金属層からの露出部をエッチングして除去する工程と、
を含み、
前記（ｄ）工程を、前記ソルダレジスト層が支持体に接触するように、前記半導体基板を前記支持体に載せて行ってもよい。
（３）この半導体装置の製造方法において、
前記（ｃ）工程で、樹脂前駆体層を形成し、パターニングし、硬化して前記ソルダレジスト層を形成してもよい。
（４）この半導体装置の製造方法において、
前記（ｃ）工程で、前記ソルダレジスト層として第１の樹脂前駆体層を形成し、前記第１の樹脂前駆体層のパターニング及び硬化前に前記（ｄ）工程を行い、
前記（ｄ）工程で、前記保護層として第２の樹脂前駆体層を形成し、前記第１の樹脂前駆体層の未硬化状態を維持しながら、前記第２の樹脂前駆体層を硬化し、
前記（ｄ）工程後に、前記第１の樹脂前駆体層をパターニングして硬化してもよい。
（５）この半導体装置の製造方法において、前記第１の樹脂前駆体層の硬化温度は、前記第２の樹脂前駆体層の硬化温度よりも高くてもよい。
（６）この半導体装置の製造方法において、
前記（ｃ）工程で、前記ソルダレジスト層として第１の樹脂前駆体層を形成し、前記第１の樹脂前駆体層のパターニング及び硬化前に前記（ｄ）工程を行い、
前記（ｄ）工程で、前記保護層として第２の樹脂前駆体層を形成し、
前記（ｄ）工程後に、前記第１の樹脂前駆体層をパターニングして、前記第１及び第２の樹脂前駆体層を同時に硬化してもよい。
（７）この半導体装置の製造方法において、
前記第１の樹脂前駆体層の硬化温度と、前記第２の樹脂前駆体層の硬化温度は同じであってもよい。
（８）この半導体装置の製造方法において、
前記ソルダレジスト層の前記配線上に開口を設ける工程と、
前記開口内に半田からなる外部端子を形成する工程と、
を更に含み、
前記外部端子を形成する工程は、前記（ｄ）工程の後に行ってもよい。
（９）本発明に係る半導体装置の製造方法は、（ａ）半導体基板の電極を有する第１の面に第１の樹脂層を形成する工程と、
（ｂ）前記（ａ）工程後に、前記電極上及び前記第１の樹脂層上に配線を形成する工程と、
（ｃ）前記（ｂ）工程後に、前記配線上に第２の樹脂層を形成する工程と、
（ｄ）前記（ｃ）工程後に、前記半導体基板の前記第１の面とは反対側の第２の面に第３の樹脂層を形成する工程と、
を含む。本発明によれば、配線層が第２の樹脂層に覆われた状態で第３の樹脂層を形成するため、第３の樹脂層形成時に第２の樹脂層が配線層の保護層としての役割を果たし、配線層の損傷の発生を抑制することができる。 (1) A method of manufacturing a semiconductor device according to the present invention includes:
(A) forming a stress relaxation layer on the first surface having the electrodes of the semiconductor substrate;
(B) after the step (a), forming a wiring on the electrode and the stress relaxation layer;
(C) After the step (b), a step of forming a solder resist layer on the wiring;
(D) after the step (c), forming a protective layer on the second surface opposite to the first surface of the semiconductor substrate;
including. According to the present invention, since the protective layer is formed in a state where the metal layer is covered with the solder resist layer, the metal layer is protected from being damaged by the solder resist layer.
(2) In this method of manufacturing a semiconductor device,
The step (b)
(B-1) forming a conductive film so as to cover the stress relaxation layer and the electrode;
(B-2) forming a plating resist layer on the conductive film so as to have an opening through which a part of the conductive film is exposed;
(B-3) forming a metal layer on the exposed portion of the conductive film from the plating resist layer by electrolytic plating performed by passing a current through the conductive film;
(B-4) removing the plating resist layer;
(B-5) using the metal layer as a mask to etch away the exposed portion of the conductive film from the metal layer;
Including
The step (d) may be performed by placing the semiconductor substrate on the support so that the solder resist layer contacts the support.
(3) In this method of manufacturing a semiconductor device,
In the step (c), a resin precursor layer may be formed, patterned, and cured to form the solder resist layer.
(4) In this method of manufacturing a semiconductor device,
In the step (c), a first resin precursor layer is formed as the solder resist layer, and the step (d) is performed before patterning and curing the first resin precursor layer.
In the step (d), a second resin precursor layer is formed as the protective layer, and the second resin precursor layer is cured while maintaining an uncured state of the first resin precursor layer. ,
After the step (d), the first resin precursor layer may be patterned and cured.
(5) In this method of manufacturing a semiconductor device, the curing temperature of the first resin precursor layer may be higher than the curing temperature of the second resin precursor layer.
(6) In this method of manufacturing a semiconductor device,
In the step (c), a first resin precursor layer is formed as the solder resist layer, and the step (d) is performed before patterning and curing the first resin precursor layer.
In the step (d), a second resin precursor layer is formed as the protective layer,
After the step (d), the first resin precursor layer may be patterned to simultaneously cure the first and second resin precursor layers.
(7) In this method of manufacturing a semiconductor device,
The curing temperature of the first resin precursor layer and the curing temperature of the second resin precursor layer may be the same.
(8) In this method of manufacturing a semiconductor device,
Providing an opening on the wiring of the solder resist layer;
Forming an external terminal made of solder in the opening;
Further including
The step of forming the external terminal may be performed after the step (d).
(9) A method of manufacturing a semiconductor device according to the present invention includes: (a) a step of forming a first resin layer on a first surface having an electrode of a semiconductor substrate;
(B) after the step (a), forming a wiring on the electrode and the first resin layer;
(C) after the step (b), forming a second resin layer on the wiring;
(D) after the step (c), a step of forming a third resin layer on a second surface opposite to the first surface of the semiconductor substrate;
including. According to the present invention, since the third resin layer is formed with the wiring layer covered with the second resin layer, the second resin layer serves as a protective layer for the wiring layer when the third resin layer is formed. It plays a role and can suppress the occurrence of damage to the wiring layer.

（第１の実施の形態）
図１（Ａ）〜図３は、本発明の第１の実施の形態に係る半導体装置の製造方法を説明する図である。本実施の形態では、半導体基板１０（例えばＳｉ（シリコン）からなる半導体ウエハ）１０を使用する。半導体基板１０には集積回路１９を形成する。詳しくは、半導体基板１０の一方の面に、周知の半導体プロセスによって集積回路１９を形成する。集積回路１９は、半導体基板１０の一方の表層に作りこまれる。また、集積回路１９に半導体基板１０に形成された内部配線を介して電気的に接続されるように電極１２を形成し、電極１２の少なくとも一部が露出する様にパッシベーション膜１４を形成する。言い換えると、集積回路１９から接続された内部配線のうち、パッシベーション膜１４から露出する部分が電極１２である。パッシベーション膜１４は無機材料（例えばＳｉ等の無機酸化物）で形成されてもよい。 (First embodiment)
FIG. 1A to FIG. 3 are diagrams for explaining a method of manufacturing a semiconductor device according to the first embodiment of the present invention. In the present embodiment, a semiconductor substrate 10 (for example, a semiconductor wafer made of Si (silicon)) 10 is used. An integrated circuit 19 is formed on the semiconductor substrate 10. Specifically, the integrated circuit 19 is formed on one surface of the semiconductor substrate 10 by a known semiconductor process. The integrated circuit 19 is formed on one surface layer of the semiconductor substrate 10. Further, the electrode 12 is formed so as to be electrically connected to the integrated circuit 19 through the internal wiring formed on the semiconductor substrate 10, and the passivation film 14 is formed so that at least a part of the electrode 12 is exposed. In other words, of the internal wiring connected from the integrated circuit 19, the portion exposed from the passivation film 14 is the electrode 12. The passivation film 14 may be formed of an inorganic material (for example, an inorganic oxide such as Si).

図１（Ａ）に示すように、半導体基板１０の電極１２を有する第１の面１６に応力緩和層（または第１の樹脂層）２０を形成する。応力緩和層２０は、少なくとも電極１２の少なくとも一部を避けて形成する。例えば、感光性樹脂によってフォトリソグラフィを適用して応力緩和層２０を形成してもよい。また、熱硬化性樹脂を使用して応力緩和層２０を形成してもよい。応力緩和層２０の側面は傾斜面になっていてもよい。この傾斜面は、熱硬化性樹脂前駆体の熱収縮によって形成される。応力緩和層２０を、後述する半導体基板１０の切断ラインを避けて形成すれば、カッタ（又はスクライバ）の目詰まりを防止することができる。   As shown in FIG. 1A, a stress relaxation layer (or first resin layer) 20 is formed on the first surface 16 having the electrodes 12 of the semiconductor substrate 10. The stress relaxation layer 20 is formed avoiding at least a part of the electrode 12. For example, the stress relaxation layer 20 may be formed by applying photolithography using a photosensitive resin. Further, the stress relaxation layer 20 may be formed using a thermosetting resin. The side surface of the stress relaxation layer 20 may be an inclined surface. This inclined surface is formed by thermal contraction of the thermosetting resin precursor. If the stress relaxation layer 20 is formed avoiding a cutting line of the semiconductor substrate 10 to be described later, clogging of the cutter (or scriber) can be prevented.

図１（Ｂ）に示すように、応力緩和層２０及び電極１２を覆うように導電膜２２を形成する。導電膜２２はパッシベーション膜１４上にも形成してよい。導電膜２２は少なくとも１層からなり、複数層から形成してもよい。例えば、応力緩和層２０及び電極１２上にチタンとタングステンの混合材料からなる下地層を形成し、その上に、後述する電解メッキで析出する金属層２８と同じ金属（例えば銅）からなる表皮層を形成してもよい。導電膜２２はスパッタリングによって形成することができる。   As shown in FIG. 1B, a conductive film 22 is formed so as to cover the stress relaxation layer 20 and the electrode 12. The conductive film 22 may also be formed on the passivation film 14. The conductive film 22 includes at least one layer, and may be formed from a plurality of layers. For example, a base layer made of a mixed material of titanium and tungsten is formed on the stress relaxation layer 20 and the electrode 12, and a skin layer made of the same metal (for example, copper) as the metal layer 28 deposited by electrolytic plating described later is formed thereon. May be formed. The conductive film 22 can be formed by sputtering.

図１（Ｃ）に示すように、導電膜２２上に導電膜２２の一部が露出する開口２４を有するようにメッキレジスト層２６を形成する。メッキレジスト層２６の開口２４は、導電膜２２の電極１２上の部分を露出するとともに、電極１２上の部分から配線の形状で連続的に延びる部分を露出している。メッキレジスト層２６は、感光性樹脂で形成することができる。感光性樹脂は、紫外線硬化性樹脂であってもよいが、熱硬化性樹脂であれば硬化を簡単に行える。感光性樹脂前駆体層を導電膜２２上に形成し、露光・現像を含むフォトリソグラフィによって開口２４を形成し、硬化することでメッキレジスト層２６を形成する。なお、感光性樹脂前駆体層を硬化するときに、開口２４の内側面が傾斜するように、開口２４を外方向に拡がるテーパー形状にしてもよい。言い換えると、メッキレジスト層２６の半導体基板１０と対向する面側の開口より、メッキレジスト層２６の半導体基板１０と対向する面とは反対面側の開口の方が大きくなっていてもよい。   As shown in FIG. 1C, a plating resist layer 26 is formed on the conductive film 22 so as to have an opening 24 from which a part of the conductive film 22 is exposed. The opening 24 of the plating resist layer 26 exposes a portion of the conductive film 22 on the electrode 12 and also exposes a portion that continuously extends from the portion on the electrode 12 in the shape of the wiring. The plating resist layer 26 can be formed of a photosensitive resin. The photosensitive resin may be an ultraviolet curable resin, but can be easily cured if it is a thermosetting resin. A photosensitive resin precursor layer is formed on the conductive film 22, the opening 24 is formed by photolithography including exposure and development, and the plating resist layer 26 is formed by curing. Note that when the photosensitive resin precursor layer is cured, the opening 24 may be tapered so that the inner surface of the opening 24 is inclined. In other words, the opening on the surface opposite to the surface of the plating resist layer 26 facing the semiconductor substrate 10 may be larger than the opening on the surface of the plating resist layer 26 facing the semiconductor substrate 10.

図１（Ｄ）に示すように、導電膜２２に電流を流して行う電解メッキによって導電膜２２のメッキレジスト層２６からの露出部上に金属層２８を形成する。電解メッキで導電膜２２は電極として使用する。金属層２８は例えば銅からなる層である。金属層２８は、メッキレジスト層２６の高さを超えないように（つまり開口２４から盛り上がらないように）形成することで、開口２４の幅で形成することができる。   As shown in FIG. 1D, a metal layer 28 is formed on the exposed portion of the conductive film 22 from the plating resist layer 26 by electrolytic plating performed by passing a current through the conductive film 22. The electroconductive film 22 is used as an electrode by electrolytic plating. The metal layer 28 is a layer made of, for example, copper. The metal layer 28 can be formed with the width of the opening 24 by forming it so as not to exceed the height of the plating resist layer 26 (that is, not rising from the opening 24).

図１（Ｅ）に示すように、メッキレジスト層２６を除去する。   As shown in FIG. 1E, the plating resist layer 26 is removed.

図１（Ｆ）に示すように、金属層２８をマスクとして、導電膜２２の金属層２８からの露出部をエッチングして除去する。このとき、エッチングによって金属層２８の表面が研磨されるので、金属層２８に傷がついてもそれを除去することができ、金属層２８上の酸化膜も除去することができる。金属層２８及び導電膜２２によって、電極１２に電気的に接続される配線２９が形成される。なお、配線２９は、金属層２８及び導電膜２２の複数の金属からなる層で形成される場合に限らず、電極１２上及び応力緩和層２０上に形成されるものであれば１層の金属から形成してもよい。   As shown in FIG. 1F, the exposed portion of the conductive film 22 from the metal layer 28 is removed by etching using the metal layer 28 as a mask. At this time, since the surface of the metal layer 28 is polished by etching, even if the metal layer 28 is damaged, it can be removed, and the oxide film on the metal layer 28 can also be removed. The metal layer 28 and the conductive film 22 form a wiring 29 that is electrically connected to the electrode 12. Note that the wiring 29 is not limited to being formed of a metal layer 28 and a layer made of a plurality of metals of the conductive film 22, but may be a single layer of metal as long as it is formed on the electrode 12 and the stress relaxation layer 20. You may form from.

図２（Ａ）に示すように、ソルダレジスト層（または第２の樹脂層）３０を形成する。ソルダレジスト層３０は、金属層２８の一部（例えばランド）を露出させるように、金属層２８のその他の部分全体を覆うように形成する。ソルダレジスト層３０は、応力緩和層２０上に載っていてもよい。ただし、ソルダレジスト層３０を、後述する半導体基板１０の切断ラインを避けて形成すれば、カッタ（又はスクライバ）の目詰まりを防止することができる。ソルダレジスト層３０は、感光性樹脂を使用し、フォトリソグラフィの工程によってパターニングし硬化して形成することができる。熱硬化性樹脂であれば熱によって硬化することができる。本実施の形態では、ソルダレジスト層３０とは硬化した層をいう。   As shown in FIG. 2A, a solder resist layer (or second resin layer) 30 is formed. The solder resist layer 30 is formed so as to cover the entire other part of the metal layer 28 so that a part (for example, land) of the metal layer 28 is exposed. The solder resist layer 30 may be placed on the stress relaxation layer 20. However, if the solder resist layer 30 is formed avoiding a cutting line of the semiconductor substrate 10 to be described later, clogging of the cutter (or scriber) can be prevented. The solder resist layer 30 can be formed by using a photosensitive resin and patterning and curing by a photolithography process. If it is a thermosetting resin, it can be cured by heat. In the present embodiment, the solder resist layer 30 refers to a cured layer.

次に、半導体基板１０の第１の面１６とは反対の第２の面３２に保護層（または第３の樹脂層）３４を形成する。この工程は、半導体基板１０を支持体３５に支持させて（あるいは載せて）行う。詳しくは、第１の面１６を支持体３５に向けて、ソルダレジスト層３０を支持体３５に接触させる。そして、図２（Ｂ）に示すように、第２の面３２に樹脂前駆体層３６を形成する。樹脂前駆体は、紫外線硬化性樹脂であってもよいが、熱硬化性樹脂であれば硬化を簡単に行える。樹脂前駆体層３６の形成は、スクリーン印刷によって行えば材料の無駄が少ないが、スピンコートによって行うことを妨げるものではない。樹脂前駆体層３６を硬化して保護層３４を形成する（図２（Ｃ）参照）。あるいは、テープ又はシートを貼り付けることで保護層３４を設けてもよい。保護層３４を設けることで、半導体基板１０の第２の面３２を保護するとともに、薄い半導体基板１０を補強することができる。本実施の形態によれば、金属層２８がソルダレジスト層３０で覆われた状態で保護層３４を形成するので、ソルダレジスト層３０によって保護されて金属層２８に傷が付かないようになる。   Next, a protective layer (or third resin layer) 34 is formed on the second surface 32 opposite to the first surface 16 of the semiconductor substrate 10. This step is performed by supporting (or placing) the semiconductor substrate 10 on the support 35. Specifically, the solder resist layer 30 is brought into contact with the support 35 with the first surface 16 facing the support 35. Then, as shown in FIG. 2B, a resin precursor layer 36 is formed on the second surface 32. The resin precursor may be an ultraviolet curable resin, but can be easily cured if it is a thermosetting resin. If the resin precursor layer 36 is formed by screen printing, there is little waste of material, but this does not prevent the resin precursor layer 36 from being formed by spin coating. The resin precursor layer 36 is cured to form the protective layer 34 (see FIG. 2C). Or you may provide the protective layer 34 by affixing a tape or a sheet | seat. By providing the protective layer 34, the second surface 32 of the semiconductor substrate 10 can be protected and the thin semiconductor substrate 10 can be reinforced. According to the present embodiment, since the protective layer 34 is formed in a state where the metal layer 28 is covered with the solder resist layer 30, the metal layer 28 is protected from being damaged by the solder resist layer 30.

図３に示すように、金属層２８上に外部端子４０を形成する。外部端子４０は、半田で形成してもよい。例えばクリーム半田を金属層２８上に設け、クリーム半田を溶融して表面張力でボール状に形成してもよい。本実施の形態では、外部端子４０を設ける前に保護層３４を形成するので、外部端子４０を避けるように半導体基板１０を支持する工夫が不要であって工程の簡略化を図ることができる。そして、半導体基板１０を切断（ダイシング又はスクライビング）して、図４に示すように、半導体装置を得ることができる。   As shown in FIG. 3, external terminals 40 are formed on the metal layer 28. The external terminal 40 may be formed of solder. For example, cream solder may be provided on the metal layer 28, and the cream solder may be melted and formed into a ball shape with surface tension. In this embodiment, since the protective layer 34 is formed before the external terminals 40 are provided, it is not necessary to devise support for the semiconductor substrate 10 so as to avoid the external terminals 40, and the process can be simplified. Then, the semiconductor substrate 10 can be cut (diced or scribed) to obtain a semiconductor device as shown in FIG.

（第２の実施の形態）
図５（Ａ）〜図５（Ｄ）は、本発明の第２の実施の形態に係る半導体装置の製造方法を説明する図である。本実施の形態では、図１（Ａ）〜図１（Ｆ）の工程を行った後に図５（Ａ）の工程を行う。 (Second Embodiment)
FIG. 5A to FIG. 5D are views for explaining a method for manufacturing a semiconductor device according to the second embodiment of the present invention. In this embodiment mode, the process shown in FIG. 5A is performed after the processes shown in FIGS.

図５（Ａ）に示すように、ソルダレジスト層として第１の樹脂前駆体層１３０を形成する。本実施の形態は、第１の樹脂前駆体層１３０のパターニング及び硬化前に保護層３４の形成（硬化を含む）を行う点で第１の実施の形態と異なる。したがって、本実施の形態でソルダレジスト層とは、パターニング前であって未硬化の状態である。   As shown in FIG. 5A, a first resin precursor layer 130 is formed as a solder resist layer. This embodiment is different from the first embodiment in that the protective layer 34 is formed (including curing) before the patterning and curing of the first resin precursor layer 130. Therefore, in this embodiment, the solder resist layer is in an uncured state before patterning.

図５（Ｂ）に示すように、保護層３４にするための第２の樹脂前駆体層１３６を形成する。この時点で、第１の樹脂前駆体層１３０は、未硬化状態であるが、パターニング可能な状態を維持できる程度にプリベークしてもよい。そして、第１の樹脂前駆体層１３０の未硬化状態（パターニングも可能な状態）を維持しながら、第２の樹脂前駆体層１３６を硬化する（図５（Ｃ）参照）。例えば、第１及び第２の樹脂前駆体層１３０，１３６がいずれも熱硬化性樹脂前駆体であれば、第１の樹脂前駆体層１３０として、硬化反応の温度が第２の樹脂前駆体層１３６よりも高い材料を使用する。   As shown in FIG. 5B, a second resin precursor layer 136 for forming the protective layer 34 is formed. At this time, the first resin precursor layer 130 is in an uncured state, but may be pre-baked to such an extent that a patternable state can be maintained. Then, the second resin precursor layer 136 is cured while maintaining the uncured state (state where patterning is possible) of the first resin precursor layer 130 (see FIG. 5C). For example, if both the first and second resin precursor layers 130 and 136 are thermosetting resin precursors, the temperature of the curing reaction is the second resin precursor layer 130 as the first resin precursor layer 130. A material higher than 136 is used.

図５（Ｄ）に示すように、第１の樹脂前駆体層１３０をパターニングして硬化（ポストベーク）する。その他の内容は第１の実施の形態で説明した内容が該当し、作用効果も同じであるため説明を省略する。   As shown in FIG. 5D, the first resin precursor layer 130 is patterned and cured (post-baked). The other contents correspond to the contents described in the first embodiment, and the description is omitted because the operational effects are the same.

（第３の実施の形態）
図６（Ａ）〜図６（Ｂ）は、本発明の第３の実施の形態に係る半導体装置の製造方法を説明する図である。本実施の形態では、図５（Ｂ）の工程を行った後に図６（Ａ）からの工程を行う。つまり、第１の樹脂前駆体層１３０の未硬化状態を維持して、保護層３４にするための第２の樹脂前駆体層１３６を形成する（図６（Ａ）参照）。そして、第２の樹脂前駆体層１３６が未硬化のまま、第１の樹脂前駆体層１３０をパターニングする（図６（Ｂ）参照）。その後、第１及び第２の樹脂前駆体層１３０，１３６を同時に硬化する。本実施の形態によれば、第１及び第２の樹脂前駆体層１３０，１３６を同時に硬化するので、両者の硬化温度が同じであってもよい。その他の内容は第１又は第２の実施の形態で説明した内容が該当し、作用効果も同じであるため説明を省略する。 (Third embodiment)
6A to 6B are views for explaining a method for manufacturing a semiconductor device according to the third embodiment of the present invention. In this embodiment, the process from FIG. 6A is performed after the process of FIG. That is, the second resin precursor layer 136 for forming the protective layer 34 is formed while maintaining the uncured state of the first resin precursor layer 130 (see FIG. 6A). Then, the first resin precursor layer 130 is patterned while the second resin precursor layer 136 remains uncured (see FIG. 6B). Thereafter, the first and second resin precursor layers 130 and 136 are simultaneously cured. According to the present embodiment, since the first and second resin precursor layers 130 and 136 are cured simultaneously, the curing temperatures of both may be the same. The other contents correspond to the contents described in the first or second embodiment, and the description is omitted because the operational effects are the same.

本発明は、上述した実施の形態に限定されるものではなく、種々の変形が可能である。例えば、本発明は、実施の形態で説明した構成と実質的に同一の構成（例えば、機能、方法及び結果が同一の構成、あるいは目的及び結果が同一の構成）を含む。また、本発明は、実施の形態で説明した構成の本質的でない部分を置き換えた構成を含む。また、本発明は、実施の形態で説明した構成と同一の作用効果を奏する構成又は同一の目的を達成することができる構成を含む。また、本発明は、実施の形態で説明した構成に公知技術を付加した構成を含む。   The present invention is not limited to the above-described embodiments, and various modifications can be made. For example, the present invention includes configurations that are substantially the same as the configurations described in the embodiments (for example, configurations that have the same functions, methods, and results, or configurations that have the same purposes and results). In addition, the invention includes a configuration in which a non-essential part of the configuration described in the embodiment is replaced. In addition, the present invention includes a configuration that achieves the same effect as the configuration described in the embodiment or a configuration that can achieve the same object. Further, the invention includes a configuration in which a known technique is added to the configuration described in the embodiment.

図１（Ａ）〜図１（Ｆ）は、本発明の第１の実施の形態に係る半導体装置の製造方法を説明する図である。1A to 1F are views for explaining a method for manufacturing a semiconductor device according to the first embodiment of the present invention. 図２（Ａ）〜図２（Ｃ）は、本発明の第１の実施の形態に係る半導体装置の製造方法を説明する図である。2A to 2C are views for explaining a method for manufacturing a semiconductor device according to the first embodiment of the present invention. 図３は、本発明の第１の実施の形態に係る半導体装置の製造方法を説明する図である。FIG. 3 is a diagram illustrating a method for manufacturing the semiconductor device according to the first embodiment of the present invention. 図４は、本発明の第１の実施の形態に係る方法で製造された半導体装置を示す図である。FIG. 4 is a diagram showing a semiconductor device manufactured by the method according to the first embodiment of the present invention. 図５（Ａ）〜図５（Ｄ）は、本発明の第２の実施の形態に係る半導体装置の製造方法を説明する図である。FIG. 5A to FIG. 5D are views for explaining a method for manufacturing a semiconductor device according to the second embodiment of the present invention. 図６（Ａ）〜図６（Ｂ）は、本発明の第３の実施の形態に係る半導体装置の製造方法を説明する図である。6A to 6B are views for explaining a method for manufacturing a semiconductor device according to the third embodiment of the present invention.

符号の説明Explanation of symbols

１０…半導体基板、 １２…電極、 １４…パッシベーション膜、 １６…第１の面 ２０…応力緩和層、 ２２…導電膜、 ２４…開口、 ２６…メッキレジスト層、 ２８…金属層、 ３０…ソルダレジスト層、 ３２…第２の面 ３４…保護層、 ３５…支持体、 ３６…樹脂前駆体層、 ４０…外部端子、 １３０…第１の樹脂前駆体層、 １３６…第２の樹脂前駆体層   DESCRIPTION OF SYMBOLS 10 ... Semiconductor substrate, 12 ... Electrode, 14 ... Passivation film, 16 ... 1st surface 20 ... Stress relaxation layer, 22 ... Conductive film, 24 ... Opening, 26 ... Plating resist layer, 28 ... Metal layer, 30 ... Solder resist Layer 32 ... second surface 34 ... protective layer 35 ... support body 36 ... resin precursor layer 40 ... external terminal 130 ... first resin precursor layer 136 ... second resin precursor layer

Claims (9)

（ａ）半導体基板の電極を有する第１の面に応力緩和層を形成する工程と、
（ｂ）前記（ａ）工程後に、前記電極上及び前記応力緩和層上に配線を形成する工程と、
（ｃ）前記（ｂ）工程後に、前記配線上にソルダレジスト層を形成する工程と、
（ｄ）前記（ｃ）工程後に、前記半導体基板の前記第１の面とは反対の第２の面に保護層を形成する工程と、
を含む半導体装置の製造方法。 (A) forming a stress relaxation layer on the first surface having the electrodes of the semiconductor substrate;
(B) after the step (a), forming a wiring on the electrode and the stress relaxation layer;
(C) After the step (b), a step of forming a solder resist layer on the wiring;
(D) after the step (c), forming a protective layer on the second surface opposite to the first surface of the semiconductor substrate;
A method of manufacturing a semiconductor device including: 請求項１に記載された半導体装置の製造方法において、
前記（ｂ）工程は、
（ｂ−１）前記応力緩和層及び前記電極を覆うように導電膜を形成する工程と、
（ｂ−２）前記導電膜上に前記導電膜の一部が露出する開口を有するようにメッキレジスト層を形成する工程と、
（ｂ−３）前記導電膜に電流を流して行う電解メッキによって前記導電膜の前記メッキレジスト層からの露出部上に金属層を形成する工程と、
（ｂ−４）前記メッキレジスト層を除去する工程と、
（ｂ−５）前記金属層をマスクとして、前記導電膜の前記金属層からの露出部をエッチングして除去する工程と、
を含み、
前記（ｄ）工程を、前記ソルダレジスト層が支持体に接触するように、前記半導体基板を前記支持体に載せて行う半導体装置の製造方法。 In the manufacturing method of the semiconductor device according to claim 1,
The step (b)
(B-1) forming a conductive film so as to cover the stress relaxation layer and the electrode;
(B-2) forming a plating resist layer on the conductive film so as to have an opening through which a part of the conductive film is exposed;
(B-3) forming a metal layer on the exposed portion of the conductive film from the plating resist layer by electrolytic plating performed by passing a current through the conductive film;
(B-4) removing the plating resist layer;
(B-5) using the metal layer as a mask to etch away the exposed portion of the conductive film from the metal layer;
Including
A method of manufacturing a semiconductor device, wherein the step (d) is performed by placing the semiconductor substrate on the support so that the solder resist layer contacts the support. 請求項１又は２に記載された半導体装置の製造方法において、
前記（ｃ）工程で、樹脂前駆体層を形成し、パターニングし、硬化して前記ソルダレジスト層を形成する半導体装置の製造方法。 In the manufacturing method of the semiconductor device according to claim 1 or 2,
A method of manufacturing a semiconductor device, wherein a resin precursor layer is formed, patterned and cured in the step (c) to form the solder resist layer. 請求項１又は２に記載された半導体装置の製造方法において、
前記（ｃ）工程で、前記ソルダレジスト層として第１の樹脂前駆体層を形成し、前記第１の樹脂前駆体層のパターニング及び硬化前に前記（ｄ）工程を行い、
前記（ｄ）工程で、前記保護層として第２の樹脂前駆体層を形成し、前記第１の樹脂前駆体層の未硬化状態を維持しながら、前記第２の樹脂前駆体層を硬化し、
前記（ｄ）工程後に、前記第１の樹脂前駆体層をパターニングして硬化する半導体装置の製造方法。 In the manufacturing method of the semiconductor device according to claim 1 or 2,
In the step (c), a first resin precursor layer is formed as the solder resist layer, and the step (d) is performed before patterning and curing the first resin precursor layer.
In the step (d), a second resin precursor layer is formed as the protective layer, and the second resin precursor layer is cured while maintaining an uncured state of the first resin precursor layer. ,
A method of manufacturing a semiconductor device, wherein the first resin precursor layer is patterned and cured after the step (d). 請求項４記載の半導体装置の製造方法において、
前記第１の樹脂前駆体層の硬化温度は、前記第２の樹脂前駆体層の硬化温度よりも高い半導体装置の製造方法。 In the manufacturing method of the semiconductor device according to claim 4,
A method for manufacturing a semiconductor device, wherein the curing temperature of the first resin precursor layer is higher than the curing temperature of the second resin precursor layer. 請求項１又は２に記載された半導体装置の製造方法において、
前記（ｃ）工程で、前記ソルダレジスト層として第１の樹脂前駆体層を形成し、前記第１の樹脂前駆体層のパターニング及び硬化前に前記（ｄ）工程を行い、
前記（ｄ）工程で、前記保護層として第２の樹脂前駆体層を形成し、
前記（ｄ）工程後に、前記第１の樹脂前駆体層をパターニングして、前記第１及び第２の樹脂前駆体層を同時に硬化する半導体装置の製造方法。 In the manufacturing method of the semiconductor device according to claim 1 or 2,
In the step (c), a first resin precursor layer is formed as the solder resist layer, and the step (d) is performed before patterning and curing the first resin precursor layer.
In the step (d), a second resin precursor layer is formed as the protective layer,
A method of manufacturing a semiconductor device, wherein after the step (d), the first resin precursor layer is patterned to simultaneously cure the first and second resin precursor layers. 請求項６記載の半導体装置の製造方法において、
前記第１の樹脂前駆体層の硬化温度と、前記第２の樹脂前駆体層の硬化温度は同じである半導体装置の製造方法。 The method of manufacturing a semiconductor device according to claim 6.
A method for manufacturing a semiconductor device, wherein a curing temperature of the first resin precursor layer and a curing temperature of the second resin precursor layer are the same. 請求項１に記載された半導体装置の製造方法において、
前記ソルダレジスト層の前記配線上に開口を設ける工程と、
前記開口内に半田からなる外部端子を形成する工程と、
を更に含み、
前記外部端子を形成する工程は、前記（ｄ）工程の後に行う半導体装置の製造方法。 In the manufacturing method of the semiconductor device according to claim 1,
Providing an opening on the wiring of the solder resist layer;
Forming an external terminal made of solder in the opening;
Further including
The step of forming the external terminal is a method for manufacturing a semiconductor device performed after the step (d). （ａ）半導体基板の電極を有する第１の面に第１の樹脂層を形成する工程と、
（ｂ）前記（ａ）工程後に、前記電極上及び前記第１の樹脂層上に配線を形成する工程と、
（ｃ）前記（ｂ）工程後に、前記配線上に第２の樹脂層を形成する工程と、
（ｄ）前記（ｃ）工程後に、前記半導体基板の前記第１の面とは反対側の第２の面に第３の樹脂層を形成する工程と、
を含む半導体装置の製造方法。 (A) forming a first resin layer on a first surface having an electrode of a semiconductor substrate;
(B) after the step (a), forming a wiring on the electrode and the first resin layer;
(C) after the step (b), forming a second resin layer on the wiring;
(D) After the step (c), a step of forming a third resin layer on the second surface opposite to the first surface of the semiconductor substrate;
A method of manufacturing a semiconductor device including:
JP2007289516A 2006-11-22 2007-11-07 Manufacturing method of semiconductor device Expired - Fee Related JP4873180B2 (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001077231A (en) * 1999-09-03 2001-03-23 Matsushita Electronics Industry Corp Semiconductor device, semiconductor wafer, and manufacture of the semiconductor device
JP2001250876A (en) * 2000-03-03 2001-09-14 Shinko Electric Ind Co Ltd Semiconductor device and its manufacturing method
JP2004241673A (en) * 2003-02-07 2004-08-26 Seiko Epson Corp Semiconductor device, manufacturing method for semiconductor device and electronic apparatus
JP2006229112A (en) * 2005-02-21 2006-08-31 Casio Comput Co Ltd Semiconductor device and its fabrication process

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001077231A (en) * 1999-09-03 2001-03-23 Matsushita Electronics Industry Corp Semiconductor device, semiconductor wafer, and manufacture of the semiconductor device
JP2001250876A (en) * 2000-03-03 2001-09-14 Shinko Electric Ind Co Ltd Semiconductor device and its manufacturing method
JP2004241673A (en) * 2003-02-07 2004-08-26 Seiko Epson Corp Semiconductor device, manufacturing method for semiconductor device and electronic apparatus
JP2006229112A (en) * 2005-02-21 2006-08-31 Casio Comput Co Ltd Semiconductor device and its fabrication process

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