JP2008148041A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of supplying a clock with less skew for over a wide range of a chip and reducing power consumption. <P>SOLUTION: The semiconductor device is provided with a semiconductor chip on which a driver 14 which outputs a clock signal and a receiver 15 which receives the clock signal are integrally formed and a waveguide 13 mounted on the semiconductor chip. In the waveguide, a transmitting antenna 20 which transmits the clock signal supplied from the driver in the waveguide and a receiving antenna 21 which receives the clock signal transmitted in the waveguide to supply it to the receiver are arranged. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device using a metal waveguide as a waveguide dedicated to a clock.

  In a system LSI that uses a clock in the GHz band, a distribution device called an H-tree is used for clock distribution (see, for example, Patent Document 1). Within the same clock domain distributed by this H-tree, the clock skew can be ignored.

  However, skew occurs between different clock domains, and skew is also caused by variations in characteristics of buffers arranged in the tree. In addition, as the clock frequency increases, the budget for skew becomes more severe and the power consumption increases.

  As another conventional clock distribution, a method called a sulphasic clock is also known (see, for example, Non-Patent Document 1). This sulphatic clock distribution is a technique for obtaining a clock wiring having no skew over a wide range by making a standing wave stand by opening one end of a transmission line having the same wavelength as the clock frequency.

  However, in this distribution method, since the loss of the transmission line on silicon (Si) is large, it is difficult to obtain complete reflection, and a skew actually occurs. In particular, Si has a large transmission loss at high frequencies, and is not suitable for high frequency clocks. In addition, skew is also caused due to the difference in amplitude depending on the position on the transmission line.

As described above, according to the conventional technology, as the clock frequency increases, the skew of the clock phase supplied from the global clock increases, which affects the jitter budget and increases the power consumption. is there.
United States Patent No.6,876,794 B2 "Digital Systems Engineering" William J. Dally & John W. Poulton Cambridge University Press (1998/08)

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor device capable of supplying a clock signal with little skew over a wide area of a chip and reducing power consumption. is there.

  According to one aspect of the present invention, a semiconductor chip in which a driver that outputs a clock signal and a receiver that receives the clock signal are integrated, a waveguide mounted on the semiconductor chip, and a waveguide disposed in the waveguide A transmitting antenna that sends out a clock signal supplied from the driver into the waveguide, and a receiver that is arranged in the waveguide and receives the clock signal transmitted through the waveguide and supplies the received clock signal to the receiver. A semiconductor device including an antenna is provided.

  According to another aspect of the present invention, a semiconductor chip in which a driver that outputs a clock signal and a receiver that receives the clock signal are integrated, and the semiconductor chip is mounted on one surface, A multilayer wiring layer having wiring penetrating on the other surface; a waveguide mounted on the other surface of the multilayer wiring layer; and a clock signal disposed in the waveguide and supplied from the driver. There is provided a semiconductor device comprising: a transmission antenna that transmits into a wave tube; and a reception antenna that is disposed in the waveguide and receives a clock signal transmitted through the waveguide and supplies the clock signal to the receiver.

  According to still another aspect of the present invention, a first semiconductor chip in which a driver that outputs a clock signal and a receiver that receives the clock signal are integrated, and a receiver that receives the clock signal are integrated. A second semiconductor chip, a waveguide mounted between the element forming surfaces of the first and second semiconductor chips facing each other, and shared by the first and second semiconductor chips; A transmitting antenna disposed in the waveguide and transmitting a clock signal supplied from the driver into the waveguide; and a clock signal disposed in the waveguide and transmitted in the waveguide. A first receiving antenna to be supplied to a receiver in the first semiconductor chip; and a clock signal disposed in the waveguide and transmitted in the waveguide to receive the second semiconductor Tsu semiconductor device and a receiving antenna a receiver in the second supply of in-flops are provided.

  According to another aspect of the present invention, a plurality of semiconductor chips each including a receiver that receives a clock signal and integrated with at least one driver that outputs a clock signal, and the plurality of semiconductor chips. A waveguide mounted on the element forming surface and shared by the plurality of semiconductor chips, a transmission antenna disposed in the waveguide and transmitting a clock signal supplied from the driver into the waveguide; There is provided a semiconductor device including a plurality of receiving antennas disposed in the waveguide, receiving a clock signal transmitted through the waveguide, and supplying the clock signal to receivers in the plurality of semiconductor chips.

  According to the present invention, a semiconductor device capable of supplying a clock signal with little skew over a wide range of chips and reducing power consumption can be obtained.

Embodiments of the present invention will be described below with reference to the drawings.
[First Embodiment]
1 and 2 are a cross-sectional view and a plan view, respectively, schematically showing a schematic configuration of the semiconductor device according to the first embodiment of the present invention. Here, the cross section along the line XX ′ in FIG. 2 corresponds to FIG.

  As shown in FIG. 1, the semiconductor device has a configuration in which a semiconductor chip 11 is mounted on one surface of a multilayer wiring layer 12 and a waveguide 13 is mounted on the other surface of the multilayer wiring layer 12. . For the connection between the multilayer wiring layer 12 and the waveguide 13, for example, a C4 connection (Controlled Collapse Chip Connection) using solder / solder for bumps is used.

  In the chip 11, in addition to various semiconductor elements, a driver 14 for outputting a clock signal and sending it into the waveguide 13 and a receiver 15 for receiving the clock signal are integrated. The driver 14 is supplied with a clock signal CLK having a predetermined frequency from a PLL (phase-locked loop) circuit. A connection point between one electrode of the MIM-capacitor 16 serving as a protection element and one end of the resistor 17 is connected to the input end of the receiver 15. A constant current source 18 is connected between the other end of the resistor 17 and a ground point.

  The multilayer wiring layer 12 is formed of a multilayer wiring layer of a Si chip, a wiring board, or the like, and includes wiring conductors 19-1 and 19-2 penetrating from the mounting surface side of the chip 11 to the mounting surface side of the waveguide 13. ing. These wiring conductors 19-1 and 19-2 are electrically connected to the transmission antenna 20, the reception antenna 21, and the ground conductor disposed in the waveguide 13. Of the three wires in each of the wiring conductors 19-1 and 19-2, one at the center is connected to the antennas 20 and 21, and two on both sides are connected to the ground conductor.

  The waveguide 13 is a rectangular metal waveguide formed using, for example, MEMS (Micro-Electro-Mechanical Systems) technology. The metal forming the waveguide 13 is sufficiently thick with respect to the skin thickness. As shown in FIG. 2, the clock signal supplied from the PLL circuit 10 integrated in the chip 11 to the transmitting antenna 20 disposed in the center of the chip 11 via the driver 14 is sent into the waveguide 13. Is done. The clock signal propagated in the waveguide 13 is received by receiving antennas 21-1, 21-2, 21-3,... Arranged in a matrix.

  Since the waveguide 13 has a much lower loss than a planar transmission line, the signal attenuation inside the waveguide 13 is small. Further, when viewed in a cross section parallel to the wave propagating in the waveguide 13, the phases are equal. Further, as shown in FIG. 3, when the width of the waveguide 13 is a, the phase velocity Vp becomes very high by bringing 2a closer to the clock wavelength λ, and the waveform having the same phase is almost entirely in the plane. can get. Therefore, if the waveguide 13 is a resonator, the phase is the same over the entire surface. Moreover, unlike the sulphasic clock distribution, there is no “node” where the voltage control is zero (a metal surface is a node).

  FIG. 4 is a cross-sectional view showing a configuration example in which the waveguide 13 shown in FIGS. 1 to 3 is formed using an LSI manufacturing process. The waveguide 13 is formed by bonding a metal substrate 31, a waveguide side wall portion 32, and a Si interposer 33. For example, the waveguide side wall portion 32 is formed by bonding two Si substrates 32A and 32B having a plane orientation (110) and performing etching to form a side wall structure of the waveguide. A barrier metal 34 is formed on the portion, and a plating layer 35 is formed of a metal such as Cu / Au. The Si interposer 33 is obtained by forming a through hole in a Si substrate and forming a plating layer 36 in the through hole. Part of the plated layer (36A, 36B, 36C) functions as an antenna, and part (36D, 36E) forms a connection part between the ground electrode on the lower surface of the waveguide and the side wall part. Bumps 37, 37,... Are formed on the antenna and the ground electrode, respectively.

  Next, in the configuration as described above, the propagation of the clock signal in the waveguide 13 will be described with reference to FIGS. FIG. 5 shows the TE10 mode electromagnetic field distribution, where the broken line represents the magnetic field and the solid arrow represents the direction of the electric field. As shown in FIG. 6, by vertically setting metal rods (transmitting antenna 20 and receiving antenna 21) in the waveguide 13, the electric field distribution shown in FIG. Is possible. Such a metal rod can be inserted into an arbitrary position in the waveguide 13.

  Note that the half value λ / 2 of the cutoff wavelength in vacuum of the waveguide 13 is 15 cm at 1 GHz, 3 cm at 5 GHz, and 1.5 cm at 10 GHz, for example, compared to the size of the chip 11 (about 10 mm square). However, it can be adjusted by filling the waveguide 13 with a low-loss dielectric (for example, a gas having a high dielectric constant). Further, as shown in FIG. 7, by forming a recess 22 in a part of the waveguide 13, the cutoff wavelength can be increased even when the width a of the waveguide 13 is the same. Specifically, the width X of the dent X = a / 2 and the depth Y = b × 9/10 are about 2.5 times.

  Therefore, according to the semiconductor device configured as described above, the waveguide 13 has much lower loss than the planar transmission line, and therefore, even if the clock frequency is increased, the skew is spread over a wide range of the chip. A small number of clocks can be supplied and power consumption can be reduced.

  In addition, the above-described semiconductor device that propagates a clock signal using the waveguide 13 only needs to integrate the driver 14 and the receiver 15 having a relatively simple circuit configuration in the chip 11, so that an optical fiber or the like can be used. In comparison with a semiconductor device that propagates a clock signal, a pattern occupying area can be reduced, and it can be used over the entire area of the chip. In a semiconductor device that optically propagates a clock, a photoelectric conversion circuit that converts an optical signal into an electric signal requires a large pattern, and is effective for a part of the chip but is used over the entire area. It is difficult.

  In the first embodiment, the configuration in which the chip 11 is mounted on the multilayer wiring layer 12 and the waveguide 13 is mounted on the multilayer wiring layer 12 has been described as an example. However, the waveguide 13 may be directly mounted in the wiring region on the element forming surface side of the chip 11. Also in this case, for example, a C4 connection using solder / solder for bumps can be used.

[Second Embodiment]
FIG. 8 is a sectional view schematically showing a schematic configuration of a semiconductor device according to the second embodiment of the present invention. In this semiconductor device, the chip 11 is thinned, and the waveguide 13 is mounted on the back side of the element formation surface.

  In the chip 11, a PLL circuit that generates a clock signal CLK, a driver 14 for sending out the clock signal, and a receiver 15 that receives the clock signal are integrated. A connection point between one electrode of the MIM-capacitor 16 serving as a protection element and one end of the resistor 17 is connected to the input end of the receiver 15. A constant current source 18 is connected between the other end of the resistor and the ground point.

  Further, the chip 11 is made of tungsten or the like, and through electrodes 24-1 and 24-2 penetrating the chip 11 are provided. One end of each of the through electrodes 24-1 and 24-2 protrudes into the waveguide 13 and functions as the transmitting antenna 20 and the receiving antenna 21. The through electrodes 24-1 and 24-2 are formed in the through holes formed in the chip 11 with an insulating film or the like interposed therebetween, and are electrically insulated from the chip 11. The through electrode 24-1 is electrically connected to the output end of the driver 14 via a wiring conductor formed on the main surface of the chip, and the through electrode 24-2 is a wiring conductor formed on the main surface of the chip. And is electrically connected to the input end of the receiver 15.

  Even with such a configuration, as in the first embodiment, a clock signal with little skew can be supplied over a wide range of the chip and the power consumption can be reduced even when the frequency is increased.

[Third Embodiment]
FIG. 9 is a sectional view schematically showing a schematic configuration of a semiconductor device according to the third embodiment of the present invention. This semiconductor device basically has the same configuration as that of the second embodiment, but differs in that a harmonic clock is distributed. That is, an odd harmonic component of the clock frequency is extracted and transmitted from the transmitting antenna 20 into the waveguide 13 (the fundamental wave component is cut off and not propagated). The frequency used in the PLL circuit is 1 / n (n = 3, 5,...) Of the clock frequency f, and the clock signal of f / n (Hz) is supplied from the driver 14 to the transmission antenna 20.

  Here, the clock of the PLL has the same frequency as the chip, and the harmonic component f (Hz) of the clock propagates in the waveguide 13. The harmonic component of the clock signal propagated through the waveguide 13 and received by the receiving antenna 21 is received by the receiver 15. This harmonic component is frequency-divided and used by the frequency dividing circuit 23 integrated in the chip 11.

  Even with such a configuration, as in the first and second embodiments, even if the frequency is increased, a clock signal with less skew can be supplied over a wide range of the chip, and power consumption can be reduced.

[Fourth Embodiment]
FIG. 10 is a cross-sectional view schematically showing a schematic configuration of the semiconductor device according to the fourth embodiment of the present invention. In this semiconductor device, a waveguide 13 is sandwiched between two chips 11-1 and 11-2, and the waveguide 13 is shared by these chips 11-1 and 11-2. That is, the device formation surfaces of the semiconductor chips 11-1 and 11-2 are opposed to each other, and the waveguide 13 is sandwiched between them.

  Although not shown, the chip 11-1 or 11-2 is provided with a driver for sending out a clock signal CLK, and each of the chips 11-1 and 11-2 is provided with a receiver for receiving the clock signal. . A connection point between one electrode of the MIM-capacitor serving as a protection element and one end of a resistor is connected to the input end of the receiver. A constant current source is connected between the other end of the resistor and the ground point. A transmitting antenna and a receiving antenna protrude into the waveguide 13. Then, a clock signal is sent from one clock supply source (driver) to the two chips 11-1 and 11-2 through the waveguide 13.

  Even with such a configuration, as in the first to third embodiments, even if the frequency is increased, a clock signal with less skew can be supplied over a wide range of the chip, and power consumption can be reduced.

  In the first to fourth embodiments described above, the structure in which both ends of the waveguide 13 are opened has been described as an example. However, if one end is covered with a metal plate, the light is radiated and dissipated to the opposite side as a reflector. Clock energy can be used. Moreover, when both ends are covered with a metal plate, it can be used as a cavity resonator.

[Fifth Embodiment]
FIG. 11 is a plan view showing a schematic configuration of a semiconductor device according to the fifth embodiment of the present invention. In this semiconductor device, the transmitting antenna 20 is provided at the corner portion of the waveguide 13, and the receiving antennas 21-1, 21-2, 21-3,... Are dispersed and arranged in a matrix in the region excluding the corner portion. Has been.

  Even with such an arrangement configuration of the transmission antenna 20 and the reception antennas 21-1, 21-2, 21-3,..., The same effects as those of the first embodiment can be obtained. Of course, the antenna arrangement of this embodiment can be applied to the configurations of the second to fourth embodiments.

[Sixth Embodiment]
FIG. 12 is a plan view showing a schematic configuration of a semiconductor device according to the sixth embodiment of the present invention. In this semiconductor device, the waveguide 13 is mounted on the element formation surfaces of the plurality of semiconductor chips 11-1, 11-2, 11-3, and the plurality of semiconductor chips 11-1, 11-2, 11-3 are used. The waveguide 13 is shared. In the semiconductor chip 11-1, a driver that outputs a clock signal and a receiver that receives the clock signal are integrated. In addition, receivers that receive clock signals are integrated in the semiconductor chips 11-2 and 11-3.

  In the waveguide 13, a transmission antenna 20 that sends out a clock signal supplied from a driver in the semiconductor chip 11-1, and a received clock signal to receive the semiconductor chip 11-1 and 11-2. , 11-3, a plurality of receiving antennas 21-1, 21-2, 21-3,.

According to such a configuration, a clock signal with little skew can be supplied to the three semiconductor chips 11-1, 11-2, and 11-3, and power consumption can be reduced. In the sixth embodiment, Although the three semiconductor chips 11-1, 11-2, and 11-3 are configured to share the waveguide 13, they may be shared by two or may be shared by four or more.

  Although the present invention has been described using the first to sixth embodiments, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the invention in the implementation stage. It is possible. Each of the above embodiments includes inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. For example, the third embodiment using a frequency dividing circuit can be applied to the first, second, and fourth to sixth embodiments. In addition, even if some constituent elements are deleted from all the constituent elements shown in each embodiment, at least one of the problems described in the column of the problem to be solved by the invention can be solved, and is described in the column of the effect of the invention. In a case where at least one of the obtained effects can be obtained, a configuration in which this configuration requirement is deleted can be extracted as an invention.

1 is a cross-sectional view schematically showing a schematic configuration of a semiconductor device according to a first embodiment of the present invention. 1 is a plan view schematically showing a schematic configuration of a semiconductor device according to a first embodiment of the present invention. The perspective view for demonstrating the relationship between the dimension of a waveguide, and the wavelength of a clock signal. FIG. 4 is a cross-sectional view showing a configuration example when the waveguide shown in FIGS. 1 to 3 is formed using an LSI manufacturing process. The schematic diagram which shows the electromagnetic field distribution of TE10 mode for demonstrating propagation of the clock signal in a waveguide. Sectional drawing which is a thing for demonstrating propagation | transmission of the clock signal in a waveguide, and shows a mode that the metal rod set up perpendicularly in the waveguide is used for a transmission antenna and a reception antenna. Sectional drawing for demonstrating propagation of the clock signal in a waveguide, and explaining the structure which controls a cutoff wavelength. Sectional drawing which shows typically schematic structure of the semiconductor device which concerns on 2nd Embodiment of this invention. Sectional drawing which shows typically schematic structure of the semiconductor device which concerns on 3rd Embodiment of this invention. Sectional drawing which shows typically schematic structure of the semiconductor device which concerns on 4th Embodiment of this invention. The top view which shows schematic structure of the semiconductor device which concerns on 5th Embodiment of this invention. The top view which shows schematic structure of the semiconductor device which concerns on 6th Embodiment of this invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 10 ... PLL circuit, 11, 11-1, 11-2, 11-3 ... Semiconductor chip, 12 ... Multilayer wiring layer, 13 ... Waveguide, 14 ... Driver, 15 ... Receiver, 16 ... MIM-capacitor, 17 ... Resistance, 18 ... Constant current source, 19-1, 19-2 ... Wiring conductor, 20 ... Transmission antenna, 21 ... Reception antenna, 22 ... Recess, 23 ... Frequency divider, 24-1, 24-2 ... Through electrode.

Claims (5)

A semiconductor chip in which a driver that outputs a clock signal and a receiver that receives the clock signal are integrated; and
A waveguide mounted on the semiconductor chip;
A transmitting antenna disposed in the waveguide and for sending a clock signal supplied from the driver into the waveguide;
A semiconductor device comprising: a receiving antenna disposed in the waveguide, receiving a clock signal transmitted through the waveguide and supplying the clock signal to the receiver. A semiconductor chip in which a driver that outputs a clock signal and a receiver that receives the clock signal are integrated; and
The semiconductor chip is mounted on one surface, and a multilayer wiring layer having a wiring penetrating from one surface to the other surface;
A waveguide mounted on the other surface of the multilayer wiring layer;
A transmitting antenna disposed in the waveguide and for sending a clock signal supplied from the driver into the waveguide;
A semiconductor device comprising: a receiving antenna disposed in the waveguide, receiving a clock signal transmitted through the waveguide and supplying the clock signal to the receiver. A first semiconductor chip in which a driver that outputs a clock signal and a receiver that receives the clock signal are integrated;
A second semiconductor chip integrated with a receiver for receiving the clock signal;
A waveguide mounted between the element forming surfaces of the first and second semiconductor chips facing each other, and shared by the first and second semiconductor chips;
A transmitting antenna disposed in the waveguide and for sending a clock signal supplied from the driver into the waveguide;
A first receiving antenna that receives a clock signal transmitted through the waveguide and supplies the clock signal to a receiver in the first semiconductor chip;
A second receiving antenna disposed in the waveguide, receiving a clock signal transmitted in the waveguide, and supplying the clock signal to a receiver in the second semiconductor chip. apparatus. A plurality of semiconductor chips each having a receiver for receiving a clock signal integrated therein and a driver for outputting the clock signal at least one integrated;
A waveguide mounted on the element formation surface of the plurality of semiconductor chips and shared by the plurality of semiconductor chips;
A transmitting antenna disposed in the waveguide and for sending a clock signal supplied from the driver into the waveguide;
A plurality of receiving antennas arranged in the waveguide, receiving a clock signal transmitted through the waveguide, and supplying the clock signal to the receivers in the plurality of semiconductor chips, respectively. .   5. The semiconductor device according to claim 1, wherein the receiver includes a frequency dividing circuit and divides and uses a harmonic component of a clock signal propagated in the waveguide. 6. .

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