JP2008146742A - Nonvolatile semiconductor memory device and its processing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory device in which a waiting time is reduced, that is accompanied by erasion processing executed before execution of processing other than erasion for securing a free region when processing other than erasion is executed. <P>SOLUTION: When erasion processing E1 is executed to secure a free capacity after processing other than erasion T1 is executed, erasion processing E1 is divided into erasion small processing E1a constituted of before erasion processing Er1 and erasion small original processing Ee1a and erasion small processing E1b constituted of erasion small original processing Ee1b and after erasion processing Eo1, processing other than erasion T2 is executed after finish of erasion small processing E1a, and residual erasion small processing E1b is executed after finish of this processing other than erasion T2 and erasion processing E1 is completed. After erasion processing E1 is finished (that is, erasion small processing E1b is finished), other processing items other than erasion T3, T4, ... are executed successively. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a nonvolatile semiconductor memory device such as a flash memory or an EEPROM (Electronically Erasable and Programmable Read Only Memory) and a processing method thereof.

  Along with the miniaturization of today's semiconductor processes, the number of circuit elements that can be mounted on a semiconductor chip of the same size has increased, and various types of small and highly functional semiconductor devices such as IC cards have been provided.

  In the semiconductor device such as an IC card, as the number of data to be handled increases year by year, in the nonvolatile memory area provided as a processing data storage area in the device, a flash memory is used instead of the conventional EEPROM. Has come to be used.

  A flash memory has a configuration in which an operation of erasing information recorded in units of blocks composed of a plurality of memory cells is performed. The capacity per block is usually 64 kB or 16 kB. However, when handling small capacity data, a small capacity block of about 1 kB or 2 kB is employed in order to reduce the waste area (for example, , See Patent Document 1). Even when such a small-capacity block is adopted, as described above, if the processing data increases, an erasing operation for each block is required to secure a free space necessary for the processing.

  FIG. 8 is a graph showing the time required for the erase operation for each block capacity. FIG. 8A shows a case where the block capacity is 16 kB, FIG. 8B shows a case where the block capacity is 4 kB, and FIG. c) shows the erase time when the block capacity is 1 kB. In FIG. 8, the erasing operation is classified into three processes of pre-erasing processing, main erasing processing, and post-erasing processing according to the processing contents, and the time required for each processing is described. Here, the pre-erase process is executed before the main erase process for the purpose of aligning the variations in the threshold voltage before erasure of the memory cells to be erased and preventing the memory cells having a low threshold voltage before the erase from being over-erased. The main process includes an erase voltage application process for each memory cell belonging to the target block to be erased and a verify process for confirming the erased state of the memory cell to be erased. The process includes a write process that is executed after the main erase process for the purpose of raising the threshold voltage for an over-erased memory cell whose threshold voltage after erasure is lower than the threshold voltage of other memory cells.

  For example, according to FIG. 8A, when the erase operation is executed when the block capacity is 16 kB, it takes about 160 ms for the pre-erase process, about 200 ms for the main erase process, and about 160 ms for the post-erase process. Requires about 0.52 s.

US Pat. No. 5,581,503

  Taking an IC card as an example, when performing non-erasing processing such as data writing and authentication, it is assumed that the erasing processing is performed before execution of the non-erasing processing for the purpose of securing a free space. FIG. 9 conceptually shows each processing flow of the nonvolatile semiconductor memory device including an erasing process performed for the purpose of securing a free capacity before the execution of the non-erase process. If the free capacity cannot be secured after sequentially executing the non-erase processes T90, T91, the empty process is secured by executing the erase process E90 before executing the non-erase process T92, and then the non-erase processes T92, T93,. Are executed sequentially. As described above, the erasing process E90 is configured by executing the pre-erase process Er90, the main erase process Ee90, and the post-erase process Eo90 in this order. After the execution of the erasure process E90 is completed, when the non-erase process is sequentially executed and the free space becomes insufficient, the erasure process is executed again to secure the free space.

  In the above case, since the non-erase process T92 is executed after the erase process E90 is completed, the time required from the instruction to execute the non-erase process T92 to the actual completion of the non-erase process T92 is as described above. This is the sum of the erase time E90 and the time required for the non-erase process T92 (several ms to several tens of ms). If the block capacity is 16 kB, approximately 0.52 to 0.55 s is required. Furthermore, when the response time of the entire IC card requires about twice as long as the total time, 1 s is required from when the instruction to execute the non-erase process is performed until the non-erase process is actually completed. A waiting time longer than that will be required. It is generally said that when a waiting time of 0.3 s or longer is required, the user of the IC card feels that the operation is slow. There is a high possibility that the IC card will be recognized as being inconvenient for the user.

  FIG. 10 is a graph showing the processing time for each process for non-erase processing (authentication processing, billing processing, etc.) and erasing processing according to the capacity of each block. FIG. In the case of 16 kB, FIG. 10B shows the case where the block capacity is 4 kB, and FIG. 10C shows the case where the block capacity is 1 kB.

  If an empty area cannot be secured by executing the non-erasing process a plurality of times, the erasing process is executed, and after the erasing process is completed, the non-erasing process is executed again. For example, when the block capacity is 16 kB (FIG. 10A), the erasing process E90 is executed to secure a free area after the non-erasing process T91 is finished and before the next non-erasing process T92 is executed. It takes about 0.55 s from the end of the non-erase process T91 to the end of the next non-erase process T92, and about 1 s for the IC card to respond. This time is required for the IC card user. It will make you feel slow. Such an erasure process is automatically executed once every time a vacant area cannot be secured, usually once every several or tens of erasures, and each time the IC card user feels stressed about the slowness of the process. It will be.

  Similarly, when the block capacity is 4 kB, as shown in FIG. 8B, approximately 40 ms is required for the pre-erase process, approximately 200 ms for the main erase process, and approximately 40 ms for the post-erase process. .28s of time is required. Considering the time required for the non-erasing process, the response time of the entire IC card requires about 0.56 to 0.58 s. At this time, as shown in FIG. 10B, after the end of the non-erase process T91, the erase process E90 is executed to secure a free area before the next non-erase process T92 is executed. It takes about 0.28 s from the end of the outer process T91 to the end of the next non-erase process T92, and about 0.56 to 0.58 s until the IC card responds. This makes the card user feel slow in processing.

  Similarly, when the block capacity is 1 kB, as shown in FIG. 8C, the pre-erase process takes about 10 ms, the main erase process takes about 200 ms, the post-erase process takes about 10 ms, and the total erase operation is about 0. .22s of time is required. Considering the time required for the non-erasing process, the response time of the entire IC card requires about 0.44 to 0.46 s. At this time, as shown in FIG. 10 (c), after the non-erase process T91 is completed, before the next non-erase process T92 is executed, the erase process E90 is executed to secure a free area, It takes about 0.22 s from the end of the outer process T91 to the end of the next non-erase process T92, and about 0.44 to 0.46 s until the IC card responds. This makes the card user feel slow in processing.

  In view of the above problems, the present invention relates to a nonvolatile semiconductor memory device that reduces a waiting time associated with an erasing process that is executed before execution of a non-erase process in order to secure a free area when executing the non-erase process. The purpose is to provide. Another object of the present invention is to provide a method for processing such a nonvolatile semiconductor memory device.

  In order to achieve the above object, a nonvolatile semiconductor memory device according to the present invention includes information recorded in a plurality of memory cells belonging to a target block by performing pre-erase processing, main erase processing, and post-erase processing in this order. In the nonvolatile semiconductor memory device in which the erase process is performed, the pre-erase process is performed to adjust a threshold voltage for a plurality of memory cells belonging to the target block before the erase main process is performed. Including a write process, wherein the main erase process includes an erase voltage application process and a verify process for all memory cells belonging to the target block, and the post-erase process belongs to the target block after execution of the main erase process. Including a write process performed for adjusting a threshold voltage for a plurality of memory cells, wherein the erase main process is performed on a non-target block other than the target block. To start the execution of the erase outside processing for click, the first, wherein the current block is automatically interruptable the verification process in the plurality of small blocks constituting the.

  According to the first characteristic configuration of the nonvolatile semiconductor memory device according to the present invention, the erase process for all memory cells belonging to the target block to be erased in one erase process is not completely completed. However, the non-erase process can be executed after the erase main process is interrupted. Conventionally, after executing non-erase processing such as authentication processing and billing processing, if it is necessary to execute erase processing to secure a free area before executing the next non-erase processing, all of the blocks belonging to the target block Since the next non-erase process is not executed until the erase process is completed for the memory cell, it took a long time to complete the non-erase process after the erase process. Even if erasure processing is not completed for all memory cells belonging to a block, the erasure processing can be automatically interrupted in units of small blocks that make up the target block, and after-interrupt processing is executed. Thus, the start of execution of the non-erasure process can be accelerated, thereby shortening the waiting time until the non-erasure process is completed. Note that even if a function for interrupting the erasure process by an external operation is provided, the erasure process can be automatically interrupted without performing the external operation. Time can be shortened automatically.

  It should be noted that it is possible to store the interruption location of the erasure process interrupted after the erasure processing is interrupted, and to execute the erasure process subsequently from the interruption location when the execution of the non-erasure process is completed. At this time, when the erase process is interrupted and the non-erase process is executed and the erase process is resumed from the interrupted location, the interrupted location is stored by the verify address that is the address of the memory cell to be verified. As good.

  Further, in addition to the first feature configuration, the nonvolatile semiconductor memory device according to the present invention is performed continuously without going through the verify process according to the number of the memory cells belonging to the small block. A second feature is that the number of times of voltage application related to the erase voltage application process is changed.

  The smaller the number of memory cells to be verified in the erase process (hereinafter referred to as “erase small process”) performed on the same small block, the more the memory cells that could not be erased correctly in each verify process. Probability of verifying decreases. In other words, if the number of memory cells to be verified in one erase small process is large, memory cells that are not correctly erased are included in the verification target as compared to the case in which the number of memory cells to be verified in one erase small process is small. Conversely, when the number of memory cells to be verified in one erase small process is small, there is a low possibility that memory cells that are not correctly erased are included as verification targets.

  Therefore, according to the second characteristic configuration of the nonvolatile semiconductor memory device according to the present invention, when the number of memory cells to be verified in one erase small process is relatively large, many erase pulses are applied in advance. In other words, if the number of memory cells to be verified in one small erase process is relatively small, the number of erase pulses to be applied is reduced. Time can be shortened. That is, according to this configuration, it is possible to achieve both reduction in processing time and execution of a normal erase operation.

  In addition to the first or second characteristic configuration, the nonvolatile semiconductor memory device according to the present invention has a third characteristic that each of the small blocks includes the same number of the memory cells.

  According to the third characteristic configuration of the nonvolatile semiconductor memory device according to the present invention, the processing time required for each erasing sub-process can be made substantially uniform, and the execution of the non-erasing process executed before the erasing process is performed. After completion, the time required until the start of the non-erase process executed after the erase subprocess can be made substantially uniform. Further, depending on the number of processes in which the same erase process (especially the erase process) is divided into N (N is a natural number of 2 or more) the erase process that is being performed (especially the erase process) It is possible to easily set the erasure point of the erasure sub-process. For example, in the case of the m-th erasure sub-process (m is a natural number less than or equal to N), An address corresponding to an approximate m / N position of all the memory cells belonging to the block may be set.

  Further, a processing method of a nonvolatile semiconductor memory device according to the present invention is a processing method in the nonvolatile semiconductor memory device having the first characteristic configuration, after the pre-erase processing is performed on the entire target block. The erase main process is sequentially executed for each small block, and the post-erase process is executed on the entire target block after the erase main process is executed on the final small block. Before the end of the main erase process for the last small block, after the main erase process for the one small block is completed, before the start of the main erase process for the other small block, The first feature is that non-erase processing is performed on the target block.

  According to the first feature of the processing method of the nonvolatile semiconductor memory device according to the present invention, the erase process is automatically temporarily suspended after execution of the erase main process for each small block, and the execution of the non-erase process is started. Therefore, the execution start of the non-erase process can be greatly accelerated compared to the conventional configuration in which the execution of the non-erase process is not started until the erase process is completely completed. Therefore, it is possible to greatly reduce the waiting time required to complete the execution of the non-erase process executed after the erase process after the execution of the non-erase process executed before the erase process.

  In addition to the first feature, the processing method of the nonvolatile semiconductor memory device according to the present invention provides the erase voltage for the entire target block before the erase main process for the final small block. After performing the application process, when the verify process for one small block is completed, the main erase process is interrupted and the non-erase process is executed. After the execution of the non-erase process is completed, the entire target block is processed. After performing the erase voltage application process, the verify process is performed on one small block that has not been subjected to the verify process before the execution of the non-erase process among the plurality of small blocks belonging to the target block. The second feature is to execute.

  In addition to the first or second feature, the processing method of the nonvolatile semiconductor memory device according to the present invention further includes the erasing in another erasing process after the erasing process in the erasing process is finished. A third feature is that the non-erase processing for the non-target block is executed one or more times before the start of preprocessing.

  According to the configuration of the present invention, when executing the non-erase process, the waiting time associated with the erase process executed before the non-erase process can be significantly reduced in order to secure a free area.

  Hereinafter, embodiments of a nonvolatile semiconductor memory device according to the present invention (hereinafter appropriately referred to as “device of the present invention”) and a processing method thereof (hereinafter appropriately referred to as “method of the present invention”) will be described with reference to the drawings. I will explain.

  The apparatus according to the present invention performs non-erase processing in order to secure the free space when there is not enough free space when executing processing other than erase processing such as data writing (hereinafter collectively referred to as “non-erase processing”). Non-volatile semiconductor memory device that executes an erasing process before executing the erasing process, and has a feature in the execution method of the erasing process, so that it is possible to reduce the time delay of executing the non-erase process associated with the execution of the erasing process To do. In each of the following embodiments, the description will be focused on the processing methods including the execution of the erasing process, which is a characteristic part of the apparatus of the present invention, and the description of the same parts as those of the conventional configuration will be omitted.

[First Embodiment]
A first embodiment (hereinafter referred to as “this embodiment” as appropriate) of a device and a method of the present invention will be described with reference to FIGS.

  FIG. 1 shows a conceptual operation flow of the apparatus of the present invention according to this embodiment, following FIG. 9 of the conventional configuration. In FIG. 1, it is assumed that a free space cannot be secured after execution of the non-erase process T1. Note that the processing groups t1 to t4 in FIG. 1 will be described later.

  As shown in FIG. 1, after executing the non-erase process T1, the erase process E1 is executed to secure a free space. At this time, the erasing process E1 is divided into an erasing small process E1a composed of an erasing pre-processing Er1 and an erasing small book processing Ee1a, and an erasing small process E1b composed of an erasing small book processing Ee1b and a post-erasing process Eo1. After the erase small process E1a is completed, the non-erasure process T2 is executed. After the non-erase process T2 is completed, the remaining erase small process E1b is executed to complete the erase process E1. After the erasing process E1 is completed (that is, after the erasing small process E1b is completed), other non-erasing processes T3, T4,.

  The erase book process Ee1a is a process of performing erase main process on approximately half of the memory cells targeted by the erase book process Ee1, and the erase book process Ee1b is the object of the erase book process Ee1. This is a process of performing the erase main process on the remaining memory cells that have not been processed by the erase book process Ee1a. It should be noted that the address of the memory cell subjected to the erase book process by the erase book process Ee1a is recorded internally after the completion of the erase book process Ee1a and before the start of the erase book process Ee1b. When executing the erase book block process Ee1b after the completion of the process T2, the address is read and the erase main process is performed on the remaining memory cells including the memory cell at the read address position. Good as there is.

  FIG. 2 is an example of a conceptual operation flow of the erase main process in the present embodiment. The erase booklet process Ee1a performed after the end of the pre-erase process Er1 and the erase booklet process Ee1b performed after the end of the non-erase process T2 are different only in the start address and end address of the verify process, and the flow of the operation Both are common. In the following, the case where the erased book processing Ee1a is executed will be described first, and then the erased book processing Ee1b will be described.

  After the end of the pre-erase process Er1, the erase voltage is applied (step # 1), and the execution of the erased booklet process Ee1a is started. This erase voltage is constituted by a pulse voltage, and for example, an erase pulse voltage having a pulse width of 4 ms can be applied intermittently 10 times.

  Next, a verify address is set (step # 2). In the case of the erase bookbinding process Ee1a, an address set as an initial value in advance is set.

  Next, verify processing is performed on the memory cell corresponding to the set initial address (step # 3). At this time, if information has not been correctly erased from the memory cell (if verification fails: No in step # 3), the process returns to step # 1 again to apply the erase voltage. On the other hand, if the information has been erased correctly (if verification is successful: Yes in step # 3), it is determined whether or not the verify address matches a predetermined end address (step # 4). . Here, in the case of the erase book processing Ee1a, as the final address, for example, when the address is sequentially incremented from the memory cell corresponding to the address of the initial value, a substantially intermediate position of the addresses of all the memory cells belonging to the target block The address corresponding to can be set as the end address. It is assumed that this final address is temporarily stored in advance in the device of the present invention.

  If the verify address matches this final address (Yes in step # 4), the erase booklet process is terminated and the process proceeds to the next process (step # 5). At this time, since the address of the memory cell subjected to the verify process is the initial address, it does not match the end address (No in step # 4), and the address of the memory cell to be newly verified is incremented by incrementing the verify address. Setting is performed (step # 2), and a verify process is performed on the memory cell (step # 3). Thereafter, this operation is repeated.

  In the erase booklet process Ee1a, when the verify address matches the final address (Yes in Step # 4), the process proceeds to the next process, that is, the non-erase process T2 (see FIG. 1). That is, in the erase booklet process Ee1a, it can be said that the verify process is not performed on all the memory cells belonging to the target block, and the process is interrupted in the middle of the verify process.

  Then, after the non-erase process T2 is completed, the erase booklet process Ee1b is started. Also in the erase booklet process Ee1b, after applying the erase voltage (step # 1), the verify address is set (step # 2). At this time, the final address of the erase booklet processing Ee1a is read from the inside, and the next address of this address is set as the verify address. Thus, the verify process is executed in the erase book process Ee1b following the verify process interrupted in the erase book process Ee1a.

  In the erase booklet process Ee1b, if the verify address matches the final address (Yes in step # 4), the process proceeds to the next process, that is, the post-erase process Eo1, and when this post-erase process Eo1 is completed, The non-erase process T3, the non-erase process T4,... Are sequentially executed. That is, when the post-erase process Eo1 is completed, the erase process E1 composed of the small erase processes E1a and E1b divided into two processes is effectively completed. In the case of the erase book process Ee1b, for example, when the addresses are sequentially incremented from the memory cell corresponding to the address of the initial value (the initial address in the erase book process Ee1a), the addresses of all the memory cells belonging to the target block It is possible to set the final address of the as the end address.

  FIG. 3 is a graph showing the processing time for each process in the non-erase process and the erase process according to FIG. 10 of the conventional configuration with respect to the flow shown in FIG. In FIG. 3, it is assumed that each block capacity is 2 kB as an example, and that each non-erase process is performed every 512 B. FIG. 4 conceptually illustrates the operation target block for each process in FIG. 3 (process groups t1 to t4).

  When the erasing process E1 is executed to secure a free area after the non-erase process T1 is executed and before the next non-erase process T2, the pre-erase process Er1 is first performed after the non-erase process T1 is finished as described above. Then, after executing the erase small process E1a composed of the erase booklet process Ee1a in this order, the non-erasure process T2 is executed (process group t1). Thereafter, after executing the erase small process E1b composed of the erase booklet process Ee1b and the post-erase process Eo1 in this order, the next non-erasure process T3 is executed (process group t2). After the non-erase process T3 is completed, an empty area is secured as a result of the completion of the erase process E1, and therefore the non-erase process T4 (process group t3) and T5 (process group t4) are sequentially executed. Further, after the end of the non-erase process T5, when it is necessary to perform an erase process to secure a free area when the next non-erase process is executed, a process group corresponding to the process groups t1 and t2 Will be executed again.

  For example, as shown in FIG. 4, when the non-erase processes T2 to T5 are processes for the memory cells belonging to the block B1, and the erase process E1 is a process for the memory cells belonging to the block B2, the process group t1 The memory cell belonging to one of the write blocks B1a is subjected to the non-erase process, the entire block B2 is subjected to the erase voltage application process of the pre-erase process and the erase main process, and the block B2 A verify process is performed on one small block B2i. Then, by the processing group t2, the memory cell belonging to B1b which is another writing block in the block B1 is subjected to the non-erase process, and the erase voltage in the main erase process is applied to the entire block B2. After the process and another small block B2j in the block B2, the verify process is performed, and then the entire block B2 is subjected to a post-erase process. Since the erase operation for the block B2 is completed by the processing groups t1 and t2, thereafter, the memory cell belonging to B1c, which is another write block in the block B1, is erased by the processing group t3 (outer erase process T4). Outer processing is performed, and processing group t4 (outer erasure processing T5) performs out-erase processing on the memory cells belonging to B1d, which is another writing block in the block B1. In this way, the processing is performed on all the memory cells belonging to the block B1 by the processing groups t1 to t4.

  In such a configuration, after the end of the non-erase process T1, the waiting time required for the end of the next non-erase process T2 is the time required for the pre-erase process Er1 (about 20 ms), and the erased book process Ee1a. This is the sum of the time required (about 100 ms) and the time required for the non-erase processing T2 (about 5 ms), which is about 125 ms. Therefore, even when the response time of the entire IC card requires about twice the total time, the non-erasure process T2 is actually completed after an instruction to execute the non-erase process T2 is issued. The waiting time required until the time is shortened to about 0.25 s, which is lower than 0.3 s, which is a waiting time for which the user feels stress.

  Similarly, after the end of the non-erase process T2, the waiting time required for the end of the next non-erase process T3 is the time required for the main erase process Ee1b (about 100 ms) and the time required for the post-erase process Eo1 (about 20 ms). ) And the time required for the non-erase process T3 (about 5 ms), which is about 125 ms. Accordingly, similarly to the waiting time of the non-erasing process T2, the waiting time required from the instruction to execute the non-erasing process T3 until the non-erasing process T3 is actually completed is shortened to about 0.25 s. It will be less than 3 s.

  That is, according to the configuration of the present embodiment, the waiting time until the execution of the non-erase process is completed can be greatly shortened compared to the conventional configuration. For example, when the present invention device is used for an IC card or the like, When normal processing (authentication processing, billing processing, etc.) of the IC card is performed as the processing, the waiting time until the processing is completed is greatly shortened, and the stress on the user can be reduced.

  In FIG. 3 described above, it has been described that each block capacity is 2 kB and each non-erase process is performed every 512 B. However, even when the non-erase process is performed every 1 kB, the process is performed once. The same explanation is possible except that the number of target blocks to be processed for non-erase processing increases. In this case, the non-erase processing for one block is completed by two processing groups.

[Second Embodiment]
A second embodiment (hereinafter referred to as “this embodiment” as appropriate) of the device and method of the present invention will be described below with reference to FIGS. Note that the present embodiment is different from the first embodiment only in the number of divisions of the erasing process, and the others are the same. Therefore, only different parts will be described below.

  FIG. 5 shows a conceptual operation flow of the device of the present invention in this embodiment, following FIG. 1 of the first embodiment. In FIG. 5, it is assumed that a free space cannot be secured after execution of the non-erase process T11.

  As shown in FIG. 5, after executing the non-erase process T11, the erase process E2 is executed to secure a free space. At this time, the erasing process E2 is composed of an erasing small process E2a composed of an erasing pre-processing Er2 and an erasing small book processing Ee2a, an erasing small processing E2b composed of an erasing small book processing Ee2b, and an erasing small book processing Ee2c The process is divided into a small erase process E2c, a small erase book process Ee2d, and a small erase process E2d composed of a post-erase process Eo2. Then, after the erase small process E2a is finished, the non-erase process T12 is executed, after the erase non-erase process T12 is finished, the erase small process E2b is executed, and after the erase process E2b is finished, the erase non-erase process T13 is executed. After the end of the outer process T12, the small erase process E2c is executed. After the end of the small erase process E2c, the non-erase process T4 is executed. After the end of the non-erase process T14, the small erase process E2d is executed to execute the erase process E2. Complete. After the erasing process E2 is finished (that is, after the erasing small process E2d is finished), the other erasing processes T15, T16,... Are sequentially executed, or the other erasing process E3 is divided in the same manner as the erasing process E2. Executed by the method.

  In such a configuration, when execution of the erasure process E2 is started after completion of the non-erase process T11, first, the pre-erase process Er2 is executed, and then the erase booklet process Ee2a is changed to the diagram in the first embodiment. This is executed according to the same procedure as in the flow of No. 2. That is, after an erase voltage is applied (step # 1), an initial address is set as a verify address (step # 2), and verification verification is performed on the set verify address (step # 3). If successful (Yes in step # 3), it is determined whether or not the verify address matches a predetermined end address (step # 4). This final address changes depending on the number of divisions in the erasing process E2. In the present embodiment, since the erase process E2 is divided into four erase subprocesses E2a to E2d, an address corresponding to approximately ¼ position of all the memory cells belonging to the target block to be erased is the final address. Can be set as Until the final address coincides with the verify address, the address of the memory cell to be verified is newly set (step # 2), and the verify process is performed on the memory cell (step # 3). If the final address matches the verify address (Yes in step # 4), the process proceeds to the next process, that is, the non-erase process T12.

  Then, after the non-erase process T12 is completed, the erase booklet process Ee2b is started. Also in the erase small book process Ee2b, after applying the erase voltage (step # 1), the verify address is set (step # 2). At this time, the final address of the erase booklet processing Ee2a is read from the inside, and the next address obtained by incrementing this address is set as the verify address. Thus, the verify process is executed in the erase book process Ee2b following the verify process interrupted in the erase book process Ee2a. On the other hand, in the erase book processing Ee2b, an address corresponding to approximately 2/4 position of all memory cells belonging to the target block to be erased, that is, approximately the center position can be set as the end address, and this end address is verified. Until the address matches, a new memory cell address to be verified is set (step # 2), and the verify process is performed on the memory cell (step # 3). If the end address matches the verify address (Yes in step # 4), the process proceeds to the next process, that is, the non-erase process T13.

  Thereafter, the erasure process E2 is completed by similarly executing the non-erase process T13, the erase book process Ee2c, the non-erase process T14, the erase book process Ee2d, and the post-erase process Eo2 in this order. After the erasing process E2 is finished (that is, after the erasing small process E2d is finished), the other erasing processes T15, T16,... Are sequentially executed, or the other erasing process E3 is divided in the same manner as the erasing process E2. Executed by the method.

  FIG. 6 is a graph showing the processing time for each process in the non-erase process and the erase process according to FIG. In FIG. 6, similarly to FIG. 3, description will be made assuming that each block capacity is 2 kB as an example, and each non-erase process is performed every 512 B. FIG. 7 conceptually illustrates the operation target block for each process in FIG. 6, and the reference numerals given to the respective blocks correspond to the reference numerals assigned to the respective processing groups in FIG. (Processing groups t11 to t14).

  When the erasing process E2 is executed to secure a free area after the non-erasing process T11 is executed and before the next non-erasing process T12 is executed, as described above, first, after the non-erasing process T11 ends, the pre-erase process Er2 Then, after executing the erase small process E2a constituted by the erase small book process Ee2a in this order, the non-erase process T12 is executed (process group t11). Thereafter, after executing the erase small process E2b constituted by the erase booklet process Ee2b, the next non-erasure process T13 is executed (processing group t12), and thereafter the erase small process E2c constituted by the erase booklet process Ee2c is executed. After that, the next non-erasure process T14 is executed (process group t13), and then the small erase process E2d composed of the erase booklet process Ee2d and the post-erase process Eo2 is executed in this order, and then the next non-erase process T15 is executed. (Processing group t14). After the non-erase process T15 is completed, since the empty area is secured by the end of the erase process E2, other non-erase processes T16, T17,... Are executed sequentially or when the next non-erase process is executed. When it is necessary to perform an erasing process for securing a free area, the processing group corresponding to the processing groups t11 to t14 is executed again.

  For example, as shown in FIG. 7, when the non-erase processing T12 to T15 is processing for the memory cells belonging to the block B11 and the erasing processing E2 is processing for the memory cells belonging to the block B12, the processing group t11 causes the block B11 to be processed. The memory cell belonging to one of the write blocks B11a is subjected to the non-erase process, the entire block B12 is subjected to the erase voltage application process of the pre-erase process and the erase main process, and the block B12 A verify process is performed on one small block B12i. Then, by the processing group t12, the memory cell belonging to B11b, which is another writing block in the block B11, is subjected to the non-erase process, and the erase voltage in the erase main process is applied to the entire block B12. The verify process is performed on the process and another small block B12j in the block B12, and the process group t13 performs an erase-out process on a memory cell belonging to B11c, which is another write block in the block B11. In addition, the entire block B12 is subjected to the erase voltage application process in the main erase process and the verify process is performed on another small block B12k in the block B12. A non-erase process is performed on a memory cell belonging to B11d, which is another write block in B11. In addition, the entire block B2 is erased, and after the erase voltage application process in the main process and the other small block B12l in the block B12 are verified, the entire block B12 is erased. Processing is performed. These processing groups t11 to t14 complete the erase operation for the block B12. Note that after completion of the processing group t14, the non-erase process may be executed on another write target block, or the erase process may be executed on another erase target block.

  In the present embodiment, after the end of the non-erase process T11, the waiting time required for the end of the next non-erase process T12 is the time required for the pre-erase process Er2 (approximately 20 ms) and the time required for the erased booklet process Ee2a. (About 50 ms) and the time required for the non-erase processing T12 (about 5 ms), which is about 75 ms. Therefore, even when the response time of the entire IC card requires about twice the total time, the non-erasure process T12 is actually completed after the execution instruction of the non-erase process T12 is issued. The waiting time required until the time is shortened to about 0.15 s, which is less than 0.3 s, which is a waiting time for which the user feels stress.

  Further, after the end of the non-erase process T12, the waiting time required for the end of the next non-erase process T13 is the time required for the main erase process Ee2b (about 50 ms) and the time required for the non-erase process T13 (about 5 ms). ), Which is about 55 ms. Accordingly, the waiting time required from the instruction to execute the non-erasure process T13 to the actual completion of the non-erase process T13 is shortened to about 0.13 s, which is less than 0.3 s. The same applies to the waiting time required until the next non-erase process T14 ends after the non-erase process T13 ends.

  Further, after the end of the non-erase process T14, the waiting time required for the end of the next non-erase process T15 is the time required for the main erase process Ee2d (about 50 ms) and the time required for the post-erase process Eo2 (about 20 ms). , And the time required for the non-erase processing T15 (about 5 ms), which is about 75 ms. Accordingly, the waiting time required from the instruction to execute the non-erasure process T15 to the actual completion of the non-erase process T15 is shortened to about 0.15 s, which is less than 0.3 s.

  As described above, in this embodiment as well, as in the first embodiment, the waiting time until the execution of the non-erase process is completed can be greatly shortened compared to the conventional configuration, thereby reducing the waiting time stress on the user. can do.

  In this embodiment, the case where the erasure process is divided into four erasure processes has been described. However, the number of divisions is not limited to four. Generally, the erasure process is performed by N (N is a natural number of 2 or more). ) Is also performed in the same manner as in the above-described embodiment (especially, when the number of divisions is 2, the processing is the same as in the first embodiment). In this case, as the final address in step # 4 in FIG. 2, the number of processes in the erase process (especially the erase book process) being performed is divided into the same erase process (especially the erase book process) by N. For example, in the case of m (m is a natural number equal to or less than N) -th erase book processing, approximately m / N positions of all memory cells belonging to the target block to be erased as the final address It is sufficient to set an address corresponding to.

  Also, the smaller the number of memory cells to be verified in the same small process, the lower the probability that a memory cell that could not be erased correctly in each verify process will be the target of verification. When the number of memory cells to be verified in each erase subprocess is approximately the same, the number of memory cells to be verified in each erase subprocess is approximately the same. Depending on the division number N, the number of times of erasing voltage application processing in step # 1 of FIG. 2 may be changed. For example, when the number of memory cells to be verified is approximately the same, if the division number N is 5 or less, the number of times of application of the erase pulse voltage with a pulse width of 4 ms is 10 times, and if N is 6 or more, the pulse width is 4 ms. The number of times of application of the erase pulse voltage can be set to 5 times.

  By setting in this way, when the division number N is small, that is, when the number of memory cells to be verified in one erase small process is large, when the division number N is large, that is, in one erase small process Compared to the case where the number of memory cells is small, there is a high possibility that memory cells that are not correctly erased are included as verification targets. Therefore, the erase operation can be performed more reliably by applying many erase pulses in advance. On the contrary, when the number of divisions N is large, that is, when the number of memory cells to be verified in one erase small process is small, there is a low possibility that memory cells that are not correctly erased are included as verification targets. Therefore, the processing time can be shortened by reducing the number of erase pulses to be applied as compared with the case where the division number N is small. That. The numerical values of the pulse width and the number of pulse application are examples, and are not limited to these.

  In each of the above-described embodiments, the description has been made assuming that the erasure process is executed in order to secure free space when the non-erase process is executed, but an instruction to execute the non-erase process is issued during the erasure process. If not, it is not always necessary to execute the erasure process separately for each erasure process. In other words, the erasing process for all the memory cells belonging to the erasure target block may be executed without interruption.

  In each of the above-described embodiments, the case where the device of the present invention is mounted on an IC card has been described as an example. However, the use of the device of the present invention is not limited to the IC card, and other semiconductor integrated devices. It can also be used for devices, and by mounting the present invention device on a semiconductor integrated device, it reduces the waiting time required for completion of processing and reduces the waiting stress of users due to processing delay. Can play.

  Further, in each of the above-described embodiments, each erasure book process has been described as executing steps # 1 to # 5 shown in FIG. 2, but the process is resumed after the erasure book process is interrupted. In the erase book process, the erase voltage is applied to all memory cells belonging to the target block in the first erase book process in the same erase book process. It is also possible to start from the verify process (step # 2) without performing (step # 1). By performing the processing in this manner, the execution of the erase book process excluding the first erase book process is completed, and the waiting time for the non-erase process can be further reduced. Even in this case, if verification fails (No in step # 3), the process may return to step # 1 and apply the erase voltage.

Conceptual operation flow in the first embodiment of the apparatus of the present invention Conceptual operation flow of erase main processing in the first embodiment of the apparatus of the present invention The processing time for each processing is graphed in time series for the processing other than deletion (authentication processing, billing processing, etc.) and deletion processing in the first embodiment of the present invention device A conceptual illustration of the operation target block for each process in FIG. Conceptual operation flow in the second embodiment of the apparatus of the present invention Processing time for each process in the second embodiment of the present invention (authentication process, billing process, etc.) and erase process are graphed in time series FIG. 6 conceptually shows an operation target block for each process in FIG. A graph showing the time required for the erase operation for each block capacity Conceptually showing each processing flow of a nonvolatile semiconductor memory device including an erasing process performed for the purpose of securing free space before execution of non-erase processing A graph showing the processing time for each process in chronological order for non-erase processing (authentication processing, billing processing, etc.) and erasure processing for each block capacity

Explanation of symbols

T1, T2, T3, T4, T5, T11, T12, T13, T14, T15, T16: Out-erase processing E1, E2: Erase processing E1a, E1b, E2a, E2b, E2c, E2d: Erase sub-process Er1, Er2: Pre-erase processing Ee1a, Ee1b, Ee2a, Ee2b, Ee2c, Ee2d: Erase booklet processing Eo1, Eo2: Post-erase processing B1, B2, B3: Block B1a, B1b, B1c, B1d, B2a, B2b, B2c, B2d: Target small block T90, T91, T92, T93: Non-erase process E90: Conventional erase process Er90: Pre-erase process Ee90: Erase main process Eo90: Post-erase process

Claims (6)

A non-volatile semiconductor storage device in which erasure processing of information recorded in a plurality of memory cells belonging to a target block is performed by performing pre-erase processing, main erase processing, and post-erasing processing in this order,
The pre-erase process includes a write process performed for adjusting a threshold voltage for a plurality of memory cells belonging to the target block before the execution of the main erase process;
The main erase process includes an erase voltage application process and a verify process for all memory cells belonging to the target block,
The post-erase process includes a write process performed for adjusting a threshold voltage for a plurality of memory cells belonging to the target block after the execution of the erase main process,
The erasure process is
Non-volatile, characterized in that in order to start execution of non-erase processing for non-target blocks other than the target block, the verify processing can be automatically interrupted in units of a plurality of small blocks constituting the target block Semiconductor memory device.   The number of times of voltage application related to the erase voltage application processing that is continuously performed without going through the verification processing is changed in accordance with the number of the memory cells belonging to the small block. Nonvolatile semiconductor memory device   3. The nonvolatile semiconductor memory device according to claim 1, wherein each of the small blocks includes the same number of the memory cells. A processing method in the nonvolatile semiconductor memory device according to claim 1,
After executing the pre-erase process on the entire target block, sequentially executing the main erase process for each small block, and after executing the main erase process on the final small block, the entire target block The post-erase processing is executed for
Before the end of the main erase process for the last small block, after the main erase process for the one small block is completed, before the start of the main erase process for the other small block, A processing method characterized by executing non-erase processing on a target block. Before the end of the erase main process for the final small block,
After executing the erase voltage application process for the entire target block, when the verify process for one small block is completed, the erase main process is interrupted and the non-erase process is executed,
After the execution of the non-erasing process, after the execution of the erasing voltage application process for the entire target block, the verification process before the execution of the non-erasing process among the plurality of small blocks belonging to the target block 5. The processing method according to claim 4, wherein the verify process is executed on one small block that has not been subjected to the process.   The non-erasure process for the non-target block is executed one or more times after the post-erase process in one erase process is finished and before the pre-erase process in another erase process is started. The processing method according to claim 4 or 5.

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