JP2008146697A - Data processor and method for detecting residual data amount of buffer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a data processor free from incorrect detection of buffer underrun by detecting exact residual amount of buffer data, and to provide a detection method of residual data amount in the buffer. <P>SOLUTION: The data processor which generates and outputs data for recording in an optical disk based on the data transmitted from a computer device has a command storage section 20 which stores a plurality of control commands which process data stored in a buffer 10 by predetermined area, and detects residual data amounts which can be output based on the sum total value in a field of iteration number of control commands stored in the command storage section 20, the number of data in which a control command is not generated although transmitted from the computer device, and the remaining number of iteration of control command under processing among control commands stored in the command storage section 20. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a data processing device for detecting the remaining amount of data in a buffer and a method for detecting the remaining amount of data in a buffer.

  2. Description of the Related Art Conventionally, an optical disk recording apparatus that writes data transferred from a computer device that is a data generation source to an optical disk such as a CD (Compact Disc) or a DVD (Digital Versatile Disk) is known.

  In order to adjust the difference between the speed of data transferred from an external computer device (hereinafter referred to as “host”) and the speed of recording data on the optical disc, A storage buffer is provided for temporarily storing data transferred from the computer device.

  By the way, in the optical disk recording device, when the speed of data transferred from the computer device is slow, a phenomenon of buffer underrun in which the remaining amount of data stored in the storage buffer is insufficient may occur. .

  When such a phenomenon occurs, the optical disk recording device interrupts writing to the optical disk and waits, and when data of a predetermined amount or more is stored in the storage buffer, the interruption is canceled and writing is performed again. Although the proof function operates (see, for example, Patent Document 1), the performance of the data recording apparatus has been degraded by the operation of the proof function.

  Here, a conventional optical disk recording apparatus will be specifically described with reference to the drawings.

  The data to be recorded on the optical disc includes the first data transferred from the host and the second data generated by the function of the data processing device constituted by LSI (Large Scale Integration) in the optical disc recording device without being transferred from the host. There are two types. In order to manage these data efficiently, the conventional data processing apparatus divides an internal SDRAM (Synchronous DRAM) into predetermined area units, and each area has a data processing command, a pointer control command used after the data processing, and a fixed amount. It takes a form that contains quantity data (see FIG. 7). Here, the “fixed amount” is 2352 bytes of data and subcode data for CD, and 2064 bytes of data from ID to EDC for DVD.

  In the data processing apparatus, a continuous area for storing data transferred from the host is a main ring buffer (hereinafter referred to as “WMRB”) as a first buffer, and a continuous area for storing other data. A buffer configuration is adopted in which the area is a sub-ring buffer (hereinafter referred to as “WSRB”), which is a second buffer, and a linear buffer (hereinafter referred to as “WLB”). In the WSRB and WLB, necessary data is prepared by firmware (hereinafter referred to as “F / W”) in the data processing apparatus before writing to the optical disk. Here, a ring buffer structure is used for WMRB and WSRB, and a linear buffer structure is used for WLB.

  Assuming that the pointer indicating the position for writing data transferred from the host is PHST, and the pointer indicating the data writing position for actually performing data processing according to the command is PFMT, PFMT2, the relationship between these pointers and the buffer configuration is shown in FIG. It becomes like this. Note that PFMT indicates a position where data processing is always performed on the WMRB, and PFMT2 indicates a position where data processing is performed on the WSRB and WLB.

  When data on the WMRB is being processed, the data processing position is determined by the PFMT, so the PFMT2 is invalid. When data on WSRB and WLB is being processed, PFMT indicates a position where data processing on WMRB is performed next, and PFMT2 indicates a position where data processing is actually performed.

  In a conventional data processing apparatus, the number of areas (hereinafter referred to as “data remaining amount”) for which data preparation has been completed but processing has not yet been performed in such a buffer configuration is calculated, and the data remaining amount is calculated. Is less than the specified value and a buffer underrun occurs, the data processor hardware (hereinafter referred to as “H / W”) performs interrupt assertion and necessary processing, and the F / W also interrupts. In response to this, buffer underrun countermeasures such as various underrun countermeasure processing were taken.

Here, in the example shown in FIG. 9, PHST points to area 6 and PFMT points to area 1. When PHST does not move in this state, PFMT processes area 1 to area 3 and then changes to WLB. After jumping and performing processing from area 8 to area 12, returning to WMRB again, processing of area 4 and area 5 is performed. Therefore, the original remaining data at this time is obtained by adding the number of WLB areas to the difference value between the pointers PHST and PFMT (hereinafter, PHST-PFMT) in consideration of the ring buffer structure.
JP 2003-77131 A

  However, in the above conventional data processing device, pointer control commands are stored in each area. Therefore, in order to determine when the PFMT jumps in H / W, pointer control commands for all areas between PHST and PFMT are used. I had to read it in advance. Such control command prefetch processing deteriorates performance and impairs real-time processing, and is fatal in the case where real-time control is necessary, such as buffer underrun. Therefore, the conventional data processing apparatus uses only the remaining data of WMRB, which is the first buffer, that is, uses only the value of PHST-PFMT without considering the remaining data of WSRB, WLB, which is the second buffer. Was determining a buffer underrun.

  When this determination method is used, for example, in the example shown in FIG. 9 above, the original data remaining amount is 10, whereas PHST-PFMT is 5, so that the data remaining amount is 5 and the buffer underrun. Judgment is made. Therefore, for example, if the buffer underrun determination threshold is set to 7, a buffer underrun is detected even though it is not originally a buffer underrun.

  When such a buffer underrun erroneous detection occurs, a buffer underrun handling process that does not require H / W and F / W is performed, and the performance deteriorates.

  In order to avoid such a problem, if it is attempted to calculate the remaining amount of data in consideration of the second buffer such as WSRB and WLB, it is necessary to read pointer control commands for all areas from PHST to PFMT. Since this operation cannot be performed in real time, it cannot be realized in a system that requires real-time performance. Further, even in a system that does not require real-time characteristics, data transmission / reception with the SDRAM is increased.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a data processing apparatus and a data remaining amount detection method that are free from erroneous detection of buffer underrun by detecting an accurate remaining amount of data in a buffer.

  In order to achieve the above object, an invention according to claim 1 is a data processing device for generating and outputting data to be recorded on a recording medium based on data transferred from a computer device. A first buffer for sequentially storing data to be transferred in units of predetermined areas; a second buffer for sequentially storing data generated in accordance with the recording processing content to the recording medium in units of predetermined areas; A command storage unit for storing a plurality of control commands having a repetition number field indicating the number of areas of data to be repeatedly processed, which is used for processing data stored in a predetermined area unit, and stored in the command storage unit A data control unit that performs predetermined processing on the data of each buffer based on the control command and outputs the data, The total number of control command repetition number fields stored in the command storage unit, the number of data transferred from the computer device but for which no control command has been generated, and stored in the command storage unit The remaining amount of data in the first buffer and the second buffer is detected based on the remaining number of repetitions of the control command being processed among the control commands being processed.

  According to a second aspect of the present invention, in the first aspect of the present invention, the number of areas of data processed by the control command is determined from the value of the repeat number field of the control command extracted from the command storage unit and transferred. An execution counter register for storing a subtracted value is provided. Based on the execution counter register, the remaining number of repetitions of the control command being processed among the control commands stored in the command storage unit is detected. To do.

  The invention according to claim 3 is transferred from the computer apparatus when writing data transferred from the computer apparatus in a predetermined packet size in the invention according to claim 1 or claim 2. A transfer data counter register for storing a fractional value for the packet size among the received data, and detecting the number of data transferred from the computer device but for which no control command is generated based on the transfer data counter register It is characterized by that.

  According to a fourth aspect of the present invention, there is provided data for detecting a remaining amount of data that can be output in a data processing device that generates and outputs data to be recorded on a recording medium based on data transferred from a computer device. In the remaining amount detection method, the step of sequentially storing the data transferred from the computer device in a predetermined area unit in the first buffer, and the data generated in accordance with the recording processing contents on the recording medium are sequentially performed in the predetermined area unit. A step of storing in the second buffer; and a control command having a repetition number field indicating the number of areas of data to be repeatedly processed, which is used for processing data stored in each buffer in a predetermined area unit. Generating sequentially according to data transferred from the computer device and storing it in the command storage unit; A step of performing a predetermined process on the data of each buffer based on a control command stored in the command storage unit and outputting the data; a sum of values in a repetition number field of the control command stored in the command storage unit; Based on the number of data transferred from the computer device but for which no control command is generated, and the remaining number of repetitions of the control command being processed among the control commands stored in the command storage unit, And detecting the remaining amount of data in the first buffer and the second buffer.

  According to the present invention, the sum of the values in the number of repetitions field of the control command stored in the command storage unit, the number of data transferred from the computer device but for which no control command is generated, and the command storage unit Since the remaining amount of data in the first buffer and the second buffer is detected based on the remaining number of repetitions of the control command being processed among the stored control commands, an accurate remaining data amount in the buffer is obtained. It can be detected, and erroneous detection of buffer underrun can be avoided.

  The data processing apparatus in the present embodiment is provided between a host that is an external computer apparatus and an optical disk recording unit that performs recording on an optical disk (e.g., an example of a recording medium) such as a CD or a DVD. Is a device that generates data to be recorded on an optical disk based on data transferred from the optical disk and outputs the data to an optical disk recording unit, and is used for an optical disk device that stores data on an optical disk. The data processing apparatus is configured by an LSI (semiconductor integrated circuit) or the like.

  The data processing apparatus stores a first buffer for sequentially storing data transferred from the host in units of predetermined areas, and a second buffer for sequentially storing data generated in accordance with the contents of recording processing on the optical disk in units of predetermined areas. And a command storage unit for storing a plurality of control commands having a repetition number field indicating the number of areas of data to be repeatedly processed, used for processing data stored in units of predetermined areas in each buffer, A data control unit that performs predetermined processing on the data in each buffer based on a control command stored in the command storage unit and outputs the data.

  Further, the data processing device includes the sum of the values in the control command repetition count field stored in the command storage unit, the number of data transferred from the host but for which no control command has been generated, and the command storage unit. The remaining amount of data in the first buffer and the second buffer is detected based on the remaining number of repetitions of the control command being processed among the stored control commands.

  Since it is configured in this way, it is possible to detect the correct remaining amount of data in the first buffer and the second buffer, and therefore it is possible to avoid erroneous detection of buffer underrun.

  In addition, as described above, since the control command stored in each buffer is stored in the command storage unit in the prior art, the number of areas of data to be processed with the generated control command can be easily detected. be able to.

  Furthermore, an execution counter register for storing a value obtained by subtracting the number of areas of data processed by the control command from the value of the control command repetition number field taken out from the command storage unit and transferred, based on the execution counter register, Since the remaining number of repetitions of the control command being processed among the control commands stored in the command storage unit is detected, the remaining number of repetitions can be detected in real time by H / W.

  In addition, when data transferred from the host is written with a predetermined packet size, a transfer data counter register is provided for storing a fractional value for the packet size of the data transferred from the host. Based on the transfer data counter register Since the number of data transferred from the host but for which no control command is generated is detected, the number of data for which no control command is generated in real time can be detected by H / W.

  Hereinafter, the data processing apparatus according to the present embodiment will be specifically described with reference to the drawings. FIG. 1 is a block diagram of a data processing apparatus 1 in the present embodiment.

  The data processing apparatus 1 according to the present embodiment temporarily stores data transferred from the host (hereinafter referred to as “received data”) and data generated according to the contents recorded on the optical disc (hereinafter referred to as “generated data”). After the data is stored in the buffer, the data is taken out from the buffer according to the contents recorded on the optical disk and transmitted to the encoder of the optical disk recording unit.

  As shown in FIG. 1, the data processing device 1 includes a data storage unit 10 that temporarily stores received data and generated data in units of predetermined areas, and each buffer of the data storage unit 10 stores the data in units of predetermined areas. A command storage unit 20 that temporarily stores control commands used to process data, a data access unit 30 that transmits / receives data to / from the data storage unit 10, and transmission / reception of control commands to / from the command storage unit 20 A command access unit 40, a data control unit 50 that performs control related to received data and generated data, a command control unit 60 that performs control related to a control command, and a CPU 70 that controls the entire data processing apparatus 1 are included. Further, the data control unit 50 determines that the buffer underrun occurs when the remaining amount of data that can be output to the encoder is equal to or less than a predetermined value, and operates the burn-proof function.

  The data storage unit 10 is composed of an SDRAM in which a storage area is divided into predetermined area units, and a WMRB (main buffer) that is a first buffer for sequentially storing received data, which is data transferred from a host, in area units. And a second buffer WSRB (sub-ring buffer) and WLB (linear buffer) for sequentially storing data generated by a CPU 70, which will be described later, in predetermined area units in accordance with the recording processing contents on the optical disk. Have. As described in the section of the prior art, these buffers write and read data based on pointers such as PHST, PFMT, and PFMT2 (see FIGS. 8 and 9).

  Note that data generated in accordance with the content of recording processing on the optical disc includes link data and pause data. Further, the number of second buffers is not limited to two and may be one. An SDRAM is used as the data storage unit 10, but is not limited thereto. Each area can store a certain amount of data.

  The command storage unit 20 is a device that temporarily stores control commands, and can use storage elements such as flip-flops, SRAMs, and SDRAMs according to system requirements, costs, and processing complexity.

  Further, as shown in FIG. 2, the control command includes a repetition number field, a pointer control field, and a data processing field.

  In the repeat number field, the number of times the process for data on the same buffer is repeated by the control command is set. By providing this field, the CPU 70 does not need to write the control command having the same data processing content to the command storage unit 20 a plurality of times, and the memory area of the command storage unit 20 can be reduced along with the load reduction of the CPU 70. . When the number of executions specified in the repetition number field is completed, the next control command is fetched and executed. When 0 is specified in the repeat number field of the control command, it means that the writing is finished.

  By adding this repeated field, it becomes possible to process a plurality of areas with one control command for an area having a common control command. As described above, the same control command stored in each area in the prior art can be shared, and the SDRAM area can be reduced.

  An example of the command storage unit 20 is shown in FIG. The command storage unit 20 includes two types of a ring command buffer (hereinafter referred to as “WRCB”) and a linear command buffer (hereinafter referred to as “WLCB”). WRCB has a ring buffer structure and WLCB has a linear buffer structure. The WRCB stores a control command for processing received data that is data transferred from the host (hereinafter referred to as “received data processing command”), and the WLCB stores generated data that is generated inside the data processing apparatus 1. Used to store control commands to be processed (hereinafter referred to as “generated data processing commands”). In addition, a pointer indicating a writing position for storing a control command is defined as PCMD, and a pointer indicating a reading position for acquiring a control command is defined as GCMD. GCMD can move between WRCB and WLCB.

  The pointer control field stores a pointer control command for controlling the PFMT, which is a read pointer indicating the position of data to be read next in each buffer. That is, in the pointer control field, how the PFMT is controlled after the area pointed to by the PFMT is processed according to the data processing command is set. Then, in accordance with the setting contents, control such as incrementing the PFMT and moving the PFMT to the designated area is performed.

  If the number of repetitions is set to 2 or more in the repetition field, the PFMT is incremented until the last repetition, and a pointer control command is issued so that the PFMT is moved to the designated area at the last repetition. Can be set.

  Furthermore, when processing the second buffer (WSRB, WLB) with a control command, the pointer control field can be set so as not to move the PFMT in order to repeatedly process one area of the buffer.

  Regarding WMRB, there is a PHST which is a write pointer indicating the head position of an unused position, and this PHST is managed by the buffer control unit 52 together with the PFMT. Here, for example, when PHST and PFMT indicate the storage positions shown in FIG. 8, data is stored in areas 1 and 2 of WMRB. The difference between PHST and PFMT is the number of areas of data stored in WMRB. In the case of FIG.

  In the data processing field, information indicating how to process each data in a predetermined area stored in the data storage unit 10 is set.

  This processing content relates to data generation according to the format of the optical disc. For example, in the case of a CD, SYNC (synchronization signal) is generated at the time of recording, and HEADER is generated.

  An example of a method for calculating the remaining buffer capacity using the command form shown in FIG. 2 will be described. As described above, when data is recorded on the optical disk, the SDRAM is divided into predetermined area units, and buffer areas such as WMRB, WSRB, and WLB are secured therein. The data on the WMRB is sent from the external host at an arbitrary timing, and the data on the WSRB and WLB is prepared by the CPU 70 in advance. Since there is a restriction that data other than WMRB must be prepared in advance by the CPU 70, the control command other than WMRB is set to the number of repetitions when the WMRB processing is completed and the control command other than WMRB can be processed. It will be possible to execute as many times as possible.

Here, the correct remaining data amount is calculated using a control command for writing a CD packet. CD packet write is a recording method in which data sent from a host is divided into packets, and link data is generated and added for each packet. When the packet size is 16 areas, the link data is 7 areas, and the number of data transferred from the host is 48 areas, the control commands stored in the command storage unit 20 are as shown in FIG. Processing is performed.
1) After processing 5 areas of WLB1 (Link-Runin), return to WMRB.
2) After processing WMRB for 16 areas, jump to WLB.
3) After processing 7 areas with WLB, return to WMRB.
4) After 16 areas of WMRB are processed, jump to WLB.
5) After processing 7 areas of WLB, return to WMRB.
6) After 16 areas of WMRB are processed, jump to WLB2.
7) Process 3 areas of WLB2 (Runout-Link).
8) End the process.

At this time, PHST increases in accordance with the data transfer from the host, but the PFMT does not change because the formatting process is not activated. In such a case, the remaining amount of data in consideration of WLB can be calculated using the value of the remaining amount of data “PHST-PFMT” on WMRB as follows.
a) When [PHST-PFMT] <16 Since the processing of 5 areas to the WLB in 1) above is confirmed,
Remaining data = [PHST−PFMT] +5
b) When 16 ≦ [PHST−PFMT] <32 Since the jump to WLB and the processing of 7 areas in 2) above are confirmed,
Remaining data = [PHST−PFMT] +12
c) When 32 ≦ [PHST−PFMT] <48 In addition to 2) above, the jump to WLB in 4) above is also determined.
Remaining data = [PHST-PFMT] +19
d) When 48 ≦ [PHST-PFMT] Since it is determined that all the processes from 1) to 7) can be performed,
Remaining data = 70
By using this calculation method, it is possible to calculate the correct remaining data amount including the data of the second buffer other than the WMRB that is the first buffer by examining the value of PHST-PFMT. However, this calculation method is valid only in a case where the PFMT does not change, and the above calculation method cannot be used in a situation where data processing is started and the PFMT is changing.

  For example, in the case of PHST-PFMT = 18, the remaining data amount is 32 when the transfer data spans two link data, but 25 when only one link data spans. That is, the remaining amount of data changes depending on the status of data transfer from the host and the status of data processing.

  Although it is possible for the CPU 70 to perform processing for detecting the status of data transfer from the host and the status of data processing in real time, if the data recording speed to the optical disk becomes high, the processing is not in time and the data is not encoded. There is a possibility that a situation that cannot be sent to At that time, unnecessary recording interruption occurs, leading to performance degradation as a data processing apparatus.

  Therefore, the data processing apparatus 1 according to the present embodiment has a configuration in which the remaining buffer capacity is calculated using the command form shown in FIG. 2 even when data processing is started and the PFMT is changing. It can be performed using W.

  In the case of data recording without using the first buffer WMRB, since the CPU 70 knows the contents of each data and the recording size, all data and control commands are stored in the designated area before recording on the optical disk. It is possible to keep. Therefore, even when high-speed recording is targeted, it is possible to record without any problem. However, in the case of data recording using the WMRB as the first buffer, the amount of data transferred from the host is not known before recording on the optical disc, so the number of transfers is counted after the data is transferred from the host, It is necessary to store control commands in the command storage unit 20. That is, the control command must be stored in real time.

  In the case of the above-described CD packet write, it is necessary to count the number of data transferred from the host and store the packet control command in the command storage unit 20 when the packet size is counted for 16 areas. The link control command must be stored at the time when data for one area is transferred from the host (when link data is determined) after the packet control command is stored.

  The process of storing control commands in real time can be performed by the CPU, but when the data recording speed to the optical disc becomes high, the situation may occur that the processing cannot be done in time and the data cannot be sent to the subsequent encoder. There is sex. At that time, unnecessary recording interruption occurs, leading to performance degradation as a data processing apparatus.

  In view of this, in the data processing apparatus 1 according to the present embodiment, a configuration in which a control command necessary for data transfer from the host is automatically stored in H / W is performed in H / W.

  The data access unit 30 accesses the data storage unit 10 according to an instruction from the data control unit 50 and writes or reads each data in the data storage unit 10. When accessing from the CPU 70, it goes through the data control unit 50. The data access unit 30 receives the buffer area number from the data control unit 50 and writes to the buffer (hereinafter referred to as “write access”) or reads from the buffer (hereinafter referred to as “read access”). The data storage unit 10 is accessed according to the received signal. In addition, when providing a field for data in each area in the data storage unit 10, a field identification signal is received from the data control unit 50, and the data storage unit 10 is accessed according to the received identification signal.

  The command access unit 40 is used when accessing a control command stored in the command storage unit 20 from the command control unit 60. Access from the CPU 70 is performed via the command control unit 60. The command access unit 40 receives a command number, a read access / write access determination signal, and the like from the command control unit 60 and transmits / receives a control command according to the received signal.

  The data control unit 50 includes a format processing unit 51 and a buffer control unit 52 therein. The format processing unit 51 is a device that performs format processing in accordance with a control command. That is, the format processing unit 51 acquires data of the corresponding area via the data access unit 30 and performs format processing according to the control command acquired from the command control unit 60. The buffer control unit 52 is a device that manages pointers in the data storage unit 10.

  The command control unit 60 has a buffer control unit 61. The buffer control unit 61 manages each pointer in the command storage unit 20, manages the remaining buffer data, and the like. FIG. 5 shows an internal register included in the command control unit 60. Note that these internal registers are initialized by the CPU 70 at the initialization stage in the data processing apparatus 1.

  As shown in FIG. 5, the command control unit 60 includes an execution command transfer unit 62 and a control command transfer unit 63.

  The execution command transfer unit 62 has a function of storing a control command in accordance with data sent from the host, and includes a control command register 81, an execution counter register 82, and the like as internal registers.

  The control command register 81 is a register that stores a control command acquired from the command storage unit 20. The control command stored in the control command register 81 is transferred to the data control unit 50 by the execution command transfer unit 62.

  The execution counter register 82 is a register that stores a value indicating how many times (for how many areas) the control command transferred to the data control unit 50 needs to be executed. The execution counter register 82 stores the value of the repeat field of the control command at the timing when the control command is acquired, and the value stored each time the format processing is performed in the format processing unit 51 of the data control unit 50 is the execution command transfer unit. One is subtracted by 62. That is, the execution counter register 82 stores a value obtained by subtracting the number of areas of data processed by this control command from the value of the control command repetition number field fetched from the command storage unit 20 and transferred. At the timing when the value of the execution counter register 82 becomes 0, the execution command transfer unit 62 acquires a new control command from the command storage unit 20 and transfers it to the data control unit 50.

  The control command transfer unit 63 has a function of notifying the data control unit 50, and as internal registers, a packet data control command register 91, a link data control command register 92, a padding data control command register 93, and a transfer It has an end control command register 94, a padding destination area register 95, a transfer end destination area register 96, a packet size (storage threshold) register 97, a transfer data counter register 98, and the like.

  The packet data control command register 91 is a register for storing a control command for processing data transferred from the host. The packet data control command register 91 stores a control command for processing data transferred from the host by the CPU 70 during initialization. The value of the repetition number field in this control command is the packet size and must match the packet size (storage threshold) register value. In the case of a DVD, it is necessary to specify 16, which is the ECC size.

  The link data control command register 92 is a register for storing a control command for processing link data. The link data control command register 92 stores a control command for processing link data by the CPU 70 at the time of initialization. The value of the repetition number field in this control command must be 7 according to the CD standard. In the case of DVD, since there is no link data, this register is not used.

  The padding data control command register 93 is a register for storing a control command for processing padding data. The padding data control command register 93 stores a control command for processing padding data by the CPU 70 at initialization. Since the value of the repetition number field in this control command varies depending on the number of data transferred from the host, it is calculated at the end of data transfer (when Sync Cache is issued).

  The transfer end control command register 94 is a register for storing a control command for processing transfer end data (CD: Runout-Link). The transfer end control command register 94 stores a control command for processing transfer end data by the CPU 70 at initialization. The value of the repetition number field in this control command must be 3 according to the CD standard. In the case of a DVD, there is no data at the end, so this register is not used.

  The padding destination area register 95 is a register for storing the head area number of an area secured as a padding destination area in the data storage unit 10. The padding destination area register 95 is a register that is used when padding processing is required and the value of the pointer control field of the control command is changed.

  The transfer end area register 96 is a register for storing the head area number of an area secured as a transfer end area (CD: Runout-Link) in the data storage unit 10. This padding destination area register 95 is used when processing the transfer end area and changing the value of the pointer control field of the control command. In the case of a DVD, there is no data at the end, so this register is not used.

  The packet size (storage threshold) register 97 is a register that stores a threshold for determining whether or not to store a packet data control command. The threshold value is stored in the register 97 by the CPU 70 at the time of initialization. The packet size is notified by a command from the host before writing. In the case of a DVD, it is necessary to specify 16, which is the ECC size.

  The transfer data counter register 98 is a register that stores a fractional value with respect to the packet size among the data transferred from the host. When the packet size is 16, the value of the transfer data counter register 98 is always 16 or less. The value of the transfer data counter register 98 must be cleared to 0 by the CPU at the time of initialization.

  The CPU 70 performs initial processing of each device according to F / W, activation, processing in response to an interrupt such as buffer underrun, access to data through the data access unit 30, access to a control command through the command access unit 40, and the like. Perform various processes.

  The operation of the data processing apparatus 1 configured as described above will be specifically described with reference to the flowchart of FIG. Note that when 1 is added to PCMD when PCMD indicates the final control command on WRCB, PCMD indicates the head control command of WRCB (loops on WRCB).

  First, the CPU 70 performs initial setting of each unit such as the data storage unit 10, the command storage unit 20, the data control unit 50, and the command control unit 60 (step S1). The initialization processing of the internal register of the command control unit 60 and data (padding data, Runout-Link data, etc.) that need to be prepared on the data storage unit 10 are also processed at this timing.

  Thereafter, when receiving the transfer data from the host, the data control unit 50 notifies the command control unit 60 of a notification (transfer notification) that the transfer data has been received. Further, when the data transfer from the host is completed and the Sync Cache command is received from the host, the command control unit 60 is notified (Sync Cache notification).

  The command control unit 60 determines whether a transfer notification or a sync cache notification is received from the data control unit 50 (step S2).

  In this process, if the command control unit 60 determines that a transfer notification has been received from the data control unit 50 (step S2: transfer notification present), the command control unit 60 increments the value of the transfer data counter register 98 by 1 (step S3), The process proceeds to step S4.

  In step S 4, the command control unit 60 determines whether the value of the transfer data counter register 98 matches the value of the packet size (storage threshold) register 97.

  In this process, if it is determined that the value of the transfer data counter register 98 does not match the value of the packet size (storage threshold) register 97 (step S4: No), the command control unit 60 performs the processes from step S2 to S4. Are repeated until the value of the transfer data counter register 98 matches the value of the packet size (storage threshold) register 97.

  On the other hand, if it is determined that the value of the transfer data counter register 98 matches the value of the packet size (storage threshold) register 97 (step S4: Yes), the command control unit 60 stores the command storage unit 20 indicated by the PCMD. A control command for packet data is stored at the storage position (step S5), the value of PCMD is incremented by 1 (step S6), and the process proceeds to step S7.

  In step S7, the command control unit 60 resets the value of the transfer data counter register 98 to zero.

  Thereafter, when the data received from the host receives the transfer data from the host, the data control unit 50 notifies the command control unit 60 of a transfer notification. At this stage, the link data for seven areas is determined. In addition, when a Sync Cache command is received from the host, the command control unit 60 is notified to that effect (Sync Cache notification).

  Similarly to step S3, the command control unit 60 determines whether a transfer notification or a sync cache notification is received from the data control unit 50 (step S8).

  In this process, if it is determined that the transfer notification or the sync cache notification is not received from the data control unit 50 (step S8: No), the command control unit 60 proceeds to step S8 until the transfer notification or the sync cache notification is received. Repeat the determination.

  On the other hand, when determining that the transfer notification or the sync cache notification is received (step S8: transfer notification present), the command control unit 60 increments the value of the transfer data counter register 98 by 1 (step S9), and the command indicated by the PCMD A control command for link data is stored in the storage position of the storage unit 20 (step S10), the value of PCMD is incremented by 1 (step S11), and the process returns to step S2.

  The command control unit 60 repeats the processes in steps S2 to S11 while the data control unit 50 receives the transfer data from the host.

  If it is determined in step S2 or step S8 that the Sync Cache notification has been received from the data control unit 50 (steps S2 and S8: with Sync Cache), the command control unit 60 determines whether to perform padding processing.

  The padding process is necessary when the number of data transferred from the host is not a multiple of the packet size, that is, when there is a fraction. That is, the data transferred from the host must be terminated in units of packets and is defined by the CD / DVD standard. The fraction of the transfer data is stored in the transfer data counter register 98. At this time, the number of padding needs to be calculated, but can be calculated by the following processing.

  That is, the packet size (storage threshold) value notified by the command from the host is stored in the packet size (storage threshold) register 97, and the value of the transfer data counter register 98 is subtracted from this value to obtain the padding size ( PADSIZE) is calculated (step S12). For example, if the CD packet size is 16 and the transfer data counter is 9, the padding size is 7.

  Thereafter, the command control unit 60 determines whether or not the final packet size is 16 (step S13). Whether or not the packet size is 16 is determined by whether or not the padding size calculated in step S12 is 0. In this process, when it is determined that the packet size is not 16 (step S13: Yes), the command control unit 60 determines that the padding process is necessary, and uses the padding size value calculated in step S12 for padding data. The value of the repetition number field of the control command register 93 is set, and the following padding processing in steps S14 to S17 is started.

  In step S14, the command control unit 60 retrieves the packet data control command from the packet data control command register 91, and stores the packet data control command in the storage location of the command storage unit 20 indicated by the PCMD (step S14). S14) The value of PCMD is incremented by 1 (step S15), and the process proceeds to step S16.

  In step S16, the command control unit 60 extracts the padding data control command from the padding data control command register 93 as the padding size value calculated in step S12 as the number of padding data control command repetitions. The control command for padding data is stored in the storage position of the command storage unit 20 indicated by PCMD (step S16), the value of PCMD is incremented by 1 (step S17), and the process proceeds to step S18.

  As described above, when the transfer data is a fraction, as a control command to be stored in the command storage unit 20, a control command for packet data that processes data for the fraction transferred from the host, and for padding data that processes padding data By storing the control commands in the order of the control commands, padding processing is realized.

  When the process of step S17 is completed, or when it is determined in step S13 that the packet size is 16 (step S13: No), the command control unit 60 transfers the transfer end data from the transfer end control command register 94. A control command for processing is taken out and stored in the storage position of the command storage unit 20 indicated by PCMD (step S18). The transfer end data is Runout-Link data, and the size is 3 and is defined by the standard. By ending this process, a series of writing processes is completed.

  Next, a series of sequences for performing format processing on the data stored in the data storage unit 10 will be described. This process is a process performed in parallel with the above-described process of storing data transferred from the host in the data storage unit 10.

  (1) First, the command control unit 60 acquires a control command at a position indicated by GCMD in the command storage unit 20 and stores it in the control command register 81. The value of the repetition number stored in the repetition number field of the control command acquired at the same time is copied and stored in the execution counter register 82. Thereafter, the value of GCMD is incremented by 1.

  (2) Next, the command control unit 60 transfers the control command acquired from the command storage unit 20 to the data control unit 50. When the data control unit 50 receives a control command from the command control unit 60, the data control unit 50 acquires data at a position indicated by the PFMT in area units.

  (3) The data control unit 50 performs format processing on the acquired data according to the control command received from the command control unit 60. When the formatting process is completed for one area, the data control unit 50 transfers the formatted data to the encoder block. At the same time, the command control unit 60 is notified that the data processing has been completed.

  (4) When the command control unit 60 receives a notification that the data processing is completed from the data control unit 50, the command control unit 60 decrements the value of the execution counter register 82 by one. Thereafter, when the command control unit 60 determines that the value of the execution counter register 82 has become 0, the process proceeds to (1) above. On the other hand, if it is determined that the value of the execution counter register 82 is not 0, the process proceeds to (3) above. Format processing is performed according to the above procedure.

  In the data processing apparatus 1 configured as described above, the command control unit 60 detects the remaining amount of data in the WMRB that is the first buffer and the WSRB and WLB that are the second buffers as follows.

  That is, the command control unit 60 includes the sum of the values in the control command repetition count field stored in the command storage unit 20, the value of the transfer data counter register 98 of the command control unit 60, and the execution counter of the command control unit 60. Based on the value of the register 82, the number of areas of unprocessed data by the control command stored in the command storage unit 20 and the data that has been transferred from the host but not stored in the control command. Detecting the number of areas and the remaining number of repetitions of the control command being processed among the control commands stored in the command storage unit 20, and adding them together, calculates the exact value of the remaining buffer data To do.

  In this way, the command control unit 60 performs the sum of the values in the control command repetition count field stored in the command storage unit 20, the value of the transfer data counter register 98 of the command control unit 60, and the execution of the command control unit 60. By adding the value of the counter register 82, the result of adding the number of areas of unprocessed data transferred from the host and stored in the buffer and the number of link data (number of areas) for which processing has been established The same result can be derived, whereby an accurate value of the remaining buffer data can be calculated.

  In the present embodiment, an example of CD packet writing has been described, but it is also possible to deal with DVD recording. The packet size needs to be 16 when recording a DVD. This is because ECC = 16 in the concept of ECC. Further, in CD packet writing, link data is required between packets. In DVD, however, link data is not required at the ECC boundary. Therefore, in the flowchart shown in FIG. . Therefore, an internal register for selecting CD / DVD or the like is prepared in the command control unit 60, and the function related to link processing is switched ON / OFF depending on the type of the optical disk.

  As described above, according to the data processing apparatus of the present embodiment, the correct remaining data amount in consideration of the second buffers WSRB and WLB can be calculated with little or no adverse effect such as performance degradation. it can. Therefore, buffer underrun detection can be performed using the correct remaining data amount, and erroneous detection of buffer underrun, which was a problem of the prior art, can be avoided. By avoiding erroneous detection of buffer underrun, unnecessary buffer underrun handling processing can be omitted, and performance deterioration due to unnecessary processing can be prevented.

  In the past, the same control command had to be written on the SDRAM a plurality of times. However, in the data processing apparatus according to the present embodiment, even when the control command is written in the SDRAM, the same command only needs to be written once. Can be reduced.

  Also, in the past, when changing a control command, it is necessary to rewrite the control command for all target areas. When rewriting a control command for multiple areas, it is necessary to access multiple areas. In some cases, access to the SDRAM may degrade the recording performance. In the data processing apparatus according to the present embodiment, since it is no longer necessary to write the same control command multiple times, the amount of access to the SDRAM is reduced even if the control command is placed in the SDRAM. Further, when the control command is stored in the SRAM, flip-flop, etc., it is not necessary to access the SDRAM by rewriting the control command. By reducing the access to the SDRAM, the processing performance is improved when the control command is corrected and recording is resumed.

  Conventionally, when processing data in each area, processing is performed by repeating control command reception, data reception, data processing, and pointer processing. However, in the data processing apparatus according to the present embodiment, the control command is Once a control command is received for a common area, each area can be processed by repeating data reception, data processing, and pointer processing, reducing the number of control command reception processing and reducing recording processing performance. improves.

  In the data processing apparatus according to the present embodiment, the transfer data from the host is counted in real time, and the control command is automatically stored by H / W, so that recording can be performed without any problem even during high-speed recording. In addition, by using H / W at a place where CPU resources are required, it is possible to cope with high speed even with low CPU resources.

It is a block diagram of a data processor concerning one embodiment of the present invention. It is a figure which shows the structure of the control command of the data processor in FIG. It is a figure which shows the structure of the command memory | storage part of the data processor in FIG. It is a figure which shows the example of the control command stored in the command memory | storage part of FIG. It is a figure for demonstrating the internal register of the command memory | storage part of FIG. 3 is a flowchart for explaining the operation of the data processing apparatus 1 of FIG. 1. It is a figure which shows the conventional data format. It is a figure for demonstrating the relationship between a pointer and a buffer structure. It is a figure for demonstrating the relationship between a pointer and a buffer structure.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Data processing apparatus 10 Data storage part 20 Command storage part 30 Data access part 40 Command access part 50 Data control part 51 Format processing part 52 Buffer control part of a data control part 60 Command control part 61 Buffer control part of a command control part 70 CPU
81 control command register 82 execution counter register 91 packet data control command register 92 link data control command register 93 padding data control command register 94 transfer end control command register 95 padding destination area register 96 transfer end destination area register 97 packet size (Storage threshold) register 98 Transfer data counter register

Claims (4)

In a data processing device that generates and outputs data for recording on a recording medium based on data transferred from a computer device,
A first buffer for sequentially storing data transferred from the computer device in units of predetermined areas;
A second buffer for sequentially storing data generated according to the content of recording processing on the recording medium in units of predetermined areas;
A command storage unit for storing a plurality of control commands having a repetition number field indicating the number of areas of data to be repeatedly processed, which is used for processing data stored in each buffer in a predetermined area unit;
A data control unit that performs a predetermined process on the data of each buffer based on a control command stored in the command storage unit, and outputs the data.
The total number of control command repetition count fields stored in the command storage unit, the number of data transferred from the computer device but for which no control command has been generated, and stored in the command storage unit A data processing device, comprising: detecting a remaining data amount of the first buffer and the second buffer based on a remaining number of repetitions of a control command being processed among the control commands being processed. An execution counter register for storing a value obtained by subtracting the number of areas of data processed by the control command from the value of the repetition number field of the control command taken out from the command storage unit and transferred;
The data processing apparatus according to claim 1, wherein a remaining number of repetitions of a control command being processed among the control commands stored in the command storage unit is detected based on the execution counter register. A transfer data counter register for storing a fractional value for the packet size among the data transferred from the computer device when writing the data transferred from the computer device with a predetermined packet size;
The data processing apparatus according to claim 1, wherein the number of data transferred from the computer apparatus but not generated with a control command is detected based on the transfer data counter register. In a data remaining amount detection method for detecting a remaining amount of data that can be output in a data processing device that generates and outputs data for recording on a recording medium based on data transferred from a computer device,
Sequentially storing data transferred from the computer device in a predetermined area unit in a first buffer;
Sequentially storing data generated according to the recording processing content on the recording medium in a second buffer in units of a predetermined area;
A control command having a repetition number field indicating the number of areas of data to be repeatedly processed is used according to the data transferred from the computer device. Sequentially generating and storing in the command storage unit,
Applying predetermined processing to the data of each buffer based on the control command stored in the command storage unit and outputting the data;
The total number of control command repetition count fields stored in the command storage unit, the number of data transferred from the computer device but for which no control command has been generated, and stored in the command storage unit Detecting the remaining amount of data in the first buffer and the second buffer based on the remaining number of repetitions of the control command being processed among the control commands being processed;
A method for detecting the remaining amount of data.

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