JP2008146499A - Analysis method and analyzer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an analysis method for efficiently performing analysis when a failure of being incapable of acquiring an operation history at all occurs, and to provide an analyzer. <P>SOLUTION: A configuration as a controller for controlling a copying machine comprises a CPU 1, a RAM 4, a ROM 6, an HDD 5, a copying machine engine 3, an ASIC 2 for control, an output port, a UART 7 as a serial interface for terminal output to a PC and an RS232C driver/receiver 8 as main components. Between each processing, a sub routine for inverting the output port is inserted. By performing such processing, how far software has advanced can easily be judged. The waveform of the output port is referred to, and to which processing the operation is advanced without stop and in what processing abnormality such as the stop of the operation is generated by some problems can be judged. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to an analysis method and an analysis apparatus, and in particular, it is possible to send a message (log) to a debug console (terminal) at the time of system start-up when the main power is turned on or before hardware initial setting when returning from an energy saving state. The present invention relates to an analysis apparatus and an analysis method for efficiently analyzing defects that have occurred before.

  In recent years, the functions of copiers and multi-function multifunction peripherals (hereinafter collectively referred to as multi-function peripherals) have become complicated, and various problems have occurred. In addition, there are many cases where manufacturers of multifunction devices and the like provide SDKs (Software Development Kits) and third parties develop their own applications to provide added value to multifunction devices and the like.

  Along with this, the complexity of functions of multifunction devices and the like has been further spurred, and the problems that occur have become more complex and diversified. It is expected that the number of third-party original applications using SDK will increase in the future.

  When software becomes complicated, analysis takes time because there are many factors that can be considered when a problem occurs. Therefore, the operation history (log) such as what kind of operation the system has performed, what processing has been performed, what kind of abnormality has been detected is important, and there is no information on the operation history when analyzing abnormal operation It is no exaggeration to say that analysis is impossible.

The operation history is sent to a PC (terminal) connected via a serial interface, or is temporarily stored in a memory so that it can be pulled out from the PC (terminal) later, or a non-volatile memory such as an SD card. Various techniques for performing failure analysis have been proposed, such as a method of accumulating data in a database and confirming the contents later on a PC (see, for example, Patent Documents 1 and 2).
JP 2006-40297 A JP-A-11-208075

  However, in recent years, abnormal operations in hardware / software that have become complicated may occur very rarely. Also, when the main power supply is turned on or when returning from energy saving, the initial settings of the hardware and before the self-diagnosis are performed. There are many cases where operation history cannot be sent to the serial interface due to abnormal operation.

  In such an abnormality, since no operation history has been acquired, it is very difficult to analyze the failure, and a high-spec and intelligent measuring instrument such as a logic analyzer is connected to the CPU bus to provide instruction fetch / data fetch levels. There arises a problem that it is necessary to analyze the software operation at.

  It is an object of the present invention to provide effective and reliable information that can efficiently perform analysis at the time of occurrence of such a failure that such an operation history cannot be acquired at all.

  The invention described in claim 1 is an analysis method characterized by comprising a step of inverting the output of a specific output port at a key point in each process of software of a controller board that controls the image processing apparatus.

  According to a second aspect of the present invention, in the method of the first aspect, the specific output port generates one pulse.

  According to a third aspect of the present invention, in the method of the first aspect, the specific output port generates one pulse having a specific width.

  According to a fourth aspect of the present invention, in the method of the first aspect, the specific output port generates a unique number of pulses.

  According to a fifth aspect of the present invention, at a key point in each processing of software of a controller board that controls the image processing apparatus, a step of generating a unique number of pulses at the first output port, and at the first output port, And a step of outputting an identification level at the second output port while generating the unique number of pulses.

  According to a sixth aspect of the present invention, in the method of the fourth or fifth aspect, the unique pulse generation includes a step of generating by hardware instead of generation of a pulse by software processing.

  According to a seventh aspect of the present invention, there is provided an analyzing apparatus comprising means for inverting an output of a specific output port at a key point in each process of software of a controller board that controls the image processing apparatus.

  The invention according to claim 8 is the apparatus according to claim 7, wherein the specific output port generates one pulse.

  According to a ninth aspect of the present invention, in the apparatus of the seventh aspect, the specific output port generates one pulse having a specific width.

  According to a tenth aspect of the present invention, in the device according to the seventh aspect, the specific output port generates a unique number of pulses.

  According to the eleventh aspect of the present invention, means for generating a unique number of pulses at the first output port at key points in each processing of the software of the controller board that controls the image processing apparatus, and the first output port And a means for outputting an identification level at the second output port while the unique number of pulses is being generated.

  According to the present invention, it is an object to provide effective and reliable information that enables efficient analysis at the time of occurrence of a problem such that such an operation history cannot be obtained at all.

  Hereinafter, an analysis apparatus and an analysis method according to an embodiment of the present invention will be described in detail with reference to the drawings. The embodiments described below are preferred embodiments of the present invention, and thus various technically preferable limitations are given. However, the scope of the present invention is particularly limited in the following description. As long as there is no description which limits, it is not restricted to these aspects.

  FIG. 1 is a block configuration diagram according to an embodiment of the present invention. The main components are a CPU 1, a RAM 4, a ROM 6, an HDD 5, a copier engine 3, a control ASIC 2, an output port, and a UART 7 and an RS232C driver / receiver 8 as a serial interface for terminal output to a PC. It is the structure as a controller which controls.

  The operation process of this embodiment will be described with reference to FIG. First, FIG. 18 shows normal processing, and log output to the PC becomes possible after processing H has been reached. Therefore, if the operation stops due to some trouble during the initial setting A, B (steps S1, 2), diagnosis A, B (steps S3, 4), and processes A to G (steps S6 to 12) before that, There is no way to know how far has gone.

  FIG. 2 is a flowchart showing an operation process according to the present embodiment. A subroutine for inverting the output port is inserted between the processes. By performing such processing, it is possible to easily determine how far the software has progressed. The inversion of the output port can be considered using an oscilloscope 10 as shown in FIG. 3, for example.

  FIG. 4 is a diagram illustrating an example of a waveform of the output port. In the situation shown in FIG. 4, since it is reversed five times, the operation proceeds without stopping until processing A in FIG. 2, and it can be determined that abnormality has occurred in processing B due to some problem or the like.

  According to the above-described embodiment, it is possible to determine how far the software has operated without performing complicated analysis such as connecting a logic analyzer or the like when an operation abnormality that cannot be obtained at all in the log can be achieved, and the efficiency of the analysis can be improved. It becomes possible.

  Next, operation processing according to another embodiment of the present invention will be described with reference to FIG. In this embodiment, a subroutine for generating one pulse at the output port is inserted each time each initial setting (A, B), diagnosis (A, B), and processing (A to H) proceeds. By performing such processing, it is possible to easily determine how far the software has progressed.

  FIG. 6 is an example showing a waveform of the output port. In the situation shown in FIG. 6, since three pulses are generated, the operation proceeds to diagnosis A in FIG. 5 without stopping, and it can be determined in diagnosis B that an abnormality has occurred such as operation stop due to some problem.

  According to the above-described embodiment, it is possible to determine how far the software has operated without performing complicated analysis such as connecting a logic analyzer or the like when an operation abnormality that cannot be obtained at all in the log can be achieved, and the efficiency of the analysis can be improved. It becomes possible.

  Next, an operation process of the apparatus according to another embodiment of the present invention will be described with reference to FIG. As in the above embodiments, the means for inverting the output port or generating a pulse cannot determine how far the software has progressed when the software branches according to conditions.

  For example, in the case of the flow shown in FIG. 7, if a means for generating one pulse shown in FIG. 2 is considered in subroutine A, initial setting A → initial setting B → initial setting D in the case of three pulses. It is not possible to determine which process of initial setting A → initial setting C → initial setting E and initial setting A → initial setting C → initial setting F has been performed. Therefore, at a specific point on the software, the pulse of which point is identified by generating one pulse having a width (period) unique to the point.

  For example, in the waveform of the output port shown in FIG. 8, after the pulse having the pulse width of 1, the pulse of 3, and the pulse of 6 is output, the operation is stopped without outputting the pulse. The operation proceeds without stopping until the initial setting C → the initial setting F, and it can be determined by diagnosis A that an abnormality has occurred such as the operation being stopped due to some problem.

  According to the above embodiment, when a failure that cannot obtain operation history at all occurs, it is possible to easily determine how far the software has advanced without connecting a logic analyzer etc. By making it possible to determine whether the operation has been performed, it is possible to improve the efficiency of analysis.

  Next, an operation process of the apparatus according to another embodiment of the present invention will be described with reference to FIG. This is a means for making it possible to determine how far the software has progressed by observing the output waveform of the output port even when the software branches according to conditions.

  For example, in the case of the flow shown in FIG. 9, at a specific point on the software, the number of pulses unique to that point is generated to identify the point of the pulse. For example, in the waveform of the output port shown in FIG. 10, the operation proceeds without stopping from the initial setting A → the initial setting C → the initial setting E, and an abnormality such as the operation stopping due to some problem occurs in the diagnosis A. I can judge.

  According to the above embodiment, it is possible to easily determine how far the software has progressed without a logic analyzer etc. when a failure occurs in which operation history can not be acquired at all, and how far the software can operate even in software that branches depending on conditions Therefore, it is possible to improve the efficiency of analysis.

  Next, FIG. 11 shows a block configuration of an apparatus according to another embodiment of the present invention. In this configuration, one output port is added to the configuration shown in FIG. 1 and an output port A and an output port B are provided.

  In the case of the embodiment described with reference to FIG. 9 above, if an asynchronous interrupt enters the processing of subroutine A, the pulse interval and pulse waveform of the output port are not controlled at a constant timing because interrupt processing is performed. It will be. A waveform example in such a case is shown in FIG. In this case, the interrupts I and II are performed while three pulse generation processes are being performed, and the interrupt III is performed while five pulse generation processes are being performed. With such an output waveform, it is impossible to specify what processing has been performed.

  The operation process of this embodiment is shown in FIG. As shown in subroutine A, by preparing two output ports, it is possible to output a high-level signal to the output port A during the pulse generation period to the output port B, so that a waveform whose timing has been lost due to interrupt processing can be assured. It is possible to identify the number of generated pulses.

  FIG. 14 shows an output waveform when the operation shown in the present embodiment is performed. As shown in the figure, since the interrupt processing is performed, the pulse width of each pulse of the output port B and the timing of pulse generation are broken. However, since a set of pulses is clarified by the information of the output port A (1 pulse → 3 pulses → 5 pulses), the operation proceeds without stopping from initial setting A → initial setting C → initial setting E, and diagnosis In A, it can be determined that an abnormality has occurred such as an operation stoppage due to some problem.

  According to the above embodiment, it is possible to specify how far the processing has progressed even with software that branches depending on the condition, and even if the timing of the pulse collapses due to interrupt processing etc., it is possible to determine how far the software has operated, Analysis efficiency can be improved.

  A block configuration of an apparatus according to another embodiment of the present invention is shown in FIGS. In the configuration example shown in FIG. 15, the pulse generator 11 for generating a pulse is connected to a local bus to which a ROM or the like is connected. However, the pulse generator is incorporated in the control ASIC and one of the functions of the ASIC is obtained. It's okay.

  FIG. 16 shows a configuration example of the simplest pulse generator. This configuration example includes a pulse generator that generates pulses, a pulse generation number setting register that sets the number of pulse generations, a counter that counts the number of pulses, and a comparator that compares the pulse number setting value and the counter value.

  The pulse generation number setting register has a register for holding a set value therein and is controlled to write by both −S (chip select) and −W (write) signals. Also, it has -CLR1 and -CLR2 terminals, and the register value is cleared (0) by asserting either signal.

  The counter counts the clock input to the CLKIN terminal and outputs it to the comparator. Also, it has -CLR1 and -CLR2 terminals, and the count value is cleared (0) by asserting either signal.

  The comparator has a function of comparing the set value from the pulse generation number setting register with the count value from the counter. The -STOP signal is asserted when the two input data match, and negated when they do not match. The -CLR signal outputs one pulse (negative pulse) when two input data match.

  The pulse generator has a function of generating a pulse based on a clock input to the CLKIN terminal and outputting the pulse to the CLKOUT terminal. In addition, pulse output is stopped while the -CLR terminal and -STOP terminal are asserted.

  FIG. 17 briefly explains the operation processing of this embodiment. -After reset release, the pulse generation number setting register value and the count value are 0. The number “3” to be generated is written in the pulse generation number setting register in a. Thereby, -STOP of the comparator output is negated (b). Since PSSTOP is negated, PSOUT from the pulse generator begins to be output (c). The counter starts a count operation when a pulse is generated (d, e, f). Since the count value matches the set value due to f, -STOP is asserted and one pulse is output to -CLR (g). As a result, the pulse output to PSOUT is stopped, and the pulse generation number setting register value and the count value are cleared (0) (h). Thereafter, the operation stops until the set value is written again to the pulse generation number setting register.

  According to the above embodiment, it is possible to specify how far processing has progressed even with software that branches depending on conditions, and by eliminating complicated software processing such as taking pulse generation timing by software processing, further software processing The load can be reduced.

  Note that the program for the CPU 1 to execute the processing shown in the flowcharts of the drawings constitutes a program according to the present invention. As a recording medium for recording the program, a semiconductor storage unit, an optical and / or magnetic storage unit, or the like can be used. By using such a program and a recording medium in a system having a configuration different from that of each of the above-described embodiments and causing the CPU to execute the program, substantially the same effect as the present invention can be obtained.

  Although the present invention has been specifically described above based on the preferred embodiments, it is needless to say that the present invention is not limited to the above-described ones and can be variously modified without departing from the gist thereof.

It is a block block diagram of the apparatus which concerns on embodiment of this invention. It is a flowchart which shows the operation processing of the apparatus which concerns on embodiment of this invention. It is a figure for demonstrating the example which performs the output port inversion which concerns on embodiment of this invention. It is a figure which shows the waveform of the output port which concerns on embodiment of this invention. It is a flowchart which shows the operation processing of the apparatus which concerns on embodiment of this invention. It is a figure which shows the waveform of the output port which concerns on embodiment of this invention. It is a flowchart which shows the operation processing of the apparatus which concerns on embodiment of this invention. It is a figure which shows the waveform of the output port which concerns on embodiment of this invention. It is a flowchart which shows the operation processing of the apparatus which concerns on embodiment of this invention. It is a figure which shows the waveform of the output port which concerns on embodiment of this invention. It is a block block diagram of the apparatus which concerns on embodiment of this invention. It is a figure which shows the waveform of the output port which concerns on embodiment of this invention. It is a flowchart which shows the operation processing of the apparatus which concerns on embodiment of this invention. It is a figure which shows the waveform of the output port which concerns on embodiment of this invention. It is a block block diagram of the apparatus which concerns on embodiment of this invention. It is a block block diagram of the pulse generator which concerns on embodiment of this invention. It is a figure for demonstrating the operation processing of the apparatus which concerns on embodiment of this invention. It is a flowchart which shows a normal operation | movement process.

Explanation of symbols

1 CPU
2 ASIC for control
3 Copier engine 4 RAM
5 HDD
6 ROM
7 UART
8 RS232C driver / receiver 9 PC (terminal)
10 Oscilloscope 11 Pulse generator

Claims (11)

  An analysis method comprising a step of inverting an output of a specific output port at a key point in each process of software of a controller board that controls the image processing apparatus.   The analysis method according to claim 1, wherein the specific output port generates one pulse.   The analysis method according to claim 1, wherein the specific output port generates one pulse having a specific width.   The analysis method according to claim 1, wherein the specific output port generates a unique number of pulses. Generating a unique number of pulses at the first output port at key points in each process of the software on the controller board that controls the image processing apparatus;
Outputting an identification level at the second output port while generating a unique number of pulses at the first output port.   6. The analysis method according to claim 4, wherein the generation of the unique pulse includes a step of generating by hardware instead of generation of a pulse by software processing.   An analysis apparatus comprising means for inverting an output of a specific output port at a key point in each process of software of a controller board that controls the image processing apparatus.   The analysis apparatus according to claim 7, wherein the specific output port generates one pulse.   8. The analysis apparatus according to claim 7, wherein the specific output port generates one pulse having a specific width.   8. The analysis apparatus according to claim 7, wherein the specific output port generates a unique number of pulses. Means for generating a unique number of pulses at the first output port at key points in each process of the controller board software that controls the image processing apparatus;
Means for outputting an identification level at the second output port while generating a unique number of pulses at the first output port.

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