JP2008141047A - Nitride semiconductor light emitting element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a nitride semiconductor light emitting element for reducing a drive power voltage with respect to the nitride semiconductor light emitting element, which has tunnel junction. <P>SOLUTION: A substrate, a first n-type nitride semiconductor layer formed on the substrate, a light emitting layer, a first p-type nitride semiconductor layer, a second p-type nitride semiconductor layer, a p-type nitride semiconductor tunnel junction layer, a n-type nitride semiconductor tunnel junction layer, and a second n-type nitride semiconductor layer are included. The p-type nitride semiconductor tunnel junction layer, and the n-type nitride semiconductor tunnel junction layer constitute a tunnel junction. In the nitride semiconductor light emitting element, a composition ratio of the indium of the p-type nitride semiconductor tunnel junction layer is larger than that of the second p-type nitride semiconductor layer. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a nitride semiconductor light emitting device, and more particularly to a nitride semiconductor light emitting device having a tunnel junction.

  Conventionally, in a nitride semiconductor light emitting diode element in which the p-type nitride semiconductor layer side is the light extraction side, the p-side electrode formed on the p-type nitride semiconductor layer satisfies the following three conditions: Is required.

  First, the first condition is that the transmittance with respect to the light emitted from the nitride semiconductor light emitting diode element is high. Next, the second condition is to have a resistivity and a thickness capable of sufficiently diffusing the injected current in the plane of the light emitting layer. Finally, the third condition is that the contact resistance with the p-type nitride semiconductor layer is low.

  As the p-side electrode formed on the p-type nitride semiconductor layer of the nitride semiconductor light-emitting diode element in which the p-type nitride semiconductor layer side is the light extraction side, conventionally, about several to 10 nm of palladium, nickel, etc. A translucent metal electrode made of a thick metal film was formed on the entire surface of the p-type nitride semiconductor layer. However, such a translucent metal electrode has a low transmittance of about 50% with respect to the light emitted from the nitride semiconductor light-emitting diode element, so that the light extraction efficiency is lowered and a high-luminance nitride semiconductor light-emitting diode element is obtained. There was a problem that it was difficult.

  Therefore, the light extraction efficiency is improved by forming a transparent conductive film made of ITO (Indium Tin Oxide) over the entire surface of the p-type nitride semiconductor layer in place of the translucent metal electrode made of a metal film such as palladium or nickel. High brightness nitride semiconductor light emitting diode devices have been manufactured. The contact resistance between the transparent conductive film and the p-type nitride semiconductor layer, which has been a concern in the nitride semiconductor light-emitting diode element formed with such a transparent conductive film, is also improved by heat treatment or the like.

  Patent Document 1 discloses a group III nitride having at least a first n-type group III nitride semiconductor multilayer structure, a p-type group III nitride semiconductor multilayer structure, and a second n-type group III nitride semiconductor multilayer structure. An n-type group III nitride semiconductor layer in the first n-type group III nitride semiconductor multilayer structure is provided with a negative electrode, and a second n-type group III group is formed on the substrate. The n-type group III nitride semiconductor layer in the nitride semiconductor multilayer structure is provided with a positive electrode, and the n-type group III nitride semiconductor layer and the p-type III in the second n-type group III nitride semiconductor multilayer structure are provided. A nitride semiconductor light-emitting diode element in which a tunnel junction is formed by a p-type group III nitride semiconductor layer having a group nitride semiconductor multilayer structure is disclosed.

In the nitride semiconductor light emitting diode element disclosed in Patent Document 1, the positive electrode is formed on the n-type group III nitride semiconductor layer in the second n-type group III nitride semiconductor multilayer structure, and the n-type Since the group III nitride semiconductor can easily increase the carrier concentration as compared with the p-type group III nitride semiconductor, compared with the conventional structure in which the positive electrode is formed on the p-type group III nitride semiconductor layer. The contact resistance can be reduced, the drive voltage is low, and a large output drive is possible. Further, it is said that reliability can be improved because heat generation at the positive electrode, which has been one of the causes of failure of the nitride semiconductor light emitting diode element, is reduced.
JP 2002-319703 A

  However, the transparent conductive film made of ITO has a problem that the optical properties are irreversibly changed at high temperatures, and the visible light transmittance is lowered. In addition, when a transparent conductive film made of ITO is used, the temperature range of the process after the formation of the transparent conductive film made of ITO is limited in order to prevent a reduction in visible light transmittance. There was a problem. Furthermore, the transparent conductive film made of ITO has a problem that it deteriorates due to driving at a high current density and becomes black.

  In the nitride semiconductor light-emitting diode element described in the example of Patent Document 1, a tunnel junction is formed by a p-type InGaN layer and an n-type InGaN layer having an In (indium) composition ratio comparable to that of the light-emitting layer. The thickness of each layer is 50 nm.

As described in the example of Patent Document 1, in order to sufficiently supply In as a solid phase, it is necessary to lower the growth temperature to about 800 ° C. However, since it is difficult to obtain a p-type InGaN layer having a high carrier concentration of 1 × 10 ¹⁹ / cm ³ or higher at low temperature, voltage loss at the tunnel junction cannot be reduced, resulting in a drive voltage of There was a problem of becoming higher.

  Accordingly, an object of the present invention is to provide a nitride semiconductor light emitting device capable of reducing the driving voltage.

  The present invention includes a substrate, a first n-type nitride semiconductor layer, a light emitting layer, a first p-type nitride semiconductor layer, and a second p-type nitride semiconductor layer formed on the substrate. A p-type nitride semiconductor tunnel junction layer, an n-type nitride semiconductor tunnel junction layer, and a second n-type nitride semiconductor layer, wherein the p-type nitride semiconductor tunnel junction layer and the n-type nitride semiconductor tunnel are included. The junction layer forms a tunnel junction, and is a nitride semiconductor light emitting device in which the indium composition ratio of the p-type nitride semiconductor tunnel junction layer is larger than the indium composition ratio of the second p-type nitride semiconductor layer. . In the present invention, “the composition ratio of indium in the p-type nitride semiconductor tunnel junction layer” refers to the total number of group III elements (Al, Ga, and In) contained in the p-type nitride semiconductor tunnel junction layer. It means the ratio of the number of In atoms. In the present invention, “the composition ratio of indium in the second p-type nitride semiconductor layer” is the total number of group III elements (Al, Ga, and In) contained in the second p-type nitride semiconductor layer. It means the ratio of the number of In atoms to the number. In the present specification, Al represents aluminum, Ga represents gallium, and In represents indium.

  In the nitride semiconductor light emitting device of the present invention, the thickness of the second p-type nitride semiconductor layer is preferably 2 nm or more.

  In the nitride semiconductor light emitting device of the present invention, the thickness of the second p-type nitride semiconductor layer is preferably greater than or equal to the critical thickness.

In the nitride semiconductor light emitting device of the present invention, the doping concentration of the p-type impurity in the second p-type nitride semiconductor layer is preferably 1 × 10 ¹⁹ / cm ³ or more.

  In the nitride semiconductor light emitting device of the present invention, the thickness of the p-type nitride semiconductor tunnel junction layer is preferably 5 nm or less.

In the nitride semiconductor light emitting device of the present invention, the p-type impurity doping concentration in the p-type nitride semiconductor tunnel junction layer is preferably 1 × 10 ¹⁹ / cm ³ or more.

  In the nitride semiconductor light emitting device of the present invention, the band gap of the first p-type nitride semiconductor layer is larger than the band gap of the second p-type nitride semiconductor layer, and the second p-type nitride semiconductor layer Is preferably larger than the band gap of the p-type nitride semiconductor tunnel junction layer.

  In the nitride semiconductor light emitting device of the present invention, the n-type nitride semiconductor tunnel junction layer preferably contains indium.

In the nitride semiconductor light emitting device of the present invention, the n-type impurity doping concentration of the n-type nitride semiconductor tunnel junction layer is preferably 1 × 10 ¹⁹ / cm ³ or more.

  In the nitride semiconductor light emitting device of the present invention, the thickness of the n-type nitride semiconductor tunnel junction layer is preferably 10 nm or less.

  In the present invention, the “p-type impurity doping concentration” indicates the atomic concentration of the p-type impurity contained in the nitride semiconductor, and the “n-type impurity doping concentration” indicates the n-type impurity contained in the nitride semiconductor. These can be quantitatively calculated by methods such as SIMS (Secondary Ion Mass Spectrometry).

  ADVANTAGE OF THE INVENTION According to this invention, the nitride semiconductor light-emitting device which can reduce a drive voltage can be provided.

  Embodiments of the present invention will be described below. In the drawings of the present invention, the same reference numerals represent the same or corresponding parts.

  FIG. 1 shows a schematic cross-sectional view of a preferred example of a nitride semiconductor light-emitting diode element which is an example of the nitride semiconductor light-emitting element of the present invention. Here, the nitride semiconductor light emitting diode element shown in FIG. 1 includes a substrate 1, a first n-type nitride semiconductor layer 2, a light emitting layer 3, and a first p layer, which are sequentially stacked on the substrate 1. Type nitride semiconductor layer 4, second p type nitride semiconductor layer 5, p type nitride semiconductor tunnel junction layer 6, n type nitride semiconductor tunnel junction layer 7, and n type nitride semiconductor evaporation suppression layer 8 and a second n-type nitride semiconductor layer 9, an n-side electrode 10 is formed on the first n-type nitride semiconductor layer 2, and a second n-type nitride semiconductor layer is formed. 9 has a configuration in which a p-side electrode 11 is formed.

  In the nitride semiconductor light emitting device having such a configuration, the contact resistance can be reduced and the driving voltage can be lowered as compared with the conventional structure in which the positive electrode is formed on the conventional p-type nitride semiconductor layer. On the other hand, there is a question as to how the voltage loss at the tunnel junction which is the junction between the p-type nitride semiconductor tunnel junction layer 6 and the n-type nitride semiconductor tunnel junction layer 7 can be reduced.

  The tunneling probability Tt at this tunnel junction is generally expressed by the following equation (1).

Tt = exp ((- 8π ( 2m e) 1/2 Eg 3/2) / (3qhε)) ... (1)
In the above formula (1), Tt denotes a tunneling probability, m _e denotes the effective mass of the conduction electrons, Eg represents an energy gap, q represents an electron charge, h represents the Planck's constant, ε represents an electric field applied to the tunnel junction.

  In order to reduce the driving voltage of the nitride semiconductor light emitting device, it is desired to increase the tunneling probability Tt. From the above equation (1), as a method for increasing the tunneling probability Tt, it is conceivable to reduce the energy gap Eg in the tunnel junction and increase the electric field ε applied to the tunnel junction.

  In order to reduce the energy gap Eg at the tunnel junction, it is preferable that the p-type nitride semiconductor tunnel junction layer 6 and the n-type nitride semiconductor tunnel junction layer 7 each contain In and have a high In composition ratio. On the other hand, when the In composition ratio of the p-type nitride semiconductor tunnel junction layer 6 is larger than the In composition ratio of the light emitting layer 3, the light emitted from the light emitting layer 3 is absorbed by the tunnel junction, It is preferable that the p-type nitride semiconductor tunnel junction layer 6 has a small thickness because the extraction efficiency decreases.

  Further, since the n-type nitride semiconductor tunnel junction layer 7 has a high activation rate of n-type impurities and can realize a high carrier concentration, it is possible to reduce the width of the depletion layer on the n side of the tunnel junction when driven. it can. Therefore, from the viewpoint of improving light extraction efficiency, the thickness of n-type nitride semiconductor tunnel junction layer 7 is preferably set to be equal to or smaller than the thickness of p-type nitride semiconductor tunnel junction layer 6.

  However, in the case where In is sufficiently taken into the p-type nitride semiconductor tunnel junction layer 6 as a solid phase, the growth temperature needs to be lowered to about 800 ° C. as described above, and the p-type nitride semiconductor is required. It is difficult to increase the carrier concentration of the tunnel junction layer 6.

  Therefore, the present invention is characterized in that the In composition ratio of the p-type nitride semiconductor tunnel junction layer 6 is made larger than the In composition ratio of the second p-type nitride semiconductor layer 5. With such a configuration, the p-type nitride semiconductor tunnel junction layer 6 causes lattice mismatch with the second p-type nitride semiconductor layer 5, and the second p-type nitride semiconductor layer 5 and the p-type nitride semiconductor layer 5. An electric field is generated at or near the interface with the nitride semiconductor tunnel junction layer 6 due to the difference in electron affinity between these layers, and the holes of the p-type nitride semiconductor tunnel junction layer 6 are attracted to the vicinity of the interface to generate a two-dimensional electron gas. appear. The carrier concentration can be locally increased in the vicinity of the interface on the p-type nitride semiconductor tunnel junction layer 6 side by the effect of the generated two-dimensional electron gas, so that the tunneling probability Tt at the tunnel junction can be increased. As a result, voltage loss at the tunnel junction can be reduced.

In order to increase the electric field ε applied to the tunnel junction, the ionized impurity concentration of both the p-type nitride semiconductor tunnel junction layer 6 and the n-type nitride semiconductor tunnel junction layer 7 may be increased. Here, since the ionized impurity concentration in the p-type nitride semiconductor tunnel junction layer 6 is preferably 1 × 10 ¹⁸ / cm ³ or more, the doping concentration of the p-type impurity in the p-type nitride semiconductor tunnel junction layer 6 is It is preferable that it is 1 × 10 ¹⁹ / cm ³ or more. In the present invention, as the p-type impurity, for example, Mg (magnesium) and / or Zn (zinc) can be doped.

Further, since the ionized impurity concentration in the n-type nitride semiconductor tunnel junction layer 7 is preferably 1 × 10 ¹⁹ / cm ³ or more, the n-type impurity doping concentration in the n-type nitride semiconductor tunnel junction layer 7 is 1 It is preferable that it is × 10 ¹⁹ / cm ³ or more. In the present invention, as the n-type impurity, for example, Si (silicon) and / or Ge (germanium) can be doped.

  Furthermore, as another method for increasing the tunneling probability Tt, there is a method of forming an intermediate level. As a method of forming the intermediate level, for example, there is a method of forming a dislocation. In order to form the dislocation, the second p-type nitride semiconductor layer 5 is the first p-type nitride semiconductor layer serving as a base. 4 and lattice mismatch, and preferably has a thickness of 2 nm or more, and preferably has a thickness of critical film thickness or more. When dislocations are formed in this way, an intermediate level is generated at the tunnel junction due to the dislocation, and carriers can tunnel through the intermediate level, so that the tunneling probability Tt can be increased, and consequently the driving voltage. Tends to be reduced.

The critical film thickness is generally represented by the following formula (2).
h _c = (a _e / (2 ^1/2 πf)) × ((1−ν / 4) / (1 + ν)) × (ln (h _c 2 ^1/2 / a _e ) +1) (2)
In the above formula (2), h _c represents the critical film thickness of the second p-type nitride semiconductor layer 5, a _e represents the lattice constant of the second p-type nitride semiconductor layer 5, and f Represents the maximum absolute value of (a _s −a _e ) / a _e , and ν represents the Poisson's ratio of the second p-type nitride semiconductor layer 5. Furthermore, a _s denotes the lattice constant of the first p-type nitride semiconductor layer 4.

  As the substrate 1, for example, a sapphire substrate, a silicon substrate, a silicon carbide substrate, a zinc oxide substrate, or the like can be used.

  Further, as the first n-type nitride semiconductor layer 2, for example, a nitride semiconductor crystal doped with an n-type impurity can be used.

Further, as the light emitting layer 3, for example, a nitride semiconductor crystal having a single quantum well (SQW) structure or a multiple quantum well (MQW) structure can be grown, and among them, Al _a In _b Ga _{1- (a + b) A} material having a multiple quantum well structure including a nitride semiconductor crystal represented by a composition formula of N (0 ≦ a ≦ 1, 0 ≦ b ≦ 1, 0 ≦ 1- (a + b) ≦ 1) is used. preferable. In the above composition formula, a represents the Al composition ratio, b represents the In composition ratio, and 1- (a + b) represents the Ga composition ratio.

  The first p-type nitride semiconductor layer 4 can be a nitride semiconductor crystal doped with a p-type impurity. For example, a p-type GaN layer is formed on a p-type nitride semiconductor layer containing Al. A grown layer, a p-type GaN layer grown on a p-type nitride semiconductor layer containing Al, and a p-type nitride semiconductor layer containing In grown thereon can be used.

The second p-type nitride semiconductor layer 5 can be a nitride semiconductor crystal doped with p-type impurities, and has a lattice mismatch with the uppermost layer of the first p-type nitride semiconductor layer 4. When it has, it is preferable to form dislocations at a stage exceeding the critical film thickness. Further, when the thickness of the p-type nitride semiconductor tunnel junction layer 6 is sufficiently thin, for example, 5 mm or less, and the depletion layer is formed also in the second p-type nitride semiconductor layer 5, In _x Ga _1-x It is preferable to use a layer in which a nitride semiconductor crystal represented by a composition formula of N (0 ≦ x <1) is doped with a p-type impurity. In the above composition formula, x represents the In composition ratio, and 1-x represents the Ga composition ratio. The doping concentration of the p-type impurity in the second p-type nitride semiconductor layer 5 is preferably 1 × 10 ¹⁹ / cm ³ or more. When the doping concentration of the p-type impurity in the second p-type nitride semiconductor layer 5 is less than 1 × 10 ¹⁹ / cm ³ , the resistivity of the second p-type nitride semiconductor layer 5 is increased, and the driving voltage is increased. May increase.

For example, when the first p-type nitride semiconductor layer 4 is formed by growing a p-type GaN layer on a p-type AlGaN layer, the second p-type nitride semiconductor layer 5 is In _x Ga _{1 -x.} It is preferable that the nitride semiconductor crystal represented by the composition formula of N (0 ≦ x <1) is a layer in which a p-type impurity is doped. When the uppermost layer of the first p-type nitride semiconductor layer 4 is a p-type AlGaN layer, the second p-type nitride semiconductor layer 5 may be a p-type GaN layer. Further, the band gap energy of the second p-type nitride semiconductor layer 5 may be greater than or equal to the energy corresponding to the wavelength of the light emitted from the light emitting layer 3 in order to prevent a decrease in light extraction efficiency.

As described above, the p-type nitride semiconductor tunnel junction layer 6 is preferably a nitride semiconductor containing In, and the ionized impurity concentration of the p-type nitride semiconductor tunnel junction layer 6 is 1 × 10 ¹⁸ / cm ^3. The above is preferable.

  The band gap relationship among the first p-type nitride semiconductor layer 4, the second p-type nitride semiconductor layer 5, and the p-type nitride semiconductor tunnel junction layer 6 is expressed by the first p-type nitride semiconductor layer 4. Is larger than the band gap of the second p-type nitride semiconductor layer 5, and the band gap of the second p-type nitride semiconductor layer 5 is larger than the band gap of the p-type nitride semiconductor tunnel junction layer 6. It is preferable. When the second p-type nitride semiconductor layer 5 has a larger band gap than the first p-type nitride semiconductor layer 4, the activation energy of the p-type dopant is increased, leading to a decrease in carrier concentration and driving. There is a risk of increasing the voltage.

As described above, in order to increase the tunneling probability Tt, the n-type nitride semiconductor tunnel junction layer 7 is preferably a nitride semiconductor containing In, and the ionized impurities of the n-type nitride semiconductor tunnel junction layer 7 The concentration is preferably 1 × 10 ¹⁸ / cm ³ or more. However, since the ionized impurity concentration of n-type nitride semiconductor tunnel junction layer 7 can be made higher than that of p-type nitride semiconductor layer, n-type nitride semiconductor tunnel junction layer 7 does not contain In such as GaN, for example. It may be a nitride semiconductor.

In addition, since the n-type nitride semiconductor tunnel junction layer 7 has a shallow donor level and a high activation rate, the ionized impurity concentration can be increased to, for example, 1 × 10 ¹⁹ / cm ³ or more. In consideration of the fact that the depletion layer is less spread toward the type nitride semiconductor tunnel junction layer 7 and that the amount of light emitted from the light emitting layer 3 is reduced, the thickness of the n type nitride semiconductor tunnel junction layer 7 The thickness is preferably 10 nm or less.

  In the n-type nitride semiconductor tunnel junction layer 7, a p-type impurity may be doped together with the n-type impurity. In this case, it is possible to expect the effects of suppressing the diffusion of p-type impurities from the p-type nitride semiconductor tunnel junction layer 6 and forming an intermediate level in the depletion layer. Can contribute.

  Further, the p-type nitride semiconductor tunnel junction layer 6 and the n-type nitride semiconductor tunnel junction layer 7 may each include an opposite conductivity type layer and / or an undoped layer, and an opposite conductivity type layer and an undoped layer. The layer thickness of each layer is preferably a thickness (for example, 2 nm or less) at which the carriers tunnel at the tunnel junction.

  In addition, by forming the n-type nitride semiconductor evaporation suppression layer 8, when the p-type nitride semiconductor tunnel junction layer 6 and / or the n-type nitride semiconductor tunnel junction layer 7 contains In, the In is contained from these layers. Evaporation can be suppressed.

Here, the n-type nitride semiconductor evaporation suppressing layer 8, for _{example, Al c In d Ga 1- (} c + d) N (0 ≦ c ≦ 1,0 ≦ d ≦ 1,0 ≦ 1- (c + d) A layer in which an n-type impurity is doped in the nitride semiconductor crystal represented by the composition formula ≦ 1) can be used, and n-type GaN is particularly preferable. In the above composition formula, c represents the composition ratio of Al, d represents the composition ratio of In, and 1- (c + d) represents the composition ratio of Ga.

  Further, by forming the second n-type nitride semiconductor layer 9, the current injected from the p-side electrode 11 formed on the second n-type nitride semiconductor layer 9 can be diffused.

Here, as the second n-type nitride semiconductor layer 8, for example, a nitride semiconductor crystal doped with an n-type impurity can be used, and among them, a layer having a low resistivity is preferable. It is desirable to be composed of GaN having a carrier concentration of 1 × 10 ¹⁸ / cm ³ or more.

  Further, as the n-side electrode 10 formed on the first n-type nitride semiconductor layer 2 and the p-side electrode 11 formed on the second n-type nitride semiconductor layer 9, for example, Ti (titanium) , Hf (hafnium) and Al (aluminum) are preferably used to form an ohmic contact using at least one metal selected from the group consisting of Al (aluminum).

  Here, the n-side electrode 10 is formed by etching the wafer after the growth of the second n-type nitride semiconductor layer 9 from the second n-type nitride semiconductor layer 9 side to thereby form the first n-type nitride. A part of the surface of the semiconductor layer 2 can be exposed and formed on the exposed surface.

  In addition, the first n-type nitride semiconductor layer 9 side of the wafer after the growth of the second n-type nitride semiconductor layer 9 is attached to a separately prepared conductive support substrate, whereby the first n At least one selected from the group consisting of Al, Pt, and Ag having high reflectivity on the support substrate side, where the type nitride semiconductor layer 2 side is the light extraction side, and the second n-type nitride semiconductor layer 9 side is the support substrate side It is also possible to form a nitride semiconductor light emitting diode element having an upper and lower electrode structure by forming a seed metal.

  According to the nitride semiconductor light-emitting diode element having such an upper and lower electrode structure, the second n-type nitride semiconductor layer 9 can have a higher carrier concentration than the conventional p-type nitride semiconductor layer. Regardless of the work function, ohmic characteristics due to carrier tunneling can be easily obtained, and the above-described highly reflective metal can be formed on the second n-type nitride semiconductor layer 9, thereby improving light extraction efficiency. There is a tendency.

(Example 1)
In Example 1, a nitride semiconductor light-emitting diode element having the configuration shown in the schematic cross-sectional view of FIG. 2 was produced. Here, the nitride semiconductor light-emitting diode device of Example 1 has a GaN buffer layer 102, an n-type GaN underlayer 103, an n-type GaN contact layer 104, a light-emitting layer 105, and a p-type AlGaN cladding layer 106 on a sapphire substrate 101. The p-type GaN contact layer 107, the p-type InGaN layer 108, the p-type tunnel junction layer 109, the n-type tunnel junction layer 110, the n-type GaN evaporation suppression layer 111, and the n-type GaN layer 112 are stacked in this order, and the n-type A pad electrode 113 is formed on the surface of the GaN layer 112, and a pad electrode 114 is formed on the surface of the n-type GaN contact layer 104.

  First, the sapphire substrate 101 was set in the reactor of the MOCVD apparatus. Then, the surface of the sapphire substrate 101 (C surface) was cleaned by raising the temperature of the sapphire substrate 101 to 1050 ° C. while flowing hydrogen into the reactor.

  Next, the temperature of the sapphire substrate 101 is lowered to 510 ° C., hydrogen as a carrier gas, ammonia and TMG (trimethyl gallium) as a source gas are flowed into the reactor, and GaN is formed on the surface (C plane) of the sapphire substrate 101. The buffer layer 102 was grown on the sapphire substrate 101 with a thickness of about 20 nm by MOCVD.

Next, the temperature of the sapphire substrate 101 is raised to 1050 ° C., hydrogen as a carrier gas, ammonia and TMG as source gases, and silane as an impurity gas are flown into the reaction furnace, and an n-type GaN underlayer 103 doped with Si is added. (Carrier concentration: 1 × 10 ¹⁸ / cm ³ ) was grown on the GaN buffer layer 102 to a thickness of 6 μm by MOCVD.

Subsequently, the n-type GaN contact layer 104 is formed to a thickness of 0.5 μm by MOCVD in the same manner as the n-type GaN underlayer 103 except that Si is doped so that the carrier concentration becomes 5 × 10 ¹⁸ / cm ^3. Then, it was grown on the n-type GaN foundation layer 103.

Next, the temperature of the sapphire substrate 101 is lowered to 700 ° C., hydrogen as a carrier gas, ammonia, TMG, and TMI (trimethylindium) as a source gas are flown into the reactor, and 2. on the n-type GaN contact layer 104. A light emitting layer 105 having a multiple quantum well structure is formed on the n-type GaN contact layer 104 by alternately growing an In _0.25 Ga _0.75 N layer having a thickness of 5 nm and a GaN layer having a thickness of 18 nm by a six-period MOCVD method. Formed. Needless to say, when the GaN layer is grown during the formation of the light emitting layer 105, TMI is not allowed to flow into the reactor.

Next, the temperature of the sapphire substrate 101 is raised to 950 ° C., hydrogen as a carrier gas, ammonia, TMG and TMA (trimethylaluminum) as source gases, and CP2Mg (cyclopentadienylmagnesium) as impurity gases are flowed into the reactor. A p-type AlGaN cladding layer 106 made of Al _0.15 Ga _0.85 N doped with Mg at a concentration of 1 × 10 ²⁰ / cm ³ was grown on the light-emitting layer 105 to a thickness of about 30 nm by MOCVD.

Next, while maintaining the temperature of the sapphire substrate 101 at 950 ° C., hydrogen as a carrier gas, ammonia and TMG as source gases, and CP2Mg as an impurity gas are allowed to flow into the reactor so that Mg is 1 × 10 ²⁰ / cm ^3. A p-type GaN contact layer 107 made of GaN doped with a concentration of 0.1 μm was grown on the p-type AlGaN cladding layer 106 by MOCVD.

Next, the temperature of the sapphire substrate 101 is lowered to 700 ° C., nitrogen as the carrier gas, ammonia, TMG and TMI as the source gas, and CP2Mg as the impurity gas flow into the reaction furnace, and Mg becomes 1 × 10 ²⁰ / cm ^3. A p-type InGaN layer 108 as a second p-type nitride semiconductor layer made of In _0.25 Ga _0.75 N doped at a concentration of 1 is deposited on the p-type GaN contact layer 107 in a predetermined range of 0 to 50 nm by MOCVD. Grow to thickness.

Thereafter, the temperature of the sapphire substrate 101 is lowered to 670 ° C., nitrogen as a carrier gas, ammonia, TMG and TMI as source gases, and CP2Mg as an impurity gas flow into the reactor, and Mg is 1 × 10 ²⁰ / cm ³ . A p-type tunnel junction layer 109 made of In _0.30 Ga _0.70 N doped at a concentration was grown on the p-type InGaN layer 108 to a thickness of 2 nm by MOCVD.

Next, while maintaining the temperature of the sapphire substrate 101 at 670 ° C., nitrogen as a carrier gas, ammonia as a source gas, TMG and TMI, and silane as an impurity gas are allowed to flow into the reaction furnace, thereby doping In _0.30 doped with Si. An n-type tunnel junction layer 110 (carrier concentration: 5 × 10 ¹⁹ / cm ³ ) made of Ga _0.70 N was grown on the p-type tunnel junction layer 109 to a thickness of 4 nm by MOCVD.

Thereafter, while maintaining the temperature of the sapphire substrate 101 at 670 ° C., nitrogen as a carrier gas, ammonia and TMG as source gases, and silane as an impurity gas are allowed to flow into the reaction furnace to form an n-type made of GaN doped with Si. A GaN evaporation suppression layer 111 (carrier concentration: 5 × 10 ¹⁹ / cm ³ ) was grown on the n-type tunnel junction layer 110 to a thickness of 15 nm.

Thereafter, the temperature of the sapphire substrate 101 is increased to 950 ° C., hydrogen as a carrier gas, ammonia and TMG as source gases, and silane as an impurity gas are allowed to flow into the reaction furnace so that Si has a concentration of 1 × 10 ¹⁹ / cm ³ . The n-type GaN layer 112 made of GaN doped with (1) was grown on the n-type GaN evaporation suppression layer 111 to a thickness of 0.2 μm by MOCVD.

  Next, the temperature of the sapphire substrate 101 was lowered to 700 ° C., and annealing was performed by flowing nitrogen as a carrier gas into the reaction furnace.

  Then, the annealed wafer was taken out of the reactor, and a mask patterned in a predetermined shape was formed on the surface of the n-type GaN layer 112 as the uppermost layer of the wafer. Then, a part of the wafer was etched from the n-type GaN layer 112 side by RIE (Reactive Ion Etching) method to expose a part of the surface of the n-type GaN contact layer 104.

  Then, a pad electrode 113 was formed on the surface of the n-type GaN layer 112, and a pad electrode 114 was formed on the surface of the n-type GaN contact layer 104. Here, the pad electrode 113 and the pad electrode 114 were simultaneously formed by sequentially laminating a Ti layer and an Al layer on the surface of the n-type GaN layer 112 and on the surface of the n-type GaN contact layer 104, respectively. Then, the nitride semiconductor light-emitting diode device of Example 1 having the configuration shown in the schematic cross-sectional view of FIG. 2 was manufactured by dividing the wafer into a plurality of chips.

  FIG. 3 shows the relationship between the thickness of the p-type InGaN layer 108 and the drive voltage in the nitride semiconductor light-emitting diode element of Example 1. In FIG. 3, the vertical axis represents the drive voltage (V) at the time of current injection of 20 mA, and the horizontal axis represents the thickness (nm) of the p-type InGaN layer 108.

  As shown in FIG. 3, the drive voltage decreased as the thickness of the p-type InGaN layer 108 increased until the thickness of the p-type InGaN layer 108 reached 20 nm. In addition, it was confirmed that the driving voltage was drastically reduced when the thickness of the p-type InGaN layer 108 as the second p-type nitride semiconductor layer was 10 nm or less.

(Example 2)
The p-type GaN contact layer 107 was fabricated under the same conditions and the same method as in Example 1 until the p-type GaN contact layer 107 was grown.

Then, the temperature of the sapphire substrate 101 is lowered to 700 ° C., nitrogen as the carrier gas, ammonia, TMG and TMI as the source gas, and CP2Mg as the impurity gas are flown into the reactor, and Mg is 1 × 10 ²⁰ / cm ³ . A p-type InGaN layer 108 as a second p-type nitride semiconductor layer made of In _0.25 Ga _0.75 N doped at a concentration was grown on the p-type GaN contact layer 107 to a thickness of 20 nm by MOCVD.

Thereafter, the temperature of the sapphire substrate 101 is lowered to 670 ° C., nitrogen as a carrier gas, ammonia, TMG and TMI as source gases, and CP2Mg as an impurity gas flow into the reactor, and Mg is 1 × 10 ²⁰ / cm ³ . A p-type tunnel junction layer 109 made of In _0.30 Ga _0.70 N doped at a concentration was grown on the p-type InGaN layer 108 to a predetermined thickness in the range of 0 to 10 nm by MOCVD.

  Thereafter, the nitride semiconductor light-emitting diode element of Example 2 was fabricated under the same conditions and the same method as in Example 1.

  FIG. 4 shows the relationship between the thickness of the p-type tunnel junction layer 109 and the drive voltage in the nitride semiconductor light-emitting diode element of Example 2. In FIG. 4, the vertical axis represents the driving voltage (V) at the time of current injection of 20 mA, and the horizontal axis represents the thickness (nm) of the p-type tunnel junction layer 109.

  As shown in FIG. 4, the drive voltage is low when the thickness of the p-type tunnel junction layer 109 is 5 nm or less, and the drive voltage is low when the thickness of the p-type tunnel junction layer 109 is 1 nm or more and 3 nm or less. Especially low.

  FIG. 5 shows the relationship between the thickness of the p-type tunnel junction layer 109 and the light output in the nitride semiconductor light-emitting diode element of Example 2. In FIG. 5, the vertical axis represents the light output (.au), and the horizontal axis represents the thickness (nm) of the p-type tunnel junction layer 109.

  As shown in FIG. 5, it was confirmed that the light output decreased as the thickness of the p-type tunnel junction layer 109 was reduced.

  From the results of FIGS. 4 and 5, from the viewpoint of reducing the drive voltage and improving the light output, the thickness of the p-type tunnel junction layer 109 is preferably 5 nm or less, and preferably 1 nm or more and 3 nm or less. It was confirmed that it was more preferable.

(Example 3)
In Example 3, a nitride semiconductor light-emitting diode element having the configuration shown in the schematic cross-sectional view of FIG. 6 was produced. Here, the nitride semiconductor light-emitting diode element of Example 3 has an ohmic electrode layer 56, a first bonding metal layer 57, a second bonding metal layer 54, a barrier layer 53, a reflection on the conductive substrate 55. Layer 52, n-type GaN layer 112, n-type GaN evaporation suppression layer 111, n-type tunnel junction layer 110, p-type tunnel junction layer 109, p-type InGaN layer 108, p-type GaN contact layer 107, p-type AlGaN cladding layer 106 The light emitting layer 105, the n-type GaN contact layer 104, the n-type GaN foundation layer 103, and the pad electrode 58 are sequentially formed.

  In Example 3, the same process as in Example 1 was performed until the p-type GaN contact layer 107 was grown.

Next, the temperature of the sapphire substrate 101 is lowered to 700 ° C., nitrogen as the carrier gas, ammonia, TMG and TMI as the source gas, and CP2Mg as the impurity gas flow into the reaction furnace, and Mg becomes 1 × 10 ²⁰ / cm ^3. A p-type InGaN layer 108 as a second p-type nitride semiconductor layer made of In _0.25 Ga _0.75 N doped at a concentration of 20 nm was grown on the p-type GaN contact layer 107 to a thickness of 20 nm by MOCVD.

Thereafter, the temperature of the sapphire substrate 101 is lowered to 670 ° C., nitrogen as a carrier gas, ammonia, TMG and TMI as source gases, and CP2Mg as an impurity gas flow into the reactor, and Mg is 1 × 10 ²⁰ / cm ³ . A p-type tunnel junction layer 109 made of In _0.30 Ga _0.70 N doped at a concentration was grown on the p-type InGaN layer 108 to a thickness of 2 nm by MOCVD.

Next, while maintaining the temperature of the sapphire substrate 101 at 670 ° C., nitrogen as a carrier gas, ammonia as a source gas, TMG and TMI, and silane as an impurity gas are allowed to flow into the reaction furnace, thereby doping In _0.30 doped with Si. An n-type tunnel junction layer 110 (carrier concentration: 5 × 10 ¹⁹ / cm ³ ) made of Ga _0.70 N was grown on the p-type tunnel junction layer 109 to a thickness of 4 nm by MOCVD.

Thereafter, while maintaining the temperature of the sapphire substrate 101 at 670 ° C., nitrogen as a carrier gas, ammonia and TMG as source gases, and silane as an impurity gas are allowed to flow into the reaction furnace to form an n-type made of GaN doped with Si. A GaN evaporation suppression layer 111 (carrier concentration: 5 × 10 ¹⁹ / cm ³ ) was grown on the n-type tunnel junction layer 110 to a thickness of 15 nm.

Thereafter, the temperature of the sapphire substrate 101 is increased to 950 ° C., hydrogen as a carrier gas, ammonia and TMG as source gases, and silane as an impurity gas are allowed to flow into the reaction furnace so that Si has a concentration of 1 × 10 ¹⁹ / cm ³ . The n-type GaN layer 112 made of GaN doped with (1) was grown on the n-type GaN evaporation suppression layer 111 to a thickness of 0.2 μm by MOCVD.

  Next, the temperature of the sapphire substrate 101 was lowered to 700 ° C., and annealing was performed by flowing nitrogen as a carrier gas into the reaction furnace.

  Then, after annealing, a second adhesion layer comprising a reflective layer 52 made of an Ag layer having a thickness of 150 nm, a barrier layer 53 made of a Mo layer having a thickness of 50 nm, and an Au layer having a thickness of 3 μm is formed on the surface of the n-type GaN layer 112. The metal layer 54 was formed in this order by EB (Electron Beam) vapor deposition.

  Next, an ohmic electrode layer 56 in which a Ti layer having a thickness of 15 nm and an Al layer having a thickness of 150 nm are stacked in this order on a separately prepared conductive substrate 55 made of conductive Si having a thickness of 120 μm by EB vapor deposition. In addition, a first bonding metal layer 57 in which an Au layer having a thickness of 100 nm and an AuSn layer having a thickness of 3 μm were stacked in this order was formed in this order.

  Then, the AuSn layer located on the outermost surface of the first bonding metal layer 57 and the Au layer located on the outermost surface of the second bonding metal layer 54 are made to face each other, using the eutectic bonding method. The bonding metal layer 57 and the second bonding metal layer 54 were joined. The temperature during eutectic bonding was 290 ° C.

  Subsequently, the third harmonic (wavelength: 355 nm) of YAG laser light is irradiated from the back side of the mirror-polished sapphire substrate 101, and the GaN buffer layer 102 and the n-type GaN underlayer 103 formed on the sapphire substrate 101 The sapphire substrate 101 and the GaN buffer layer 102 were removed by thermally decomposing the interface portion.

Thereafter, a pad electrode 58 was formed by laminating a Ti layer and an Au layer in this order on the surface of the n-type GaN foundation layer 103 exposed by removing the sapphire substrate 101 and the GaN buffer layer 102. Then, the nitride semiconductor light-emitting diode element of Example 3 having the configuration shown in the schematic cross-sectional view of FIG. 6 was manufactured by dividing the wafer after the formation of the pad electrode 58 into a plurality of chips. In the nitride semiconductor light emitting diode device of Example 3, the carrier concentration of the n-type GaN foundation layer 103 is set to 5 × 10 ¹⁸ / cm in order to reduce the contact resistance between the n-type GaN foundation layer 103 and the pad electrode 58. ^{It was set to 3} .

  The driving voltage of the nitride semiconductor light emitting diode device of Example 3 at the time of current injection of 20 mA is 4.0 V, and the conventional nitride semiconductor light emitting diode device having the upper and lower electrode structures described later (the nitride semiconductor light emitting device of Comparative Example 1). It was confirmed that the drive voltage could be reduced as compared with the diode element.

(Comparative Example 1)
In Comparative Example 1, a nitride semiconductor light-emitting diode element having the configuration shown in the schematic cross-sectional view of FIG. 7 was produced. Here, the nitride semiconductor light-emitting diode element of Comparative Example 1 has an ohmic electrode layer 56, a first bonding metal layer 57, a second bonding metal layer 54, a barrier layer 53, a reflection on the conductive substrate 55. The layer 52, the p-type GaN contact layer 107, the p-type AlGaN cladding layer 106, the light emitting layer 105, the n-type GaN contact layer 104, the n-type GaN foundation layer 103, and the pad electrode 58 are sequentially formed.

  In the nitride semiconductor light emitting diode device of Comparative Example 1, the p-type InGaN layer 108, the p-type tunnel junction layer 109, the n-type tunnel junction layer 110, the n-type GaN evaporation suppression layer 111, and the n-type GaN layer 112 are formed. The nitride semiconductor light emitting diode element of Example 3 has the same configuration as that of Example 3 except for the above.

  The driving voltage of the nitride semiconductor light emitting diode device of Comparative Example 1 at the time of 20 mA current injection is 6.0 V, which is higher than the driving voltage of the nitride semiconductor light emitting diode device of the Example 3 at the time of 20 mA current injection. It was confirmed. This is because the contact resistance between the p-type GaN contact layer 107 and the reflective layer 52 made of an Ag layer is high.

  In the nitride semiconductor light emitting diode device of Comparative Example 1, a reflective layer composed of a p-type GaN contact layer 107 and an Ag layer with a metal having a high work function such as Pd or Ni as a thin film of about several nm in order to reduce the driving voltage. In this case, since Pd and Ni have low reflectivity, light from the light emitting layer 105 is absorbed and light output is considered to be reduced.

  It should be understood that the embodiments and examples disclosed herein are illustrative and non-restrictive in every respect. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  According to the present invention, the driving voltage of a nitride semiconductor light emitting element such as a nitride semiconductor light emitting diode element having a tunnel junction and emitting blue light (for example, a wavelength of 430 nm or more and 490 nm or less) can be reduced.

It is typical sectional drawing of a preferable example of the nitride semiconductor light-emitting diode element which is an example of the nitride semiconductor light-emitting element of this invention. It is typical sectional drawing of the nitride semiconductor light-emitting diode element of Examples 1-2. FIG. 3 is a diagram showing the relationship between the thickness of the p-type InGaN layer and the drive voltage in the nitride semiconductor light-emitting diode element of Example 1. 6 is a diagram showing the relationship between the thickness of a p-type tunnel junction layer and the drive voltage in the nitride semiconductor light-emitting diode element of Example 2. FIG. 6 is a diagram showing the relationship between the thickness of the p-type tunnel junction layer and the light output in the nitride semiconductor light-emitting diode element of Example 2. FIG. 6 is a schematic cross-sectional view of a nitride semiconductor light-emitting diode element according to Example 3. FIG. 6 is a schematic cross-sectional view of a nitride semiconductor light-emitting diode element of Comparative Example 1. FIG.

Explanation of symbols

  1 substrate 2 first n-type nitride semiconductor layer 3 light emitting layer 4 first p-type nitride semiconductor layer 5 second p-type nitride semiconductor layer 6 p-type nitride semiconductor tunnel junction layer 7 n-type nitride semiconductor tunnel junction layer, 8 n-type nitride semiconductor evaporation suppression layer, 9 second n-type nitride semiconductor layer, 10 n-side electrode, 11 p-side electrode, 52 reflective layer, 53 barrier layer, 54 Second adhesive metal layer, 55 conductive substrate, 56 ohmic electrode layer, 57 first adhesive metal layer, 101 sapphire substrate, 102 GaN buffer layer, 103 n-type GaN underlayer, 104 n-type GaN contact layer, 105 light emitting layer, 106 p-type AlGaN cladding layer, 107 p-type GaN contact layer, 108 p-type InGaN layer, 109 p-type tunnel junction layer, 110 n-type tunnel junction layer, 111 n GaN evaporation suppressing layer, 112 n-type GaN layer, 113 and 114 pad electrode.

Claims (10)

  A substrate, a first n-type nitride semiconductor layer, a light emitting layer, a first p-type nitride semiconductor layer, a second p-type nitride semiconductor layer, and a p-type formed on the substrate A nitride semiconductor tunnel junction layer, an n-type nitride semiconductor tunnel junction layer, and a second n-type nitride semiconductor layer, the p-type nitride semiconductor tunnel junction layer and the n-type nitride semiconductor tunnel junction The layer forms a tunnel junction, and the composition ratio of indium in the p-type nitride semiconductor tunnel junction layer is larger than the composition ratio of indium in the second p-type nitride semiconductor layer, Nitride semiconductor light emitting device.   2. The nitride semiconductor light emitting device according to claim 1, wherein a thickness of the second p-type nitride semiconductor layer is 2 nm or more.   2. The nitride semiconductor light emitting device according to claim 1, wherein a thickness of the second p-type nitride semiconductor layer is not less than a critical thickness. 4. The nitride semiconductor light-emitting element according to claim 1, wherein a doping concentration of p-type impurities in the second p-type nitride semiconductor layer is 1 × 10 ¹⁹ / cm ³ or more. 5. .   5. The nitride semiconductor light emitting device according to claim 1, wherein a thickness of the p-type nitride semiconductor tunnel junction layer is 5 nm or less. 6. The nitride semiconductor light emitting device according to claim 1, wherein a doping concentration of a p-type impurity in the p-type nitride semiconductor tunnel junction layer is 1 × 10 ¹⁹ / cm ³ or more.   The band gap of the first p-type nitride semiconductor layer is larger than the band gap of the second p-type nitride semiconductor layer, and the band gap of the second p-type nitride semiconductor layer is the p-type nitride. The nitride semiconductor light-emitting element according to claim 1, wherein the nitride semiconductor light-emitting element is larger than a band gap of the semiconductor tunnel junction layer.   The nitride semiconductor light emitting device according to claim 1, wherein the n-type nitride semiconductor tunnel junction layer contains indium. 9. The nitride semiconductor light emitting device according to claim 1, wherein a doping concentration of the n-type impurity in the n-type nitride semiconductor tunnel junction layer is 1 × 10 ¹⁹ / cm ³ or more.   10. The nitride semiconductor light emitting device according to claim 1, wherein the n-type nitride semiconductor tunnel junction layer has a thickness of 10 nm or less.

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