JP2008140952A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve the manufacturing yield of a semiconductor device having a pad electrode on the surface thereof. <P>SOLUTION: A vertical MISFET of trench-type gate structure is formed on a semiconductor substrate, and a surface protective film as the top layer is formed by spin coating method after forming the gate wiring and the source wiring. Then, a resist pattern RP1 having an opening 28a at the location wherein a gate pad electrode is to be formed is formed on the surface protective film, and an opening 29a is formed in the surface protective film by etching the surface protective film using the resist pattern RP1 as the etching mask. The gate pad electrode is formed of the gate wiring exposed from the opening 29a. Although the planar shape of the opening 28a in the resist pattern RP1 is a rectangular shape, the portion thereof nearest to the corner 44a of a semiconductor device region 10A which becomes a semiconductor chip later is rounded and retreated in the direction leaving from the corner 44a. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a technique effective when applied to a method for manufacturing a semiconductor device in which a surface protective film is formed by spin coating and then a pad opening is formed.

  The semiconductor chip has a pad electrode for external connection on its surface. The pad electrode is formed by forming a conductor layer for the pad electrode on the semiconductor substrate on which the semiconductor element is formed, and then forming a surface protective film so as to cover the conductive layer, and providing an opening in the surface protective film. It can form by exposing the conductor layer for pad electrodes from a part.

Japanese Laid-Open Patent Publication No. 2006-222121 (Patent Document 1) describes a semiconductor chip in which a vertical power MISFET having a trench type gate structure is formed and a source pad electrode and a gate pad electrode are formed on the surface. .
JP 2006-222121 A

  According to the study of the present inventor, the following has been found.

  The surface protective film is made of, for example, a polyimide resin and can be formed by using a spin coat method or the like. However, since the chemical solution for film formation easily moves along the groove-shaped scribe region, In the surface, a portion having a non-uniform thickness of the surface protective film (a locally thin portion or a locally thick portion) is generated. In order to form the pad electrode, a photoresist pattern having an opening at a position where the pad electrode is to be formed is formed on the surface protection film, and the surface protection film is etched using the photoresist pattern as an etching mask. Then, a pad electrode opening is formed, and the pad electrode conductor layer is exposed from the pad electrode opening. However, the amount of side etching of the surface protective film differs between the thick part and the thin part of the surface protective film. Therefore, if the thickness of the surface protective film is not uniform as described above, the shape of the pad electrode opening of the surface protective film may be deformed with respect to the shape of the opening of the photoresist pattern. There is. That is, there is a possibility that the shape of the pad electrode opening in the surface protective film deviates from the shape of the opening in the photoresist pattern (pattern deformation). This may reduce the alignment margin of the pad electrode opening with respect to the pad electrode conductor layer, and may reduce the manufacturing yield of the semiconductor device.

  An object of the present invention is to provide a technique capable of improving the manufacturing yield of a semiconductor device.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  According to the present invention, a resist pattern having an opening at a position where a pad electrode is to be formed is formed on a surface protective film, and the surface protective film is etched using the resist pattern as an etching mask to thereby form a pad electrode opening in the surface protective film The pad electrode conductor layer is exposed to expose the planar shape of the opening of the resist pattern, but the portion closest to the corner of the semiconductor device area that will later become a semiconductor chip is receded away from the corner. It is made into the shape made to do.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  The manufacturing yield of the semiconductor device can be improved.

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. There are some or all of the modifications, details, supplementary explanations, and the like. Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number. Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted. In the following embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary.

  In the drawings used in the embodiments, hatching may be omitted even in a cross-sectional view so as to make the drawings easy to see. Further, even a plan view may be hatched to make the drawing easy to see.

  A method for manufacturing a semiconductor device and a semiconductor device according to an embodiment of the present invention will be described with reference to the drawings.

  FIG. 1 is a top view (plan view) showing a chip layout of a semiconductor device (semiconductor chip) 1 according to the present embodiment, and FIG. 2 is a bottom view (plan view) of the semiconductor device 1.

  The semiconductor device 1 will be described in detail later. For example, after various semiconductor elements or semiconductor integrated circuits are formed on a semiconductor substrate (semiconductor wafer) made of single crystal silicon or the like, the semiconductor substrate is subjected to back grinding if necessary. Then, the semiconductor substrate (semiconductor wafer) is separated into each semiconductor device (semiconductor chip) 1 by dicing or the like.

  In the present embodiment, as the semiconductor device 1, for example, a semiconductor chip on which a vertical power MISFET (Metal Insulator Semiconductor Field Effect Transistor) having a trench gate structure is formed can be used.

  The semiconductor device 1 has two main surfaces located on opposite sides, a front surface (main surface on the semiconductor element forming side) 1a and a back surface (main surface opposite to the front surface 1a) 1b. 1 shows the front surface 1a side, and FIG. 2 shows the back surface 1b side. As shown in FIG. 1 and FIG. 2, the semiconductor device 1 includes a source pad electrode (surface electrode) 2s and a gate pad electrode (surface electrode) 2g formed on the front surface 1a, and a back surface formed on the entire back surface 1b. And a drain electrode (back electrode) 2d. The source pad electrode 2s is electrically connected to the source of the MISFET formed in the semiconductor device 1, and the gate pad electrode 2g is electrically connected to the gate electrode of the MISFET formed in the semiconductor device 1. The back drain electrode 2d is electrically connected to the drain of the MISFET formed in the semiconductor device 1. As shown in FIG. 1, the semiconductor device 1 according to the present embodiment has pad electrodes (here, a source pad electrode 2s and a gate pad electrode 2g) formed on the surface 1a. 2 g is arranged in the vicinity of the corner 3 of the surface 1 a of the semiconductor device 1.

  Next, the manufacturing process of the semiconductor device 1 of the present embodiment will be described with reference to FIGS. 3 to 11 are main-portion cross-sectional views during the manufacturing process of the semiconductor device of the present embodiment. 3 to 11 show a part of two adjacent semiconductor device regions (semiconductor element formation region, chip region) 10A and a scribe region (cutting region) 10B between the semiconductor device regions 10A. As will be described later, each semiconductor device region 10A is a region that later becomes an individual semiconductor chip (semiconductor device 1).

To manufacture the semiconductor device 1, first, as shown in FIG. 3, for example, on the main surface of a semiconductor substrate (semiconductor wafer) 11 a made of, for example, n ⁺ type single crystal silicon into which arsenic (As) is introduced. An epitaxial layer 11b made of n ⁻ type single crystal silicon is grown to form a semiconductor substrate (semiconductor wafer, so-called epitaxial wafer) 11. Then, after forming an insulating film (silicon oxide film) on the main surface of the semiconductor substrate 11, the insulating film is patterned to form an insulating film 12 (SiO ₂ plate).

  Next, the p-type well 13 is formed by ion-implanting a p-type impurity (for example, boron (B)) into the main surface of the semiconductor substrate 11.

  Next, as shown in FIG. 4, a trench for forming a trench gate, that is, a gate trench 14 is formed by dry etching the semiconductor substrate 11 using a photoresist pattern (not shown) as an etching mask. The depth of the gate trench 14 is deeper than the p-type well 13 and shallower than the bottom of the epitaxial layer 11b.

  Next, a relatively thin gate insulating film (silicon oxide film) 15 is formed on the inner wall surface (side surface and bottom surface) of the gate trench 14 by using, for example, a thermal oxidation method.

  Next, a conductor film (gate electrode material film) made of, for example, a low resistance polycrystalline silicon film is formed on the main surface of the semiconductor substrate 11. Then, a photoresist pattern (not shown) that covers the gate wiring formation region and exposes the other region is formed on the conductor film, and the conductor film is formed using the photoresist pattern as an etching mask. By etching back, a gate portion 16 made of low-resistance polycrystalline silicon or the like embedded in the gate trench 14 and a gate wiring portion (gate lead portion) 16a formed integrally with the gate portion 16 are formed. Form.

  Next, as shown in FIG. 5, a channel region 17 is formed by ion implantation of a p-type impurity (for example, boron (B)) into the main surface of the semiconductor substrate 11. Then, the source region 18 is formed by ion-implanting an n-type impurity (for example, arsenic (As)) into the main surface of the semiconductor substrate 11.

  Next, as shown in FIG. 6, an insulating film (interlayer insulating film) 22 is formed on the main surface of the semiconductor substrate 11 and patterned using a photolithography technique and an etching technique. At this time, a contact hole 23 exposing the main surface of the semiconductor substrate 11 and a through hole 24 exposing a part of the gate wiring portion 16 a are formed in the insulating film 22. The photolithography method (lithography method) is a method of patterning a photoresist film (resist film) into a desired pattern (resist pattern) by a series of steps of coating, exposing and developing a photoresist film (resist film). .

Next, the semiconductor substrate 11 exposed from the contact hole 23 is etched to form a hole 25. Then, a p ⁺ type semiconductor region is formed by, for example, ion implantation of a p type impurity (for example, boron (B)) into the semiconductor substrate 11 exposed from the contact hole 23 and the hole 25.

  Next, for example, a titanium tungsten film (not shown) is formed on the main surface of the semiconductor substrate 11 as necessary, and then an aluminum film 26 is formed thereon by a sputtering method or the like. The aluminum film 26 is a conductor layer mainly composed of aluminum such as a single aluminum film or an aluminum alloy film.

  Next, as shown in FIG. 7, the laminated film of the titanium tungsten film and the aluminum film 26 is patterned by using a photolithography technique and an etching technique. Thereby, surface electrodes such as the gate wiring (gate electrode) 26a and the source wiring 26b are formed.

  Next, as shown in FIG. 8, an insulating film (protective film, surface protective film) 27 for surface protection made of, for example, polyimide resin (polyimide resin) is formed on the main surface of the semiconductor substrate 11. (Film formation).

  Next, as shown in FIG. 9, a resist pattern (photoresist pattern, resist film, photoresist film) RP1 is formed on the main surface of the semiconductor substrate 11, that is, on the insulating film 27, using a photolithography technique. To do. The resist pattern RP1 is formed on the main surface of the semiconductor substrate 11 so as to cover each semiconductor device region 10A. In each semiconductor device region 10A, an opening 29a (gate pad electrode 2g), which will be described later, is to be formed (position). It has an opening 28a, and has an opening 28b in a region (position) where an opening 29b (source pad electrode 2s) to be described later is to be formed.

  Next, as shown in FIG. 10, using the resist pattern RP1 as an etching mask, the insulating film 27 (the insulating film 27 exposed from the openings 28a and 28b of the resist pattern RP1) is selectively etched. The insulating film 27 is patterned by an etching process of the insulating film 27 using the resist pattern RP1 as an etching mask (hereinafter referred to as an “etching process of the insulating film 27”), and the gate wiring 26a and the source wiring 26b are formed on the insulating film 27. Opening portions 29a and 29b are formed so as to expose the portions, and bonding pads (here, gate pad electrode 2g and source pad electrode 2s) are formed. The gate wiring 26a exposed from the opening 29a of the insulating film 27 becomes the gate pad electrode 2g of the semiconductor device 1, and the source wiring 26b exposed from the opening 29b of the insulating film 27 becomes the source pad electrode 2s. Therefore, the openings 29a and 29b are openings for pad electrode formation. Of these, the opening 29a is an opening (pad opening) for the gate pad electrode 2g, and the opening 29b is a source pad electrode. This is an opening (pad opening) for 2s.

  The etching process of the insulating film 27 can be performed by wet etching. At this time, the etching solution is an etching solution that can selectively etch the insulating film 27 while suppressing the etching of the conductor film (here, the aluminum film 26) constituting the gate wiring 26a and the source wiring 26b. Tetramethylammonium) aqueous solution or the like can be used.

  Thereafter, the resist pattern RP1 is removed by ashing or the like.

  Next, the back surface of the semiconductor substrate 11 is thinned by grinding or polishing as necessary. Thereafter, as shown in FIG. 11, the drain electrode 31 is formed by depositing, for example, nickel, titanium, nickel and gold on the back surface of the semiconductor substrate 11 by vapor deposition. The drain electrode 31 becomes the back drain electrode 2d of the semiconductor device 1.

  In this manner, a semiconductor element such as a vertical power MISFET having a trench gate structure is formed on the semiconductor substrate 11.

  FIG. 12 is a plan view (overall plan view) schematically showing the entire semiconductor substrate 11 during the manufacturing process of the semiconductor device, and corresponds to the same process steps as FIG.

  As shown in FIG. 12, a plurality of semiconductor device regions 10 </ b> A are arranged in an array (matrix) on the main surface of the semiconductor substrate 11.

  3 to 11, the semiconductor substrate 11 is cut or diced using a dicing saw or the like along the scribe region 10B between the semiconductor device regions 10A shown in FIG. Thus, the semiconductor substrate 11 is cut and separated into individual semiconductor device regions 10A (semiconductor device 1). Each separated semiconductor device region 10 </ b> A becomes the semiconductor device 1.

  In this way, the semiconductor device 1 in which the vertical power MISFET having the trench gate structure is formed is manufactured. Note that the vertical MISFET corresponds to a MISFET in which a current between the source and the drain flows in the thickness direction of the semiconductor substrate (a direction substantially perpendicular to the main surface of the semiconductor substrate).

  FIG. 13 is a main part plan view (partial enlarged plan view) showing a part of the semiconductor substrate 11 during the manufacturing process of the semiconductor device. FIG. 13 corresponds to a plan view of the main part in the process of forming the insulating film 27. At this stage, the pad electrode openings 29a and 29b have not yet been formed. In FIG. 13, the positions where the openings 29a and 29b are formed (that is, the positions where the gate pad electrode 2g and the source pad electrode 2s are formed) are indicated by dotted lines. Further, FIG. 13 is a plan view, but in order to make the drawing easy to see, the region 43a where the film thickness of the insulating film 27 is reduced and the region 43b where the thickness is increased are hatched.

  The insulating film 27 can be formed by spin coating. For example, while the semiconductor substrate 11 is adsorbed to a wafer chuck (not shown) or the like and rotated at a predetermined rotation speed, a chemical solution for forming the insulating film 27 (a liquid film forming material, here a polyimide solution) is applied to the semiconductor substrate. The insulating film 27 can be formed by applying the film forming material to the entire main surface of the semiconductor substrate 11 by dropping it onto the center of the main surface of the semiconductor substrate 11.

  Since the spin coating method is used, the chemical solution for forming the insulating film 27 flows from the center of the main surface of the semiconductor substrate 11 to the outer peripheral side. In the stage before the formation of the insulating film 27 (the stage of FIG. 7), the insulating film 22 and the aluminum film are formed in the semiconductor substrate region 10A, while the insulating film 22 and the aluminum film are formed in the scribe region 10B. The film 26 is not formed. For this reason, on the main surface of the semiconductor substrate 11, the scribe region 10 </ b> B is in a groove-like state whose height is lower than that of the semiconductor device region 10 </ b> A. For this reason, the chemical for forming the insulating film 27 is likely to move along the scribe region 10B.

  Therefore, as shown in FIG. 13, the chemical solution that has flowed in the direction of the arrow 41a along the scribe region 10B extending in the X direction and the scribe extending in the Y direction (direction intersecting or orthogonal to the X direction). The chemical solution flowing in the direction of the arrow 41b along the region 10B collides at the intersection 42 between the scribe region 10B in the X direction and the scribe region 10B in the Y direction. Due to this collision, the chemical solution for forming the insulating film 27 is likely to accumulate in the region 43b shown in FIG. 13, so that the insulating film 27 is formed thick, and in the region 43a shown in FIG. 13, the insulating film 27 is formed. Therefore, the insulating film 27 is thinly formed.

  In each semiconductor device region 10A, the region 43a where the film thickness of the insulating film 27 is reduced is a corner portion 44a on the side toward the center of the main surface of the semiconductor substrate 11 among the four corner portions of the semiconductor device region 10A. It is a nearby region. In each semiconductor device region 10A, the region 43b where the thickness of the insulating film 27 is increased is a corner portion 44a on the side toward the center of the main surface of the semiconductor substrate 11 among the four corner portions of each semiconductor device region 10A. Is a region near the corner 44b on the opposite side (diagonal line side). The corner portion 44a of the semiconductor device region 10A and the corner portion 44b of the other semiconductor device region 10A disposed at a position facing the diagonal direction are opposed to each other via the intersection 42 of the scribe region 10B.

Such a phenomenon occurs when the aluminum film 26 is thicker than the film thickness T ₂ (see FIG. 8) of the insulating film 27 in the scribe region 10B when the insulating film 27 is formed. When the thickness T ₁ (see FIG. 6) of the aluminum film 26 in the scribe region 10B at the time is thicker (T ₁ > T ₂ ), it becomes more prominent. This is because the chemical solution needs to run on the aluminum film 26 in order for the chemical solution for forming the insulating film 27 to flow from the scribe region 10B to the semiconductor device region 10A, and when the aluminum film 26 is thick, the chemical solution collided at the intersection 42 described above. This is because it becomes more difficult to flow near the corner 44a of the semiconductor device region 10A. As an example, the deposition thickness T ₂ of the insulating film 27 may be, for example 3μ about, deposition thickness T ₁ of the aluminum film 26 may be, for example, 5μm about.

  FIG. 14 is a principal plan view (partial enlarged plan view) showing a part of the semiconductor substrate 11 during the manufacturing process of the semiconductor device of the first comparative example, and corresponds to FIG. 13 of the present embodiment. is there. The openings 129a and 129b, the gate pad electrode 102g, and the source pad electrode 102s in FIG. 14 correspond to the openings 29a and 29b, the gate pad electrode 2g, and the source pad electrode 2s in the present embodiment, respectively. In the first comparative example of FIG. 14, unlike the present embodiment, the gate pad electrode 102g (the opening 129a for the gate pad electrode 102g) is not arranged near the corner of the semiconductor device region 10A. The semiconductor device region 10A is disposed near the center of the side. For this reason, the formation position of the gate pad electrode 102g does not overlap the region 43a where the film thickness of the edge film 27 is thin. Therefore, the film thickness of the insulating film 27 is increased in the etching process when the opening 129a for the gate pad electrode 102g is formed. There is no influence of the thin region 43a.

  However, for example, from the viewpoint of routing of the wiring (gate wiring 26a and source wiring 26b), the viewpoint of mounting the semiconductor device, or the viewpoint of miniaturization of the semiconductor device, the semiconductor device 1 of the present embodiment, It may be preferable to arrange a pad electrode (here, the gate pad electrode 2g) in the vicinity of the corner of the surface 1a of the device 1.

  As shown in FIG. 1, the semiconductor device 1 according to the present embodiment has pad electrodes (here, source pad electrode 2s and gate pad electrode 2g) formed on the surface 1a. The electrode 2g is disposed in the vicinity of the corner 3 of the surface 1a of the semiconductor device 1. Since each semiconductor device region 10A becomes the semiconductor device 1 as described above, the semiconductor device 1 is manufactured in the vicinity of the corner (first position) 44a of the semiconductor device region 10A corresponding to the corner 3. The gate pad electrode 2g (the opening 29a for the gate pad electrode 2g) is provided. For this reason, as shown in FIG. 13, a part of the gate pad electrode 2g (the opening 29a for the gate pad electrode 2g) overlaps the region 43a where the film thickness of the insulating film 27 is thin. In this case, as described in detail below, in the region 43a where the film thickness of the insulating film 27 is thin, the amount of side etching may increase, which may cause pattern deformation of the opening 29a. In the present embodiment, the planar shape of the opening 28a of the resist pattern RP1 is devised.

  15 and 16 are main part plan views of the semiconductor device during the manufacturing process, and an enlarged view of a region corresponding to the region 46 shown in FIG. 13 is shown. FIG. 15 corresponds to the same process step (stage where the resist pattern RP1 is formed) as in FIG. 9, and FIG. 16 corresponds to the same process step as above (the insulating film 27 is etched to form openings 29a and 29b). Step). In FIG. 16, in order to make the drawing easier to see, the planar position of the opening 28a of the resist pattern RP1 is indicated by a solid line, and the planar position of the opening 29a (the bottom of the opening 29a) of the insulating film 27 is indicated by a dotted line. is there. FIGS. 17 and 18 are main part plan views of the semiconductor device of the second comparative example during the manufacturing process, and correspond to FIGS. 15 and 16 of the present embodiment, respectively. The resist pattern RP201 and its opening 228a shown in the second comparative example in FIGS. 17 and 18 correspond to the resist pattern RP1 and its opening 28a in the first embodiment, and correspond to the second pattern in FIG. The opening 229a of the insulating film 27 shown in the comparative example corresponds to the opening 29a of the insulating film 27 of the present embodiment.

  In the second comparative example of FIGS. 17 and 18, the planar shape of the opening 228a of the resist pattern RP201 is a square shape (rectangular shape). On the other hand, in the present embodiment, as shown in FIGS. 15 and 16, the planar shape of the opening 28a of the resist pattern RP1 is a planar shape in which the corner 51 where pattern deformation can occur is rounded. Yes.

  If side etching of the insulating film 27 does not occur in the etching process of the insulating film 27 (the process from FIG. 9 to FIG. 10 above), the openings 28a and 228a of the resist patterns RP1 and RP201 and the openings 29a of the insulating film 27 229a coincides with the plane. However, in the etching process of the insulating film 27, side etching of the insulating film 27 (etching in a direction parallel to the main surface of the semiconductor substrate 11) occurs. Due to the side etching, the openings 29a and 229a of the insulating film 27 and the openings 28a and 228a of the resist patterns RP1 and RP201 do not completely coincide with each other, and the opening 29a of the insulating film 27 is formed as shown in FIG. , 29b are inclined from a direction perpendicular to the main surface of the semiconductor substrate 11, and the openings 29a, 229a of the insulating film 27 are more than the openings 28a, 228a of the resist patterns RP1, RP201 as shown in FIGS. The shape spreads outward. In particular, when wet etching is used for etching the insulating film 27, the insulating film 27 is isotropically etched, so that side etching of the insulating film 27 occurs. The amount of side etching of the insulating film 27 in the etching process of the insulating film 27 depends on the film thickness of the insulating film 27 and increases as the thickness of the insulating film 27 decreases.

  In the etching process of the insulating film 27, it is necessary to reliably expose the gate wiring 26a and the source wiring 26b at the bottoms of the openings 29a and 29b, so that the insulating film 27 in the semiconductor device region 10A is matched with a thick part. Therefore, it is necessary to determine the etching amount (overetching amount) of the insulating film 27. For this reason, as shown in FIG. 13, there is a region 43a in which the insulating film 27 is partially thin in the semiconductor device region 10A, and when the openings 29a and 229a are formed in a region including the region 43a, the insulating film 27 is thin. The side etching amount locally increases only in the region 43a.

  As described above, in the semiconductor device region 10A, in the vicinity of the corner 44a of each semiconductor device region 10A, the insulating film 27 is thinner than other portions of the semiconductor device region 10A. For this reason, when the openings 29a and 229a are formed (arranged) in the vicinity of the corner 44a of the semiconductor device region 10A, the insulating film 27 is partially thin, and the insulating film 27 near the corner 44a (region 43a) The amount of side etching is locally higher than other portions.

  Accordingly, when the planar shape of the opening 228a of the resist pattern RP201 is a square shape (rectangular shape) as in the second comparative example of FIG. 17, when the insulating film 27 is etched using the resist pattern RP201 as an etching mask. As described above, the insulating film 27 is partially thin in the vicinity of the corner portion 44a (region 43a), so that the side etching amount of the insulating film 27 is more locally in the vicinity of the corner portion 251 of the opening 228a than in other portions. Become more. For this reason, as shown in FIG. 18, the shape of the opening 229a of the insulating film 27 locally deviates from the shape of the opening 228a of the resist pattern RP201 near the corner 44a of the semiconductor device region 10A. End up.

  As a result, pattern deformation occurs in the opening 229a of the insulating film 27 (the pattern of the opening 229a of the insulating film 27 is deformed from the pattern of the opening 228a of the resist pattern RP201). That is, in the opening 229a formed in the insulating film 27, as shown in FIG. 18, the portion closest to the corner 44a of the semiconductor device region 10A (the portion corresponding to the corner 251) is locally formed from the rectangular pattern. It becomes the shape which was expanded. This reduces the alignment margin of the opening 229a with respect to the aluminum film 26 (here, the gate wiring 26a). In order to cope with this, it is conceivable to make the film thickness distribution of the insulating film 27 uniform in the semiconductor device region 10A. However, it is difficult to make the film thickness distribution uniform by the spin coating film forming method.

  Further, when the locally expanded portion of the opening 229a is detached from the aluminum film 26 (here, the gate wiring 26a) and the side surface of the aluminum 26 is exposed from the opening 229a of the insulating film 27, the following is performed. Problems can arise. For example, an increase in leakage current due to a decrease in moisture resistance (moisture can easily enter), a bonding wire connection failure with respect to the pad electrode (here, the gate pad electrode 2g), or on the pad electrode (here, the gate pad electrode 2g) For example, a bump formation failure at the time of bump electrode formation. Therefore, the width of the aluminum film 26 at the position where the pad electrode is to be formed is further increased in order to prevent the locally expanded portion of the opening 229a from being detached from the aluminum film 26 (here, the gate wiring 26a). However, this is disadvantageous for miniaturization of the semiconductor device.

  As described above, the insulating film 27 is locally thinned in the semiconductor device region 10A in the vicinity of the corner 44a (the region 43a). For this reason, in this embodiment, the pad electrode opening (here, the opening 29a for the gate pad electrode 2g) is formed (placed) in the vicinity of the corner 44a of the semiconductor device region 10A. The layout (planar shape) of the opening 28a of the resist pattern RP1 for forming the opening 29a provided in the vicinity of 44a is preliminarily considered in consideration of pattern deformation caused by the locally thin film thickness of the insulating film 27. Make corrections.

  That is, in this embodiment, as shown in FIGS. 15 and 16, the planar shape of the opening 28a of the resist pattern RP1 is the same as the opening 228a of the resist pattern RP201 of the second comparative example of FIGS. A rectangular shape (rectangular shape) similar to the above is used as a base (reference, basic), but a corner portion 51 (a portion corresponding to the corner portion 251 of the second comparative example in FIGS. 17 and 18) where pattern deformation may occur. The flat shape is rounded. As a result, the planar shape of the opening 28a of the resist pattern RP1 is such that the portion closest to the corner 44a of the semiconductor device region 10A (here, the corner 51 of the opening 28a) is retreated in a direction away from the corner 44a. It has a different shape.

  Also in the present embodiment, when the insulating film 27 is etched using the resist pattern RP1 as an etching mask, the insulating film 27 is partially thin in the vicinity of the corner 44a (the region 43a) as described above. In the vicinity of the corner 51 of 28a, the side etching amount of the insulating film 27 can be locally larger than the other portions. Therefore, also in the present embodiment, the shape of the opening 29a of the insulating film 27 locally deviates from the shape of the opening 28a of the resist pattern RP1 near the corner portion 44a of the semiconductor device region 10A (pattern). Deformation).

  However, in the present embodiment, as shown in FIG. 15, the corner 51 that can increase the side etching amount is rounded with respect to the planar shape of the opening 28a of the resist pattern RP1. For this reason, as shown in FIG. 16, the shape of the opening 29a of the insulating film 27 is locally larger than the shape of the opening 28a of the resist pattern RP1 in the vicinity of the corner 44a (the region 43a) of the semiconductor device region 10A. However, the planar shape of the finally formed opening 29a is a pattern having a substantially rectangular shape (rectangular shape) or a shape close thereto.

  That is, in the present embodiment, the planar shape (planar layout) of the opening 28a of the resist pattern RP1 is shown in FIGS. 15 and 16 in consideration of the non-uniformity of the side etching amount due to the non-uniformity of the insulating film 27. As shown, the portion closest to the corner portion 44a of the semiconductor device region 10A (here, the corner portion 51 of the opening portion 28a) is shaped to recede in a direction away from the corner portion 44a. As a result, the portion where the side etching amount can locally increase (here, the corner portion 51 of the opening 28a) is retreated in a direction away from the corner portion 44a of the semiconductor device region 10A by the amount of increase in the side etching. . For this reason, the planar shape of the opening 29a of the insulating film 27 formed in the present embodiment is the pattern of the opening 228a of the resist pattern RP201 of the second comparative example as shown in FIG. Pattern), and when the insulating film 27 in the semiconductor device region 10A has a uniform thickness and the side etching amount of the insulating film 27 is uniform, the planar shape can be made substantially the same. .

  Therefore, in the present embodiment, even if the non-uniformity of the film thickness of the insulating film 27 in the semiconductor device region 10A (a phenomenon in which the insulating film 27 is locally thinned in the vicinity of the corner portion 44a) occurs, no adverse effect occurs. The opening 29a (particularly the portion corresponding to the corner 51 of the opening 28a) is separated from the aluminum film 26 (here, the gate wiring 26a) (the side surface of the aluminum film 26 is exposed from the opening 29a of the insulating film 27). Can be prevented). Further, the alignment margin of the opening 29a with respect to the aluminum film 26 (here, the gate wiring 26a) can be improved. For this reason, the manufacturing yield of the semiconductor device can be improved.

  As described above, in this embodiment, the non-uniformity of the film thickness of the insulating film 27 in the semiconductor device region 10A (a phenomenon in which the insulating film 27 is locally thinned in the vicinity of the corner portion 44a) can be accepted. Management of the film forming process 27 is facilitated. Further, the insulating film 27 can be formed by a spin coating method in which film thickness non-uniformity easily occurs, and a polyimide resin film suitable as a surface protective film can be easily formed as the insulating film 27. be able to.

  Further, in the present embodiment, the opening 29a of the insulating film 27 can be prevented from coming off from the aluminum film 26 (here, the gate wiring 26a) (the side surface of the aluminum 26 is exposed from the opening 29a of the insulating film 27). Therefore, the moisture resistance can be improved to reduce the leak current, the connection reliability of the bonding wire to the pad electrode can be improved, and the bump formation failure when the bump electrode is formed on the pad electrode can be prevented. In addition, the opening 29a can be prevented from being detached from the aluminum film 26 (here, the gate wiring 26a) without increasing the width of the aluminum film 26 at the position where the pad electrode is to be formed, which is advantageous for downsizing of the semiconductor device. Become.

  In FIG. 15 and FIG. 16, the planar shape of the opening 28a of the resist pattern RP1 is a planar shape with rounded corners 51 where pattern deformation can occur, but the planar shape of the opening 28a of the resist pattern RP1. However, the present invention is not limited to this, and can be changed according to the film thickness distribution of the insulating film 27. For example, the shape shown in FIGS. 19 and 20 are plan views showing modifications of the planar layout of the opening 28a of the resist pattern RP1 of the present embodiment, and correspond to FIGS. 15 and 16, respectively.

  That is, in FIGS. 19 and 20, the planar shape of the opening 28a of the resist pattern RP1 has a rectangular shape (rectangular shape) similar to the planar shape of the opening 228a of the resist pattern RP201 of the second comparative example of FIG. Base (standard, basic). In FIGS. 19 and 20, two sides in contact with the corner 51 (the portion corresponding to the corner 251 of the second comparative example in FIGS. 17 and 18) where pattern deformation may occur are in the vicinity of the corner 51. The semiconductor device region 10A has a shape that is retracted in a direction away from the corner 44a.

  19 and 20, as in the case of FIGS. 15 and 16, the shape of the opening 29a of the insulating film 27 is locally in the vicinity of the corner 44a of the semiconductor device region 10A. Even if the shape of the opening 28a is larger than that of the opening 28a, the opening 29a can be prevented from coming off the aluminum film 26 (the side surface of the aluminum 26 is not exposed from the opening 29a of the insulating film 27).

  15 and 16, the planar shape of the opening 28a of the resist pattern RP1 is a planar shape in which only the corner 51 where the pattern deformation can occur is rounded, and the other corner 51a is rounded. Without holding it, the square (rectangular) corners (substantially perpendicular corners) of the base were kept. On the other hand, as shown in FIGS. 21 and 22, the planar shape of the opening 28a of the resist pattern RP1 is not limited to the corner 51 where pattern deformation can occur, but other corners 51a (4 in FIGS. 21 and 22). It is also possible to have a planar shape with roundness for all the corners). FIGS. 21 and 22 are plan views showing other variations of the planar layout of the opening 28a of the resist pattern RP1 of the present embodiment, and correspond to FIGS. 15 and 16, respectively.

  In the case of FIGS. 21 and 22, as in the case of FIGS. 15 and 16, the shape of the opening 29a of the insulating film 27 is locally the vicinity of the corner 44a of the semiconductor device region 10A. Even if the shape of the opening 28a is larger than that of the opening 28a, the opening 29a can be prevented from coming off the aluminum film 26 (the side surface of the aluminum 26 is not exposed from the opening 29a of the insulating film 27).

  However, in the case of FIGS. 21 and 22, since the corner 51a other than the corner 51 of the opening 28a of the resist pattern RP1 is also rounded, the planar shape of the opening 29a of the insulating film 27 to be formed is As shown in FIG. 22, the corners are rounded.

  As described above, in the present embodiment, the planar shape (planar layout) of the opening 28a of the resist pattern RP1 in consideration of the nonuniformity of the side etching amount due to the nonuniformity of the insulating film 27 is shown in FIGS. 19 or 21, the portion closest to the corner 44 a of the semiconductor device region 10 </ b> A (here, the corner 51 of the opening 28 a) is retreated in a direction away from the corner 44 a. It is. As a result, even if non-uniformity of the film thickness of the insulating film 27 in the semiconductor device region 10A (a phenomenon in which the insulating film 27 is locally thinned in the vicinity of the corner portion 44a) occurs, no adverse effect occurs, and the opening 29a is formed. It is possible to prevent the aluminum film 26 (here, the gate wiring 26a) from coming off. Therefore, the alignment margin of the opening 29a with respect to the aluminum film 26 (here, the gate wiring 26a) can be improved, and the manufacturing yield of the semiconductor device can be improved.

  Further, the position or direction of the semiconductor device region 10A or the semiconductor device 1 is recognized in various manufacturing processes of the semiconductor device 1 after the opening 29a is formed or a package or electronic device assembly process using the manufactured semiconductor device 1. In some cases, straight portions of the pad electrode openings 29a and 29b are used. In this case, the position or direction of the opening 29a for the pad electrode (here, the gate pad electrode 2g) is easier to recognize when the opening 29a has a shape close to a square shape (rectangular shape). Therefore, as shown in FIG. 21, the corner 51a other than the corner 51 closest to the corner 44a of the semiconductor device region 10A is deformed with respect to the corner of the opening 28a of the resist pattern RP1 as shown in FIG. As shown in FIG. 19, the opening 29 a formed in the insulating film 27 is formed by deforming only the corner 51 closest to the corner 44 a of the semiconductor device region 10 </ b> A (retracting in the direction away from the corner 44 a). The shape is close to a square shape (rectangular shape). Therefore, as shown in FIG. 15 and FIG. 19, when only the corner 51 closest to the corner 44a of the semiconductor device region 10A is deformed, the position or direction of the semiconductor device region 10A or the semiconductor device 1 in various steps. Is more preferable because it is easy to recognize.

  The present embodiment is not limited to the manufacturing process of the semiconductor device in which the trench gate type MISFET is formed on the semiconductor substrate 11, but also to the manufacturing process of the semiconductor device in which various other semiconductor elements are formed on the semiconductor substrate. Can be applied. However, in the case of a semiconductor device in which a trench gate type MISFET is formed, the thickness of the conductor film for forming the pad electrode (here, the aluminum film 26) is increased, and the surface protective film (here, in the semiconductor device region 10A) is increased. Then, since the non-uniformity of the thickness of the insulating film 27) is likely to occur, the effect of applying this embodiment (the present invention) is great.

  Further, the non-uniformity of the film thickness of the surface protective film (here, the insulating film 27) in the semiconductor device region 10A as described above (a phenomenon in which the film is locally thinned in the vicinity of the corner portion 44a) 27) is likely to occur when formed by spin coating. Therefore, if the present embodiment (the present invention) is applied when the surface protective film (insulating film 27) is formed by the spin coating method, the effect is greater.

  Further, as described above, the insulating film 27 is locally thinned in the semiconductor device region 10A in the vicinity of the corner portion, and the film thickness of the insulating film 27 tends to be almost uniform in the region away from the corner portion. . For this reason, the pad electrode opening (opening of the insulating film 27) formed (arranged) in a region away from the corner of the semiconductor device region 10A is as shown in FIG. 15, FIG. 19, or FIG. It is preferable to make a square shape (rectangular shape) without performing correction. In this embodiment, the opening 29a is formed with respect to the pad electrode opening (here, the opening 29a for the gate pad electrode 2g) formed (arranged) in the vicinity of the corner 44a of the semiconductor device region 10A. The opening 28a of the resist pattern RP1 for formation is corrected as shown in FIG. 15, FIG. 19, or FIG.

Further, in the semiconductor device region 10A, the insulating film 27 tends to be thin in the vicinity of the corner portion 44a of the semiconductor device region 10A, particularly in the region within about 100 μm from the corner portion 44a of the semiconductor device region 10A. It is. Therefore, when this embodiment (the present invention) is applied to the case where even a part of the pad electrode opening (here, the opening 29a) is within 100 μm from the corner 44a of the semiconductor device region 10A, More effective. In this case, in the manufactured semiconductor device 1, the distance D ₁ from the corner 3 of the semiconductor device 1 shown in FIG. 1 to the pad electrode (here, the gate pad electrode 2 g) is 100 μm or less (D ₁ ≦ 100 μm). Become. Therefore, when manufacturing the semiconductor device 1 in which the distance D ₁ from the corner 3 of the semiconductor device 1 to the pad electrode (here, the gate pad electrode 2g) is 100 μm or less (D ₁ ≦ 100 μm), If the form (the present invention) is applied, the effect is greater.

  In addition, a plurality of semiconductor device regions 10A are formed on the semiconductor substrate (semiconductor wafer) 11. However, in consideration of ease of manufacturing, the patterns are arranged in the same direction with respect to the plurality of semiconductor device regions 10A of the semiconductor substrate 11. (Semiconductor element pattern, insulating film pattern, wiring pattern, opening pattern, etc.) are formed. Therefore, as shown in FIG. 12, the plurality of semiconductor device regions 10 </ b> A of the semiconductor substrate 11 have pad electrode openings in the vicinity of the corners 44 a on the side facing the center of the main surface of the semiconductor substrate 11. (Here, the opening 29a of the gate pad electrode 2g) and the opening for the pad electrode (here, the opening of the gate pad electrode 2g) in the vicinity of the other corners (including the corner 44b). 29a) will be mixed.

  However, when the pad electrode opening 29a is formed in the vicinity of the corner of the semiconductor device region 10A, the problem that the opening 29a may be detached from the aluminum film 26 due to an increase in the side etching amount may occur. This is a case where the film thickness of the insulating film 27 is locally thinned in the region to be formed. When the film thickness of the insulating film 27 is uniform in the region where the opening 29a is to be formed, or when the film thickness of the insulating film 27 is locally thick, the amount of side etching is appropriate or small. There is no problem that the opening 29a is detached from the aluminum film 26.

  For this reason, in the semiconductor device region 10A of the semiconductor substrate 11, when the pad electrode openings 29a are formed in the vicinity of the corners of the semiconductor device region 10A, the corners are the four corners of the semiconductor device region 10A. In any case, it is preferable to apply this embodiment. That is, when the pad electrode opening 29a is formed in the vicinity of an arbitrary one of the four corners of the semiconductor device region 10A, the opening 28a of the resist pattern RP1 for forming the opening 29a. Is corrected as shown in FIG. 15, FIG. 19, or FIG. Accordingly, when a plurality of semiconductor devices 1 are manufactured from one semiconductor substrate 11, the pad electrode opening 29 a can be prevented from being detached from the aluminum film 26 in any of the semiconductor devices 1. For this reason, the manufacturing yield of the semiconductor device 1 can be improved.

In the semiconductor device 1 shown in FIG. 1, while the gate pad electrode 2 g (opening 29a for) near the corner portion 3 is disposed (the distance D ₁ is the position to be 100μm or less), The source pad electrode 2s (opening 29b for use) is disposed relatively far from the corners 3a and 3b of the surface 1a (a distance longer than 100 μm). Therefore, the opening 28a of the resist pattern RP1 for forming the opening 29a for the gate pad electrode 2g is corrected as shown in FIG. 15, FIG. 19, or FIG. 21, but the source pad electrode 2s. The opening 28b of the resist pattern RP1 for forming the opening 29b for use can be made to have a quadrangular shape (rectangular shape) without performing such correction.

However, when at least one of the distances D ₂ and D ₃ from the corners 3a and 3b of the semiconductor device 1 shown in FIG. 1 to the source pad electrode 2s is 100 μm or less (D ₂ ≦ 100 μm or D ₃ ≦ 100 μm). It is preferable that the planar shape of the opening 28b of the resist pattern RP1 is corrected in substantially the same manner as that performed on the opening 28a. That is, in this case, the planar shape of the opening 28b of the resist pattern RP1 is the portion closest to the corner of the semiconductor device region 10A (here, the portion corresponding to the corner 51 of the opening 28b). It is preferable to make the shape retreated in the direction away from the corner. For example, the planar shape of the opening 28b of the resist pattern RP1 can be set to a planar shape substantially similar to the planar shape of the opening 28a shown in FIG. 15, FIG. 19, or FIG. As a result, even if the insulating film 27 is thinly formed near the corner of the semiconductor device region 10A, the opening 29b for the source pad electrode 2s is formed as in the case of the opening 29a for the gate pad electrode 2g. It is possible to prevent disconnection from the source wiring 26b.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The present invention is effective when applied to a method of manufacturing a semiconductor device having a pad electrode.

It is a top view of the semiconductor device which is one embodiment of the present invention. It is a bottom view of the semiconductor device which is one embodiment of the present invention. It is sectional drawing in the manufacturing process of the semiconductor device of one embodiment of this invention. FIG. 4 is a cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 3; FIG. 5 is a cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 4; FIG. 6 is a cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 5; FIG. 7 is a cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 6; FIG. 8 is a cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 7; FIG. 9 is a cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 8; FIG. 10 is a cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 9; FIG. 11 is a cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 10; It is a top view which shows the whole semiconductor substrate in the manufacturing process of a semiconductor device. It is a principal part top view which shows a part of semiconductor substrate in the manufacturing process of the semiconductor device of one embodiment of this invention. It is a principal part top view which shows a part of semiconductor substrate in the manufacturing process of the semiconductor device of a 1st comparative example. It is a principal part top view in the manufacturing process of the semiconductor device of one embodiment of this invention. It is a principal part top view in the manufacturing process of the semiconductor device of one embodiment of this invention. It is a principal part top view in the manufacturing process of the semiconductor device of the 2nd comparative example. It is a principal part top view in the manufacturing process of the semiconductor device of the 2nd comparative example. It is a principal part top view which shows the modification of the plane layout of the opening part of a resist pattern. It is a principal part top view when it etches using the resist pattern of FIG. It is a principal part top view which shows the other modification of the plane layout of the opening part of a resist pattern. It is a principal part top view when it etches using the resist pattern of FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor device 1a Front surface 1b Back surface 2d Back surface drain electrode 2g, 102g Gate pad electrode 2s, 102s Source pad electrode 3, 3a, 3b Corner | angular part 10A Semiconductor device area | region 10B Scribe area | region 11 Semiconductor substrate 11a Semiconductor substrate 11b Epitaxial layer 12 Insulating film 13 p-type well 14 gate trench 15 gate insulating film 16 gate portion 16a gate wiring portion 17 channel region 18 source region 22 insulating film 23 contact hole 24 through hole 25 hole 26 aluminum film 26a gate wiring 26b source wiring 27 insulating films 28a and 28b Openings 29a, 29b Openings 31 Drain electrodes 41a, 41b Arrows 42 Intersections 43a, 43b Regions 44a, 44b Corners 51, 51a, 251 Corners 129a, 129b Openings 228a, 229a Open Part RP1, RP201 resist pattern

Claims (5)

A method for manufacturing a semiconductor device having a first pad electrode disposed in the vicinity of a first corner of a main surface,
(A) a step of preparing a semiconductor substrate;
(B) forming a first conductor layer for forming the first pad electrode on the first main surface of the semiconductor substrate;
(C) forming a first insulating film on the first main surface of the semiconductor substrate so as to cover the first conductor layer;
(D) forming a resist pattern having a first opening on the first insulating film;
(E) forming a second opening in the first insulating film by etching the first insulating film exposed from the first opening using the resist pattern as an etching mask; Forming the first pad electrode by exposing the first conductor layer at the bottom;
Have
In the planar shape of the first opening of the resist pattern formed in the step (d), a portion closest to the first position of the semiconductor substrate corresponding to the first corner is defined as the first position. A method for manufacturing a semiconductor device, wherein the semiconductor device has a shape retreated in a direction away from the semiconductor device. In the manufacturing method of the semiconductor device according to claim 1,
The planar shape of the first opening of the resist pattern formed in the step (d) is based on a rectangular opening pattern, and the corner closest to the first position in the rectangular opening pattern. A method of manufacturing a semiconductor device, wherein the portion is deformed so as to recede in a direction away from the first position. In the manufacturing method of the semiconductor device according to claim 1,
In the step (c), the first insulating film is formed by a spin coating method. In the manufacturing method of the semiconductor device according to claim 1,
A method of manufacturing a semiconductor device, wherein a distance from the first corner portion to the first pad electrode is 100 μm or less. In the manufacturing method of the semiconductor device according to claim 1,
The method of manufacturing a semiconductor device, wherein the first conductor layer is a conductor layer mainly composed of aluminum, and the first insulating film is a polyimide resin film.

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