JP2008140400A - Electronic tag and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To thin a noncontact type electronic tag, and to improve its reliability. <P>SOLUTION: An inlet 1 for the electronic tag is equipped with an antenna 3 comprising Cu foil stuck on one surface of a rectangular insulating film 2 comprising a polyimide resin film, and a semiconductor chip 5 connected to the antenna 3. A slit 7 whose one end reaches the fringe of the antenna 3 is formed approximately at the center of the antenna 3. Au bumps 9a, 9b and dummy Au bumps 9c, 9d constituting circuit terminals are formed on the main surface of the semiconductor chip 5, and the four Au bumps 9a, 9b, 9c and 9d are connected to a lead 10 formed integrally with the antenna 3. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a non-contact type electronic tag and a manufacturing technique thereof, and more particularly, to a technique effective when applied to thinning and high reliability of an electronic tag.

  A non-contact type electronic tag is a tag in which desired data is stored in a memory circuit in a semiconductor chip and this data is read using a microwave.

Japanese Patent Laid-Open No. 10-13296 (Patent Document 1) discloses an example of this type of non-contact type electronic tag. This electronic tag has a structure in which a microwave receiving antenna is constituted by a lead frame, and a semiconductor chip mounted on the lead frame is sealed with resin.
Japanese Patent Laid-Open No. 10-13296

  Since the electronic tag stores data in a memory circuit in the semiconductor chip, there is an advantage that a large amount of data can be stored as compared with a tag using a barcode. In addition, the data stored in the memory circuit has an advantage that unauthorized tampering is difficult as compared with the data stored in the barcode.

  However, since this type of electronic tag has a more complicated structure than a tag using a barcode or the like, its manufacturing cost is high, which is one factor hindering the spread of the electronic tag.

  Accordingly, the present inventor has been developing an inexpensive electronic tag inlet having a simplified structure. This inlet has a structure in which a semiconductor chip is mounted on an antenna constituted by a lead frame, the antenna and the semiconductor chip are electrically connected by an Au wire, and the semiconductor chip and the Au wire are sealed with a potting resin.

  However, since the inlet connects the antenna composed of the lead frame and the semiconductor chip with an Au wire, if the semiconductor chip and the Au wire are sealed with potting resin, the thickness of the entire inlet increases to about 0.6 mm. As a result, there arises a problem that the thinning required for the inlet for the electronic tag cannot be realized and a problem that it is difficult to obtain sufficient flexibility against bending deformation of the antenna portion.

  An object of the present invention is to provide a technique capable of realizing thinning and high reliability of an electronic tag.

  Another object of the present invention is to provide a technology capable of realizing a low-priced electronic tag that is thin and highly flexible.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.
(1) The electronic tag of the present invention comprises a main surface, a back surface opposite to the main surface, an insulating film having a device hole reaching the back surface from the main surface, and a conductor layer. An antenna affixed to the main surface of the insulating film such that the back surface is opposite to the main surface of the insulating film, and is located inside the device hole. A semiconductor chip mounted on the back surface of the antenna via a plurality of bump electrodes, and a resin for sealing the semiconductor chip and the plurality of bump electrodes.
(2) The electronic tag manufacturing method of the present invention includes the following steps.
(A) preparing an insulating film having a main surface, a back surface opposite to the main surface, and a device hole reaching the back surface from the main surface;
(B) a step of preparing an antenna comprising a conductor layer and having a main surface, a back surface opposite to the main surface, and a slit reaching the back surface from the main surface;
(C) a step of attaching the antenna to the main surface of the insulating film such that the back surface of the antenna faces the main surface of the insulating film;
(D) supplying a semiconductor chip to the inside of the device hole from the back surface side of the insulating film, and mounting the semiconductor chip on the back surface of the antenna via a plurality of bump electrodes;
(E) A step of supplying a resin from the main surface side of the antenna through the slit of the antenna to seal the semiconductor chip and the plurality of bump electrodes.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  According to one embodiment of the present invention, a thin electronic tag with high bending strength can be realized at a low price.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

  FIG. 1 is a plan view (front side) showing an electronic tag inlet of this embodiment, FIG. 2 is a plan view showing a part of FIG. 1 in an enlarged manner, and FIG. 3 is an electronic tag inlet of this embodiment. FIG. 4 is a plan view (back side) showing the electronic tag inlet of the present embodiment, and FIG. 5 is an enlarged plan view showing a part of FIG.

  An electronic tag inlet (hereinafter simply referred to as an inlet) 1 of the present embodiment constitutes a main part of a non-contact type electronic tag provided with an antenna for receiving microwaves. The inlet 1 includes an antenna 3 made of a Cu foil adhered to one surface of an elongated rectangular insulating film 2 and a semiconductor chip 5 connected to the antenna 3 with the surface and side surfaces sealed with a potting resin 4. I have. A cover film 6 for protecting the antenna 3 and the semiconductor chip 5 is laminated on one surface of the insulating film 2 (surface on which the antenna 3 is formed) as necessary.

  The length of the antenna 3 along the long side direction of the insulating film 2 is, for example, 56 mm, and is optimized so that microwaves with a frequency of 2.45 GHz can be received efficiently. Further, the width of the antenna 3 is 3 mm, and the antenna 3 is optimized so that both the downsizing of the inlet 1 and the securing of strength can be achieved.

  An “L” -shaped slit 7 whose one end reaches the outer edge of the antenna 3 is formed at the substantially central portion of the antenna 3, and a semiconductor sealed with a potting resin 4 in the middle of the slit 7. Chip 5 is mounted.

  6 and 7 are enlarged plan views showing the vicinity of the central portion of the antenna 3 in which the slit 7 is formed. FIG. 6 shows the front side of the inlet 1 and FIG. 7 shows the back side. In these drawings, illustration of the potting resin 4 and the cover film 6 for sealing the semiconductor chip 5 is omitted.

  As shown in the figure, a device hole 8 formed by punching out a part of the insulating film 2 is formed in the middle of the slit 7, and the semiconductor chip 5 is disposed at the center of the device hole 8. Yes. The size of the device hole 8 is, for example, length × width = 0.8 mm × 0.8 mm, and the size of the semiconductor chip 5 is length × width = 0.48 mm × 0.48 mm.

  As shown in FIG. 6, on the main surface of the semiconductor chip 5, for example, four Au bumps 9a, 9b, 9c, 9d are formed. Each of the Au bumps 9 a, 9 b, 9 c, 9 d is connected to a lead 10 that is formed integrally with the antenna 3 and has one end extending inside the device hole 8.

  Of the four leads 10, two leads 10 extend from one of the antennas 3 divided into two by the slit 7 to the inside of the device hole 8 and are electrically connected to the Au bumps 9 a and 9 c of the semiconductor chip 5. It is connected to the. The remaining two leads 10 extend from the other side of the antenna 3 to the inside of the device hole 8 and are electrically connected to the Au bumps 9 b and 9 d of the semiconductor chip 5.

  FIG. 8 is a plan view showing a layout of four Au bumps 9a, 9b, 9c, 9d formed on the main surface of the semiconductor chip 5, FIG. 9 is an enlarged sectional view in the vicinity of the Au bump 9a, and FIG. FIG. 11 is an enlarged cross-sectional view in the vicinity of the Au bump 9 c, and FIG. 11 is a block diagram of a circuit formed on the semiconductor chip 5.

  The semiconductor chip 5 is composed of a single crystal silicon substrate having a thickness of about 0.15 mm, and a circuit composed of rectification / transmission, clock extraction, selector, counter, ROM, etc. as shown in FIG. 11 is formed on the main surface. Has been. The ROM has a storage capacity of 128 bits and can store a large amount of data compared to a storage medium such as a barcode. In addition, the data stored in the ROM has an advantage that unauthorized tampering is difficult as compared with the data stored in the barcode.

  Four Au bumps 9a, 9b, 9c and 9d are formed on the main surface of the semiconductor chip 5 on which the circuit is formed. These four Au bumps 9a, 9b, 9c, 9d are located on a pair of virtual diagonal lines indicated by a two-dot chain line in FIG. 8, and the intersection of these diagonal lines (the center of the main surface of the semiconductor chip 5). It is laid out so that the distance from is almost equal. These Au bumps 9a, 9b, 9c, and 9d are formed using, for example, a well-known electrolytic plating method, and the height thereof is, for example, about 15 μm.

  The layout of these Au bumps 9a, 9b, 9c, and 9d is not limited to the layout shown in FIG. 8, but is preferably a layout that easily balances the weight at the time of chip connection. It is preferable that the polygon formed by the tangent line of the Au bump in the planar layout is arranged so as to surround the center of the chip.

  Of the four Au bumps 9a, 9b, 9c, 9d, for example, the Au bump 9a constitutes an input terminal of the circuit shown in FIG. 11, and the Au bump 9b constitutes a GND terminal. The remaining two Au bumps 9c and 9d constitute dummy bumps not connected to the circuit.

  As shown in FIG. 9, the Au bump 9a constituting the input terminal of the circuit is formed on the uppermost metal wiring 22 exposed by etching the passivation film 20 covering the main surface of the semiconductor chip 5 and the polyimide resin 21. Is formed. In addition, a barrier metal film 23 is formed between the Au bump 9a and the uppermost metal wiring 22 to increase the adhesion between them. The passivation film 20 is composed of, for example, a laminated film of a silicon oxide film and a silicon nitride film, and the uppermost metal wiring 22 is composed of, for example, an Al alloy film. Further, the barrier metal film 23 is composed of a laminated film of, for example, a Ti film having a high adhesion to an Al alloy film and a Pd film having a high adhesion to the Au bump 9a. Although illustration is omitted, the connection part between the Au bump 9b and the uppermost metal wiring 22 constituting the GND terminal of the circuit has the same configuration as described above. On the other hand, as shown in FIG. 10, Au bumps 9c (and 9d) constituting dummy bumps are connected to a metal layer 24 formed in the same wiring layer as the uppermost metal wiring 22, but this metal Layer 24 is not connected to the circuit.

  As described above, the inlet 1 of the present embodiment is provided with a slit 7 having one end reaching the outer edge of the antenna 3 in a part of the antenna 3 formed on one surface of the insulating film 2, and divided into two by the slit 7. The input terminal (Au bump 9a) of the semiconductor chip 5 is connected to one side of the antenna 3, and the GND terminal (Au bump 9b) of the semiconductor chip 5 is connected to the other side. With this configuration, since the effective length of the antenna 3 can be increased, the inlet 1 can be reduced in size while ensuring the necessary antenna length.

  Further, the inlet 1 of the present embodiment is provided with Au bumps 9a and 9b and dummy Au bumps 9c and 9d constituting circuit terminals on the main surface of the semiconductor chip 5, and these four Au bumps 9a. , 9b, 9c, 9d are connected to the lead 10 of the antenna 3. With this configuration, the effective contact area between the Au bump and the lead 10 becomes larger than when only the two Au bumps 9a and 9b connected to the circuit are connected to the lead 10, so that the Au bump and the lead 10 The adhesive strength, that is, the connection reliability between the two is improved. Further, by arranging the four Au bumps 9a, 9b, 9c, 9d on the main surface of the semiconductor chip 5 in the layout as shown in FIG. 8, the lead 10 is provided on the Au bumps 9a, 9b, 9c, 9d. The semiconductor chip 5 does not tilt with respect to the insulating film 2 when connected. Thereby, since the semiconductor chip 5 can be reliably sealed with the potting resin 4, the manufacturing yield of the inlet 1 is improved.

  Next, the manufacturing method of the inlet 1 comprised as mentioned above is demonstrated using FIGS.

  FIG. 12 is a plan view showing the insulating film 2 used for manufacturing the inlet 1, and FIG. 13 is a plan view showing a part of FIG.

  As shown in the drawing, the insulating film 2 is carried into the manufacturing process of the inlet 1 while being wound around the reel 25. A large number of antennas 3 are formed in advance on one surface of the insulating film 2 at a predetermined interval. In order to form these antennas 3, for example, a Cu foil having a thickness of about 18 μm is bonded to one surface of the insulating film 2, and this Cu foil is etched into the shape of the antenna 3. At this time, the above-described slit 7 and lead 10 are formed in each antenna 3. Thereafter, Sn (tin) plating is applied to the surface of the lead 10. In order to form the insulating film and the antenna further thinly, for example, a first Cu film is formed on the surface of the insulating film having a thickness of about 38 μm by a sputtering method, and the first Cu film is used as a seed layer by an electrolytic plating method. A second Cu film thicker than the first Cu film may be formed, and the first and second Cu films may be patterned.

  The insulating film 2 conforms to the standard of film carrier tape, and is made of, for example, a polyimide resin film having a width of 50 μm or 70 mm and a thickness of 75 μm, and a part of the device film shown in FIGS. 8 is formed. In addition, sprocket holes 26 for conveying the insulating film 2 are formed at both sides of the insulating film 2 at a predetermined interval. The device hole 8 and the sprocket hole 26 are formed by punching a part of the insulating film 2 with a punch.

  Next, as shown in FIG. 14, the reel 25 is mounted on the inner lead bonder 30 including the bonding stage 31 and the bonding tool 32, and the antenna 3 is moved while moving the insulating film 2 along the upper surface of the bonding stage 31. The semiconductor chip 5 is connected to.

  In order to connect the semiconductor chip 5 to the antenna 3, as shown in FIG. 15 (enlarged view of the main part of FIG. 14), the semiconductor chip 5 is mounted on a bonding stage 31 heated to about 100 ° C. After positioning the device hole 8 of the insulating film 2 directly above 5, the bonding tool 32 heated to about 400 ° C. is pressed against the upper surface of the lead 10 protruding inside the device hole 8, and Au bumps (9a to 9d) And lead 10 are brought into contact with each other. At this time, by applying a predetermined load to the bonding tool 32 for about 2 seconds, an Au—Sn eutectic alloy layer is formed at the interface between the Sn plating formed on the surface of the lead 10 and the Au bumps (9a to 9d). Then, the Au bumps (9a to 9d) and the lead 10 are bonded to each other.

  Next, a new semiconductor chip 5 is mounted on the bonding stage 31. Subsequently, the insulating film 2 is moved by one pitch of the antenna 3, and then the same operation as described above is performed, whereby the semiconductor chip 5 Is connected to the antenna 3. Thereafter, the semiconductor chip 5 is connected to all the antennas 3 formed on the insulating film 2 by repeating the same operation as described above. The insulating film 2 for which the connection work between the semiconductor chip 5 and the antenna 3 has been completed is conveyed to the next resin sealing step while being wound around the reel 25.

  In order to improve the connection reliability between the Au bumps (9a to 9d) and the lead 10, the four leads 10 are extended in a direction orthogonal to the long side direction of the antenna 3 as shown in FIG. Better. As shown in FIG. 17, when the four leads 10 are extended in parallel with the long side direction of the antenna 3, when the completed inlet 1 is bent, the Au bumps (9 a to 9 d) and the leads 10 are Since a strong tensile stress acts on the joint, there is a risk that the connection reliability between the two will be reduced.

  In the resin sealing process of the semiconductor chip 5, as shown in FIGS. 18 and 19, the potting resin 4 is supplied to the upper surface and the side surface of the semiconductor chip 5 mounted inside the device hole 8 using a dispenser 33, Thereafter, the potting resin 4 is baked in a heating furnace. Although illustration is omitted, also in this resin sealing step, the potting resin 4 is supplied and baked while the insulating film 2 is moved. Then, the insulating film 2 after the resin sealing operation is completed is transported to the next inspection process in a state of being wound on the reel 25, and the connection state and appearance quality of the semiconductor chip 5 and the antenna 3 are inspected. Since a large number of antennas 3 formed on the insulating film 2 are electrically separated from each other, the continuity test between the individual antennas 3 and the semiconductor chip 5 can be easily performed. Then, the manufacturing process of the inlet 1 is completed by laminating the cover film 6 (see FIG. 3) on one surface of the insulating film 2 (surface on which the antenna 3 is formed).

  As shown in FIG. 20, the inlet 1 manufactured as described above is packed in a state of being wound around a reel 25 and shipped to a customer.

  A customer who has purchased the inlet 1 cuts the insulating film 2 to obtain an individualized inlet 1 as shown in FIGS. 1 to 5, and then combines the inlet 1 with another member. To produce an electronic tag. For example, FIG. 21 shows an example in which a double-sided adhesive tape or the like is attached to the back surface of the inlet 1 to produce an electronic tag, which is attached to the surface of an article such as a slip 34.

  According to the above-described embodiment, since the antenna 3 is configured by the thin Cu foil attached to one surface of the flexible insulating film 2, it is thinner than an inlet having an antenna based on Cu. And the inlet 1 which is rich in flexibility can be realized. Further, since the terminals (Au bumps 9a and 9b) of the semiconductor chip 5 are directly connected to the leads 10 formed integrally with the antenna 3, the method is compared with a method in which the antenna 3 and the semiconductor chip 5 are connected using bonding wires. Then, the thickness of the inlet 1 can be reduced by the amount of no wire loop.

  Further, by using the insulating film 2 in which a large number of antennas 3 are formed at predetermined intervals, the inlet 1 is manufactured, that is, the connection between the antenna 3 and the semiconductor chip 5, the resin sealing and inspection of the semiconductor chip 5, and the subsequent shipment. Can be done consistently.

  Further, since the semiconductor chip 5 is arranged in the device hole 8 of the insulating film and the lead 10 and the terminal of the semiconductor chip 5 are connected inside the device hole 8, the appearance inspection of the connecting portion between the lead 10 and the terminal is easy. In addition, it is easy to protect the connecting portion between the lead 10 and the terminal by filling the potting resin 4.

  In the embodiment, the inlet 1 is manufactured using the insulating film 2 in which the device hole 8 is formed. For example, as shown in FIG. 22, the surface of the insulating film 12 that does not have the device hole 8 is formed by the method described above. The antenna 3 and the lead 10 may be integrally formed, and the terminals (Au bumps 9 a and 9 b) of the semiconductor chip 5 may be connected to the lead 10. In this case, after connecting the lead 10 and the terminal (Au bumps 9a, 9b), as shown in FIG. 23, the gap between the lead 10 and the terminal (Au bumps 9a, 9b) is filled with the underfill resin 13.

  When the insulating film 12 as described above is used, the lead 10 and the terminals (Au bumps 9a and 9b) can be reliably connected as compared with the case where the insulating film 2 in which the device hole 8 is formed is used. The connection reliability between the two is improved, and the dummy bumps (9c, 9d) can be omitted. However, since the connection part of the lead 10 and the terminals (Au bumps 9a, 9b) cannot be visually recognized from the back surface side of the insulating film 12, a device is required for the appearance inspection method. In addition, a device for reliably filling the underfill resin 13 in a very narrow gap between the lead 10 and the terminals (Au bumps 9a and 9b) is required.

  In the above-described embodiment, the antenna 3 is configured using the Cu foil attached to the insulating film 2 made of polyimide resin. For example, the antenna 3 is formed using an Al (aluminum) foil attached to one surface of the insulating film 2. The material cost of the inlet 1 can be reduced by configuring it or by configuring the insulating film 2 with a resin (for example, polyethylene terephthalate) cheaper than the polyimide resin. When the antenna 3 is made of an Al foil, the connection between the Au bumps (9a to 9d) of the semiconductor chip 5 and the antenna 3 is preferably performed, for example, by forming an Au / Al junction using both ultrasonic waves and heating.

  The present invention can be applied to a non-contact type electronic tag.

It is a top view (surface side) which shows the inlet for electronic tags which is one embodiment of the present invention. It is a top view which expands and shows a part of FIG. It is a side view which shows the inlet for electronic tags which is one embodiment of this invention. It is a top view (back side) which shows the inlet for electronic tags which is one embodiment of the present invention. It is a top view which expands and shows a part of FIG. It is a principal part enlarged plan view (surface side) of the inlet for electronic tags which is one embodiment of this invention. It is a principal part enlarged plan view (back side) of the inlet for electronic tags which is one embodiment of this invention. It is a top view of the semiconductor chip mounted in the inlet for electronic tags which is one embodiment of this invention. FIG. 9 is a cross-sectional view of a bump electrode formed on the main surface of the semiconductor chip shown in FIG. 8 and its vicinity. FIG. 9 is a cross-sectional view of a dummy bump electrode formed on the main surface of the semiconductor chip shown in FIG. 8 and the vicinity thereof. It is a block diagram of the circuit formed in the main surface of the semiconductor chip shown in FIG. It is a top view which shows a part of elongate insulating film used for manufacture of the inlet for electronic tags which is one embodiment of this invention. It is a top view which expands and shows a part of insulating film shown in FIG. It is the schematic of the inner lead bonder which shows a part (semiconductor chip and antenna connection process) of the manufacturing process of the inlet for electronic tags which is one embodiment of this invention. It is the schematic which expands and shows the principal part of the inner lead bonder shown in FIG. It is a principal part enlarged plan view of the insulating film which shows a part (semiconductor chip and antenna connection process) of the manufacturing process of the inlet for electronic tags which is one embodiment of this invention. It is a principal part enlarged plan view of the insulating film which shows a part (semiconductor chip and antenna connection process) of the manufacturing process of the inlet for electronic tags which is one embodiment of this invention. It is the schematic which shows a part (resin sealing process of a semiconductor chip) of the manufacturing process of the inlet for electronic tags which is one embodiment of this invention. It is a principal part enlarged plan view of the insulating film which shows a part of manufacturing process of the inlet for electronic tags (resin sealing process of a semiconductor chip) which is one embodiment of this invention. It is a side view which shows the state which wound up the insulating film used for manufacture of the inlet for electronic tags which is one embodiment of this invention on the reel. It is explanatory drawing which shows the usage method of the electronic tag using the inlet for electronic tags which is one embodiment of this invention. It is a principal part expanded sectional view of the insulating film which shows a part (semiconductor chip and antenna connection process) of the manufacturing process of the inlet for electronic tags which is other embodiment of this invention. It is a principal part expanded sectional view of the insulating film which shows a part (semiconductor chip and antenna connection process) of the manufacturing process of the inlet for electronic tags which is other embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Inlet for electronic tags 2 Insulating film 3 Antenna 4 Potting resin 5 Semiconductor chip 6 Cover film 7 Slit 8 Device hole 9a, 9b Au bump 9c, 9d Dummy bump 10 Lead 12 Insulating film 13 Underfill resin 20 Passivation film 21 Polyimide resin 22 Most Upper metal wiring 23 Barrier metal film 24 Metal layer 25 Reel 26 Sprocket hole 30 Inner lead bonder 31 Bonding stage 32 Bonding tool 33 Dispenser 34 Voucher

Claims (6)

An insulating film having a main surface, a back surface opposite to the main surface, and a device hole reaching the back surface from the main surface;
An antenna made of a conductor layer, having a main surface and a back surface opposite to the main surface, the antenna being attached to the main surface of the insulating film such that the back surface faces the main surface of the insulating film; ,
A semiconductor chip mounted on the back surface of the antenna via a plurality of bump electrodes so as to be located inside the device hole;
A resin for sealing the semiconductor chip and the plurality of bump electrodes;
The electronic tag characterized by including. The antenna is formed integrally with the antenna and has a plurality of leads extending inside the device hole;
The electronic tag according to claim 1, wherein the plurality of bump electrodes are electrically connected to the plurality of leads of the antenna, respectively. The antenna has a slit;
2. The electronic tag according to claim 1, wherein the antenna is attached to the main surface of the insulating film such that the slit overlaps the device hole of the insulating film in a planar manner. An electronic tag manufacturing method including the following steps:
(A) preparing an insulating film having a main surface, a back surface opposite to the main surface, and a device hole reaching the back surface from the main surface;
(B) a step of preparing an antenna comprising a conductor layer and having a main surface, a back surface opposite to the main surface, and a slit reaching the back surface from the main surface;
(C) a step of attaching the antenna to the main surface of the insulating film so that the back surface of the antenna faces the main surface of the insulating film;
(D) supplying a semiconductor chip to the inside of the device hole from the back surface side of the insulating film, and mounting the semiconductor chip on the back surface of the antenna via a plurality of bump electrodes;
(E) A step of supplying resin from the main surface side of the antenna through the slit of the antenna to seal the semiconductor chip and the plurality of bump electrodes. The antenna is formed integrally with the antenna and has a plurality of leads extending inside the device hole;
5. The method of manufacturing an electronic tag according to claim 4, wherein in the step (d), the plurality of leads of the antenna and the plurality of bump electrodes are electrically connected to each other.   5. The electron according to claim 4, wherein, in the step (c), the antenna is attached to the main surface of the insulating film so that the slit is planarly overlapped with the device hole of the insulating film. Tag manufacturing method.

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