JP2008134838A - Bus device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To facilitate accurate fault analysis on the occurrence of a fault in a bus device or an external bus. <P>SOLUTION: A bus device 10a, connected to both an internal bus 30 and an external bus 20, includes a local register 14 for storing first data, an internal bus controller 11, a bus configuration register 15 for storing second data, a bus interface controller 13, and a data transfer controller 12. The bus device also includes a data collector 16 for collecting from the internal bus controller at least one of the access history of the internal bus controller to the internal bus, the input/output history of the first data to the local register and the input/output history of the second data to the bus configuration register, collecting from the bus interface controller the access history of the bus interface controller to the external bus and the input/output history of the second data to the bus configuration register, and then extracting the history data and outputting it to an external memory unit through the internal bus. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a bus device that facilitates failure analysis when input / output to the bus device is involved as a cause of a failure of an external bus.

 In a system that includes an external bus such as a PCI bus, it becomes clear that some trouble has occurred in the bus device or bus, and when it is necessary to investigate the cause, it is generally necessary to use an external device such as a bus analyzer or logic analyzer. The cause of the failure is analyzed by connecting the device to an external bus or by connecting an external circuit for analysis to the controller IC of the bus device. However, these analyzers are expensive. In addition, when an external circuit for analysis is used, a mounting space is required on the substrate. More importantly, failures that occur in the field environment often do not reproduce in the laboratory environment for analysis due to differences in the environment surrounding the system. In such a case, there are many cases where post-analysis using the analyzer is difficult.

 Various methods have been proposed as countermeasures against the above-described problems (analyzer is expensive, it is difficult to attach an external circuit, and it is difficult to reproduce a failure in post-mortem analysis).

 In Patent Document 1, a PCI bus trace circuit for observing a PCI bus without requiring a special measuring device is proposed. The PCI bus trace circuit includes a PCI bus analysis circuit, analyzes all transactions on the bus, and observes an error factor of the PCI bus. The detected error factor of the bus is written in the RAM in the PCI device. According to this PCI bus trace circuit, bus information can be traced without an external circuit or analyzer. In addition, by installing this circuit in a device that is actually used, fault information can be acquired immediately in the field environment.

 Patent Document 2 discloses PCI bus error information in a non-volatile memory that stores a logic circuit configuration of an FPGA in a PCI device that configures a PCI controller circuit using an FPGA (field programmable gate array). An information processing apparatus for recording has been proposed. This information processing apparatus can also solve the above-described problems.

Patent Document 3 describes a PCI device that collects data inside a PCI device based on a data collection instruction and transmits the collected data on a PCI bus. According to this PCI device, even when a failure is detected in the PCI device and setting information related to the PCI bus is lost or not set correctly, data collection in the PCI device can be reliably performed.
JP-A-11-149421 Japanese Patent No. 3553006 Japanese Patent No. 3584977

  However, in actual trouble analysis, there are many cases in which it is difficult to elucidate the cause of the failure of the external bus using only the external bus information. For example, when the system is operating without any problem until just before the failure of the external bus and a certain bus abnormality occurs suddenly, an external bus signal indicating the occurrence of an error is transmitted on the external bus by the bus device. This external bus signal is information indicating only the type of error, and is not information indicating the background and cause of the failure such as why the error has occurred. Therefore, it is difficult to analyze an error based only on the external bus signal.

  According to the conventional bus trace technology described above, it is possible to grasp in detail the operation status on the external bus side including the PCI bus, but if the failure occurs due to a factor other than the external bus side, the analysis is Have difficulty. For example, it is assumed that a bus device error occurs only when a CPU instruction is written to a register in the bus device via the internal bus and a signal reception timing on the external bus side satisfies a specific condition. In the prior art, only the bus device error information generated as a result is stored. Since the true occurrence condition of the failure depends on the timing of the write operation on the internal bus side, it is necessary to reliably record and save the information on the internal bus side when the error occurs.

  Moreover, since not only the internal bus but also a power supply and an interrupt signal can be a cause of failure, it is necessary to secure such information.

  The present invention solves the above-described problems of the prior art, and an object of the present invention is to provide a bus device that can perform failure analysis accurately and easily when a failure occurs in a bus device or an external bus.

  In order to solve the above problems, the bus device according to the present invention is a bus device connected to an internal bus and an external bus, and is a first storage means for storing first data. An internal bus control unit for controlling access to the internal bus and controlling input / output of the first data to / from the first storage unit of the internal bus; and a second storage unit for storing second data; A bus interface control unit that controls access to the external bus and controls input / output of second data to / from the second storage unit of the external bus or the internal bus; the internal bus control unit; and the bus interface control unit A data transfer control unit that controls the transfer process of the second data by relaying, and an access history of the internal bus control unit with respect to the internal bus Collecting at least one of the input / output history of the first data to the first storage means and the input / output history of the second data to the second storage means from the internal bus control unit, and the bus interface to the external bus The access history of the control unit and the input / output history of the second data with respect to the second storage means are collected from the bus interface control unit, and the history data based on each collected history is extracted and externally transmitted via the internal bus. And a data collection unit for outputting to the storage device.

  According to a second aspect of the present invention, in the first aspect, the data collection unit is connected to the external bus, is connected to the first bus for collecting information on the external bus, and is connected to the internal bus. And a second interface for collecting bus information.

  According to a third aspect of the present invention, in the first or second aspect, when the bus interface control unit detects an error signal defined in the specification of the external bus during communication with the external bus, the type of error And a first warning signal indicating information relating to the timing of error occurrence to the data collection unit, and the data collection unit outputs the error occurrence timing from each history collected based on the first warning signal. The historical data is extracted.

  According to a fourth aspect of the present invention, there is provided a bus device connected to the internal bus and the external bus, the first storage means for storing the first data, access to the internal bus, and control of the internal bus. An internal bus control unit that controls input / output of the first data to / from the first storage unit; a second storage unit that stores second data; and an access to the external bus, and the external bus or the internal Data for controlling a transfer process of the second data by relaying a bus interface control unit that controls input / output of second data to / from the second storage unit of the bus, and the internal bus control unit and the bus interface control unit A transfer control unit, an access history of the internal bus control unit with respect to the internal bus, an input / output history of first data with respect to the first storage unit, and A controller tracer that collects and holds at least one of input / output histories of second data for the second storage means from the internal bus control unit, an access history of the bus interface control unit for the external bus, and the second storage Data collection for extracting and collecting history data based on each history held by the controller tracer and the bus tracer, and a bus tracer for collecting and holding the input / output history of the second data for the means from the bus interface control unit And a control unit.

  According to a fifth aspect of the present invention, in the fourth aspect, at least one of the controller tracer and the bus tracer holds a trace unit that collects the histories and a caution pattern that indicates an access pattern in a specific order. And a pattern matching unit that matches the history collected by the trace unit with the pattern requiring attention. The pattern matching unit includes the history collected by the trace unit and A second warning signal is output to the data collection control unit when the caution pattern is matched.

  According to a sixth aspect of the present invention, in the fourth or fifth aspect, when the bus interface control unit detects an error signal defined in the specifications of the external bus during communication with the external bus, the type of error And a third warning signal indicating information relating to the timing of error occurrence is output to the data collection control unit via the bus tracer.

  A seventh aspect of the present invention provides the bus tracer according to any one of the fourth to sixth aspects, wherein the bus tracer includes a bus tracer-dedicated interface connected to the external bus and collecting information on the external bus. It is characterized by.

  According to an eighth aspect of the present invention, in any one of the fourth to seventh aspects, the controller tracer includes a controller tracer dedicated interface connected to the internal bus and collecting information of the internal bus. It is characterized by.

  The invention according to claim 9 is the power tracer according to any one of claims 4 to 8, wherein the power tracer that collects and holds the power supply state from the power supply unit of the system on which the bus device is mounted to the bus device. Further, the data collection control unit further extracts and collects power data based on a power supply state held by the power tracer.

  A tenth aspect of the present invention is the data collection method according to any one of the fourth to ninth aspects, further comprising an I / O tracer that collects and holds an interrupt signal in a system in which the bus device is mounted. The control unit further extracts and collects interrupt signal data based on the interrupt signal held by the I / O tracer.

  The invention according to claim 11 is the data acquisition control unit according to any one of claims 6 to 10, wherein the data collection control unit extracts at least one of the history data, the power supply data, and the interrupt signal data. When collecting, data is extracted based on at least one of the second warning signal and the third warning signal.

  According to a twelfth aspect of the present invention, in any one of the fourth to eleventh aspects, the data collection control unit receives at least one of the collected history data, the power supply data, and the interrupt signal data. The data is output to an external storage device via an internal bus.

  A thirteenth aspect of the present invention is the storage medium according to any one of the fourth to eleventh aspects, wherein at least one of the history data, the power supply data, and the interrupt signal data collected by the data collection control unit is stored. An internal memory circuit is further provided.

  A fourteenth aspect of the present invention provides the data collection control unit according to any one of the fourth to eleventh aspects, wherein the data collection control unit surrounds at least one of the collected history data, the power supply data, and the interrupt signal data. It outputs to an external memory circuit via the module internal bus.

  According to the first aspect of the present invention, the data collection unit has an access history of the internal bus control unit with respect to the internal bus, an input / output history of the first data with respect to the first storage unit, and a second data with respect to the second storage unit. Since at least one of the input / output histories is collected from the internal bus control unit, the access history of the bus interface control unit for the external bus and the second data input / output history for the second storage means are collected from the bus interface control unit. It becomes easy to analyze various causes of failure when an event occurs, such as when an error signal is found in the external bus signal. Even when the failure can be reproduced only in the actual operating environment of the system, data can be easily collected.

  According to the second aspect of the present invention, since the data collection unit includes the first interface and the second interface, information can be collected directly from the external bus and the internal bus. Therefore, even if a failure occurs in the bus interface control unit or the internal bus control unit, information can be collected from the external bus and the internal bus without any problem.

  According to the third aspect of the present invention, when the bus interface control unit detects an error signal defined in the specification of the external bus at the time of communication with the external bus, the information on the type of error and the timing of occurrence of the error Is output to the data collecting unit, the data collecting unit can extract the history data when the error signal is detected based on the first warning signal.

  According to the fourth aspect of the present invention, the controller tracer that collects and holds the information on the internal bus side, the bus tracer that collects and holds the information on the external bus side, and is held by the controller tracer and the bus tracer. Since it includes a data collection control unit that extracts and collects history data based on each recorded history, it becomes easy to analyze various causes of failure when an event occurs. Even when the failure can be reproduced only in the actual operating environment of the system, data can be easily collected.

  According to the invention described in claim 5 of the present invention, the caution pattern indicating the access pattern in a specific order and the collected histories are collated, so that the histories at the time of the access pattern that is likely to cause a failure are collected. Can do.

  According to the sixth aspect of the present invention, when the bus interface control unit detects an error signal defined in the specification of the external bus at the time of communication with the external bus, the information on the type of error and the timing of occurrence of the error Is output to the data collection control unit via the bus tracer, the data collection control unit can know the error type and the timing at which the error signal is detected.

  According to the seventh aspect of the present invention, since the bus tracer includes the bus tracer dedicated interface, information can be collected directly from the external bus. Therefore, even if a failure occurs in the bus interface control unit, information can be collected from the external bus without any problem.

  According to the eighth aspect of the present invention, the controller tracer includes the controller tracer-dedicated interface, so that information can be collected directly from the internal bus. Therefore, even if a failure occurs in the internal bus control unit, information can be collected from the internal bus without any problem.

  According to the ninth aspect of the present invention, the data collection control unit collects power supply data based on the power supply state from the power supply tracer, so that it is easily analyzed when the power supply is a cause of the failure. It can be performed.

  According to the tenth aspect of the present invention, the data collection control unit collects the interrupt signal data from the I / O tracer. Therefore, when the interrupt signal causes a failure, the data collection control unit can easily analyze the data. It can be carried out.

  According to the eleventh aspect of the present invention, since the data collection control unit can extract each data at the time of event occurrence based on the second warning signal or the third warning signal, the operation at the time of event occurrence is possible. Analysis can be performed easily.

  According to the twelfth aspect of the present invention, the data collection control unit outputs the collected data to the external storage device via the internal bus, so that necessary data can be appropriately stored in the external storage device. it can.

  According to the thirteenth aspect of the present invention, since the internal memory circuit for storing data is provided, it is not necessary to store the data in the external storage device via the internal bus, and a failure occurs in the internal bus. Data can be stored safely and securely.

  According to the fourteenth aspect of the present invention, the data collection control unit outputs the collected data to the external memory circuit via the peripheral module internal bus, and therefore saves it in the external storage device via the internal bus. This is unnecessary, and even when a failure occurs in the internal bus, data can be stored safely and reliably. Even when the internal memory circuit having a sufficient capacity cannot be provided in the bus device due to restrictions on mounting of the bus device, a sufficient storage capacity can be secured in the external memory circuit.

  DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments of a bus device of the present invention will be described in detail with reference to the drawings.

  Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of the bus device 10a and its periphery according to the first embodiment of the present invention.

  First, the configuration of the present embodiment will be described. As shown in FIG. 1, a bus device 10a is connected to an external bus 20 and an internal bus 30, and has an internal bus control unit 11, a data transfer control unit 12, a bus interface control unit 13, a local register 14, and a bus configuration register. 15 and a data collection unit 16.

  In addition, the bus device 10 a, the CPU 32, the main memory 34, and the external storage device 36 are connected to each other via the internal bus 30.

  The connection form of the main memory 34, the CPU 32, the external storage device 36, and the internal bus 30 described above is one example. For example, the structure connected to the internal bus 30 via the hub interface not shown connected on the internal bus 30 can also be taken. In any case, in order to access the main memory 34, the CPU 32, and the external storage device 36 from the bus device 10a, it is necessary to go through the internal bus 30.

  The internal bus control unit 11 controls access of the bus device 10a to the internal bus 30 and accepts operations performed on the bus device 10a from the internal bus 30 side. When data transfer is performed between the bus device 10a and the internal bus 30, the following three can be cited. The first is a case where the CPU 32 executes data transfer with other bus devices on the external bus 20 by a program. The second case is when the bus device 10 a controls the external bus 20 as a bus master and directly accesses the main memory 34. The third is a case where another bus device becomes a bus master and the bus device 10a executes data transfer as a target device.

  Further, the internal bus control unit 11 confirms an error defined in the internal bus specification for access to the internal bus 30. Further, the internal bus control unit 11 controls input / output of the first data to / from the local register 14 of the internal bus 30. The first data will be described later.

  The bus interface control unit 13 controls access of the bus device 10 a to the external bus 20. That is, like the internal bus control unit 11, the bus interface control unit 13 performs data transfer between the bus device 10a and the external bus 20 in the three cases of data transfer by the CPU 32, bus master transfer, and target operation. It becomes an interface when transfer is performed.

  The bus interface control unit 13 detects an error signal defined in the specification of the external bus 20 when communicating with the external bus 20. When detecting an error signal, the bus interface control unit 13 outputs a first warning signal indicating information regarding the type of error and the timing of occurrence of the error to the data collection unit 16.

  Further, the bus interface control unit 13 controls input / output of second data to / from the bus configuration register 15 of the external bus 20 or the internal bus 30. The second data will be described later.

  The data transfer control unit 12 relays the internal bus control unit 11 and the bus interface control unit 13 to control transfer processing of data (including second data) necessary as a function of the bus device 10a. The basic functions of the bus device 10a are executed by the configuration of the internal bus control unit 11, the data transfer control unit 12, and the bus interface control unit 13.

  The local register 14 corresponds to the first storage means of the present invention and stores the first data. Here, the first data is a setting for controlling basic operations of the external bus 20 side function and the internal bus 30 side function of the bus device 10a. For example, the operation mode setting as the external bus device (whether host operation is possible, There are various types such as memory address setting, external bus clock setting, power management setting, interrupt setting (presence / absence of interrupt signal) as seen from the internal bus 30.

  The local register 14 is connected to the internal bus control unit 11, and data is input / output to / from the internal bus 30 via the internal bus control unit 11. In the local register 14, the setting is not written from the external bus 20 side.

  The bus configuration register 15 corresponds to the second storage means of the present invention and stores second data. Here, the second data is a detailed setting of the function on the external bus 20 side of the bus device 10a. For example, the ID as the external bus device, the vendor ID, the memory address setting viewed from the external bus 20, the latency setting, and the device state There are various types such as dedicated memory space setting, interrupt setting, and function enable / disable setting.

  The bus configuration register 15 is connected to the bus interface control unit 13, and data is input / output to / from the external bus 20 or the internal bus 30 via the bus interface control unit 13.

  The data collection unit 16 displays the access history of the internal bus control unit 11 with respect to the internal bus 30, the input / output history of the first data with respect to the local register 14, and the input / output history of the second data with respect to the bus configuration 15. Collect from. In the present embodiment, the data collection unit 16 collects all histories, but it is not always necessary to collect all histories, and any one of them may be used. Here, the input / output history of the second data with respect to the bus configuration register 15 refers to that performed with the internal bus 30 via the internal bus control unit 11.

  The data collection unit 16 collects the access history of the bus interface control unit 13 for the external bus 20 and the input / output history of the second data for the bus configuration register 15 from the bus interface control unit 13. Here, the input / output history of the second data with respect to the bus configuration register 15 indicates that performed between the bus configuration register 15 and the external bus 20 via the bus interface control unit 13.

  The data collection unit 16 stores each collected history by a predetermined capacity. After storing each history up to the capacity limit, the data collection unit 16 deletes the oldest history every time the latest history is stored.

  The data collection unit 16 extracts history data based on each collected history. When the history data is extracted, the data collection unit 16 extracts history data at the timing of occurrence of an error from each collected history based on the first warning signal.

  Further, the data collection unit 16 is connected to the external bus 20 and collects information on the external bus 20, and the second interface 16 b is connected to the internal bus 30 and collects information on the internal bus 30. Is provided. These two interfaces are not essential. If these two interfaces do not exist, the data collection unit 16 collects information on the internal bus 30 via the internal bus control unit 11 and information on the external bus 20 via the bus interface control unit 13.

  The data collection unit 16 outputs the extracted history data for failure cause analysis to the external storage device 36 outside the bus device 10 a via the internal bus 30.

  Next, the operation of the bus device 10a according to the first embodiment will be described. During normal communication, the bus device 10a operates as a general bus device. After power-on reset of the bus device 10a, the CPU 32 initializes the values of the local register 14 and the bus configuration register 15.

  The bus device 10a performs a communication operation as a normal bus device based on the setting contents of both registers. The normal communication operation described here is an arbitration function of an external bus device (a function that gives an external bus control right in accordance with a bus right request from each external bus device when the bus device 10a operates as a host of the external bus) The memory read function, the memory write function, the I / O read function, the I / O write function, etc. during the bus master operation and the bus target operation are shown.

  Terms and operations related to normal communication described above are the same as those in the general PCI bus specification. In each operation, the data transfer control unit 12 controls the entire normal communication of the bus device 10a. The internal bus control unit 11 and the bus interface control unit 13 are interfaces between the internal bus 30 and the bus device 10a and between the external bus 20 and the bus device 10a, respectively, and between the external bus 20 and the internal bus 30. Mediate communication.

  The characteristic operation of the present invention is the operation when the failure of the external bus 20 described below is suspected or when the failure of the external bus 20 is suspected. As described above, the data collection unit 16 collects the access history of the internal bus control unit 11 for the internal bus 30 and the access history of the bus interface control unit 13 for the external bus 20.

  Thereafter, the data collection unit 16 extracts history data based on each collected history. There are various timings when the data collection unit 16 extracts the history data. For example, when the bus interface control unit 13 detects an error signal defined in the external bus specification in the external bus signal when communicating with the external bus 20. is there. For example, a PERR # signal (parity error signal) in a PCI bus signal is applicable. In this case, the bus interface control unit 13 outputs a first warning signal indicating information regarding the type of error and the timing of occurrence of the error to the data collection unit 16.

  The data collection unit 16 to which the first warning signal is input extracts history data based on each collected history. At that time, the data collection unit 16 obtains the history data at the same timing as the error occurrence timing based on the first warning signal, the access history of the internal bus control unit 11 for the internal bus 30, the local register 14 and the bus configuration register 15. The data is extracted from the input / output history of the first data and the second data and the history of the access history of the bus interface control unit 13 for the external bus 20.

  Further, the data collection unit 16 outputs information regarding the extracted history data, error type, and error occurrence timing to the external recording device 36 via the internal bus 30, and stores the data.

  There are various methods for synchronizing the timing of error occurrence and history. For example, the data collection unit 16 has a clock capable of obtaining time information, and time information is always added to the collected history. Can be.

 As described above, according to the bus device 10a according to the first embodiment of the present invention, the data collection unit 16 has the access history of the internal bus control unit 11 with respect to the internal bus 30, and the input / output history of the first data with respect to the local register 14. In addition, the input / output history of the second data for the bus configuration register 15 is collected from the internal bus control unit 11, and the access history of the bus interface control unit 13 for the external bus 20 and the second data input to the bus configuration register 15 are entered. Since the output history is collected from the bus interface controller 13, it becomes easy to analyze various causes of failure when an event occurs, such as when an error signal is found in the external bus signal.

 In the prior art, only the information on the external bus 20 side is stored. In the present embodiment, not only the information on the external bus 20 side but also the true cause of the failure may be included. Certain information on the internal bus 30 side is stored by the data collection unit 16 via the internal bus control unit 11. Therefore, it is possible to easily analyze a failure whose cause is difficult to elucidate only by the information on the external bus 20 side or a failure when the operation on the internal bus 30 side is involved as a failure occurrence condition.

 Even in the case where a failure occurs only in the actual operating environment of the system, and the failure cannot be reproduced in the laboratory environment, various data can be used in the same way as when the failure is reproduced in the laboratory where the data collection environment is maintained. It becomes possible to analyze the cause of failure.

  Furthermore, since the data collection unit 16 includes the first interface 16a and the second interface 16b, information can be collected directly from the external bus 20 and the internal bus 30. Therefore, even if a failure occurs in the bus interface control unit 13 or the internal bus control unit 11, information can be collected from the external bus 20 and the internal bus 30 without any problem.

  When the bus interface control unit 13 detects an error signal defined in the specification of the external bus 20 during communication with the external bus 20, the bus interface control unit 13 outputs a first warning signal indicating information on the type of error and the timing of occurrence of the error. Since it outputs to the data collection part 16, the data collection part 16 can extract the log | history data at the time of error signal detection from each collected log | history based on a 1st warning signal.

  FIG. 2 is a block diagram showing the configuration of the bus device 10b and its peripherals according to the second embodiment of the present invention. The difference from the configuration of the first embodiment is that the bus device 10 b includes a bus tracer 18, a controller tracer 19, and a data collection control unit 17 instead of the data collection unit 16.

  The bus tracer 18 is connected to the bus interface control unit 13 and the data collection control unit 17, and the bus interface shows the access history of the bus interface control unit 13 for the external bus 20 and the input / output history of the second data to the bus configuration register 15. Collected from the control unit 13 and held. Here, the input / output history of the second data with respect to the bus configuration register 15 indicates that performed between the bus configuration register 15 and the external bus 20 via the bus interface control unit 13.

  The controller tracer 19 is connected to the internal bus control unit 11 and the data collection control unit 17, and the access history of the internal bus control unit 11 with respect to the internal bus 30, the input / output history of the first data with respect to the local register 14, and the bus configuration. At least one input / output history of the second data for the register 15 is collected from the internal bus control unit 11 and held. Here, the input / output history of the second data with respect to the bus configuration register 15 refers to that performed with the internal bus 30 via the internal bus control unit 11.

  The data collection control unit 17 is connected to the bus tracer 18, the controller tracer 19, and the internal bus 30, and extracts and collects history data based on each history held by the controller tracer 19 and the bus tracer 18.

  The bus interface control unit 13 detects an error signal defined in the specification of the external bus 20 when communicating with the external bus 20. When detecting an error signal, the bus interface control unit 13 outputs a third warning signal indicating information on the type of error and the timing of occurrence of the error to the data collection control unit 17 via the bus tracer 18.

  Next, the configuration of the controller tracer 19 and the bus tracer 18 will be described in more detail. FIG. 3 is a block diagram illustrating the configuration of the controller tracer 19 according to the second embodiment of the present invention. FIG. 4 is a block diagram showing the configuration of the bus tracer 18 according to the second embodiment of the present invention. As shown in FIG. 3, the controller tracer 19 includes a trace unit 42a, a pattern matching unit 44a, a cautionary pattern holding unit 46a, a bus history holding buffer 47a, and a register history holding buffer 48a.

  The trace unit 42a is connected to the pattern matching unit 44a, the bus history holding buffer 47a, the register history holding buffer 48a, the data collection control unit 17, and the internal bus control unit 11, and collects each history.

  The trace unit 42a collects the access history of the internal bus control unit 11 with respect to the internal bus 30 from the internal bus control unit 11, and outputs it to the bus history holding buffer 47a. The bus history holding buffer 47a holds the input access history.

  The trace unit 42a collects the input / output history of the first data for the local register 14 and the input / output history of the second data for the bus configuration register 15 from the internal bus control unit 11 and outputs them to the register history holding buffer 48a. To do. The register history holding buffer 48a holds each input history.

  The caution pattern holding unit 46a is connected to the pattern matching unit 44a and holds a caution pattern indicating an access pattern in a specific order set in advance. In the present embodiment, the caution pattern holding unit 46 a is provided in the controller tracer 19, but may be provided outside the controller tracer 19.

  The pattern matching unit 44a is connected to the trace unit 42a and the caution pattern holding unit 46a, and collates each history collected by the trace unit 42a with a caution pattern every time the trace unit 42a collects history information. Furthermore, the pattern matching unit 44a outputs a second warning signal to the data collection control unit 17 via the trace unit 42a when each history collected by the trace unit 42a matches the caution pattern.

As shown in FIG. 4, the bus tracer 18 has the same configuration as the controller tracer 19 and will not be described again. However, the controller tracer 19 and the bus tracer 18 do not necessarily have the same configuration. For example, the bus tracer 18 can be configured by only the trace unit 42b, the bus history holding buffer 47b, and the register history holding buffer 48b. is there.
The trace unit 42a and the pattern matching unit 44a are mounted as a semiconductor logic circuit and a register (volatile RAM memory). The caution pattern holding unit 46a is mounted as a nonvolatile ROM memory such as a flash ROM.

  In addition, the bus history holding buffer 47a and the register history holding buffer 48a have capacity limitations, and the oldest history is deleted each time the latest history is held in order to prevent overflow of history data. The bus history holding buffer 47 a and the register history holding buffer 48 a can be provided outside the controller tracer 19.

  Since the trace part 42b in the bus tracer 18 shown in FIG. 4 is different from the trace part 42a shown in FIG. 3, the trace part 42b will be described.

  The trace unit 42b is connected to the pattern matching unit 44b, the bus history holding buffer 47b, the register history holding buffer 48b, the data collection control unit 17, and the bus interface control unit 13, and collects each history.

  The trace unit 42b collects the access history of the bus interface control unit 13 with respect to the external bus 20 from the bus interface control unit 13 and outputs it to the bus history holding buffer 47b. The bus history holding buffer 47b holds the input access history.

  The trace unit 42b collects the input / output history of the second data with respect to the bus configuration register 15 from the bus interface control unit 13 and outputs it to the register history holding buffer 48b. Here, the input / output history of the second data with respect to the bus configuration register 15 indicates that performed between the bus configuration register 15 and the external bus 20 via the bus interface control unit 13. The register history holding buffer 48b holds an input / output history that has been input.

  Next, the operation of the bus device 10b according to the second embodiment will be described. About the operation | movement similar to Example 1, the overlapping description is abbreviate | omitted. The characteristic operation of the present invention is the operation when the failure of the external bus 20 described below is suspected or when the failure of the external bus 20 is suspected. As described above, the controller tracer 19 and the bus tracer 18 hold the access history of the internal bus control unit 11 for the internal bus 30 and the access history of the bus interface control unit 13 for the external bus 20, respectively.

  Thereafter, the data collection control unit 17 extracts history data based on each history collected in the following three cases.

  The first case is when the bus interface control unit 13 detects an error signal defined in the external bus specification as an external bus signal during communication with the external bus 20. In this case, the bus interface control unit 13 outputs a third warning signal indicating information regarding the type of error and the timing of occurrence of the error to the data collection control unit 17 via the bus tracer 18. Since the subsequent operation is the same as the operation when the first warning signal is output in the first embodiment, the duplicated description is omitted.

  There are various methods for synchronizing the timing of error occurrence and history. For example, the data collection control unit 17 has a clock capable of obtaining time information. The controller tracer 19 and the bus tracer 18 With reference to the clock possessed by the collection control unit 17, it is assumed that time information is always added to the collected history.

  The second case is a case where the pattern collation unit 44b in the bus tracer 18 collates each history collected by the trace unit 42b with a caution pattern and matches. The pattern matching unit 44b in the bus tracer 18 outputs a second warning signal to the data collection control unit 17 via the trace unit 42b.

  Here, the second warning signal includes information regarding the type of history that has been matched, the type of pattern that needs attention, and the degree of matching. There are two types of adaptations that indicate the degree of adaptation. One is “strict matching”, and there is a portion where the history and the pattern requiring attention completely match. The other is “order matching”, which does not completely match, but the same signal order as the pattern requiring attention appears in the history. That is, in “order matching”, it is sufficient that the order of signals is the same as a whole, and signals of a pattern different from the pattern requiring attention may be inserted between individual signals. “Strict matching” has a higher degree of matching than “order matching”.

  In addition, the pattern matching unit 44b in the bus tracer 18 is not only an input / output history for the bus configuration register 15 from the external bus 20 side, but also from the internal bus 30 side via the bus interface control unit 13 as a conformity check mechanism. Verification is performed for all access histories including the input / output history for the bus configuration register 15 to be performed.

  The data collection controller 17 to which the second warning signal is input extracts and collects history data based on each history collected and held in the controller tracer 19 and the bus tracer 18.

  Specifically, the data collection control unit 17 stores the historical data at the same timing as the required pattern generation timing based on the second warning signal, and the internal bus control unit 11 for the internal bus 30 held in the controller tracer 19. The access history, the data input / output history between the internal bus 30 and the local register 14, and the data input / output history between the internal bus 30 and the bus configuration register 15 are extracted and collected.

  Further, the data collection control unit 17 stores history data at the same timing as the occurrence of the caution pattern based on the second warning signal, the access history of the bus interface control unit 13 with respect to the external bus 20 held in the bus tracer 18, The data is extracted and collected from the data input / output history between the internal bus 30 and the bus configuration register 15 and the data input / output history between the external bus 20 and the bus configuration register 15.

  Further, the data collection control unit 17 obtains the type information of the caution pattern checked by the bus tracer 18 based on the second warning signal.

  Further, the data collection control unit 17 outputs the extracted history data, the type of caution pattern type, and the information regarding the timing of the caution pattern generation to the external recording device 36 via the internal bus 30 and stores the data.

  The third case is a case where the pattern collation unit 44a in the controller tracer 19 collates each history collected by the trace unit 42a with the caution pattern and matches. The pattern matching unit 44a in the controller tracer 19 outputs a second warning signal to the data collection control unit 17 via the trace unit 42a.

  Since the operation of the data collection control unit 17 to which the second warning signal is input is the same as that in the second case, a duplicate description is omitted.

  As described above, according to the bus device 10b according to the second embodiment of the present invention, in addition to the same effects as the first embodiment, the controller tracer 19 that collects and holds information on the internal bus 30 side, and the external bus 20 is provided with a bus tracer 18 that collects and holds information on the 20 side, and a data collection control unit 17 that extracts and collects history data based on each history held by the controller tracer 19 and the bus tracer 18. Sometimes it becomes easy to analyze various causes of failure.

  Further, since the pattern matching units 44a and 44b collate the caution pattern indicating the access pattern in a specific order with the collected histories, the external bus 20 side and the internal bus 30 side at the time of the access pattern that is likely to cause a failure. Information can be collected. In other words, the bus device 10b is not limited to the errors defined in the specifications of the external bus 20 and the internal bus 30, but is also empirically obtained bus signals that are prone to failure, input / output to the local register 14 and the bus configuration register 15. Information on the external bus 20 side and the internal bus 30 side can be collected and analyzed on the condition that the history pattern appears.

  Further, the bus interface control unit 13 sends a third warning signal indicating information regarding the type of error and the timing of occurrence of an error when detecting an error signal defined in the specifications of the external bus during communication with the external bus 20 to the bus tracer. 18, the data collection control unit 17 can know the timing at which the error signal is detected, and not only the information on the external bus 20 side but also the information on the internal bus 30 side. Information can be saved.

  Next, FIG. 5 is a block diagram showing a configuration of the bus device 10c according to the third embodiment of the present invention. 5 to 11, the CPU 32, the main memory 34, and the external storage device 36 are not shown, but are simply omitted. The difference from the configuration of the second embodiment is that the bus tracer 18 a includes a bus tracer dedicated interface 52 connected to the external bus 20 and can collect information on the external bus 20.

  Therefore, the bus tracer 18a can collect information on the external bus 20 without going through the bus interface control unit 13.

  Unlike the bus interface control unit 13, the bus tracer 18a does not need to be involved in normal communication of the bus device 10c. Therefore, the bus tracer-dedicated interface 52 does not need a function of writing to the external bus 20 and only needs to read information of the external bus 20.

  The bus tracer 18a collects and holds the access history of the bus interface control unit 13 for the external bus 20 and the input / output history of the second data for the bus configuration register 15 from the bus interface control unit 13 as in the second embodiment. It is the same.

  Therefore, the bus tracer 18 a can compare the access history of the bus interface control unit 13 with respect to the external bus 20 and the information of the external bus 20 via the bus tracer dedicated interface 52. Thereby, it is possible to confirm whether or not the operation of the communication function of the bus interface control unit 13 with respect to the external bus 20 is normal. In this case, the bus tracer 18a holds only the information of the external bus 20 collected via the bus tracer dedicated interface 52 in the bus history holding buffer 47b, and holds the access history for the external bus 20 collected from the bus interface control unit 13. do not do. The access history of the bus interface control unit 13 with respect to the external bus 20 is used only for confirmation of normal operation.

  Next, the operation of the bus device 10c according to the third embodiment will be described. When each component in the bus device 10c is operating normally, the bus tracer 18a directly collects information on the external bus 20 from the bus tracer dedicated interface 52 without going through the bus interface control unit 13. Other operations are the same as those in the second embodiment.

  The bus tracer 18 needs to collect from the bus interface control unit 13 the access history for the external bus 20 when a failure occurs, which is necessary for elucidating the cause of the failure. However, in the configuration of the second embodiment, when a failure occurs in the bus interface control unit 13, the bus tracer 18 cannot collect the access history of the bus interface control unit 13 for the external bus 20.

  On the other hand, in the configuration of the present embodiment, the bus tracer 18a is provided with the bus tracer dedicated interface 52 that is the information collection path of the external bus 20, so that the operation of the bus interface control unit 13 is not affected. Therefore, it is possible to continue collecting information on the external bus 20.

 As described above, according to the bus device 10c according to the third embodiment of the present invention, even when a failure occurs in the bus interface control unit 13, the bus device 10c can acquire information on the external bus 20. . As a result, the bus access history on the side of the external bus 20 useful for elucidating the cause of the failure can be collected even in the case of a bus device failure caused by the bus interface control unit 13 (the failure surfaced in the form of a communication failure of the external bus 20). It is possible to analyze the failure easily.

 Other effects are the same as those of the second embodiment.

  Next, FIG. 6 is a block diagram illustrating a configuration of the bus device 10d according to the fourth embodiment of the present invention. The difference from the configuration of the second embodiment is that the controller tracer 19 a includes a controller tracer dedicated interface 54 connected to the internal bus 30 and can collect information on the internal bus 30.

  Therefore, the controller tracer 19a can collect information on the internal bus 30 without going through the internal bus control unit 11.

  Similarly to the case of the third embodiment, the controller tracer 19a does not need to be involved in normal communication of the bus device 10d. Therefore, the controller tracer dedicated interface 54 does not need a function of writing to the internal bus 30 and only needs to read information of the internal bus 30.

  The controller tracer 19a also includes an access history of the internal bus control unit 11 with respect to the internal bus 30, an input / output history of the first data with respect to the local register 14 via the internal bus control unit 11, and a bus configuration register via the internal bus control unit 11. As in the second embodiment, at least one of the input / output histories of the second data for 15 is collected from the internal bus control unit 11 and held.

  Therefore, the controller tracer 19 a can compare the access history of the internal bus control unit 11 with respect to the internal bus 30 and the information of the internal bus 30 via the controller tracer dedicated interface 54. Thereby, it is possible to confirm whether or not the operation of the communication function of the internal bus control unit 11 for the internal bus 30 is normal. In this case, the controller tracer 19a holds only the information of the internal bus 30 collected via the controller tracer dedicated interface 54 in the bus history holding buffer 47a, and holds the access history for the internal bus 30 collected from the internal bus control unit 11. do not do. The access history of the internal bus control unit 11 with respect to the internal bus 30 is used only for confirmation of normal operation.

  Next, the operation of the bus device 10d according to the fourth embodiment will be described. When each component in the bus device 10d is operating normally, the controller tracer 19a collects information on the internal bus 30 directly from the controller tracer dedicated interface 54 without going through the internal bus control unit 11. Other operations are the same as those in the second embodiment.

  In the configuration of the second embodiment, the controller tracer 19 a cannot collect the access history of the internal bus control unit 11 for the internal bus 30 when a failure occurs in the internal bus control unit 11.

  On the other hand, in the configuration of the present embodiment, the controller tracer 19a includes the controller tracer-dedicated interface 54, which is the information collection path of the internal bus 30, so that the operation of the internal bus control unit 11 is not affected. Therefore, it is possible to continue collecting information on the internal bus 30.

 As described above, according to the bus device 10d according to the fourth embodiment of the present invention, even when a failure occurs in the internal bus control unit 11, the bus device 10d can acquire information on the internal bus 30. . As a result, even in the case of a bus device failure caused by the internal bus control unit 11, it is possible to collect the bus access history on the side of the internal bus 30 that is useful for elucidating the cause of the failure, and it is possible to easily analyze the failure.

  Other effects are the same as those of the second embodiment.

  Next, FIG. 7 is a block diagram showing the configuration of the bus device 10e according to the fifth embodiment of the present invention. The difference from the configuration of the second embodiment is that the bus device 10 e includes a power supply tracer 60 instead of the controller tracer 19.

  The power tracer 60 collects and holds the power supply state from the power supply unit of the system on which the bus device 10e is mounted to the bus device 10e.

  The power supply tracer 60 is located at an interface unit from the system power supply unit 70 which is a power supply unit of the system on which the bus device 10e is mounted to the power supply line of the bus device 10e, and is connected to the system power supply unit 70 and the data collection control unit 17a. Yes.

  The power supply tracer 60 holds a power supply state (current value of supplied power and time-series data of voltage values) to the bus device 10e in a power supply history buffer (not shown). The power supply history buffer performs the same operation as the bus history holding buffer 47a of the second embodiment.

  The data collection controller 17a extracts and collects each history data as described in the second embodiment, and further extracts and collects power data based on the power supply state held by the power tracer 60.

  Next, the operation of the bus device 10e according to the fifth embodiment will be described. The data collection control unit 17a extracts and collects history data from the bus tracer 18 when the second warning signal or the third warning signal is input, as in the second embodiment. At that time, power source data at the same timing as the timing at which an error or a caution pattern occurs is further extracted and collected from the power source tracer 60.

  In addition, the data collection control unit 17 a outputs the collected history data and power supply data to the external storage device 36 via the internal bus 30. Thereby, in addition to the bus information of the external bus 20, data related to the power supply state to the bus device 10e can be stored.

  As described above, according to the bus device 10e according to the fifth embodiment of the present invention, the cause of the failure is a power supply state to the bus device 10e (for example, abnormal fluctuation in supply voltage or instantaneous power failure). The cause of the failure can be clarified smoothly.

  In the prior art, since there was no means for collecting and holding the power state of the device, it was necessary to collect power state data using a measuring instrument in a laboratory environment. However, according to the configuration of the fifth embodiment of the present invention, the data collection control unit collects power supply data based on the power supply state from the power supply tracer, so that it is possible to collect power state data on the bus device 10e side. Power supply data can be collected in combination with history data based on the access history to the external bus 20. Therefore, based on the communication processing of the bus device 10e and the synchronization data of the power supply state, the analysis can be easily performed when the power supply is a cause of the failure.

  Next, FIG. 8 is a block diagram showing the configuration of the bus device 10f according to the sixth embodiment of the present invention. The difference from the configuration of the fifth embodiment is that the bus device 10 f further includes a controller tracer 19.

  Since the operations of the power supply tracer 60 and the controller tracer 19 are the same as those in the fifth embodiment and the second embodiment, respectively, duplicate description is omitted.

  Next, the operation of the bus device 10f according to the sixth embodiment will be described. The data collection controller 17a extracts and collects historical data from the bus tracer 18 and the controller tracer 19 when the second warning signal or the third warning signal is input, as in the second embodiment. . At that time, power source data at the same timing as the timing at which an error or a caution pattern occurs is further extracted and collected from the power source tracer 60.

  In addition, the data collection control unit 17 a outputs the collected history data and power supply data to the external storage device 36 via the internal bus 30. Thereby, in addition to the bus information of the external bus 20 and the internal bus 30, data regarding the power supply state to the bus device 10e can be stored.

  As described above, according to the bus device 10f according to the sixth embodiment of the present invention, history data based on the access history to the internal bus 30 can be collected in addition to the effects of the fifth embodiment. Therefore, analysis for elucidating the cause of the failure can be easily performed based on the communication processing of the internal bus 30 and the external bus 20 of the bus device 10f and the synchronization data of the power supply state.

  Next, FIG. 9 is a block diagram showing the configuration of the bus device 10g according to the seventh embodiment of the present invention. The difference from the configuration of the second embodiment is that the bus device 10 g further includes an internal memory circuit 62.

 The internal memory circuit 62 stores the history data collected by the data collection control unit 17c. The internal memory circuit 62 can store not only history data but also power data and interrupt signal data described later.

 The internal memory circuit 62 is mounted in the bus device 10g as a writable non-volatile ROM memory such as a flash ROM, and can retain data even after the bus device 10g is powered off.

 The data collection control unit 17 c outputs history data collected from the bus tracer 18 and the controller tracer 19 to the internal memory circuit 62. For this reason, the data collection control unit 17 c does not output history data to the external storage device 36, and therefore does not need to be connected to the internal bus 30.

 Next, the operation of the bus device 10g according to the seventh embodiment will be described. The process until the data collection control unit 17c collects history data from the bus tracer 18 and the controller tracer 19 is the same as in the second embodiment. The data collection control unit 17 c outputs the collected history data to the internal memory circuit 62.

 As described above, according to the bus device 10g according to the embodiment 7 of the present invention, since it is not necessary to store the data in the external storage device 36 via the internal bus 30, even if a failure occurs in the internal bus 30, The bus device 10g can safely and reliably store history data for failure factor analysis.

  Next, FIG. 10 is a block diagram showing the configuration of the bus device 10h according to the eighth embodiment of the present invention. The difference from the configuration of the second embodiment is that the data collection control unit 17d in the bus device 10h is connected to the external memory circuit 64 via the peripheral module internal bus 66. The peripheral module internal bus 66 is different from the internal bus 30. The peripheral module internal bus 66 is an in-system bus that operates independently of the internal bus 30 and the external bus 20.

 The external memory circuit 64 is provided outside the bus device 10h and stores history data collected by the data collection control unit 17d. The external memory circuit 64 can store not only history data but also power data and interrupt signal data described later.

 The data collection control unit 17d outputs the history data collected from the bus tracer 18 and the controller tracer 19 to the external memory circuit 64 via the peripheral module internal bus 66. Therefore, the data collection control unit 17d does not need to be connected to the internal bus 30 because it does not output history data to the external storage device 36.

 Next, the operation of the bus device 10h according to the eighth embodiment will be described. The process until the data collection control unit 17d collects history data from the bus tracer 18 and the controller tracer 19 is the same as in the second embodiment. The data collection control unit 17d outputs the collected history data to the external memory circuit 64.

  As described above, according to the bus device 10h according to the eighth embodiment of the present invention, it is not necessary to store the data in the external storage device 36 via the internal bus 30, and even if a failure occurs in the internal bus 30, the module Since the internal bus 66 is independent of the internal bus 30, the bus device 10 h can store the history data for failure factor analysis in the external memory circuit 64 safely and reliably.

 Further, the bus device 10g in the seventh embodiment cannot secure a sufficient storage capacity for the internal memory circuit 62 due to mounting restrictions in many cases. On the other hand, the bus device 10h in the seventh embodiment has an internal memory. It is not necessary to have the circuit 62, and the external memory circuit 64 having a sufficient storage capacity exists outside, so that a margin in mounting can be secured.

 Therefore, the bus device 10h can secure an external memory circuit 64 having a sufficient storage capacity as a recording device for failure analysis data outside the bus device 10h without being affected by mounting restrictions, and a failure of the internal bus 30. The history data for failure analysis can be stored in the external memory circuit 64 safely at times.

  Next, FIG. 11 is a block diagram showing the configuration of the bus device 10i according to the ninth embodiment of the present invention. The difference from the configuration of the second embodiment is that the bus device 10 i includes an I / O tracer 68 instead of the controller tracer 19.

  The I / O tracer 68 collects and holds interrupt signals in the system in which the bus device 10i is mounted. Here, the interrupt signal is, for example, an NMI (non-maskable) interrupt, a WDT (watchdog timer) signal, a DMAC (direct memory access controller) interrupt, a UBC (user break controller), or the like.

  The I / O tracer 68 is located at the interface unit of each signal line (excluding the internal bus 30, the external bus 20, and the power supply line) from the system on which the bus device 10i is mounted to the bus device 10i, and is connected to the data collection control unit 17e. It is connected.

  The I / O tracer 68 holds an interrupt signal in the system in which the bus device 10i is mounted in an I / O history buffer (not shown). The I / O history buffer performs the same operation as the bus history holding buffer 47a of the second embodiment.

  The data collection control unit 17e extracts and collects each history data as described in the second embodiment, and further extracts and collects interrupt signal data based on the interrupt signal held by the I / O tracer 68.

  Next, the operation of the bus device 10i according to the ninth embodiment will be described. The data collection controller 17e extracts and collects history data from the bus tracer 18 when the second warning signal or the third warning signal is input, as in the second embodiment. At this time, interrupt signal data at the same timing as the timing at which an error or a caution pattern has occurred is further extracted from the I / O tracer 68 and collected.

  The data collection control unit 17e outputs the collected history data and interrupt signal data to the external storage device 36 via the internal bus 30. As a result, in addition to the bus information of the external bus 20, data related to input / output signals (interrupts, WDT signals) to the bus device 10i can be stored.

  Further, when the controller tracer 19 is further provided, it goes without saying that the bus information of the internal bus 30 can also be collected.

  As described above, according to the bus device 10i according to the ninth embodiment of the present invention, the cause of the failure is an input / output signal (for example, an NMI interrupt at an unexpected timing) from another device in the system. It becomes easy to elucidate the cause of failure in case.

 In order to obtain logs related to these input / output signals (interrupt, WDT, etc.) with the prior art, it is necessary to assemble a program for acquiring input / output signals in advance in the program on the CPU 32 side. However, the configuration of this embodiment makes it easy to collect interrupt signals.

 Furthermore, in the prior art, even if it is possible to record the signal history on the CPU 32 side, it is difficult to record the time in synchronism with the bus operation history on the bus device 10i side, and it is difficult to analyze the cause of the failure. It was. However, since the interrupt signal data can be collected in combination with the history data by the data collection control unit 17e by the configuration of the present embodiment, the cause of the failure can be easily clarified based on the communication processing of the bus device 10i and the synchronization data of the interrupt signal. Can be done.

  The bus device according to the present invention can be used for an external bus including a PCI bus and a bus device connected to an internal bus.

It is a block diagram which shows the structure of the bus device of the form of Example 1 of this invention, and its periphery. It is a block diagram which shows the structure of the bus device of the form of Example 2 of this invention, and its periphery. It is a block diagram which shows the structure of the controller tracer in the bus device of the form of Example 2 of this invention. It is a block diagram which shows the structure of the bus tracer in the bus device of the form of Example 2 of this invention. It is a block diagram which shows the structure of the bus device of the form of Example 3 of this invention. It is a block diagram which shows the structure of the bus device of the form of Example 4 of this invention. It is a block diagram which shows the structure of the bus device of the form of Example 5 of this invention. It is a block diagram which shows the structure of the bus device of the form of Example 6 of this invention. It is a block diagram which shows the structure of the bus device of the form of Example 7 of this invention. It is a block diagram which shows the structure of the bus device of the form of Example 8 of this invention. It is a block diagram which shows the structure of the bus device of the form of Example 9 of this invention.

Explanation of symbols

10a, 10b, 10c, 10d, 10e, 10f, 10g, 10h, 10i Bus device 11 Internal bus control unit 12 Data transfer control unit 13 Bus interface control unit 14 Local register 15 Bus configuration register 16 Data collection unit 16a First interface 16b Second interface 17, 17a, 17b, 17c, 17d, 17e Data collection control unit 18, 18a Bus tracer 19, 19a Controller tracer 20 External bus 30 Internal bus 32 CPU
34 Main memory 36 External storage devices 42a and 42b Trace units 44a and 44b Pattern matching units 46a and 46b Caution pattern holding units 47a and 47b Bus history holding buffers 48a and 48b Register history holding buffer 52 Bus tracer dedicated interface 54 Controller tracer dedicated interface 60 Power Tracer 62 Internal Memory Circuit 64 External Memory Circuit 66 Peripheral Module Internal Bus 68 I / O Tracer 70 System Power Supply

Claims (14)

A bus device connected to an internal bus and an external bus,
First storage means for storing first data;
An internal bus control unit that controls access to the internal bus and controls input / output of the first data to and from the first storage unit of the internal bus;
Second storage means for storing second data;
A bus interface controller for controlling access to the external bus and controlling input / output of second data to / from the second storage means of the external bus or the internal bus;
A data transfer control unit that controls a transfer process of the second data by relaying between the internal bus control unit and the bus interface control unit;
At least one of the access history of the internal bus control unit for the internal bus, the input / output history of the first data to the first storage means, and the input / output history of the second data to the second storage means is the internal bus control. And collecting the access history of the bus interface controller with respect to the external bus and the input / output history of the second data with respect to the second storage means from the bus interface controller, and based on each collected history A data collection unit that extracts history data and outputs it to an external storage device via the internal bus;
A bus device comprising: The data collection unit
A first interface connected to the external bus for collecting information on the external bus;
A second interface connected to the internal bus for collecting information of the internal bus;
The bus device according to claim 1, further comprising: The bus interface control unit collects a first warning signal indicating information on an error type and an error occurrence timing when an error signal defined in the specification of the external bus is detected during communication with the external bus. Output to the
3. The bus device according to claim 1, wherein the data collection unit extracts history data at the timing of occurrence of the error from each history collected based on the first warning signal. 4. A bus device connected to an internal bus and an external bus,
First storage means for storing first data;
An internal bus control unit that controls access to the internal bus and controls input / output of the first data to and from the first storage unit of the internal bus;
Second storage means for storing second data;
A bus interface controller for controlling access to the external bus and controlling input / output of second data to / from the second storage means of the external bus or the internal bus;
A data transfer control unit that controls a transfer process of the second data by relaying between the internal bus control unit and the bus interface control unit;
At least one of the access history of the internal bus control unit for the internal bus, the input / output history of the first data to the first storage means, and the input / output history of the second data to the second storage means is the internal bus control. A controller tracer to collect and hold from the department,
A bus tracer that collects and holds an access history of the bus interface control unit to the external bus and an input / output history of second data to the second storage unit from the bus interface control unit;
A data collection control unit for extracting and collecting history data based on each history held by the controller tracer and the bus tracer;
A bus device comprising: At least one of the controller tracer and the bus tracer is
A trace unit for collecting each history;
A caution pattern holding unit that holds a caution pattern indicating an access pattern in a specific order;
A pattern matching unit that matches each history collected by the trace unit with the pattern requiring attention;
5. The pattern matching unit outputs a second warning signal to the data collection control unit when each of the histories collected by the trace unit matches the caution pattern. The described bus device.   The bus interface control unit outputs a third warning signal indicating information on an error type and an error occurrence timing when an error signal defined in the specification of the external bus is detected during communication with the external bus. 6. The bus device according to claim 4, wherein the data is output to the data collection control unit via a bus.   The bus device according to claim 4, wherein the bus tracer includes a bus tracer-dedicated interface that is connected to the external bus and collects information of the external bus.   8. The bus device according to claim 4, wherein the controller tracer includes a controller tracer-dedicated interface connected to the internal bus and collecting information on the internal bus. 9. A power tracer that collects and holds a power supply state from the power supply unit of the system on which the bus device is mounted to the bus device;
The bus device according to any one of claims 4 to 8, wherein the data collection control unit further extracts and collects power data based on a power supply state held by the power tracer. An I / O tracer that collects and holds interrupt signals in a system including the bus device;
10. The bus according to claim 4, wherein the data collection control unit further extracts and collects interrupt signal data based on the interrupt signal held by the I / O tracer. device.   The data collection control unit extracts and collects at least one of the history data, the power supply data, and the interrupt signal data based on at least one of the second warning signal and the third warning signal. The bus device according to any one of claims 6 to 10, wherein data is extracted.   5. The data collection control unit outputs at least one of the collected history data, the power supply data, and the interrupt signal data to an external storage device via the internal bus. 12. The bus device according to any one of 11 above.   12. The internal memory circuit for storing at least one of the history data, the power supply data, and the interrupt signal data collected by the data collection control unit. The bus device according to item 1.  The data collection control unit outputs at least one of the collected history data, the power supply data, and the interrupt signal data to an external memory circuit through a peripheral module internal bus. The bus device according to claim 11.

Images