JP2008130788A - Macro cell - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To dispense with wiring route correction for evading crosstalk, to shorten the period of timing adjustment in a whole semiconductor integrated circuit, and to hold the perfection of a signal. <P>SOLUTION: A macro cell 100 includes: a semiconductor substrate 101; a plurality of wiring layers 102 arranged on the semiconductor substrate 101; and a plurality of input/output terminals where a bus signal is inputted/outputted. The terminals among the plurality of terminals, whose projected positions on a projection surface in parallel with the semiconductor substrate 101 are mutually adjacent, are arranged in the mutually different wiring layers 102. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a macro cell having input / output terminals for bus signals on a semiconductor substrate.

  In general, in a semiconductor integrated circuit, a desired circuit operation is realized by connecting a plurality of circuit elements including memory elements arranged on a semiconductor substrate with signal wirings made of a metal thin film. However, when the signal wiring is actually wired on the semiconductor substrate, the propagation time of the signal flowing through the signal wiring is fluctuated due to the influence of crosstalk caused by the wiring capacitance with other signal wiring, and the semiconductor integrated circuit In some cases, the normal operation of the circuit cannot be obtained because the timings of the signals flowing through the signal wirings do not match.

  In particular, a macrocell represented by a memory element is mostly provided with a multi-bit bus signal, and the propagation time of a signal flowing through a signal wiring is likely to vary due to the influence of crosstalk between the bit signals. Can be seen. For this reason, in the design stage of a semiconductor integrated circuit, when signal wiring is wired on a semiconductor substrate, it is important to reduce the influence of crosstalk with other signal wirings and reduce fluctuations in signal propagation time. ing.

In order to reduce the influence of crosstalk, for example, there is one in which the individual wirings constituting the bus wiring are interchanged with each other at an arbitrary position on the wiring (see, for example, Patent Document 1). In addition, there is a signal line of a different signal bus disposed between adjacent signal line pairs of the signal bus (see, for example, Patent Document 2).
In addition, as a technology for reducing fluctuations in signal propagation time due to the influence of crosstalk in a semiconductor integrated circuit, a signal whose signal propagation time fluctuates due to the influence of crosstalk after all signal wirings are wired in the semiconductor integrated circuit. Some wirings reduce the influence of crosstalk by increasing the wiring interval between signal wirings or inserting a shield wiring between signal wirings.
JP 2004-235542 A JP 2003-7823 A

  However, in order to widen the wiring interval between signal lines or to insert a shield wiring between signal lines, a wiring area for that purpose is required, and there is not always enough free space on the semiconductor substrate. Not necessarily.

  Therefore, in order to provide an empty area, not only the signal wiring affected by the crosstalk is changed, but also the wiring of the signal wiring that has already been timed or that is not affected by the crosstalk. May be forced to change.

  Then, due to this path change, if the delay amount of the signal wiring that is in timing changes and a new signal wiring that does not match timing appears, the signal wiring that was not affected by the crosstalk is crossed. There is a possibility that it will be affected by the talk and it will be difficult to converge the entire timing and maintain the integrity of the signal line.

  The present invention has been made paying attention to the above-mentioned problems, and does not require wiring path correction for avoiding crosstalk, realizing a short period of timing adjustment of the entire semiconductor integrated circuit and maintaining signal integrity. It aims to provide a possible macro cell.

In order to solve the above problems, one embodiment of the present invention provides:
A semiconductor substrate;
A plurality of wiring layers provided on the semiconductor substrate;
A plurality of terminals to which bus signals are input or output,
Among the plurality of terminals, terminals whose positions projected on a projection plane parallel to the semiconductor substrate are adjacent to each other are arranged in different wiring layers.

  According to the present invention, wiring path correction for avoiding crosstalk is unnecessary, and it is possible to realize a shortened period of timing adjustment of the entire semiconductor integrated circuit and maintenance of signal integrity.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following description of each embodiment and their modifications, components having the same functions as those described once will be assigned the same reference numerals and description thereof will be omitted. In addition, when there are a plurality of the same components (components having the same reference numerals) in the same drawing and it is necessary to distinguish between them, subscripts (A, B, C ·・ ・) Is added for identification.

Embodiment 1 of the Invention
FIG. 1 is a plan view of a macro cell 100 according to Embodiment 1 of the present invention as viewed from the upper side. FIG. 2 is a cross-sectional view of the macro cell 100 taken along lines I to I in FIG.

  The macro cell 100 includes a semiconductor substrate 101, a wiring layer 102, input / output terminals 103, and input / output terminals 104. Among these, a plurality of wiring layers 102, input / output terminals 103, and input / output terminals 104 are provided. As shown in FIG. 1 and the like, these are subscripts (A, B, C) after the reference numerals. To identify them.

  As shown in FIG. 2, the wiring layers 102 </ b> A to 102 </ b> B are formed on the semiconductor substrate 101.

  The input / output terminals 103A to 103C and the input / output terminals 104A to 104C are connected to other circuit elements (for example, macrocells) via signal wiring (input / output terminal connection wirings 105A to 105C and input / output terminal connection wirings 106A to 106C). And a multi-bit bus signal is input or output. The macro cell 100 and other circuit elements are connected to each other to constitute a semiconductor integrated circuit that realizes a desired circuit operation. The input / output terminal connection wires 105A to 105C and the input / output terminal connection wires 106A to 106C are made of a metal thin film.

  Among the input / output terminals 103 </ b> A to 103 </ b> C and the input / output terminals 104 </ b> A to 104 </ b> C, terminals whose positions projected on the projection plane parallel to the semiconductor substrate 101 are adjacent to each other are arranged in different wiring layers. In this embodiment, in each wiring layer, each input / output terminal is disposed on the side surface of the wiring layer.

  Specifically, for example, as shown in FIG. 1, the input / output terminal 103A and the input / output terminal 104A whose positions projected on the projection plane parallel to the semiconductor substrate 101 are adjacent to each other are as shown in FIG. These are arranged in different wiring layers 102A to 102B. That is, in this embodiment, the input / output terminals 103A to 103C are provided on the side surface of the wiring layer 102A, and the input / output terminals 104A to 104C are provided on the side surface of the wiring layer 102B.

  FIG. 3 shows an example of a macro cell having three wiring layers. In the macro cell 110, the input / output terminals 103A to 103C are disposed on the wiring layer 102A, the input / output terminals 104A to 104C are disposed on the wiring layer 102B, and the input / output terminals 111A to 111C are disposed on the wiring layer 102C.

  With the above configuration, in the macro cell 100 and the macro cell 110, the wiring layers of the input / output terminals can be different for each bit adjacent to the bus signal. That is, even if automatic wiring is performed in the layout process, it is possible to reduce the influence of crosstalk due to the parallel wiring of the signal wiring around the macro cell.

  Therefore, according to the present embodiment, it is not necessary to modify the wiring path for avoiding the influence of crosstalk. This makes it possible to eliminate the side effects of correction on signal wiring that is not affected by crosstalk and signal wiring that has been affected by wiring path correction. As a result, it is possible to reduce the timing adjustment of the entire semiconductor integrated circuit and maintain the integrity of the signal.

<< Embodiment 2 of the Invention >>
FIG. 4 is a perspective view of a macro cell 200 according to Embodiment 2 of the present invention, and is a diagram showing the arrangement of input / output terminals. 5 is a plan view of the macro cell 200 as viewed from above, and FIG. 6 is a cross-sectional view of the macro cell 200 taken along lines V to V in FIG.

  In the macro cell 200, not only the wiring layer but also a surface (arrangement surface) on which terminals on the wiring layer are arranged is different for each bit adjacent to each other.

  Specifically, in the macro cell 200, the input / output terminals 103A to 103C are provided on the upper surface (a surface parallel to the semiconductor substrate 101) of the wiring layer 102A. The input / output terminals 104A to 104C are provided on the side surface of the wiring layer 102B.

  Therefore, according to the macro cell 200, even if the automatic wiring of the layout process is performed, the input / output terminal connection wirings 105A to 105C connected to the input / output terminals 103A to 103C and the input / output terminals 104A as shown in FIG. It is possible to secure a sufficient wiring distance when viewed in cross section with the input / output terminal connection wirings 106A to 106C.

  Therefore, also in this embodiment, the wiring path correction for avoiding the influence of the crosstalk is not necessary, and other signal wirings having the same timing, which has been a problem due to the wiring path correction in the past, It becomes possible to eliminate the correction side effect on the signal wiring not affected by the crosstalk. As a result, it is possible to shorten the period of timing adjustment of the entire semiconductor integrated circuit and maintain signal integrity.

<< Embodiment 3 of the Invention >>
FIG. 7 is a diagram illustrating input / output terminals of the macro cell 300 according to the third embodiment of the present invention. The macro cell 300 is configured by adding a plurality of shielding terminals 301 to the macro cell 100 of the first embodiment. FIG. 7 shows a shield terminal 301 provided on the wiring layer 102A, and each shield terminal 301 is identified by adding a suffix of A to D after the reference numeral.

  The shield terminals 301A to 301D are provided between the respective bits of the input / output terminals, and the shield wirings 302A to 302D are respectively connected thereto.

  That is, in this embodiment, since the shielding terminals are provided between the input / output terminal connection wirings, even if automatic wiring is performed in the layout process, the influence of crosstalk between the input / output terminal connection wirings. Can be reduced. For example, the shield wiring 302B is formed between the input / output terminal connection wiring 105A and the input / output terminal connection wiring 105B, and the shield wiring 302C is formed between the input / output terminal connection wiring 105B and the input / output terminal connection wiring 105C. Therefore, it is possible to reduce the influence of crosstalk due to signal transition of the input / output terminal connection wiring 105A and the input / output terminal connection wiring 105C.

  Therefore, according to the present embodiment, it is possible to more reliably avoid the influence of crosstalk. Conventionally, other signal wirings having the appropriate timing, which have been a problem due to wiring path correction, It becomes possible to eliminate the correction side effect on the signal wiring not affected by the crosstalk. As a result, it is possible to shorten the period of timing adjustment of the entire semiconductor integrated circuit and maintain signal integrity.

<< Embodiment 4 of the Invention >>
FIG. 8 is a diagram illustrating input / output terminals of the macro cell 400 according to the fourth embodiment of the present invention. The macro cell 400 is provided with a plurality of ground terminals 401 as the shield terminals 301 </ b> A to D of the macro cell 300. FIG. 8 shows a grounding terminal 401 provided on the wiring layer 102A. Each grounding terminal 401 is identified by adding an A to D suffix after the reference numeral. The ground terminals 401 </ b> A to 401 </ b> D are grounded via the ground connection wiring 402.

  Thus, in the present embodiment, even if the automatic wiring is performed in the layout process, for example, the ground connection wiring 402 is formed between the input / output terminal connection wiring 105A and the adjacent input / output terminal connection wiring 105B, and the shield wiring The effect is obtained. Also, the distance between each bit signal is secured. Therefore, the influence of crosstalk due to signal transition between adjacent input / output terminal connection wirings can be reduced. Therefore, as in the first embodiment, by correcting the wiring path for avoiding the influence of the crosstalk, the correction side effect on the signal wiring having another timing or the signal wiring not affected by the crosstalk is eliminated. As a result, it is possible to shorten the timing adjustment of the entire semiconductor integrated circuit and to maintain the signal integrity.

  Furthermore, since a ground wiring is formed between the input / output terminal connection wirings and the ground wiring to the macro cell is strengthened, it can be expected to suppress IR-DROP (voltage drop) inside the macro cell.

<< Embodiment 5 of the Invention >>
FIG. 9 is a diagram illustrating input / output terminals of the macro cell 500 according to the fifth embodiment of the present invention. The macro cell 500 is provided with a plurality of power supply terminals 501 as the shield terminals 301 </ b> A to D of the macro cell 300. FIG. 9 shows a power supply terminal 501 provided on the wiring layer 102A, and each power supply terminal 501 is identified by adding an A to D suffix after the reference numeral. The power supply terminals 501A to 501D are connected to a power supply via a power supply connection wiring 502.

  As a result, even if the automatic wiring is performed in the present embodiment or the layout process, for example, the power connection wiring 502 is formed between the input / output terminal connection wiring 105A and the adjacent input / output terminal connection wiring 105B, and the shield wiring The effect is obtained. Also, the distance between each bit signal is secured. Therefore, the influence of crosstalk due to signal transition between adjacent input / output terminal connection wirings can be reduced. Therefore, as in the first embodiment, by correcting the wiring path for avoiding the influence of the crosstalk, the correction side effect on the signal wiring having another timing or the signal wiring not affected by the crosstalk is eliminated. As a result, it is possible to shorten the timing adjustment of the entire semiconductor integrated circuit and to maintain the signal integrity.

  In addition, since the power supply wiring is formed between the input / output terminal connection wirings and the power supply wiring to the macro cell is strengthened, suppression of IR-DROP (voltage drop) inside the macro cell can also be expected.

Embodiment 6 of the Invention
FIG. 10 is a diagram illustrating input / output terminals of the macro cell 600 according to the sixth embodiment of the present invention. The macro cell 600 is provided with a plurality of floating wiring terminals 601 as the shielding terminals 301 </ b> A to 301 </ b> D of the macro cell 300. FIG. 10 illustrates a floating wiring terminal 601 provided on the wiring layer 102A, and each floating wiring terminal 601 is identified by adding an A to D suffix after the reference numeral. The floating wiring terminals 601A-D are connected to the floating wirings 602A-D. Thereby, the effect of shield wiring is acquired.

  Therefore, even in this embodiment, even if automatic wiring is performed in the layout process, for example, the floating wiring 602 is formed between the input / output terminal connection wiring 105A and the adjacent input / output terminal connection wiring 105B, and the effect of the shield wiring is improved. can get. Also, the distance between each bit signal is secured. Therefore, the influence of crosstalk due to signal transition between adjacent input / output terminal connection wirings can be reduced. Therefore, as in the first embodiment, by correcting the wiring path for avoiding the influence of the crosstalk, the correction side effect on the signal wiring having another timing or the signal wiring not affected by the crosstalk is eliminated. As a result, it is possible to shorten the timing adjustment of the entire semiconductor integrated circuit and to maintain the signal integrity.

  In combination with Embodiments 4 to 6, an input / output terminal connection wiring pair with a floating wiring in between, an input / output terminal connection wiring pair with a ground wiring in between, and an input / output terminal connection with a power supply wiring in between The wiring pairs may be mixed.

<< Embodiment 7 of the Invention >>
FIG. 11 is a block diagram showing a configuration of a macro cell 700 according to Embodiment 7 of the present invention. The macro cell 700 is an example of a macro cell that can vary the drive capability of an output cell connected to an input / output terminal. This output cell can be applied to any of the first to sixth embodiments. FIG. 11 illustrates an output cell on the wiring layer 102A.

  As shown in FIG. 11, the macro cell 700 has an internal terminal 701, a drive cell 702A, a drive cell 702B, an inverter 703, and a drive capability switching terminal 704, one for each bit of the output signal. Is provided.

  The internal terminal 701 is configured to receive an output signal from the inside of the macro cell 700.

  The driving cell 702A and the driving cell 702B are tristate buffers having different driving capabilities. Each input of the drive cell 702A and the drive cell 702B is connected to the corresponding internal terminal 701, and each output is connected to the same input / output terminal.

  The drive capability switching terminals 704A to 704B are configured to receive a control signal for controlling whether or not the drive cells 702A to 702B can output. The control signal input from the drive capability switching terminal 704 is input to the control terminal of the drive cell 702A, and whether or not the drive cell 702A can output is controlled.

  The inverter 703 inverts the control signal input from the drive capability switching terminal 704 and outputs the inverted signal to the control terminal of the drive cell 702B.

  With the above configuration, one of the drive cell 702A and the drive cell 702B becomes ready for output in accordance with the control signal input from the drive capability switching terminal 704.

  That is, in the present embodiment, the drive capability of the output terminal can be switched from outside the macro cell. Therefore, when a timing error or glitch occurs in the signal wiring due to the influence of the crosstalk, the crosstalk can be reduced by switching the driving capability of the input / output terminals from the outside. In other words, even if crosstalk occurs, it is possible to avoid the influence of crosstalk without changing the route of the wiring around the macro cell. As a result, the timing adjustment of the entire semiconductor integrated circuit can be shortened and the signal can be completely transmitted. Can be maintained.

  As shown in FIG. 12, a control signal may be input from a separate drive capability switching terminal 704 to the control terminals of the drive cell 702A and the drive cell 702B.

  Further, as shown in FIG. 13, three or more drive cells (four in this example) may be provided in each input / output terminal. In this case, a selection circuit 705 for selecting any one drive cell is provided in accordance with the input control signal. In this example, since four drive cells are provided, a 2-bit control signal is given to the selection circuit 705 using two drive capability switching terminals 704 for each input / output terminal. As a result, the driving ability can be varied in four stages.

<< Embodiment 8 of the Invention >>
FIG. 14 is a block diagram showing a configuration of a macro cell 800 according to Embodiment 8 of the present invention. The macro cell 800 is an example of a macro cell including a plurality of output terminals 802 having different driving capabilities for each bit. As shown in FIG. 14, the macro cell 800 includes a plurality of internal terminals 701, drive cells 801, and output terminals 802.

  A plurality of drive cells 801 are provided corresponding to one internal terminal 701 (that is, one bit). In the example shown in FIG. 14, two drive cells 801 </ b> A and B are provided corresponding to one internal terminal 701. The output terminal 802 is provided corresponding to each drive cell 801. In the example of FIG. 14, the drive cells 801 corresponding to the same bit and the output terminals 802 corresponding to the same bit are identified by adding a suffix (A, B) after the code.

  In the macro cell 800, the drive cells 801 corresponding to the same bit (drive cells 801A and B in the example of FIG. 14) have different drive capabilities. Each of them receives a signal from the corresponding internal terminal 701, and its output is connected to different output terminals 802 (in the example of FIG. 14, the output terminal 802A and the output terminal 802B).

  Therefore, according to the present embodiment, it is possible to select the output terminal 802 (output terminal 802A and output terminal 802B) having different driving capabilities for each bit. Thereby, when a timing error or a glitch occurs in the signal wiring due to the influence of the crosstalk, the crosstalk can be reduced by appropriately selecting an input / output terminal used for output.

  In the macro cell 800, each bit may have a different driving capability.

  The macro cell according to the present invention does not require a wiring path correction for avoiding crosstalk, has the effect that the timing adjustment of the entire semiconductor integrated circuit can be shortened and the integrity of the signal can be realized, and the semiconductor substrate It is useful as a macro cell having input / output terminals for the above bus signals.

FIG. 3 is a plan view of the macro cell 100 according to Embodiment 1 as viewed from the upper side. FIG. 2 is a cross-sectional view of the macro cell 100 taken along lines I to I in FIG. 1. It is an example of a macro cell having three wiring layers. 6 is a perspective view of a macro cell 200 according to Embodiment 2. FIG. It is the top view which looked at the macrocell 200 from the upper side. It is sectional drawing of the macrocell 200 along VV of FIG. FIG. 6 is a diagram illustrating input / output terminals of a macro cell 300 according to a third embodiment. 6 is a diagram showing input / output terminals of a macro cell 400 according to Embodiment 4. FIG. FIG. 10 is a diagram illustrating input / output terminals of a macro cell 500 according to a fifth embodiment. FIG. 10 is a diagram illustrating input / output terminals of a macro cell 600 according to a sixth embodiment. FIG. 10 is a block diagram illustrating a configuration of a macro cell 700 according to Embodiment 7. FIG. 10 is a block diagram showing a modification of the macro cell 700 according to the seventh embodiment. FIG. 10 is a block diagram showing a modification of the macro cell 700 according to the seventh embodiment. FIG. 10 is a block diagram illustrating a configuration of a macro cell 800 according to an eighth embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Macrocell 101 Semiconductor substrate 102 Wiring layer 103 Input / output terminal 104 Input / output terminal 105 Input / output terminal connection wiring 106 Input / output terminal connection wiring 110 Macrocell 111 Input / output terminal 200 Macrocell 300 Macrocell 301 Shield terminal 302 Shield wiring 400 Macrocell 401 For grounding Terminal 402 Ground connection wiring 500 Macro cell 501 Power supply terminal 502 Power connection wiring 600 Macro cell 601 Floating wiring terminal 602 Floating wiring 700 Macro cell 701 Internal terminal 702 Driving cell 703 Inverter 704 Driving ability switching terminal 705 Selection circuit 800 Macro cell 801 Driving Cell 802 Output terminal

Claims (6)

A semiconductor substrate;
A plurality of wiring layers provided on the semiconductor substrate;
A plurality of terminals to which bus signals are input or output,
Among the plurality of terminals, terminals whose positions projected on a projection plane parallel to the semiconductor substrate are adjacent to each other are arranged in different wiring layers. The macrocell of claim 1,
2. A macrocell according to claim 1, wherein, among the plurality of terminals, terminals whose positions projected on a projection plane parallel to the semiconductor substrate are adjacent to each other have different arrangement planes on the wiring layer. The macrocell of claim 1,
Furthermore, the macrocell characterized by having a terminal for shielding for every terminal which the position projected on the projection surface parallel to the said semiconductor substrate adjoins mutually. The macrocell of claim 3,
Each of the shielding terminals is one of a grounding terminal, a power supply terminal, and a floating wiring terminal. The macrocell of claim 1,
The macro cell characterized in that the plurality of terminals can vary the driving capability. The macrocell of claim 1,
Furthermore, it includes two drive cells with different drive capabilities from each other,
The two drive cells have the same signal as input,
Each of the outputs of the two drive cells is connected to a different terminal of the plurality of terminals, respectively.

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