JP2008124376A - Method of connecting element substrate - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of connecting an element substrate with which a GaN-LED array or the like formed on a transparent substrate can be packaged with high density and removal of a growth substrate is not required, as for other than GaN-LED. <P>SOLUTION: The disclosed method includes the steps of: aligning a transparent substrate 101 and a circuit board 106; injecting photo-sensitive fillers 111 between the transparent substrate 101 and the circuit board 106; irradiating light from a side of the transparent substrate 101 and exposing the fillers with wiring 105 of the relevant substrate as a light shielding mask; forming a void 403 between wiring of the transparent substrate 101 and the circuit board 106 by dissolving a light nonirradiated part of the exposed fillers; and embedding a conductive material within the void 403 and electrically connecting the wiring of the transparent substrate and the circuit board. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to an element substrate connection method requiring high-density wiring, and more particularly to an element substrate connection method suitable for mounting an optical element array chip formed on a transparent substrate on a circuit board.

  In recent years, LED arrays have been developed in the field of electrophotographic and pattern exposure apparatuses for printed wiring boards or high-luminance and high-definition displays. In the LED array, PN junction diodes of optical semiconductors such as GaAs, AlInGaP, and GaN are arranged and formed on a growth substrate in a minute and high density by a semiconductor process.

  A typical example of the size and pitch of the LED array formed on the growth substrate is, for example, a size of 300 μm to 5 μm, and a resolution as a pattern exposure apparatus is 100 dpi (dot per inch) to 2400 dpi. Research and development aimed at more than that is underway.

  As described above, it is relatively easy for an LED array to form a minute and high-density array of LEDs and wiring connected to the LEDs by a semiconductor process, and the high definition reaches 10 μm or less.

  However, when wire bonding is performed at the stage of connecting the LED array chip to a circuit board such as a driver, the wiring interval needs to be 40 μm to 100 μm. For example, it cannot be used at a pitch of 10 μm and 2400 dpi. On the other hand, a connection method that does not use wire bonding has been proposed.

  For example, Patent Document 1 discloses a mounting method using bumps. That is, an example is disclosed in which the LED array chip formed on the GaAs substrate is flip-chip mounted by bumps with the element surface facing the circuit substrate. In the method of this document, when bumps are first formed and connected by pressure bonding, the size of the bumps is currently limited to 20 to 30 μm and cannot be applied to a pitch of 10 μm or less.

  On the other hand, Patent Document 2 discloses a mounting method using metallization. That is, a method is disclosed in which an LED array chip formed on a GaAs substrate is bonded with an element surface facing a circuit substrate through an insulating layer, and then a GaAs growth substrate that is opaque and thick with respect to the emission wavelength is removed. Yes. According to the method of this document, a device film thickness that enables metallization over the formation of a via hole or over a step can be realized, and high-density mounting can be realized.

By the way, in recent years, blue LED arrays using GaN semiconductors have been developed, and it is conceivable to use the blue LED arrays as exposure light sources and the like. The blue LED array has the characteristic that the emission intensity does not decrease even when the defect density of the semiconductor crystal is high compared to other compound optical semiconductors such as GaAs, and it has an advantage when the light emitting element is miniaturized. (Non-Patent Document 1).
US Pat. No. 5,612,225 US Pat. No. 5,940,683 Choi, et.al., Applied Physics Letters Vol.83, Number 22, pp.4483 (2003)

  It is difficult to increase the density by directly applying the technique described in Patent Document 2 to a GaN-LED. That is, the growth substrate of the GaN-LED is a sapphire substrate or a GaN substrate, and unlike the GaAs substrate, its removal is not easy.

  There is virtually no etchant that can wet-etch thick films, and some sapphire substrates have a small spot unit called laser lift-off, but it is difficult to increase the area and the cost is high. There is also a problem of damage. Further, since the sapphire substrate is transparent to the blue light emission wavelength, it is not necessary to remove the substrate for purposes other than metallization.

  An object of the present invention is to enable high-density mounting of a GaN-LED array or the like formed on a transparent substrate. In addition to the GaN-LED, a method for connecting element substrates that does not require removal of the growth substrate is provided.

  In the present invention, the first substrate and the second substrate are electrically connected to each other when the connection portions of the first and second substrates are electrically opposed to each other with the first and second substrates having at least one substrate having optical transparency. The alignment with the second substrate is performed, and a photosensitive filler is disposed between the first and second substrates. Thereafter, light is irradiated from the light transmissive substrate side of the first and second substrates, and the filler is exposed using the connection portion of the substrate as a light shielding mask. Further, the non-photosensitive portion of the filler after exposure is dissolved to form a cavity between the connecting portions of the first and second substrates, and a conductive material is embedded in the cavity to fill the first and second substrates. Are electrically connected to each other.

  In the present invention, the first and second substrates having at least one substrate facing each other are opposed to each other, and the connection portions of the first and second substrates are electrically connected to each other. The substrate and the second substrate are aligned, and a photosensitive filler is disposed between the first and second substrates. Thereafter, light is irradiated from the light transmissive substrate side of the first and second substrates, and the filler is exposed using the electric wiring portion of the substrate as a light shielding mask. Further, the non-photosensitive portion of the filler after exposure is dissolved to form a cavity between the first and second substrates, and a conductive material is provided in the cavity to connect the first and second substrates. Connect each other electrically.

  According to the present invention, it is possible to connect the connection portions of two substrates at a high density without removing the transparent substrate. In particular, it can be suitably used for connection of element substrates when a blue LED array is used.

  Next, the best mode for carrying out the invention will be described in detail with reference to the drawings.

(First embodiment)
FIG. 1 is a cross-sectional view showing two substrates connected by an element substrate connection method according to the present invention. The two substrates are a transparent substrate 101 and a circuit substrate 106. An LED element 102 is mounted on the transparent substrate 101, and a circuit 107 such as a drive circuit for the LED element 102 is mounted on the circuit board 106.

  FIG. 2A is a plan view of the transparent substrate 101 on which the array of the LED elements 102 and the wiring 105 are formed as seen from above. FIG. 2B is a plan view of the circuit board 106 in which the circuit 107 is formed inside the substrate and the wiring 108, the wiring 110, and the connection bumps 109 are formed on the substrate surface, as viewed from above.

  FIG. 1 is a cross-sectional view in which the two circuit boards are connected with their upper surfaces (front surfaces) facing each other, that is, the transparent substrate 101 is connected upside down, and the cross section taken along the line AA ′ in FIG. Corresponding. This has a so-called flip chip configuration.

  Hereinafter, the outline of the substrate connecting method according to the present embodiment will be described with reference to FIG. In FIG. 1, an LED element 102 is a pn junction diode composed of an n-type GaN-based semiconductor from the transparent substrate 101 side and a p-type GaN-based semiconductor on the surface side with an active layer interposed therebetween. An electrode 104 is formed on the p side by vapor-depositing a Ni / Au two-layer metal thin film. At that time, in order to avoid unnecessary conduction, the SiN-based insulating film 103 is patterned, and the electrode 104 is in contact only with the opening.

  The n-side electrode 105 is formed by vapor-depositing a Ti / Al two-layer metal thin film. In this embodiment, the n-side electrode 105 is formed by extending on the transparent substrate 101 as an n-side wiring layer. Yes. The LED elements 102 are arrayed one-dimensionally at a pitch of 10 μm, the size of the p-electrode 104 is about 2 μm square, the thickness of the n-electrode / wiring 105 is about 5 μm, and the pitch between the wirings is 10 μm.

  The circuit board 106 is a Si substrate, and a circuit 107 for driving the LED element is formed therein. In the present embodiment, a plurality of MOS transistors are formed, and a circuit 107 that performs switching of lighting / non-lighting of the LED element 102 by a combination of a transfer gate and a logic circuit is formed.

  The connection from the circuit 107 to the LED element 102 is performed through two wirings formed on the surface of the circuit board 106 of the wiring 108 wired from the common electrode on the + side and the wiring 110 that is the individual wiring on the negative side. The negative side wiring 110 is formed with a thickness of about 5 μm and a wiring pitch of 10 μm.

  A bump 109 is formed on the wiring 108 on the + side wiring, and the bump 109 is connected to the p electrode 104 of the LED element 102 by pressure bonding. The gap between the two substrates is about 20 μm, and the gap 111 is filled with a filler 111. As for the minus side wiring, after an array-like cavity is formed between the wiring 110 and the wiring 105, the corresponding upper and lower wirings between the substrates are connected by the plated metal 112.

  FIG. 3 is a bird's eye view showing an outline of the wiring portion. A filler 111 is filled between the transparent substrate 101 and the circuit substrate 106, and a cavity formed immediately below the wiring 105 is embedded with a plated metal 112. FIG. 3 three-dimensionally shows a state where the wiring 110 on the circuit board 106 side and the wiring 105 on the transparent substrate 101 side are connected.

  In this way, the LED element 102 emits light by controlling and energizing from the circuit board 106 side with the + and − sides connected. The emitted light 113 passes through the transparent substrate 101 and is extracted to the upper surface.

  Next, the substrate connection method according to the present embodiment will be described in detail for each process with reference to FIG. FIG. 4A shows a substrate placement process. A transparent substrate 101 on which elements and circuits are formed and a circuit substrate 106 are arranged to face each other. In this case, automatic alignment between the wiring 105 and the wiring 110 of the two substrates is performed using a camera.

  FIG. 4B shows a substrate connection process. In FIG. 4B, the alignment of the two substrates is completed in the alignment process of FIG. In this step, the p-electrode (array) 104 of the transparent substrate 101 and the bumps 109 of the circuit substrate 106 are connected by pressure bonding. When crimping, heat and ultrasonic waves can be applied, and conditions are set as appropriate. It is also possible to separately provide a spacer in a portion other than the bump 109 to manage the gap after the pressure bonding.

  FIG. 4C shows a filler placement step. In this step, a so-called underfill agent (filler) 111 is filled in the gap formed between the substrates. By underfilling, the reliability of the mounted substrate can be increased, and at the same time, this can be used as a mold for plating connection described later. As the underfill agent, a negative photosensitive type novolak photoresist is used. A negative type photoresist can be used as a photo-curing resin that is photo-cured by irradiating with ultraviolet rays from blue, and if a mask pattern is used during photo-sensitivity, it is possible to easily form a fine shape at the μm level. A photo-curing resin may be used as the filler 111.

  FIG. 4D shows a light exposure process. In this step, exposure light 401 is irradiated from the transparent substrate 101 side to partially expose the filler 111. In the photosensitive and non-photosensitive processes, the transparent substrate 101 on which the wiring 105 is formed functions as if it is a contact exposure photomask. That is, a portion corresponding to the light-shielding material on the transparent substrate 101 such as immediately below the wiring portion 105 is a non-photosensitive portion, and other portions are photosensitive portions that are exposed to light transmitted through the transparent substrate 101.

  An ultrahigh pressure mercury lamp is used as the exposure light source. The exposure wavelength is mainly i-line (365 nm) and h-line (405 nm). The wiring to be a mask is a 5 μm line and space, and has a line width that can be charged and decomposed by contact exposure.

  FIG. 4E shows the development process. In this step, the non-photosensitive portion 402 of the filler 111 that has been exposed to light is dissolved using a developer. This is performed by immersing the non-photosensitive portion 402 in a developer. In this embodiment, an alkaline developer corresponding to a novolac type photoresist is used. As a result, a cavity 403 is formed between the corresponding upper and lower wirings immediately below each wiring. Depending on the conditions, the exposure amount (light illuminance × exposure time) and the development time can be adjusted as appropriate to optimize the shape of the cavity.

  FIG. 4F shows a plating connection process. In this step, the wiring 105 and the wiring 110 are connected by the plated metal 112. In this embodiment, it is formed by electroless Ni plating and flash gold plating. The surfaces of the wiring 105 and the wiring 110 are made of Al. The plating process is performed as follows.

  First, as pretreatment, the oxide film is removed by acid cleaning using nitric acid, and then the surface of Al is replaced with Zn by a zincate-containing zincate solution to deposit Zn.

  After that, it is immersed in a plating bath of 80-90 ° C., which is mainly composed of a complexing agent prepared by mixing nickel sulfate, sodium hypophosphite, succinic acid, etc., and adjusted to PH 4-5 with a PH adjusting agent containing sodium hydroxide. A Ni plating film is grown. After the Ni films grown from the upper and lower wirings are in contact, the growth continues for a while.

  This is to increase the contact area and improve the connection. After the Ni plating, the Ni surface is replaced with Au by flash Au plating using a plating bath mainly composed of potassium gold cyanide and a complexing agent and adjusted from weakly acidic to neutral by a pH adjusting agent. A water washing treatment is performed between the above steps as necessary.

  Through the above steps, the transparent substrate 101 and the circuit board 106 can be connected with a 5 μm line width and a 10 μm pitch, and a high-density LED array of 2400 dpi or more can be mounted. Therefore, for example, it can be suitably used for the connection of the element substrate when the blue LED array as described above is used.

(Second Embodiment)
Next, a second embodiment of the present invention will be described with reference to FIGS. In this embodiment, electric Au plating is used as a plating method, and by introducing a plating process with higher selectivity, it is possible to achieve a reliable and productive connection even at a further narrow pitch. .

  Further, as the wiring of the LED element, a method of performing array wiring on the p side and common wiring on the n side is used, and the common wiring on the n side is taken out to the back side of the transparent substrate through the through hole 501 penetrating the transparent substrate 101. Is. In addition, the photosensitive filler is introduced by coating before connecting the substrate.

  FIG. 5 is a sectional view showing two substrates connected by the connection method of the present embodiment. The two substrates are a transparent substrate 101 and a circuit substrate 106. On these two substrates, LED elements and circuits are formed as in FIG.

  FIG. 6A is a top view of the transparent substrate 101 on which the array of the LED elements 102, the wiring 105, and the n-electrode 503 are formed. FIG. 6B is a top view of the circuit board 106 on which the wiring 110 is formed on the substrate surface, the insulating film 505 covering a part of the wiring 110, and the electroplating power supply pad 504 to which the wiring 110 is connected together. is there.

  FIG. 5 is a cross-sectional view showing a state in which the two substrates face each other, that is, the transparent substrate 101 is connected upside down, and is shown in a cross-section at BB ′ in FIG. Correspond. This has a so-called flip chip configuration.

  Next, the outline of the substrate connecting method according to the present embodiment will be described with reference to FIG. In FIG. 5, an LED element 102 is a pn junction diode composed of an n-type GaN-based semiconductor from the transparent substrate 101 side and a p-type GaN-based semiconductor on the surface side with an active layer interposed therebetween. An electrode 104 is formed by vapor-depositing a Ni / Au two-layer metal thin film on the p side, but an SiN-based insulating film 103 is patterned to avoid unnecessary conduction, and an electrode is formed only at the opening. 104 is in contact.

  The p-side electrode 104 is connected to an arrayed individual wiring 105. The wiring 105 is formed by depositing a Ti / Au thin film on the insulating film 103.

  For the n-side wiring, a transparent substrate in which through-holes 501 formed by laser processing in advance are electrically connected by plating is prepared, and the n-GaN layer of LED element 102 and the metal of through-hole 501 are connected on the front side. Ti / Al two-layer thin film metal wiring 502 is deposited.

  Similarly, a Ti / Al two-layer metal thin film is vapor-deposited on the back side of the through-hole 501 to form a wiring 503, which is connected to the negative side of the circuit inside the circuit board 106 at a portion (not shown) as a negative common electrode. ing. Laser processing is performed by condensing the light spot to about 30 μm using the third harmonic of the YAG crystal pulse laser.

  The transparent substrate 101 to be processed is a sapphire substrate and a GaN layer, and the thickness is 450 μm. The thickness can be reduced to about 70 μm by grinding and polishing in advance. The diameter of the through hole 501 to be processed is 30 to 100 μm. The YAG laser can be processed by a second harmonic as well as the third harmonic, and the conditions can be appropriately selected depending on the state of damage, processing waste, or the like.

  The LED elements 102 are an array arranged one-dimensionally at a pitch of 10 μm. The size of the p electrode 104 is about 2 μm square, the thickness of the p-side wiring 105 is about 5 μm, and the pitch between the wirings is 10 μm.

  On the other hand, the + side wiring from the circuit to the LED element 102 is performed using a normal Si-LSI process such as a via hole (not shown) through the wiring 110 which is an array individual wiring. The + -side wiring 110 is formed with a thickness of about 5 μm and a wiring pitch of 10 μm.

  The gap between the two substrates is about 20 μm, and the gap is filled with a filler 111. After forming an array-like cavity between the wirings 110 and 105, the negative side wiring is formed by the plating metal 112. Corresponding upper and lower wirings between the two substrates are connected.

  FIG. 7 is a bird's eye view showing an outline of the wiring portion. A filler 111 is filled between the transparent substrate 101 and the circuit substrate 106, and a cavity formed immediately below the wiring 105 is embedded with a plated metal 112. FIG. 7 three-dimensionally shows a state in which the wiring 110 on the circuit board 106 side and the wiring 105 on the transparent substrate 101 side are connected.

  Next, the substrate connection method of this embodiment will be described. The substrate connection process is basically the same as that shown in FIG. 4 except for the substrate connection process, filler placement process, and plating connection process. In the present embodiment, the order of the substrate connecting step and the filler arranging step is reversed, and the substrate is connected after the filler is arranged. Hereinafter, mainly different steps will be described.

  First, the alignment process of the two substrates is performed in the same manner as in FIG. 4, and then the process proceeds to the filler arrangement process. In the filler arranging step, a so-called underfill agent is applied by a spin coater. After coating, the process proceeds to the substrate connection process without drying and baking.

  In the substrate connecting step, the transparent substrate 101 and the circuit substrate 106 are joined by pressure bonding with a spacer interposed therebetween. In this step, the two substrates are simply joined. After joining, baking is performed as necessary. The baking conditions are, for example, 90 ° C. and 20 minutes in the atmosphere. Thereafter, the exposure process and the development process are performed in the same manner as in FIG. When the development process is completed, the process proceeds to the plating connection process.

  In the plating connection step, the wiring 105 and the wiring 110 are connected by electroplating. The surfaces of the wiring 105, the wiring 110, and the power supply pad 504 are formed of Au. The process of connecting the Aus together by electroplating is performed as follows.

  First, as pretreatment, degreasing treatment with an organic solvent and acid cleaning are performed. The power supply pad 504 is connected to the cathode side and immersed in a plating bath. The anode is energized using Pt. The plating bath is, for example, a neutral bath of about 65 ° C. adjusted to PH 5.5 to 7.5, mainly composed of potassium gold cyanide, potassium dihydrogen phosphate, dipotassium hydrogen phosphate, citric acid and the like. . A water washing treatment is performed between the above steps as necessary.

  The wiring 110 is supplied with power through the power supply pad, and Au grows in a portion where the wiring surface is exposed. The plating solution is supplied from the end where the substrates are connected, the cavity is filled, and the upper and lower wirings 105 and 110 are connected, but Au grows only from the wiring 110 on the circuit board 106, and the transparent substrate 101 side The wiring 105 does not grow. The insulating film 505 is formed in order to prevent Au from growing outside the end portion and blocking the entrance of the cavity.

  Through the above steps, the substrates are electrically connected with high density at a pitch of 10 μm by electric Au plating. However, since the array wirings are connected in common by the power supply pad 504, it is necessary to separate them in order to drive individually. The broken lines c-c 'and C-C' shown in FIGS. 5 to 7 indicate that the circuit board is separated at this position by cutting, cleavage, or the like after the plating is finished. By separating at this position, the array wiring is electrically separated, and the LED elements connected to each can be driven independently.

  In the present embodiment, in addition to the effects of the first embodiment, since the transparent substrate is not removed, it is resistant to scratches and strong, and thus has an effect of helping to protect the element.

(Third embodiment)
In this embodiment, the circuit board is connected in wafer size, and the transparent substrate is connected in chip size. It is possible to mount only the non-defective transparent substrate LED chip only on the non-defective part of the circuit board wafer, and the yield can be increased.

  FIG. 8 is a schematic view of mounting a transparent substrate LED array chip on a circuit board wafer. Circuit board chips 106 are formed in a grid pattern on the circuit board wafer 801, and each is in a state before being divided. In this state, first, a circuit defect is measured. This is recorded for the defective chip portion 802.

  Next, only the non-defective product of the transparent substrate LED array chip produced on the separately produced transparent substrate wafer is connected to the circuit board chip 106 using the connection method of the present invention as described above. FIG. 8 is a schematic diagram showing a configuration in which three transparent substrate LED array chips are arranged and connected in series to one circuit board chip.

  Thus, the yield can be improved by selecting and connecting only non-defective products. In addition, since the connection method of the present invention enables such wafer-level connection, of course, the same effect can be obtained if the two are connected in a divided state. Efficiency is reduced because parts of size must be handled. Since the method of the present invention can be connected even at a wafer size, the yield can be improved and the efficiency can be improved.

  The present invention is not limited to the above embodiment, and the sequence and the like can be variously changed. In addition to the following configuration, the device configuration of the LED light source or the light source array can be selected and used as appropriate.

  For example, in the above-described embodiment, the LED elements are all connected to the same common electrode, so-called static drive configuration, but the wiring and drive may be so-called matrix type. In this case, the common electrode side may be divided into a plurality of blocks and connected to the drive circuit, and a configuration capable of time-series block scanning may be used.

  In addition to the above embodiment, a wide variety of plating connection processes can be used. For example, it goes without saying that activation treatment with Pd can be used instead of zincate treatment in the pretreatment of electroless plating, or a non-cyan bath can be used in electroplating.

  In the first embodiment, the filler is injected after the bump connection. However, when using the bump connection method in which anisotropic conductive particles are mixed, the bump is used and the filler is arranged first. It is also possible.

  Furthermore, in the above-described embodiment, the LED element of the light emitting element has been described, but the light emitting element may be a laser diode or a surface emitting type. In addition to the light emitting element, the light receiving element is useful because the light transmitted through the transparent substrate can be received by the high-density array, and the light modulation element is an element that brings about a change in reflectance and transmittance by electric drive. It is also possible to mount the array at a high density.

  Further, as the GaN element, in addition to the optical element, a transistor element excellent in high voltage resistance and environmental resistance can be mounted with high density by using the method of the present invention.

  Furthermore, although the example which connects the transparent substrate 101 and the circuit board 106 was shown, this invention is not limited to this, At least one should just be a transparent substrate. Moreover, although the example which connects wiring is shown, this invention is not limited to this. For example, it can be used for connection between various connection parts such as connection between electrodes formed on a substrate or connection between electrodes and wiring.

(Fourth embodiment)
FIG. 9 is a schematic view showing an embodiment when an LED print head of an electrophotographic printer is configured using the connection method of the present invention.

  A plurality of circuit board chips 106 and transparent substrate LED array chips 101 mounted by the method described in the third embodiment are fixed to the base body 901 and connected to a driving power source and a controller by wires (not shown). .

  The emitted light 113 from the transparent substrate LED chip 101 is imaged on the photosensitive drum 903 by an erecting equal-magnification imaging system 902 fixed at a predetermined position. In this embodiment, as the erecting equal-magnification imaging system 902, a lens array in which refractive index distribution type fiber lenses 902 are arrayed is used. In this way, a high-resolution print head of 2400 dpi or more using a GaN optical semiconductor can be realized.

  The substrate connection method of the present invention can be used for a high-definition display or the like as another application example.

It is a schematic diagram which shows 1st Embodiment of the connection method of the element substrate which concerns on this invention. It is a schematic diagram which shows the upper surface of the two board | substrates of FIG. FIG. 2 is a bird's-eye view showing in detail the vicinity of a connection portion between the wiring patterns of the two substrates in FIG. 1. It is a schematic diagram which shows each process of the connection method of the element substrate which concerns on this invention. It is sectional drawing which shows the 2nd Embodiment of this invention. It is a schematic diagram which shows the upper surface of the two board | substrates of FIG. It is a bird's-eye view which shows the connection part vicinity of the wiring pattern of 2nd Embodiment in detail. It is a schematic diagram which shows the 3rd Embodiment of this invention. It is a perspective view which shows the 4th Embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 101 Transparent substrate 102 LED element 103 Insulating film 104 Electrode 105 Wiring 106 Circuit board 107 Circuit 108 Wiring 109 Bump 110 Wiring 111 Photosensitive filler 112 Plating metal 113 LED emitted light 401 Exposure light 402 Non-photosensitive part 403 Cavity 501 Through-hole and through-hole Wiring 502 n-electrode 503 Back side wiring 504 Power supply pad 505 Insulating film 801 Circuit board wafer 802 Circuit board chip defective part 901 Base 902 Erecting equal magnification imaging system 903 Photosensitive drum

Claims (7)

Connection of an element substrate for electrically connecting the connection portion of the first substrate and the connection portion of the second substrate with the first and second substrates having at least one substrate facing each other facing each other. In the method
Aligning the first substrate and the second substrate;
Disposing a photosensitive filler between the first substrate and the second substrate;
Irradiating light from the light-transmitting substrate side of the first and second substrates, and exposing the filler using a connection portion of the substrate as a light shielding mask;
A step of dissolving a non-photosensitive portion of the filler after the exposure to form a cavity between the connecting portions of the first and second substrates;
Electrically connecting the connecting portions of the first and second substrates by embedding a conductive material in the cavity; and
A method for connecting element substrates, comprising: 2. The element substrate connection method according to claim 1, wherein a light-emitting element, a light-receiving element, or a light modulation element is mounted on a light-transmitting substrate among the first and second substrates. 3. The connection part of the first and second substrates is electrically connected to each other by forming a metal film by plating inside the cavity in the electrical connection step. Method of connecting the element substrates. 4. The element substrate connection method according to claim 1, wherein the transparent substrate among the first and second substrates is a sapphire substrate. 5. The element substrate connection method according to claim 2, wherein the light emitting element is a GaN PN junction. 6. The element substrate connection method according to claim 1, wherein the photosensitive filler is a negative type photoresist or a photo-curing resin. Connection of an element substrate for electrically connecting the connection portion of the first substrate and the connection portion of the second substrate with the first and second substrates having at least one substrate facing each other facing each other. In the method
Aligning the first substrate and the second substrate;
Disposing a photosensitive filler between the first substrate and the second substrate;
Irradiating light from the light-transmitting substrate side of the first and second substrates, and exposing the filler using the electric wiring portion of the substrate as a light shielding mask;
A step of dissolving a non-photosensitive portion of the filler after the exposure to form a cavity between the first and second substrates;
Providing a conductive material in the cavity to electrically connect the connection portions of the first and second substrates;
A method for connecting element substrates, comprising: