JP2008123273A - Signal bus occupancy arbitrating method and data transfer device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a signal bus arbitrating method capable of arbitrating the occupancy right of a signal bus among a plurality of devices by a simple circuit configuration, and a data transfer device. <P>SOLUTION: This invention relates to: the signal bus occupancy arbitrating method in the data transfer device including at least one signal bus and a plurality of devices which respectively occupy the signal bus in accordance with an occupancy enabling signal and performs data transfer through the signal bus; and the data transfer device, wherein the current count value patrolling each count value existing in a predetermined count section according to a time elapse is stored, at least one permission timing count value that coincides with any of count values is stored in each device, the current value is compared with the permission timing count value of one device of devices in accordance with an occupancy request signal generated by the device, and only when both the values coincide with each other, the occupancy enabling signal is supplied to the device. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention provides a data transfer apparatus including a signal bus such as a PCI (Peripheral Component Interconnect) bus and a plurality of devices that perform data transfer by sharing the signal bus, and the signal bus is used between the devices. The present invention relates to a signal bus occupation arbitration method for arbitrating the bus occupation right and such a data transfer apparatus.

  In general, in an information processing apparatus such as a server system, a workstation, or a personal computer, data is transferred to and from a plurality of devices such as a hard disk via a PCI bus. Data transfer on a signal bus such as a PCI bus is performed by temporarily occupying a bus by one device. Therefore, if bus use requests from multiple devices compete at the same time, the bus is occupied between these multiple devices. Arbitration processing or arbitration is required for the right.

The bus access arbitration system disclosed in Patent Document 1 is measured by a data amount monitoring unit that measures the number of bus access requests issued from each device and the amount of data transferred by each device, and a data amount monitoring unit. The new priority of each device is calculated based on the number of generated bus access requests and the amount of data transferred, and the new priority level of the cyclic priority algorithm is set for that device based on the new priority of each device. Priority level updating means to be provided.
JP 2000-148670 A

  Such prior art, when mediating the priority of each device with all devices, monitors traffic such as the number of bus access requests that have fluctuated and the amount of data transferred, and based on the traffic, the cyclic priority The priority is dynamically controlled by adding complicated means such as an algorithm. Therefore, determining the priority by providing a traffic monitoring circuit or the like requires a complicated circuit configuration and is disadvantageous in terms of cost.

  An object of the present invention is to provide a signal bus occupation arbitration method and a data transfer apparatus capable of arbitrating a signal bus occupation right among a plurality of devices with a simple circuit configuration.

A signal bus occupation arbitration method according to the present invention is a data transfer apparatus including at least one signal bus and a plurality of devices each of which occupies the signal bus according to an occupation permission signal and performs data transfer via the signal bus. A signal bus occupation arbitration method, and a current count value holding step for holding a current count value that circulates each count value within a predetermined count section as time elapses;
A permission timing count value holding step for holding at least one permission timing count value that matches any one of the count values for each device, and an occupation request signal generated by one of the devices, An exclusive permission signal supply step of comparing the current count value with the permission timing count value of the one device and supplying the exclusive permission signal to the one device only when both values match. And

  A data transfer apparatus according to the present invention is a data transfer apparatus including at least one signal bus and a plurality of devices each of which occupies the signal bus in response to an occupation permission signal and performs data transfer via the signal bus. Current count value holding means for holding a current count value that circulates each count value within a predetermined count interval as time elapses, and at least one permission timing count value that matches one of the count values for each device In accordance with the occupancy request signal generated by the permission timing count value holding means and one of the devices, the current count value is compared with the permission timing count value of the one device, and both values match. And an exclusive permission signal supply means for supplying the exclusive permission signal to the one device only in the case of being performed.

  According to the signal bus occupation arbitration method and the data transfer device according to the present invention, the signal bus occupation right can be arbitrated between a plurality of devices with a simple circuit configuration.

Embodiments of the present invention will be described in detail with reference to the accompanying drawings.
<First embodiment>
FIG. 1 shows a first embodiment of the present invention, and shows an overall configuration including a data transfer apparatus according to the present invention. The data transfer apparatus 10 includes a PCI bus 30 that is a signal bus, a plurality of devices 41 to 44, and a PCI bus arbitration circuit 50. A plurality of PCI devices 41 to 44 are connected to the PCI bus 30. Usually, the PCI device means an auxiliary storage device such as a main storage device or a hard disk device that can be connected to the PCI bus, or various peripheral devices such as a video card, a sound card, or a LAN card. The PCI bus 30 is connected to a host CPU 20 that is a central processing unit. In this embodiment, one signal bus 20 and four PCI devices 41 to 44 are shown as examples. However, the present invention is not limited thereto, and the data transfer device according to the present invention includes two or more signal buses. And five or more PCI devices.

  Each of the PCI devices 41 to 44 performs data transfer with another device such as the host CPU 20 via the PCI bus 30 according to the function. At this time, each of the PCI devices 41 to 44 exchanges the Req signal and the Gnt signal with the PCI bus arbitration circuit 50. The PCI bus arbitration circuit 50 is a circuit that performs arbitration, that is, arbitration, with the PCI devices 41 to 44. The PCI device that wants to use the PCI bus 30, for example, the PCI device 41 sends a Req signal to the PCI bus arbitration circuit 50. The PCI bus arbitration circuit 50 generates a Gnt signal for permitting bus occupation in consideration of the use status of the PCI bus 30 and the contention conditions of the requests of the PCI devices 41 to 44, and supplies this to the PCI device 41. . The PCI device 41 occupies the PCI bus 30 according to the Gnt signal and performs data transfer.

  Referring to FIG. 2, the number of Req and Gnt signals for each PCI device and the distribution of data transfer amount are shown. For example, in a normal PCI bus arbitration circuit, in order to maintain the fairness of each PCI device, it is configured so that only a specific PCI device does not receive permission continuously at the time of contention, and the Req signal as shown in the figure. Is controlled so that the number of Reqs to be transmitted and the number of Gnts for generating the Gnt signal are equal. However, this alone may transfer a large amount of data depending on the PCI device. That is, as shown in this figure, even if the number of Reqs to output the Req signal is the same for all the PCI devices 41 to 44, only the PCI device 41 has its occupied time, that is, the bus usage time per time. May be long. In this case, the PCI bus 41 occupies the largest share of the entire bus, and just using a circuit that counts only the Req count and Gnt count can maintain fairness for each PCI device. I understand that there is no. The signal bus occupation arbitration method and the data transfer apparatus according to the present invention avoid such inconvenience as described below.

  FIG. 3 shows a detailed configuration of the PCI bus arbitration circuit 50 shown in FIG. The PCI bus arbitration circuit 50 includes a cyclic counter 51 and a plurality of slot circuits S1 to S4. The cyclic counter 51 is a counter in which, for example, the count values from 0 to 7 are cyclically repeated, that is, repeated over time as predetermined count intervals 0 to N in synchronization with the PCI bus clock signal. The latest or current count value of the cyclic counter 51 is supplied to the plurality of slot circuits S1 to S4.

  Each of the plurality of slot circuits S1 to S4 includes registers R1 to R4 and decoders D1 to D4, respectively. The registers R1 to R4 are registers that hold at least one permission timing count value. The permission timing count value is at least one integer corresponding to any one of count intervals 0 to N which are integer intervals. The permission timing count value (hereinafter referred to as a register value) can be changed at any time from the host CPU 20 connected to the PCI bus 30 regardless of the passage of time.

  Referring to this figure, for example, 0 is set in register R1, 1 and 2 are set in register R2, 3, 4 and 5 are set in register R3, and 6 and 7 are set in register R4. A set example is shown. The number of permission timing count values set in each of the registers R1 to R4 gives an allocation of the occupation time of the PCI bus 30 guaranteed to each of the corresponding PCI devices 41 to 44.

  Each of the decoders D1 to D4 includes an enable timing count value supplied from each of the registers R1 to R4, that is, a register value, a current count value supplied from the cyclic counter 51, and each of the external PCI devices 41 to 44. It consists of a circuit that takes a logical product (AND) with the supplied Req signal.

  As shown in the figure, for example, the decoders D1 to D4 are realized by two AND operation elements AND1 and AND2. In this case, the current count value and the register value are connected to the two input terminals of the AND operation element AND1, the AND output of the AND operation element AND1 is supplied to one input terminal of the AND operation element AND2, and so on. The Req signal is supplied to the input terminal. The Gnt signal is output from the AND output terminal of the AND operation element AND2. The output Gnt signal is supplied to each of the corresponding PCI devices 41 to 44.

  FIG. 4 illustrates the operation of the data transfer apparatus according to the present invention. The current count value changes so that the cyclic counter 51 circulates from 0 to 7 repeatedly. The timing for receiving the Req signal of each of the PCI devices 41 to 44 is only when the register value input to each of the decoders D1 to D4 is equal to the current count value. At other timings, the input Req signal is in a wait state.

  It is assumed that a Req signal is input from the PCI device 43 at a time point as illustrated. At this time, since the PCI device 42 is permitted, the Req signal of the PCI device 43 is in a waiting state until the permitted timing is met. The timing at which the PCI device 43 is permitted is after the permission timing at which the register value (3, 4, 5) of the PCI device 43 matches the current count value as shown in the figure.

  FIG. 5 shows a distribution in which the data transfer amount is made uniform for each PCI device. As described above, the proportion of the timing at which each of the PCI devices 41 to 44 is permitted is determined by the number of register values set in each of the registers R to R4. In the case of the present embodiment, as a result, the bus occupation times of the PCI devices 41 to 44 are as follows: PCI device 41: 1/8, PCI device 42: 2/8, PCI device 43: 3/8, and PCI device 44: 2 / As shown in FIG. As a result, as shown in the figure, the data transfer amount achieved by each of the PCI devices 41 to 44 is almost equalized.

In the first embodiment described above, the right to occupy the signal bus is easily arbitrated among a plurality of PCI devices by a simple circuit configuration including a cyclic counter and a register for which permission timing is set. If it is desired to change the distribution of the respective occupation times, the distribution of the PCI devices can be changed at any time by the host CPU changing the register value of the register.
<Second embodiment>
FIG. 6 shows a processing procedure for executing the signal bus occupying arbitration method according to the second embodiment of the present invention. In the first embodiment, the signal bus occupancy arbitration method according to the present invention is implemented using hardware elements such as logical product operation elements. However, the second embodiment is a signal bus according to the present invention. A form in which the occupation arbitration method is realized by a sequential processing process by a microprocessor or the like is shown. Here, the components such as the cyclic counter and the register shown in FIG. 3 are realized by developing them in a main memory connected to the microprocessor. It is assumed that the current count value of the circulation counter circulates in a predetermined count section, and the permitted timing count value is held in advance for each PCI device.

  The PCI bus arbitration circuit 50 waits for a Req signal to be sent from a certain PCI device (step S1). Next, the PCI bus arbitration circuit 50 determines whether or not there is a Req signal (step S2). If there is no Req signal, the wait state for the Req signal in step S1 is continued. On the other hand, if there is a Req signal, the PCI bus arbitration circuit 50 compares the current count value with the permission timing count value of the PCI device (step S3) and determines whether or not both values match (step S3). Step S4). If the current count value does not match the permission timing count value, the PCI bus arbitration circuit 50 waits for a predetermined time such as an integer multiple of the PCI bus clock cycle (step S5).

  On the other hand, if the current count value matches the permission timing count value, the PCI bus arbitration circuit 50 generates a Gnt signal and supplies it to the PCI device that sent the Req signal (step S6).

  In the second embodiment described above, the configuration of the PCI bus arbitration circuit can be replaced with a sequential processing device such as a microprocessor in place of the logical product element in the first embodiment. There is an effect.

  In the above embodiments, there is provided a PCI arbitration method and circuit for arbitrating a right to occupy a signal bus according to a changeable priority with a simple circuit configuration. Such a configuration can be configured only by hardware, and thus has an advantage that no load for arbitration is applied to the host CPU. On the other hand, if a certain load is allowed on the host CPU, the host CPU monitors traffic on the signal bus, and dynamically adjusts the signal bus occupancy distribution according to the bus usage status of each device. Is also possible.

  The signal bus occupancy arbitration method and circuit according to the present invention are not limited to the PCI bus, but can also be applied to other data transfer apparatuses that perform data transfer by sharing a plurality of signal buses for serial transfer by each device, such as the PCI Express standard. obtain.

1 is a block diagram illustrating an overall configuration including a data transfer apparatus according to a first embodiment of this invention. It is a graph which shows the frequency | count of Req signal and Gnt signal for every PCI device, and distribution of data transfer amount. FIG. 2 is a block diagram showing a detailed configuration of a PCI bus arbitration circuit shown in FIG. 1. It is a chart explaining operation | movement of the data transfer apparatus by this invention. It is a graph which shows the distribution in which the data transfer amount was equalized for every PCI device. It is a sequence diagram which shows the 2nd Example of this invention and shows the process sequence which performs the signal bus occupation arbitration method.

Explanation of symbols

10 data transfer device 20 host CPU
30 PCI bus 41 to 44 PCI device 50 PCI bus arbitration circuit 51 cyclic counter
AND1, AND2 AND operation element D1-D4 decoder R1-R4 register S1-S4 slot circuit

Claims (6)

A signal bus occupancy arbitration method in a data transfer device including at least one signal bus and a plurality of devices each occupying the signal bus in response to an occupancy permission signal and performing data transfer via the signal bus,
A current count value holding step for holding a current count value that circulates each count value within a predetermined count section as time passes;
A permission timing count value holding step for holding at least one permission timing count value that matches any of the count values for each device;
In response to an occupancy request signal generated by one of the devices, the current count value is compared with the permission timing count value of the one device, and only when both values match, the first device An occupancy permission signal supply step for supplying the occupancy permission signal to
A signal bus occupancy arbitration method comprising:   2. The signal bus occupation arbitration method according to claim 1, wherein the current count value holding step holds a current count value that circulates in synchronization with a clock signal of the signal bus.   2. The signal bus occupying arbitration method according to claim 1, wherein the permission timing count value holding step includes a step of changing the permission timing count value in response to a change request in the course of the time. A data transfer apparatus including at least one signal bus and a plurality of devices each occupying the signal bus in response to an occupancy permission signal and performing data transfer via the signal bus,
Current count value holding means for holding a current count value that circulates each count value in a predetermined count section as time elapses;
Permission timing count value holding means for holding at least one permission timing count value that matches any of the count values for each device;
In response to an occupancy request signal generated by one of the devices, the current count value is compared with the permission timing count value of the one device, and only when both values match, the first device Occupancy permission signal supply means for supplying the occupancy permission signal to
A data transfer device comprising:   5. The data transfer apparatus according to claim 4, wherein the current count value holding means holds a current count value that circulates in synchronization with the clock timing of the signal bus.   5. The data transfer apparatus according to claim 4, wherein the permission timing count value holding means includes means for changing the permission timing count value in response to a change request in the middle of the passage of time.

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