JP2008117962A - Semiconductor relay - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To realize a semiconductor relay capable of using it up to about 20 Gbps, by minimizing its parasitic inductance. <P>SOLUTION: The semiconductor relay comprises a semiconductor substrate disposed on a grounded metal plate, an insulating layer and a single-crystal layer which are laminated successively on the semiconductor substrate, a light emitting diode connected with wirings formed on the single-crystal layer, photovoltaic elements, a thyristor, diodes, and a pair of output FETs which are formed in the single-crystal layer, and four signal pads formed separately from the grounded metal plate. Hereupon, the anode and cathode of the light emitting diode are connected respectively with two ones of the signal pads via bonding wires, and the respective drain electrodes of the output FETs are connected with the other two ones of the signal pads via the bonding wires, and further, electronic components provided on the semiconductor substrate wherefrom the bottom surfaces of the grounded metal plate and the signal pads are excluded are sealed with a resin-sealed type package. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention is used in devices that handle wide-band and high-speed digital signals such as semiconductor testers, measuring instruments, communication devices, and video devices, and that require high reliability, and in particular, control ultra-high-speed signals over the microwave band. The present invention relates to a semiconductor relay.

  As a conventional example of a solid-state semiconductor relay that includes a light emitting element and a photovoltaic element and controls a high-frequency signal such as an RF signal or a video signal, there are the following documents.

Japanese Patent Laid-Open No. 05-268042 JP-A-11-163705 JP 2000-340830 A JP 2002-57563 A

FIGS. 7A and 7B show an example of a conventional solid-state semiconductor relay described in Patent Document 1 and Japanese Patent Laid-Open No. 05-268042 described above. FIG. b) is a circuit diagram thereof.
As shown in FIG. 7B, in the conventional semiconductor relay, the light emitting diode 2 is turned on by a voltage applied between the input terminals 1 and 1A, and a plurality of photovoltaic elements 10 are cascaded by the emitted light. An electromotive force is generated in the photovoltaic element 3.

  Between the anode electrode and the cathode electrode at both ends of the photovoltaic element 3, both ends of the thyristor 6 are connected via a first diode 4 and a second diode 5, respectively. Further, the N-pole gate of the thyristor 6 is connected to the connection point between the anode electrode of the photovoltaic element 3 and the anode electrode of the first diode 4, and the cathode electrode of the photovoltaic element 3 and the second diode 5 are similarly connected. A P-pole gate of the thyristor 6 is connected to a connection point with the cathode electrode.

  The anode electrode (hereinafter, electrode is omitted) and the cathode of the thyristor 6 are connected to the gate 7a and the back gate 7b of the two enhancement type MOSFETs 7, respectively. When these MOSFETs 7 are turned on, the drain electrode 7c is turned on. The load between the output terminals 8 and 8A connected to -7c is closed.

  In this semiconductor relay, the thyristor 6 is in an off state with the light emitting diode 2 turned on, and the resistance value is extremely high. Accordingly, the electric charge generated by the electromotive force generated in the photovoltaic element 3 is immediately applied to the gate 7 a of the output MOSFET 7 via the first diode 4 and the second diode 5.

  Next, when the voltage applied to the input terminals 1 and 1A disappears and the light emitting diode 2 is extinguished, the voltage generated by the photovoltaic power 3 disappears, but is output by the first and second diodes 4 and 5 and the thyristor 6. The gate voltage of the enhancement type DMOSFET 7 is kept as it is.

  In this state, the voltage of the photovoltaic element 3 decreases due to self-discharge, so that the diodes 4 and 5 are first turned off. For this reason, the impedance of the N pole gate and the P pole gate of the thyristor 6 becomes extremely high, and the thyristor 6 is turned on with a very small current. When the voltage further decreases, the N-pole gate or P-pole gate of the thyristor 6 is forward-biased.

  Since the sensitivity of the gate of the thyristor 6 is extremely high, the thyristor 6 is turned on by a slight self-discharge current of the photovoltaic element 3. Furthermore, since the thyristor 6 has a self-holding characteristic, once it is turned on, the thyristor 6 is kept on until the voltage between the anode and the cathode drops to about 1V. For this reason, the electric charge accumulated in the gate 7a of the output enhancement MOSFET 7 is quickly discharged through the thyristor 6, and the MOSFET 7 is turned off.

  By the way, in the conventional semiconductor relay described above, as shown in FIGS. 7A and 7B, bonding wires 11 are used for wiring between elements and between leads, and leads 15 of a lead frame package are used for board mounting. . When an RF signal is applied, the bonding wire 11 and the lead 15 have high impedance with respect to the ground plane, and influence as parasitic inductance. In particular, when the RF signal exceeds several GHz, transmission characteristics at the time of ON are deteriorated.

  For example, each bonding wire 11 has a length of 2 mm, has a parasitic inductance of about 0.5 nH per mm, and the lead 15 has a parasitic inductance of about 0.5 nH. Assuming that the two leads 15 are in series with the signal line when turned on, the impedance of the signal line is 80 ohms at 2.5 GHz with respect to the signal line, and the signal line has a characteristic impedance of 50Ω. Attenuates to the following voltage levels:

In recent years, communication equipment has been required to have a transmission band of 5 Gbps to 10 Gbps, and thus a device whose transmission characteristics are greatly degraded at 2.5 GHz cannot be used.
In addition, when the semiconductor relay is placed in an off state not only when it is on, but also between the signal transmission line and the DC voltage source, that is, AC between the signal transmission line and the ground, the parasitic inductance is off-biased with the parasitic inductance. An LC series resonance circuit is formed by the parasitic capacitance of the MOSFET 7.

As a result, the signal transmitted through the signal transmission line flows to the ground side in this resonance frequency band, and the signal quality is greatly deteriorated in this band.
As a method for solving this problem, in the above-mentioned Patent Document 3 and Japanese Patent Application Laid-Open No. 2000-340830, as shown in the unsealed diagram of FIG. 8, the drain, gate, and source electrodes of the semiconductor element are on one surface side of the same substrate. One or more pairs of integrated lateral MOSFET chips 21 formed as lateral structure elements formed on the printed circuit board 36, a printed wiring board 36 on which the light receiving chip 6 and the light emitting element 1 are mounted, and a signal formed on the printed wiring board 36. And a bump provided on the transmission line to which the chip is bonded.

  According to the configuration shown in FIG. 8, a pair of semiconductor elements are formed as in-chip wiring with a short wiring distance, and the chip is directly bump-bonded onto the printed wiring board 36, thereby bonding wires and package leads. The inductance component can be reduced, and the insertion loss for the high frequency signal can be reduced.

  However, when such a configuration is used, there is a problem that equipment for mounting the chip on the printed wiring board 36 and equipment for a wire bonder are required on the chip user side, resulting in an increase in manufacturing cost.

  Further, in order to increase the frequency as a secondary problem, miniaturization of the package of the semiconductor relay has been promoted. Lead pads have also been miniaturized along with the miniaturization of packages, but in recent years lead-free products have been promoted, and due to the synergistic relationship between size and solder strength, adhesion to mounting boards has become inferior. As a result, there was a problem that even a weak impact could cause the substrate to fall off or break.

  Therefore, in order to minimize the parasitic inductance, the present invention has a structure that eliminates as much as possible the signal routing by the bonding wires and leads for wiring and the signal propagation in the leads of the lead frame in order to minimize the parasitic inductance. Thus, it is to provide a semiconductor relay that can be used up to about 10 GHz, or up to about 20 Gbps in terms of digital signals. A secondary purpose is to provide a large ground solder surface on the back surface of the package, and to realize a semiconductor relay having excellent adhesion to a mounting board even in a small package.

The present invention was made to solve the above problems, and in the semiconductor relay according to claim 1,
A semiconductor substrate disposed on a ground metal plate; wiring formed on the semiconductor substrate; light-emitting diodes flip-chip mounted and connected to the wiring via bumps; and light formed on the semiconductor substrate An electromotive force element, a thyristor, a diode and a set of two output FETs, and four signal pads formed separately from the ground metal plate,
Each of the anode and cathode of the light emitting diode is connected to two of the signal pads via bonding wires, and the other two drain electrodes of the set of two output FETs and the other two of the signal pads are bonding wires. The electronic components on the semiconductor substrate except for the ground metal plate and the bottom surface of the signal pad are sealed with a resin-sealed package.

In claim 2, in the semiconductor relay according to claim 1,
The semiconductor substrate including the insulating layer and the single crystal layer is an SOI substrate or a compound semiconductor substrate.

4. The semiconductor relay according to claim 3, wherein the compound semiconductor substrate is disposed on a ground metal plate, and the light emitting diode, the photovoltaic element, the thyristor, the diode, and a set of two output FETs formed on the compound semiconductor substrate. And four signal pads formed separately from the ground metal plate,
Each of the anode and cathode of the light emitting diode is connected to two of the signal pads via bonding wires, and the other two drain electrodes of the set of two output FETs and the other two of the signal pads are bonding wires. The electronic components on the semiconductor substrate except for the ground metal plate and the bottom surface of the signal pad are sealed with a resin-sealed package.

In Claim 4, in the semiconductor relay of Claims 1 to 3,
The resin leadless lead frame dress package.

In Claim 5, in the semiconductor relay according to Claims 1 to 4,
The ground metal plate and the signal pad are exposed on the back surface of the resin-sealed package.

In Claim 6, in the semiconductor relay according to Claims 1 to 5,
The set of two output FETs is of a depletion type, and the output of the set of two output FETs is in a conductive state when the light emitting diode is off.

As is apparent from the above description, the present invention has the following effects.
According to invention of Claim 1, 5,
The photovoltaic device, which is a photoelectric conversion device, the thyristor constituting the control circuit, the diodes 4 and 5, and the output FET are integrally formed on the semiconductor substrate as an integrated circuit, so that the wire bonding of the signal path is an input / output portion. In these two locations, the shortest wiring on the same chip was realized by eliminating any wire bonding between elements and reducing the parasitic inductance. As a result, it has become possible to realize frequency characteristics up to the 10 GHz band.

  According to the invention described in claim 2, since the semiconductor substrate is an SOI substrate or a compound semiconductor substrate, it is possible to separate the photovoltaic element, the thyristor, the diode, and the output FET, thereby realizing an integrated circuit. It has become possible to reduce the defective rate and failure rate by reducing the manufacturing cost and the number of parts.

  In addition, by configuring the output FET with a compound semiconductor such as GaAs or InP having a high electron mobility, further wideband frequency characteristics and high-speed response can be realized, dielectric loss is small (tan δ = 0.004), and the substrate It has become possible to reduce the transmission loss on the above line.

  According to the invention described in claim 3, since the light emitting diode, the photovoltaic element, the thyristor, the diode, and the output FET are formed on the compound semiconductor substrate, the integrated circuit can be realized, the manufacturing cost can be reduced, and the number of parts can be reduced. The failure rate and failure rate can be reduced due to the decrease in

According to the fourth aspect of the present invention, since the resin-encapsulated package is a leadless package, there is no parasitic inductance due to the physical length of the leads, and the high frequency characteristics are excellent. In addition, since the semiconductor substrate is installed on a ground metal plate provided on the back side of the package, the impedance on the wiring on the semiconductor substrate can be designed by the line width and the thickness of the semiconductor substrate, and impedance mismatching can be performed. I was able to reduce it.
Further, since the ground metal plate is exposed on the back surface of the package, it can be used as a large ground solder surface, so that it is possible to increase the fixing force to the mounting printed circuit board.

  According to the sixth aspect of the present invention, each set of two output FETs is of a depletion type, and the output of the set of two output FETs is in a conductive state when the light emitting diode is off. Since the primary side is turned off, that is, the light emitting diode is not lit, the output terminal on the secondary side can be operated in a conductive state, and power saving can be achieved for the use of a switch with many conductive states. . Further, since it is normally on, the electrostatic discharge breakdown resistance between the output terminals 15a and 15b can be increased.

  FIG. 1A and FIG. 1B are configuration diagrams showing an embodiment of the present invention. FIG. 1A is a perspective view, and FIG. 1B is a circuit diagram.

  In these drawings, the semiconductor relay of the present invention is flip-chip mounted on a semiconductor substrate 51 placed on a resin-sealed leadless lead frame package 62 and a ground metal plate 64 at the center of the back surface thereof. , The light emitting diode 52 electrically connected to the wiring of the semiconductor substrate 51 by the bump 52b, the signal pads 65a to 65d of the resin-sealed leadless lead frame package 62, the signal pads 65a to 65d, the semiconductor substrate 51, and It is composed of bonding wires 61 a to 61 d for electrically connecting the light emitting diode 52.

  The resin-encapsulated leadless leadframe package 62 is a ceramic substrate or resin substrate, a semiconductor substrate 51, and a light-emitting diode 52 placed on the substrate, and after bonding wires, a package using resin encapsulation is a leadless package. It may be configured.

  Here, a transparent silicon resin 63 is filled so that a gap between the light emitting diode 52 flip-chip mounted on the semiconductor substrate 51 and the semiconductor substrate 51 becomes a light guide path, thereby preventing the sealing resin from entering the package.

FIG. 2 is a schematic configuration diagram of a device in which a photovoltaic element 53 that is a photoelectric conversion element, a thyristor 56 that constitutes a control circuit, diodes 54 and 55, and output FETs 57 and 58 are integrally formed as an integrated circuit. The semiconductor substrate 51 includes a configuration holding silicon substrate 51c, an insulating layer 51b made of a silicon oxide film, and a silicon single crystal layer 51a. The silicon single crystal layer 51a is doped with n ⁻ immediately after the formation of the substrate, but in order to realize the device configuration shown in FIG. 2, an active layer is formed by ion implantation-annealing according to the purpose.

Next, the operation of the circuit diagram of the conductor relay shown in FIG.
In the ON state, the light emitting diode 52 is turned on by a voltage applied between the primary side input terminals 65d and 65c, and an electromotive force is generated in the plurality of photovoltaic elements 53 connected in cascade by the emitted light.

  Between the anode electrode and the cathode electrode at both ends of the photovoltaic element 53, both ends of the thyristor 56 are connected via a first diode 54 and a second diode 55, respectively. In addition, an N-pole gate of the thyristor 56 is connected to a connection point between the anode electrode of the photovoltaic element 53 and the anode electrode of the first diode 54, and the cathode electrode of the photovoltaic element 53 and the second diode 55 are similarly connected. A P-pole gate of the thyristor 56 is connected to a connection point with the cathode electrode.

  The anode electrode (hereinafter abbreviated as an electrode) and the cathode of the thyristor 56 are connected to the gate electrodes of two enhancement type MOSFETs 57 and 58, respectively, and the thyristor 56 is turned on when the light emitting diode 52 is turned on when the primary side is on. Since a voltage higher than the anode of the diode 54 by the band gap of the diode 54 is applied to the N-pole gate of the thyristor 56 and a voltage lower than the cathode of the diode 55 by the band gap of the diode 55 is applied to the P-pole gate of the thyristor 56. And the resistance value becomes extremely high.

  Therefore, the voltage generated by the electromotive force generated in the photovoltaic element 53 is a voltage obtained by subtracting the band gap of the diodes 54 and 55 to the gate electrodes of the output MOSFETs 57 and 58 via the first diode 54 and the second diode 55. Then, the output MOSFETs 57 and 58 are turned on. When these MOSFETs 57 and 58 are turned on, the secondary-side output terminals 65a and 65b connected to the drain electrode become conductive.

  In the transition from the on state to the off state, when the voltage applied to the input terminals 65d and 65c disappears and the light emitting diode 52 is extinguished, the voltage generated by the photovoltaic element 53 disappears, and the photovoltaic element 53 Voltage decreases due to self-discharge. As a result, first, the diodes 54 and 55 are turned off.

  In this state, the gate voltages of the output enhancement type MOSFETs 57 and 58 are maintained as they are. The impedances of the N pole gate and the P pole gate of the thyristor 56 in the off state are extremely high. Due to the slight self-discharge current of the photovoltaic element 53, the potential of the N-pole gate of the thyristor 56 is lowered from the anode, the P-pole gate of the thyristor 56 is raised from the cathode potential, and is forward-biased as the thyristor 56. The thyristor 56 is turned on by the bias.

  Furthermore, since the thyristor 56 has a self-holding characteristic, once the thyristor 56 is turned on, the thyristor 56 is kept on until the voltage between the anode and the cathode drops to about 0.5V. For this reason, the electric charges accumulated in the gate electrodes of the output enhancement MOSFETs 57 and 58 are quickly discharged through the thyristor 56, and the MOSFETs 57 and 58 are turned off.

That is, the diodes 54 and 55 and the thyristor 56 constitute a circuit for discharging the charge accumulated in the gate electrodes of the output enhancement MOSFETs 57 and 58 at a high speed in accordance with the displacement from the primary on to the off. .
When the charge held in the gate electrodes of the output enhancement MOSFETs 57 and 58 is discharged and the potential drops to about 0.5 V, the thyristor 56 is turned off. In this state, the output terminals 65a and 65b are non-conductive.

  The photovoltaic element 53, the thyristor 56, the diodes 54 and 55, and the enhancement type MOSFETs 57 and 58 are configured as an integrated circuit on the semiconductor substrate 51 using an SOI substrate by the device configuration shown in FIG.

In FIG. 2, 51 is a semiconductor substrate made of SOI, 51c is a configuration holding silicon substrate, 51b is an insulating layer made of a silicon oxide film, and 51a is a silicon single crystal doped with n ⁻ immediately after the formation of the substrate. In order to realize a device configuration as shown in the figure, an active layer is formed by ion implantation-annealing or the like according to the purpose.
Electrical isolation between devices is obtained by a silicon oxide film 51b in the substrate thickness direction and a depletion layer by a PN junction in which either the P side or the N side is floating in 51a.

  According to the above-described configuration, the photovoltaic element 53 that is a photoelectric conversion element, the thyristor 56 that constitutes the control circuit, the diodes 54 and 55, and the output FETs 57 and 58 are integrally formed on the semiconductor substrate 1 as an integrated circuit. As a result, the wire bonding of the signal path is made only at the two input / output portions 61a and 61b, and by removing any wire bonding between the elements to reduce the parasitic inductance, the shortest wiring on the same chip can be realized. The frequency characteristic up to the band can be realized.

  Further, the photovoltaic element 53, the thyristor 56, the diodes 54 and 55, and the output FETs 57 and 58 are configured on an SOI substrate or a semi-insulating substrate, so that the elements can be separated and an integrated circuit can be realized. it can.

  Further, since a leadless package is used as the package 62, there is no parasitic inductance due to the physical length of the lead, and the high frequency characteristics are excellent. The semiconductor substrate 51 is installed on a ground metal plate 64 provided on the back surface of the package 62.

Thereby, the impedance on the wiring on the semiconductor substrate 51 can be designed by the line width and the thickness of the semiconductor substrate 51, and impedance mismatching can be reduced.
As a secondary effect, one surface of the ground metal plate 64 is exposed on the back surface of the package 62 and can be used as a large ground solder surface, so that it is possible to increase the fixing force to the mounting printed board.

Next, a second embodiment will be described with reference to the schematic configuration diagrams of FIGS. 3 (a, b) and FIG. In this embodiment, the semiconductor substrate 51 is made of a compound semiconductor such as GaAs or InP.
Therefore, the photovoltaic element 53, the thyristor 56 constituting the control circuit, the diodes 54 and 55, the output FETs 57 and 58, and the insulator for element separation of the resistor 59 are not required in the substrate. Further, the dielectric loss of the compound semiconductor is small (tan δ = 0.004), and the transmission loss on the line on the semiconductor substrate 51 can be reduced.

  As shown in FIGS. 3B and 4, the output FETs 57 and 58 are depletion type N-channel MESFETs capable of high withstand voltage and high speed operation. Therefore, the gate bias is zero and it is in the on state. When the light emitting diode 52 is turned on, a negative bias is applied to the gate-source voltage, and the output FETs 57 and 58 are turned off. Therefore, the secondary side is turned off and on with respect to the primary side on / off.

  The polarity of the photovoltaic element 53, the thyristor 56 constituting the control circuit, and the diodes 54 and 55 are reversed from those of the first embodiment in order to reverse the primary side on and off, and the secondary side off and on. Yes. In this embodiment, as shown in FIG. 3B, a resistor 59 is provided to fix the gate bias when the thyristor 56 is in the OFF state. This resistor 59 is a high resistance of several tens of kΩ or more.

According to the above-described configuration, the output FETs 57 and 58 are formed of the compound semiconductor, so that the electron mobility is high, and further, wideband frequency characteristics and high-speed response can be realized.
In addition, since the dielectric loss of the compound semiconductor is small (tan δ = 0.004 or so), the transmission loss on the line on the semiconductor substrate 51 can be reduced.

  Further, the primary side is off, that is, the light emitting diode 52 is not lit, and the secondary side output terminals 65a and 65b are in a conductive state. Therefore, if it is used for a switch having many conductive states, power saving can be achieved. Moreover, since it becomes normally on, the electrostatic discharge destruction tolerance between the output terminals 65a and 65b can be raised.

  Further, since the secondary side output terminals 15a and 15b are in a conductive state in the primary side off state, the electrostatic withstand voltage between the output terminals 65a and 65b is increased. As a result, it is possible to increase the yield when manufacturing the semiconductor relay and when manufacturing a product using the semiconductor relay.

Next, a third embodiment will be described with reference to the schematic configuration diagrams of FIGS. 5 (a, b) and FIG. Also in this embodiment, the semiconductor substrate 51 is made of a compound semiconductor such as GaAs or InP. As shown in FIGS. 5A and 6, the light emitting diode 52 is also integrally formed on the semiconductor substrate 51 as an integrated circuit as shown in FIG. 5A and FIG. .

  FIG. 6 shows a device configuration of an integrated circuit of the light emitting diode 52, the photoelectric conversion element 53, the diodes 54 and 55, the thyristor 56, and the FET output switch elements 57 and 58. In such a configuration, since the light emitting diode 52 and the photoelectric conversion element 53 are on the same plane, the transparent silicon resin 63 is disposed so as to cover both the light emitting diode 52 and the photoelectric conversion element 53 so as to operate as a light guide path. .

According to the above-described configuration, the light emitting diode 52 is also integrally formed on the semiconductor substrate 51 as an integrated circuit, so that the manufacturing cost can be reduced and the manufacturing yield can be improved.
In addition, since the light emitting diode 52 is also integrally formed on the semiconductor substrate 51 as an integrated circuit, the resin-sealed leadless lead frame package 62 can be thinned.

The above description merely shows a specific preferred embodiment for the purpose of explanation and illustration of the present invention.
Therefore, the present invention is not limited to the above-described embodiments, and includes many changes and modifications without departing from the essence thereof.

It is the block diagram and circuit diagram of the semiconductor relay which show one Example of this invention. It is a schematic block diagram of the device which built the semiconductor element of FIG. 1 as an integrated circuit. It is the block diagram and circuit diagram of the semiconductor relay which show another Example. It is a schematic block diagram of the device which built the semiconductor element of FIG. 3 as an integrated circuit. It is the block diagram and circuit diagram of the semiconductor relay which show another Example. It is a schematic block diagram of the device which built the semiconductor element of FIG. 5 as an integrated circuit. It is a block diagram of the semiconductor relay which shows a prior art example. It is a block diagram of the semiconductor relay which shows another prior art example.

Explanation of symbols

51 Semiconductor substrate 52 Light-emitting diode 53 Photovoltaic element 54,55 Diode 56 Thyristor 57,58 Output FET
59 Resistance 61a to 61d Bonding wire 62 Resin-sealed package 63 Transparent silicon resin 64 Ground metal plate 65a to 65d Signal pad

Claims (6)

A semiconductor substrate disposed on a ground metal plate; wiring formed on the semiconductor substrate; light-emitting diodes flip-chip mounted and connected to the wiring via bumps; and light formed on the semiconductor substrate An electromotive force element, a thyristor, a diode and a set of two output FETs, and four signal pads formed separately from the ground metal plate,
Each of the anode and cathode of the light emitting diode is connected to two of the signal pads via bonding wires, and the other two drain electrodes of the set of two output FETs and the other two of the signal pads are bonding wires. A semiconductor relay characterized in that electronic components on the semiconductor substrate except for the ground metal plate and the bottom surface of the signal pad are sealed with a resin-sealed package.   2. The semiconductor relay according to claim 1, wherein the semiconductor substrate including the insulating layer and the single crystal layer is an SOI substrate or a compound semiconductor substrate. A compound semiconductor substrate disposed on a ground metal plate, a light emitting diode, a photovoltaic element, a thyristor, a diode, and a set of two output FETs formed on the compound semiconductor substrate, and isolated from the ground metal plate Consisting of four signal pads,
Each of the anode and cathode of the light emitting diode is connected to two of the signal pads via bonding wires, and the other two drain electrodes of the set of two output FETs and the other two of the signal pads are bonding wires. A semiconductor relay characterized in that electronic components on the semiconductor substrate except for the ground metal plate and the bottom surface of the signal pad are sealed with a resin-sealed package.   4. The semiconductor relay according to claim 1, wherein the resin-encapsulated package is a leadless package.   5. The semiconductor relay according to claim 1, wherein the ground metal plate and the signal pad are exposed on a back surface of the resin-encapsulated package.   The set of two output FETs is configured as a depletion type, and the output of the set of two output FETs is in a conductive state when the light emitting diode is off. Item 6. The semiconductor relay according to Item 1.

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