JP2008116375A - Pressure transducer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce circuit dimension and consumption current in a pressure transducer detecting pressure applied from outside to acquire the digital measurement data. <P>SOLUTION: The pressure transducer includes a bridge circuit composed of four piezoresistive elements, a switch circuit supplying power potential to a first node of the bridge circuit, a drive circuit connected with a second node of the bridge circuit, an amplification circuit for amplifying potential difference between a third node and the fourth node of the bridge circuit, a converting circuit where, in a first duration corresponding to a predetermined potential value and a second duration corresponding to an output potential value of the amplification circuit, by counting the number of pulses included in clock signal are counted to acquire a first count value and a second count value, respectively, and a controller operating the converting circuit after the time specified since making the switch circuit into on-state at the onset time of pressure measurement. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a pressure transducer that includes a pressure sensor and an electronic circuit, detects pressure applied from the outside by gas or liquid, and converts the pressure into a digital measurement value that can be processed by a microcomputer.

  Pressure sensors that convert externally applied pressure into electrical signals are realized using strain gauges and coils by using the piezoresistive effect and magnetostrictive effect methods, and are widely used in the fields of industrial measurement equipment and medical equipment. ing. In particular, in recent years, there is an increasing demand for such a pressure sensor to reduce the circuit scale and current consumption.

  As a pressure sensor utilizing the piezoresistive effect, a piezoresistive pressure sensor in which a plurality of piezoresistive elements are formed on the surface of a silicon wafer and the back surface is made into a diaphragm by etching processing is widely known. A piezoresistive pressure sensor uses the principle that when a pressure is applied from the outside by gas or liquid, the diaphragm bends and the resistance value of the piezoresistive element changes, and for example, measures the combustion pressure of an automobile engine. It is used for.

  In general, in a piezoresistive pressure sensor, a plurality of piezoresistive elements connected to each other form a bridge circuit, which is applied from the outside by taking the difference (output voltage) between two output potentials in the bridge circuit. A change in pressure can be detected. Since the output voltage taken out from the piezoresistive pressure sensor is a very small analog signal, it is necessary to amplify the analog signal and convert it into a digital signal in order to perform signal processing in the microcomputer.

  However, when a general A / D (analog / digital) conversion circuit is used, the circuit scale and current consumption increase. Therefore, it is desirable that a pressure transducer that detects pressure and converts it into a digital measurement value does not use such an A / D conversion circuit.

  As a related technique, the following Patent Document 1 discloses a minute difference detection circuit capable of detecting a constant difference between two circuit elements to be compared. This minute difference detection circuit includes two coils or two capacitors to be compared, an RLC circuit that outputs a detection potential difference corresponding to a constant difference between the two coils or two capacitors in response to step-like energization, A voltage comparator that exhibits a hysteresis characteristic with high and low level thresholds using a signal proportional to the detected potential difference as input, and energization control that drives the RLC circuit with first and second different drive voltages And an identification control unit for identifying a constant difference between two coils or two capacitors.

  In this minute difference detection circuit, a potential difference corresponding to an inductance difference between two coils or a capacitance difference between two capacitors or a value obtained by integrating the potential difference is compared with a predetermined voltage and is inversely proportional to a constant difference between two circuit elements. It is described that since a pulse train having a period is generated and the period is identified by minute interval pulse counting, the smaller the constant difference is, the longer the period of the pulse train is, and the identification resolution can be improved.

  Patent Document 2 below discloses a transducer that eliminates a differential amplifier circuit and obtains an output signal in which a measured value is expressed by a pulse width or a pulse number with a simple circuit centered on a logic circuit. This transducer has a bridge type sensor circuit mainly composed of piezoresistive elements connected in a bridge type, two comparators each having two corner voltages of the bridge type sensor circuit as one input, and gradually increasing at a predetermined rate of change. Or a ramp voltage generation circuit that generates a gradually decreasing ramp voltage and applies it to the other input of both comparators, and a pulse width corresponding to the time from when one output of both comparators is inverted until the other output is inverted And a gate circuit for outputting the above signal.

As described in Patent Document 1 and Patent Document 2, it is known to obtain a digital measurement value by generating a pulse signal having a frequency or a pulse width corresponding to a difference between two output potentials of a bridge circuit. Yes. Thereby, a digital measurement value can be obtained with a simple configuration centering on a logic circuit without using an A / D conversion circuit with a large circuit scale and large current consumption. However, since a constant current of about several mA always flows through the bridge circuit, the consumption current is not sufficiently reduced.
Japanese Patent Laying-Open No. 2005-210146 (4th, 5th page, FIG. 1) JP-A-8-247801 (2nd and 3rd pages, FIG. 1)

  Therefore, in view of the above points, an object of the present invention is to reduce circuit scale and current consumption in a pressure transducer that detects a pressure applied from the outside and obtains a digital measurement value.

  In order to solve the above-described problem, a pressure transducer according to one aspect of the present invention is turned on according to a control circuit and a bridge circuit including four piezoresistive elements that change resistance values according to externally applied pressure. A switch circuit that supplies a power supply voltage to the first node of the bridge circuit; a drive circuit that is connected to the second node of the bridge circuit and that causes a current to flow through the bridge circuit when the switch circuit is in an on state; An amplifier circuit for amplifying a potential difference between the third node and the fourth node, a first period corresponding to a predetermined potential magnitude, and a second corresponding to the output potential magnitude of the amplifier circuit In this period, the first count value and the second count value are respectively counted by counting the number of pulses included in the clock signal. A control unit that generates a control signal to be supplied to the conversion circuit and the switch circuit to be calculated, and calculates a value related to pressure based on the first and second count values, and when measuring pressure is started, And a control unit that operates the conversion circuit after a predetermined period has elapsed since the control signal is activated and the switch circuit is turned on.

  Here, the conversion circuit is in accordance with the capacitor and the first control circuit supplied from the control unit according to the second control signal supplied from the control unit, and the third control signal supplied from the control unit. A second charging circuit that charges the capacitor with the output potential of the amplifier circuit; a discharge circuit that discharges the charge charged in the capacitor according to a fourth control signal supplied from the control unit; and a voltage across the capacitor. A logic circuit for generating an enable signal activated in a first period corresponding to a magnitude of a predetermined potential and a second period corresponding to the magnitude of an output potential of the amplifier circuit; and an output from the logic circuit The first count is obtained by counting the number of pulses included in the clock signal in the first and second periods in which the enable signal to be activated is activated. And a second count value may include a counter for determining respectively.

  The amplifier circuit includes a first buffer amplifier that inputs a potential of the third node of the bridge circuit, a second buffer amplifier that inputs a potential of the fourth node of the bridge circuit, and a first buffer amplifier. A differential amplifier that amplifies the potential difference between the output potential and the output potential of the second buffer amplifier may be included.

  According to the present invention, it is possible to reduce the circuit scale by obtaining the digital measurement value by counting the number of pulses of the clock signal in the period corresponding to the difference between the two output potentials of the bridge circuit, and to supply power to the bridge circuit. A switch circuit for supplying or disconnecting voltage is provided, and the control unit controls this to reduce current consumption.

The best mode for carrying out the present invention will be described below in detail with reference to the drawings. In addition, the same reference number is attached | subjected to the same component and description is abbreviate | omitted.
FIG. 1 is a circuit diagram showing a configuration of a pressure transducer according to the first embodiment of the present invention. As shown in FIG. 1, the pressure transducer 1 includes a detection circuit 10, a switch circuit (transistor) 15, a drive circuit 20, an amplifier circuit 30, a conversion circuit 40, a control unit 50, and a frequency divider circuit 55. Is included.

  The detection circuit 10 is a circuit that converts an external pressure applied by atmospheric pressure, liquid, or the like into an electrical signal, and includes four piezoresistive elements 11 to 14 each having a resistance value of about several hundred Ω to several kΩ. . The diffusion type piezoresistive elements 11 to 14 are formed on the surface of the silicon chip, and the diaphragm is formed by flattening the back surface of the silicon chip by etching or the like, and the silicon chip is stored in a cylindrical case having a diameter of about 10 mm. Thus, the detection circuit 10 is created.

  When pressure is applied to the diaphragm from the outside, the diaphragm is bent, and the resistance values of the piezoresistive elements 11 to 14 formed on the surface of the silicon chip slightly change. The piezoresistive element has a small change in resistance value as compared with a resistance change type sensor element such as a thermistor. Therefore, when using a piezoresistive element as a sensor element, like the detection circuit 10, the four piezoresistive elements 11-14 are mutually connected, and a Wheatstone bridge circuit is comprised. In the Wheatstone bridge circuit, a constant current I is supplied between the node A and the node B. Further, a potential difference (output voltage) between the node C and the node D is taken out and input to the amplifier circuit 30.

For example, the piezoresistive elements 11 to 14 having the same resistance value R (Ω) are arranged at predetermined positions on the diaphragm, and the diaphragm bends when pressure is applied from the outside. As a result, in the piezoresistive elements 11 and 12, the resistance value increases by a very small amount ΔR to (R + ΔR), and in the piezoresistive elements 13 and 14, the resistance value decreases by a very small amount ΔR (R−ΔR). ) Accordingly, the voltage V _C at the node _C and the voltage V _{D at the} node D are unbalanced, so that a change in the resistance value of the piezoresistive element can be detected as a differential signal.

As shown in FIG. 1, the drain of a P-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor) 15 is connected to the node A of the detection circuit 10. Further, the power supply voltage V _DD is supplied to the source of the transistor 15, and the control signal CTL 1 is supplied to the gate of the transistor 15 from the control unit 50. When the transistor 15 is turned on in accordance with the control signal CTL1, the power supply voltage V _DD is supplied to the node A.

The drive circuit 20 includes an N-channel MOSFET 21, an operational amplifier 22, and a resistor 23. The node B of the detection circuit 10 is connected to the drain of the transistor 21 in the drive circuit 20. The source of the transistor 21 is connected to the power supply voltage V _SS via a resistor 23, to the gate of the transistor 21, the output voltage of the operational amplifier 22 is supplied. In the present embodiment, the power supply voltage _{VSS is set} to the ground voltage (0 V).

For example, a reference voltage V _REF generated by a plurality of voltage dividing resistors and a constant voltage diode is input to the non-inverting input terminal of the operational amplifier 22. Further, the voltage extracted from the connection point between the source of the transistor 21 and the resistor 23 is fed back to the inverting input terminal of the operational amplifier 22, and the drive circuit 20 operates as a constant current circuit. In the operational amplifier 22, almost the same voltage as V _REF appears at the non-inverting input terminal by the generally known imaginary short operation. Accordingly, since the current I flowing through the resistor 23 is obtained from I = V _REF / R23, the driving current I of the pressure sensor can be set based on this equation.

  In this embodiment, it is set to about 1.5 mA. A resistor for limiting current may be inserted between the output terminal of the operational amplifier 22 and the gate of the transistor 21.

  Generally, a constant current circuit or a constant voltage circuit is used as a circuit for driving a bridge circuit composed of a plurality of piezoresistive elements. However, it is known that when a bridge circuit composed of piezoresistive elements is driven by a constant current circuit, the temperature characteristics of the output voltage are improved as compared with the case of driving by a constant voltage circuit. Therefore, in the present embodiment, the drive circuit 20 is configured by a constant current circuit.

  In the present embodiment, by setting the control signal CTL1 to the high level, the transistor 15 can be turned off, and the current flowing through the detection circuit 10 can be cut off. Therefore, when pressure is not detected, current consumption can be reduced by reducing the current flowing through the detection circuit 10 to almost zero.

The difference (sensitivity) between the output voltage V _C and the output voltage V _D of the detection circuit 10 is about several mV, but is amplified by the amplifier circuit 30 to a level at which the logic circuit can be operated. The amplifier circuit 30 includes resistors 31 to 34 and an operational amplifier 35. The output voltage V _C of the detection circuit 10 is input to the non-inverting input terminal of the operational amplifier 35 via the resistor 31, and the output voltage V _D of the detection circuit 10 is input to the inverting input terminal of the operational amplifier 35 via the resistor 33. Entered.

The output signal of the operational amplifier 35 is supplied to the source of the P-channel transistor 43 in the subsequent conversion circuit 40 and is fed back to the inverting input terminal via the resistor 34. The non-inverting input terminal of the operational amplifier 35 is connected to the ground voltage V _SS via a resistor 32. The resistors 31 to 34 and the operational amplifier 35 connected in this way operate as a differential amplifier circuit (differential amplifier) that amplifies the difference between the output voltage V _C and the output voltage V _D.

The values of the resistors 31 to 34 are set such that, for example, the output voltage V _OP of the operational amplifier 35 in a state where no pressure is applied to the detection circuit 10 is ½ of the power supply voltage V _DD . The output voltage V _OP of the operational amplifier 35 when no pressure is applied to the detection circuit 10 is referred to as an offset voltage. The output voltage V _OP of the operational amplifier 35 changes in the range of the offset voltage V _DD / 2 to the power supply voltage V _DD according to the pressure applied to the detection circuit 10.

The conversion circuit 40 includes a capacitor 45 for charging / discharging, a P-channel transistor 41 and a resistor 42 that form a first charging path for charging the capacitor 45, and a second charging path for charging the capacitor 45. A P-channel transistor 43 and a resistor 44 to be formed, an N-channel transistor 46 that forms a discharge path for discharging the charge charged in the capacitor 45, and a Schmitt trigger buffer 47 that converts the voltage VE of the node _E to a logic level. When counts the aND circuit 48 generates a count enable signal _{V CE} by performing a logical operation on the basis of the output signal _{V ST} and the control signal CTL4 of the Schmitt trigger buffer 47, a pulse of the clock signal in accordance with a count enable signal _{V CE} Counter 49.

The transistor 41 is supplied with the power supply voltage V _{DD at the} source and performs a switching operation in accordance with the control signal CTL2 input to the gate. The drain of the transistor 41 is connected to one end (node E) of the capacitor 45 through the resistor 42. On the other hand, the transistor 43 is supplied with the output voltage V _OP of the operational amplifier 35 of the amplifier circuit 30 at the source, and performs a switching operation according to the control signal CTL3 input to the gate. The drain of the transistor 43 is connected to one end (node E) of the capacitor 45 through the resistor 44. The transistor 46 has a drain connected to one end of the capacitor 45 (node E), the source is connected to the ground voltage V _SS, performs the switching operation in accordance with the control signal CTL4 input to the gate. The other end of the capacitor 45 is connected to the ground voltage _{V SS.}

The control unit 50 is configured by a digital circuit or a CPU and software, and generates control signals CTL1 to CTL4 based on a system clock signal. The transistors 41, 43, and 46 perform switching in accordance with the control signals CTL2 to CTL4 output from the control unit 50, so that the capacitor 45 is charged through the first charging path and then charged through the discharging path. Is discharged, and after the capacitor 45 is charged via the second charging path, the charge of the capacitor 45 is discharged via the discharging path. As a result, the voltage V _{E at the} node E changes.

Schmitt trigger buffer 47 is determined by the input voltage V _E of node E, and outputs a logical value of high or low level according to two thresholds. AND circuit 48, the output signal and the control signal CTL4 and the period is at a high level both of the Schmitt trigger buffer 47 activates the count enable signal V _CE at a high level. Here, if the output voltage of the amplifier circuit 30 is increased, the activation period (pulse count number) of the count enable signal _VCE is correspondingly increased.

For example, the frequency dividing circuit 55 divides the system clock signal supplied to the control unit 50 to generate the clock signal supplied to the counter 49. The counter 49 counts the number of pulses included in the clock signal during the period in which the count enable signal V _CE is activated, obtains a count value, and outputs this to the control unit 50. Therefore, the pressure transducer 1 can convert a change in pressure applied to the detection circuit 10 from the outside into a count value that is a digital measurement value.

  In the above, at least a part of the circuit other than the resistors 42 and 44 and the capacitor 45 of the detection circuit 10 and the conversion circuit 40 may be incorporated in the microcomputer together with the CPU. In general, a microcomputer that has a built-in resistance value / frequency conversion circuit (also called “R / F converter”) and can configure a temperature sensor by externally attaching a reference resistor, thermistor, and capacitor with a small temperature coefficient has been developed. Has been. If such a microcomputer is used, the pressure transducer 1 subjected to temperature compensation can be easily configured. Alternatively, the switch circuit 15, the drive circuit 20, and the amplifier circuit 30 may be integrated into an IC or a hybrid IC, and a module integrated with the detection circuit 10 by a flexible substrate or the like may be configured as a module. The integrated circuit and the detection circuit 10 may be integrated into a single chip and configured as an integrated sensor.

Next, the operation of the pressure transducer according to the present embodiment will be described with reference to FIG.
FIG. 2 is a waveform diagram showing changes in signals at various parts of the pressure transducer shown in FIG. When the apparatus or system on which the pressure transducer 1 is mounted is turned on, the power supply voltage V _DD and the system clock signal are supplied to the pressure transducer 1. When pressure is not measured (pause mode), the control unit 50 sets the control signal CTL1 to the high level. Therefore, the transistor 15 is turned off, and almost no current flows through the detection circuit 10, so that the current consumption of the pressure transducer 1 can be reduced.

At this time, since the control unit 50 sets the control signals CTL2, CTL3, and CTL4 to the high level, the transistors 41 and 43 are turned off, the transistor 46 is turned on, and the count enable signal output from the AND circuit 48 _VCE is deactivated to a low level.

  For example, the control unit 50 causes the pressure transducer 1 to shift from the pause mode to the measurement mode in accordance with a command supplied from the outside. In the measurement mode, first, the control unit 50 activates the control signal CTL1 to a low level for a predetermined period. Thereby, the transistor 15 is turned on, the constant current I flows by the drive circuit 20, and the detection circuit 10 starts operation.

  When the warm-up of the detection circuit 10 is completed after a stabilization period (for example, 10 seconds) in which the piezoresistive elements 11 to 14 of the bridge circuit are thermally stabilized, the control unit 50 activates the control signal CTL2 to a low level. And the control signal CTL4 is deactivated to a low level. In this way, by starting the operation of the conversion circuit 40 after the stabilization period has elapsed, it is possible to prevent an unstable operation of the pressure transducer 1 when the detection circuit 10 is activated.

When the control signal CTL2 is activated to a low level, the transistor 41 is turned on, so that the capacitor 45 is charged through the first charging path. Accordingly, the voltage V _{E at the} node E rises above the threshold value V _TH1 of the Schmitt trigger buffer 47 during the time constant τ ₁ determined by the resistance value of the resistor 42 and the capacitance of the capacitor 45, and Schmitt the output signal V _ST trigger buffer 47 is activated to a high level.

When the control signal CTL2 period tau ₁ has elapsed since the activation, the control unit 50 is configured to deactivate the control signal CTL2 to the high level, and activates the control signal CTL4 to the predetermined time period a high level. As a result, the count enable signal V _CE output from the AND circuit 48 is activated to a high level. Further, since the transistor 41 is turned off, the first charging path is electrically cut off, and the transistor 46 is turned on, so that the charge of the capacitor 45 is discharged through the discharge path. Therefore, as shown in FIG. 2, the voltage V _{E at the} node E falls below the threshold V _TH2 of the Schmitt trigger buffer 47, and the output signal V _ST of the Schmitt trigger buffer 47 is deactivated to a low level. As a result, the count enable signal V _CE output from the AND circuit 48 is deactivated to a low level. As a result, the count enable signal V _CE, the control signal CTL4 is in the period from being activated to the high level until the voltage V _E of node E drops below the threshold value V _TH2, are activated to a high level.

The count enable signal V _CE output from the AND circuit 48 is supplied to the counter 49. The counter 49 counts the number of pulses included in the clock signal during the period in which the count enable signal _VCE is activated to a high level. The count value of the counter 49 is stored in a memory or the like inside the microcomputer as the reference pulse number.

After a sufficient period for discharging the capacitor 45 has elapsed, the control unit 50 deactivates the control signal CTL4 to low level, and then activates the control signal CTL3 to low level. When the control signal CTL3 is activated to a low level, the transistor 43 is turned on, so that the capacitor 45 is charged through the second charging path. Therefore, the voltage V _{E at the} node E rises above the threshold value V _TH1 of the Schmitt trigger buffer 47 during the time constant τ ₂ determined by the resistance value of the resistor 44 and the capacitance of the capacitor 45, and Schmitt the output signal V _ST trigger buffer 47 is activated to a high level.

In FIG. 2, three types of voltages V _{E1 to} V _E3 at the node E are shown according to the pressure applied to the detection circuit 10 from the outside. Here, when no pressure is applied to the diaphragm of the detection circuit 10, the output voltage V _C and the output voltage V _D are balanced, and the voltage difference is almost zero. At that time, the output voltage V _OP of the operational amplifier 35 of the amplifier circuit 30 becomes the offset voltage V _DD / 2.

On the other hand, when the pressure to the diaphragm of the detection circuit 10 is added, the output voltage V with the resistance value of the piezoresistive element changes by the diaphragm deflects, the output voltage V _C in response to deflection increases _D decreases. The difference between the output voltage V _C and the output voltage V _D is about several mV, but when amplified by the amplifier circuit 30, the output voltage V _OP of the operational amplifier 35 of the amplifier circuit 30 becomes the offset voltage V _DD / 2. It changes in the range of the power supply voltage V _DD .

When the control signal CTL3 period tau ₂ has elapsed since the activation, the control unit 50 is configured to deactivate the control signal CTL3 to the high level, and activates the control signal CTL4 to the predetermined time period a high level. As a result, the count enable signal V _CE output from the AND circuit 48 is activated to a high level. Further, since the transistor 43 is turned off, the second charging path is electrically cut off, and the transistor 46 is turned on, so that the charge of the capacitor 45 is discharged through the discharge path. Therefore, as shown in FIG. 2, the voltage V _{E at the} node E falls below the threshold V _TH2 of the Schmitt trigger buffer 47, and the output signal V _ST of the Schmitt trigger buffer 47 is deactivated to a low level. As a result, the count enable signal V _CE output from the AND circuit 48 is deactivated to a low level. As a result, the count enable signal V _CE, the control signal CTL4 is in the period from being activated to the high level until the voltage V _E of node E drops below the threshold value V _TH2, are activated to a high level.

In FIG. 2, three types of count enable signals V _{CE1 to} V _CE3 are shown according to the pressure applied to the detection circuit 10 from the outside. As shown in FIG. 2, the amplifier circuit 30 higher the voltage V _E of node E when the charging is performed to the capacitor 45 through the second charging path is larger, the activation count enable signal V _CE is the high level The period of time will be longer.

The count enable signal V _CE output from the AND circuit 48 is supplied to the counter 49. The counter 49 counts the number of pulses included in the clock signal during the period in which the count enable signal _VCE is activated to a high level. The count value of the counter 49 is stored in the memory or the like inside the microcomputer as the number of detected pulses.

  The control unit 50 obtains a difference between the number of detected pulses and the number of reference pulses, and calculates a pressure according to the difference. When the measurement of the pressure ends, the control unit 50 deactivates the control signal CTL1 to a high level and turns off the transistor 15.

  Here, the zero point adjustment and sensitivity adjustment of the piezoresistive elements 11 to 14 and the like can be processed by the hardware or software of the control unit 50 based on the digitized pulse number (count value). There is no need to configure a circuit or the like as an external circuit, and an increase in circuit scale can be prevented.

Next, a second embodiment of the present invention will be described.
FIG. 3 is a circuit diagram showing a configuration of a pressure transducer according to the second embodiment of the present invention. The configuration of the pressure transducer 2 shown in FIG. 3 is the same as the configuration of the pressure transducer 1 according to the first embodiment shown in FIG. The amplifier circuit 60 includes a first buffer amplifier composed of an operational amplifier 61 and a resistor 62, a second buffer amplifier composed of an operational amplifier 63 and a resistor 64, and a difference composed of a resistor 31 to a resistor 34 and an operational amplifier 35. Dynamic amplification circuit (differential amplifier). The differential amplifier circuit is the same as that shown in FIG.

  Such an amplifier circuit is known as an instrumentation amplifier. According to this, since the input impedances of the first and second buffer amplifiers can be extremely increased, an accurate operational amplification operation can be performed. Further, as shown in FIG. 3, the gain of the amplifier circuit 60 is increased by inserting a resistor 65 between the inverting input terminal of the operational amplifier 61 and the inverting input terminal of the operational amplifier 63. The operation of the pressure transducer 2 is the same as that in the first embodiment described with reference to FIGS. 1 and 2.

1 is a circuit diagram showing a configuration of a pressure transducer according to a first embodiment of the present invention. The wave form diagram which shows the change of the signal in each part of the pressure transducer shown in FIG. The circuit diagram which shows the structure of the pressure transducer which concerns on the 2nd Embodiment of this invention.

Explanation of symbols

  1, 2 pressure transducer, 10 detection circuit, 11-14 piezoresistive element, 15, 41, 43 P channel transistor, 20 drive circuit, 21, 46 N channel transistor, 22, 35, 61, 63, operational amplifier, 23, 31 ˜34, 42, 44, 62, 64, 65 Resistance, 30, 60 Amplifier circuit, 40 Converter circuit, 45 Capacitor, 47 Schmitt trigger buffer, 48 AND circuit, 49 Counter, 50 Control unit, 51 Dividing circuit

Claims (3)

A bridge circuit composed of four piezoresistive elements whose resistance value is changed by pressure applied from the outside;
A switch circuit that is turned on in accordance with a control signal and supplies a power supply potential to the first node of the bridge circuit;
A drive circuit connected to a second node of the bridge circuit and for passing a current through the bridge circuit when the switch circuit is in an on state;
An amplifier circuit for amplifying a potential difference between a third node and a fourth node of the bridge circuit;
By counting the number of pulses included in the clock signal in the first period corresponding to the magnitude of the predetermined potential and in the second period corresponding to the magnitude of the output potential of the amplifier circuit, A conversion circuit for respectively obtaining a first count value and a second count value;
A control unit that generates a control signal to be supplied to the switch circuit and calculates a value related to pressure based on the first and second count values, and activates the control signal when starting measurement of pressure The control unit that operates the conversion circuit after a predetermined period has elapsed since the switch circuit is turned on.
A pressure transducer comprising: The conversion circuit is
A capacitor,
A first charging circuit that charges the capacitor with a predetermined potential in accordance with a second control signal supplied from the control unit;
A second charging circuit that charges the capacitor with an output potential of the amplifier circuit according to a third control signal supplied from the control unit;
A discharge circuit for discharging the charge charged in the capacitor according to a fourth control signal supplied from the control unit;
Based on the voltage across the capacitor, an enable signal that is activated in a first period corresponding to the magnitude of a predetermined potential and a second period corresponding to the magnitude of the output potential of the amplifier circuit is generated. Logic circuit;
In the first and second periods in which the enable signal output from the logic circuit is activated, the first count value and the second count are obtained by counting the number of pulses included in the clock signal. A counter for each value,
The pressure transducer of claim 1, comprising: The amplifier circuit is
A first buffer amplifier for inputting a potential of a third node of the bridge circuit;
A second buffer amplifier for inputting a potential of a fourth node of the bridge circuit;
A differential amplifier for amplifying a potential difference between an output potential of the first buffer amplifier and an output potential of the second buffer amplifier;
The pressure transducer according to claim 1, comprising:

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