JP2008109110A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce parasitic resistance in an amplifier circuit, restrain reduction of photosensitivity of a photoelectric conversion element provided in a semiconductor device, and stably operate the amplifier circuit for amplifying an output current of the photoelectric conversion element. <P>SOLUTION: The semiconductor device comprises: a photoelectric conversion element; a current mirror circuit having at least two thin film transistors; a high potential power supply connected electrically with the thin film transistors; and a low potential power supply connected electrically with the thin film transistors. When the thin film transistor on a reference side is an n type one, the thin film transistor on the reference side is disposed in the vicinity of the low potential power supply. When the thin film transistor on the reference side is a p type one, the thin film transistor on the reference side is disposed in the vicinity of the high potential power supply. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a photoelectric conversion device and a semiconductor device including the photoelectric conversion device, and more particularly to a photoelectric conversion device including a thin film semiconductor element and a manufacturing method thereof. In addition, the present invention relates to an electronic device using a photoelectric conversion device.

  Many photoelectric conversion devices generally used for detecting electromagnetic waves are known. For example, devices that detect infrared rays from ultraviolet rays are collectively called optical sensors. Among them, a device that detects light in the visible light region with a wavelength of 400 nm to 700 nm is called a visible light sensor, and is used in many devices that require illuminance adjustment and on / off control according to the human living environment. Yes.

  Particularly in a display device, the brightness around the display device is detected and the display luminance is adjusted. This is because it is possible to reduce wasteful power by detecting ambient brightness and obtaining appropriate display brightness. For example, such an optical sensor for brightness adjustment is used in a mobile phone or a personal computer.

  Further, not only the brightness of the surroundings but also the brightness of the backlight of a display device, particularly a liquid crystal display device, is detected by an optical sensor to adjust the brightness of the display screen.

In such an optical sensor, a photodiode is used for a sensing portion, and an output current of the photodiode is amplified by an amplifier circuit. For example, a current mirror circuit is used as such an amplifier circuit (see, for example, Patent Document 1).
Japanese Patent No. 3444093

  Many conventional amplifier circuits have a multi-stage configuration including a correction circuit, and a large power supply voltage is required. In recent years, it has been required to stably supply a power supply voltage in constructing an electric circuit from various aspects such as energy saving and high performance.

  However, the amplifying circuit as described above, for example, a current mirror circuit, is composed of a thin film transistor (TFT), and a parasitic resistance due to a wiring layer resistance or a contact resistance of a conductive layer constituting the TFT and a wiring connected thereto. There was a problem that would occur.

  In particular, in the current mirror circuit, it will be described below that if a parasitic resistance is generated in the TFT on the reference side, the range of the detected light intensity may be reduced.

  FIG. 3 is a circuit diagram of a conventional semiconductor device including a photodiode and an amplifier circuit. The semiconductor device in FIG. 3 includes a current mirror circuit 1011 including a power source 1001, a photodiode 1003, a reference-side TFT 1004, and an output-side TFT 1005. A parasitic resistance 1006 is generated in the reference TFT 1004.

Let R be the resistance value of the parasitic resistance 1006. A voltage V _gate applied to the gate electrodes of the TFTs 1004 and 1005 when the parasitic resistance 1006 is not generated is set to V ₁ . Also the voltage _{V gate} applied to the gate electrode of the TFT1004 and 1005 when the parasitic resistance 1006 is generated as _{V 2.}

As shown in FIG. 4, when the parasitic resistance 1006 is generated, the upper limit of V _gate when the output current (photocurrent) is saturated is reduced by ΔV = R × I, from V ₁ to V _2. End up. That is, a decrease in the upper limit of V _gate leads to a decrease in the upper limit of photocurrent I. Furthermore, the intensity of light that can be sensed decreases.

The photocurrent I saturates at I ₁ when V ₁ , but saturates at I ₂ when V ₂ , and no longer flows. Since the photocurrent I is proportional to the light intensity E as shown in FIG. 5, if the photocurrent I is saturated at I ₂ , the maximum light intensity E that can be sensed is L ₂ , and the photoelectric conversion device Sensitivity will decrease.

  In view of the above problems, the present invention suppresses the parasitic resistance generated in the TFT on the reference side of the current mirror circuit, prevents the voltage applied to the gate electrode from decreasing, and suppresses the decrease in sensitivity of the photoelectric conversion device. This is the issue.

The present invention includes a photoelectric conversion element, a current mirror circuit having a reference thin film transistor and an output side thin film transistor, the current mirror circuit amplifying the output of the photoelectric conversion element, and a high potential electrode and a low potential electrode. A power source having a potential electrode, the reference thin film transistor and the output thin film transistor are n-type thin film transistors, and one of a source electrode and a drain electrode of the reference thin film transistor is connected to the photoelectric conversion element Electrically connected to the high potential electrode, one of a source electrode and a drain electrode of the thin film transistor on the output side is electrically connected to the high potential electrode, and the other of the source electrode and the drain electrode of the reference thin film transistor is A source electrode of the thin film transistor on the output side, electrically connected to the low potential electrode The other of the fine drain electrode connected said low potential electrode and electrically, the reference side of the thin film transistor is positioned at the close to the low-potential electrode than the output side of the thin film transistor. The length of the wiring that electrically connects the thin film transistor on the reference side and the low potential electrode is shorter than the length of the wiring that electrically connects the thin film transistor on the output side and the low potential electrode. The length of the current path between the reference side thin film transistor and the low potential electrode is shorter than the length of the current path between the output side thin film transistor and the low potential electrode. Accordingly, the present invention relates to a semiconductor device characterized in that a decrease in voltage applied to the gate electrode of the reference-side thin film transistor is suppressed.
The present invention also includes a photoelectric conversion element, a current mirror circuit having a reference thin film transistor and an output side thin film transistor, wherein the current mirror circuit amplifies the output of the photoelectric conversion element, The reference thin film transistor and the output thin film transistor are p-type thin film transistors, and one of the source electrode and the drain electrode of the reference thin film transistor is electrically connected to the high potential electrode. One of the source electrode and the drain electrode of the output side thin film transistor is electrically connected to the high potential electrode, and the other of the source electrode and the drain electrode of the reference thin film transistor is connected to the photoelectric conversion element. A source of the output side thin film transistor electrically connected to the low potential electrode Kyokuoyobi other drain electrode is connected the low potential electrode and electrically, the reference side of the thin film transistor is placed closer and the high-potential electrode than the output side of the thin film transistor. The length of the wiring that electrically connects the thin film transistor on the reference side and the high potential electrode is shorter than the length of the wiring that electrically connects the thin film transistor on the output side and the high potential electrode. The length of the current path between the reference side thin film transistor and the high potential side electrode is shorter than the length of the current path between the output side thin film transistor and the high potential electrode. Accordingly, the present invention relates to a semiconductor device characterized in that a decrease in voltage applied to the gate electrode of the reference-side thin film transistor is suppressed.

  The present invention also includes a photoelectric conversion element, a current mirror circuit including a reference thin film transistor and a plurality of output-side thin film transistors, wherein the current mirror circuit amplifies the output of the photoelectric conversion element to generate a high potential A power source having an electrode and a low potential electrode, the reference thin film transistor and the plurality of output side thin film transistors are n-type thin film transistors, and one of the source thin film transistor and the drain electrode of the reference thin film transistor is the photoelectric transistor. Electrically connected to the high potential electrode via a conversion element, and one of the source electrode and drain electrode of the plurality of output side thin film transistors is electrically connected to the high potential electrode, and the source of the reference thin film transistor The other of the electrode and the drain electrode is electrically connected to the low potential electrode, and the plurality of output side The other of the source electrode and the drain electrode of the membrane transistor is electrically connected to the low potential electrode, and the reference-side thin film transistor is disposed closer to the low potential electrode than each of the plurality of output-side thin film transistors. The The length of the wiring that electrically connects the thin film transistor on the reference side and the low potential electrode is shorter than the length of the wiring that electrically connects the thin film transistor on the output side and the low potential electrode. The length of the current path between the reference side thin film transistor and the low potential electrode is shorter than the length of the current path between the plurality of output side thin film transistors and the low potential electrode.

  The present invention also includes a photoelectric conversion element, a current mirror circuit including a reference thin film transistor and a plurality of output-side thin film transistors, wherein the current mirror circuit amplifies the output of the photoelectric conversion element to generate a high potential A power source having an electrode and a low potential electrode, the reference thin film transistor and the plurality of output side thin film transistors are p-type thin film transistors, and one of the source thin film transistor and the drain electrode of the reference thin film transistor Electrically connected to the potential electrode, one of the source electrode and drain electrode of the plurality of output side thin film transistors is electrically connected to the high potential electrode, and the other of the source electrode and drain electrode of the reference thin film transistor is Electrically connected to the low potential electrode via the photoelectric conversion element, and the plurality of output side The other of the source electrode and the drain electrode of the film transistor is electrically connected to the low potential electrode, and the thin film transistor on the reference side is disposed closer to the high potential electrode than each of the thin film transistors on the output side. The The length of the wiring that electrically connects the thin film transistor on the reference side and the high potential electrode is shorter than the length of the wiring that electrically connects the thin film transistor on the output side and the high potential electrode. The length of the current path between the reference side thin film transistor and the high potential electrode is shorter than the length of the current path between each of the plurality of output side thin film transistors and the high potential electrode.

  The present invention relates to a photoelectric conversion element, a current mirror circuit that amplifies the output of the photoelectric conversion element and has at least two thin film transistors, a high-potential power supply electrically connected to each of the thin film transistors, and each of the thin film transistors Of the thin film transistors, the reference-side thin film transistor is disposed close to the low-potential power source, and is applied to the gate electrode of the reference-side thin film transistor. The present invention relates to a semiconductor device characterized by suppressing a decrease in voltage.

  According to another aspect of the present invention, a photoelectric conversion element, an output of the photoelectric conversion element, a reference side thin film transistor, a current mirror circuit having a plurality of output side thin film transistors, the reference side thin film transistor, and the plurality of output sides are provided. A high potential power source electrically connected to each of the thin film transistors, a low potential power source electrically connected to each of the reference side thin film transistor and the plurality of output side thin film transistors, and the reference side thin film transistor The present invention relates to a semiconductor device, which is disposed closer to the low-potential power supply than each of the output-side thin film transistors.

  Note that in this specification, the thin film transistor on the reference side is arranged as close to the low potential power source as the design rule permits.

  Note that in this specification, a semiconductor device refers to a device including a semiconductor layer, and an entire device including an element including a semiconductor layer is also referred to as a semiconductor device.

  According to the present invention, a photoelectric conversion device in which a reduction in photosensitivity is suppressed can be obtained. In addition, since the occurrence of parasitic resistance is suppressed, it is possible to obtain a highly reliable product with stable circuit operation.

[Embodiment 1]
This embodiment is shown in FIGS. 1, 2, 3, 4, 5, 6, 6, 7, 8, 10, 11, 11A to 11C, and 12. This will be described below with reference to FIGS. 12A to 12C, FIGS. 13A to 13B, and FIGS. 14A to 14C.

  However, it will be readily understood by those skilled in the art that the present invention can be implemented in many different modes, and that various modifications can be made without departing from the spirit and scope of the present invention. The Therefore, the present invention is not construed as being limited to the description of this embodiment mode.

  Note that in all the drawings for describing the embodiments, the same portions or portions having similar functions are denoted by the same reference numerals, and repetitive description thereof is omitted.

  As shown in FIG. 1, the semiconductor device of this embodiment includes a current mirror circuit 111 composed of transistors 104 and 105, and a power source (bias) 101. In this embodiment mode, thin film transistors (TFTs) are used as the transistors 104 and 105, and the TFTs 104 and 105 are n-channel TFTs.

  A current mirror circuit composed of n-channel TFTs is composed of a reference-side TFT 104 and an output-side TFT 105 (see FIG. 1). By applying the same voltage to the gate portions of the reference TFT 104 and the output TFT 105, the current flowing in the output TFT 105 is controlled based on the current flowing in the reference TFT 104.

  FIG. 2 shows a block diagram. 2 includes a photodiode 103, a current mirror circuit 111 having a reference-side TFT 104 and an output-side TFT 105, a high-voltage potential (VDD) connection electrode (also referred to as a “high-potential electrode”) 141, a low-voltage potential. (VSS) connection electrode (also referred to as “low potential electrode”) 142, photodiode 103 and TFTs 104 and 105 are electrically connected to wiring 144, TFTs 104 and 105, and electrode 141 is electrically connected to wiring 145, TFT 104 and 105 and a wiring 146 (a wiring 146a, a wiring 146b, a wiring 146c, a wiring 146d, and the like) that electrically connect the electrode 142 and the electrode 142. In FIG. 2, only four wirings 146 (wiring 146a, wiring 146b, wiring 146c, and wiring 146d) are shown, but the number may be determined as necessary. The output-side TFT 105 is formed of a plurality of TFTs, and an output current (photocurrent) is amplified according to the number of TFTs.

  As shown in FIG. 26, the reference side TFT 104 may be formed separately from the output side TFT 105. In that case, the electrode 142 may be electrically connected to the electrode 142 through a wiring 147 different from the wiring 146.

The TFT 104 on the reference side is disposed near the electrode 142 so that the voltage V _gate applied to the gate electrode does not decrease due to wiring resistance or the like.

The reference-side TFT 104 is disposed closer to the electrode 142 than the output-side TFT 105. The length of the wiring that electrically connects the TFT 104 on the reference side and the electrode 142 is shorter than the length of the wiring that electrically connects the TFT 105 on the output side and the electrode 142. The length of the current path between the reference-side TFT 104 and the electrode 142 is shorter than the length of the current path between the output-side TFT 105 and the electrode 142. As a result, it is possible to suppress a reduction in the voltage V _gate applied to the gate electrode.

When parasitic resistance occurs in the reference side TFT 104, the voltage V _gate applied to the gate electrode of the TFT 104 is changed from the gate-source voltage V _gs to the resistance value R × output current (photocurrent) I (= ΔV) of the parasitic resistance. Will fall by the amount of.

FIG. 4 is a diagram showing the relationship between the voltage V _gate applied to the gate electrode of the TFT 104 and the output current (photocurrent) I. The horizontal axis is the voltage V _gate (linear scale), and the vertical axis is the photocurrent I (log scale). is there. FIG. 5 shows the relationship between illuminance E and output current (photocurrent) I, where the horizontal axis represents illuminance E (log scale) and the vertical axis represents photocurrent I (log scale).

As shown in FIG. 4, when parasitic resistance occurs, V _gate is changed from V ₁ (V _gate when the parasitic resistance is minimum) to V ₂ (V ₁ −ΔV: V _gate when the parasitic resistance is generated). turn into. The photocurrent I saturates at I ₁ when V ₁ , but saturates at I ₂ when V ₂ , and stops flowing any more. Since the photocurrent I is proportional to the light intensity E as shown in FIG. 5, if the photocurrent I is saturated at I ₂ , the maximum light intensity E that can be sensed is L ₂ , and the photoelectric conversion device Sensitivity will decrease.

However, in practice, it is difficult to set the parasitic resistance such as the wiring resistance to 0, and thus V ₁ may not necessarily match V _gate when the parasitic resistance is not generated.

However, in the present invention, the TFT 104 on the reference side is disposed near the connection electrode 142 for the low potential voltage V _ss , so that the wiring resistance between the TFT 104 and the electrode 142 can be minimized, and parasitic resistance is generated. Can be minimized. Thereby, the fall of the sensitivity of a photoelectric conversion apparatus can be suppressed.

  In order to further reduce the wiring resistance, the width of the wiring that electrically connects the TFT 104 and the electrode 142 may be increased, or the film thickness of the conductive film forming the wiring may be increased.

By the way, as a method of extracting an output signal format as a voltage, which is generally said to be easy to perform signal processing, there is a method of converting a current into a voltage by a load resistor _RL . Specifically, as shown in FIG. 6, in a circuit having a photodiode 123 and a current mirror circuit 111, a power supply 101, an output terminal 124, and a load resistance _RL , an output current using the load resistance _RL. Can be converted into a voltage and an output signal can be taken out as a voltage at the output terminal 124. A circuit in which the circuit 123 including the current mirror circuit 111 of FIG. 1 is incorporated in the circuit of FIG. 6 will be described below.

  In FIG. 1, the gate electrode of the TFT 104 constituting the current mirror circuit 111 is electrically connected to the gate electrode of another TFT 105 constituting the current mirror circuit 111, and is further referred to as a drain electrode (also referred to as “drain terminal”) of the TFT 104. ) Is electrically connected.

  The drain terminal of the TFT 104 is electrically connected to the drain terminal of the TFT 105 through the photodiode 103.

  A source electrode (also referred to as “source terminal”) of the TFT 104 is electrically connected to the source terminal of the TFT 105.

In the present embodiment, the output terminal 124 of the circuit 123 including the current mirror circuit 111 is electrically connected to the low potential side of the power supply 101 via the load resistor _RL .

  In FIG. 1, the gate electrode of the TFT 105 constituting the current mirror circuit 111 is electrically connected to the drain terminal of the TFT 104.

  Further, since the gate electrodes of the TFTs 104 and 105 are connected to each other, a common potential is applied.

  FIG. 1 illustrates an example of a current mirror circuit using two TFTs. At this time, when 104 and 105 have the same characteristics, the ratio of the reference current and the output current is 1: 1.

  7 and 8 show circuit configurations for increasing the output value by n times. The circuit configuration in FIG. 7 corresponds to the n TFTs 105 in FIG. As shown in FIG. 7, by setting the ratio of the n-channel TFT 104 and the n-channel TFT 105 to 1: n, the output value can be increased by n times. This is the same principle as increasing the channel width W of the TFT and increasing the allowable amount of current that can be passed through the TFT n times.

  For example, when designing the output value to be 100 times, a target current can be obtained by connecting one n-channel TFT 104 and 100 n-channel TFTs 105 in parallel.

  FIG. 8 shows a detailed circuit configuration of the circuit 118i (circuit 118a, circuit 118b, etc.) in FIG.

  The circuit configuration of FIG. 8 is based on the circuit configurations of FIGS. 1 and 7, and the same elements are denoted by the same reference numerals. That is, the gate electrode of the TFT 105i is electrically connected to the terminal 119i, and the drain terminal is electrically connected to the terminal 120i. The source terminal of the TFT 105i is electrically connected to the terminal 121i.

  In order to describe the circuit 118a, the circuit 118b, and the like in FIG. 7, a circuit 118i, which is one of them, is shown in FIG. Since the circuit 118i is based on the circuit configuration of FIG. 1, the reference numerals with “i” in FIG. 8 are the same as the reference numerals without “i” in FIG. That is, for example, the TFT 105 in FIG. 1 and the TFT 105 i in FIG. 8 are the same.

  Accordingly, in FIG. 7, the n-channel TFT 105 is composed of n n-channel TFTs 105a, 105b, 105i, and the like. As a result, the current flowing through the TFT 104 is amplified n times and output.

  7 and 8, the same reference numerals are used to indicate the same components as those in FIG.

  1 shows the current mirror circuit 111 as an equivalent circuit using an n-channel TFT, but a p-channel TFT may be used instead of the n-channel TFT.

  When the amplifier circuit is formed of a p-channel TFT, an equivalent circuit shown in FIG. 9 is obtained. As shown in FIG. 9, the current mirror circuit 203 has p-channel TFTs 201 and 202. The p-channel TFT 201 is disposed at a position closer to the high potential electrode 141 than the p-channel TFT 202. The length of the electrical connection wiring between the p-channel TFT 201 and the electrode 141 is shorter than the length of the electrical connection wiring between the p-channel TFT 202 and the electrode 141. The length of the current path between the p-channel TFT 201 and the electrode 141 is shorter than the length of the current path between the p-channel TFT 202 and the electrode 141. 1 and 9 are denoted by the same reference numerals. In order to extract the output signal format as a voltage, a configuration using the circuit 204 instead of the circuit 123 in FIG. 6 may be used.

  FIG. 10 shows a cross-sectional view of the current mirror circuit 111 including the TFTs 104 and 105 and the circuit 123 including the photodiode 103 in FIG.

  In FIG. 10, 210 is a substrate, 212 is a base insulating film, and 213 is a gate insulating film.

  The connection electrode 285, the terminal electrode 281, the source electrode or drain electrode 282 of the TFT 104, and the source electrode or drain electrode 283 of the TFT 105 are stacked layers of a refractory metal film and a low resistance metal film (such as an aluminum alloy or pure aluminum). It has a structure. Here, the connection electrode 285, the terminal electrode 281, the source or drain electrodes 282 and 283 have a three-layer structure in which a titanium film (Ti film), an aluminum film (Al film), and a Ti film are sequentially stacked.

  Further, instead of the laminated structure of the refractory metal film and the low resistance metal film, a single-layer conductive film can be used. As such a single-layer conductive film, titanium (Ti), tungsten (W), tantalum (Ta), molybdenum (Mo), neodymium (Nd), cobalt (Co), zirconium (Zr), zinc (Zn), An element selected from ruthenium (Ru), rhodium (Rh), palladium (Pd), osmium (Os), iridium (Ir), platinum (Pt), or an alloy material or a compound material containing the element as a main component A single-layer film or a single-layer film made of these nitrides, for example, titanium nitride, tungsten nitride, tantalum nitride, or molybdenum nitride can be used.

  In FIG. 10, n-channel TFTs 104 and 105 each show an example of a top-gate TFT having a structure including one channel formation region (referred to as a “single gate structure” in this specification). There may be a plurality of structures to reduce variations in on-current value.

  Further, in order to reduce the off-current value, a lightly doped drain (LDD) region may be provided in the n-channel TFTs 104 and 105. An LDD region is a region in which an impurity element is added at a low concentration between a channel formation region and a source region or a drain region formed by adding an impurity element at a high concentration. When the LDD region is provided, There is an effect that the electric field in the vicinity of the drain region is relaxed to prevent the TFT from being deteriorated by hot carrier injection.

  In order to prevent a decrease in the on-current value due to hot carriers, the n-channel TFTs 104 and 105 have a structure in which an LDD region is overlapped with a gate electrode through a gate insulating film (in this specification, “GOLD (Gate− (Drain Overlapped LDD) structure ”).

  When the GOLD structure is used, there is an effect that the electric field in the vicinity of the drain region is further relaxed and TFT deterioration due to hot carrier injection is prevented, compared with the case where the LDD region is not formed overlapping the gate electrode. With such a GOLD structure, the electric field strength in the vicinity of the drain region is relaxed, hot carrier injection is prevented, and TFT deterioration is effective.

  The TFTs 104 and 105 forming the current mirror circuit 111 may be not only a top gate type TFT but also a bottom gate type TFT, for example, an inverted stagger type TFT.

  The wiring 215 is electrically connected to the drain wiring (also referred to as a drain electrode) or the source wiring (also referred to as a source electrode) of the TFT 104. Reference numerals 216 and 217 denote insulating films, and reference numeral 285 denotes a connection electrode. Note that the insulating film 217 is preferably a silicon oxide film formed by a CVD method. When the insulating film 217 is a silicon oxide film formed by a CVD method, the fixing strength is improved.

  The terminal electrode 250 is formed in the same process as the wiring 215, and the terminal electrode 281 is formed in the same process as the connection electrode 285.

  The terminal electrode 221 is mounted on the electrode 261 of the substrate 260 with solder 264. The terminal electrode 222 is formed in the same process as the terminal electrode 221 and is mounted on the electrode 262 of the substrate 260 with solder 263.

  In the following, a process for manufacturing a semiconductor device including the photodiode 103 and the current mirror circuit 111 having the TFTs 104 and 105 shown in FIG. 10 will be described with reference to FIGS. A description will be given with reference to FIGS. 12A to 12C and FIGS. 13A to 13B.

  First, an element is formed over a substrate (first substrate 210). Here, AN100 which is one of glass substrates is used as the substrate 210.

  Next, a silicon oxide film (thickness: 100 nm) containing nitrogen is formed as a base insulating film 212 by plasma CVD, and further a semiconductor film such as an amorphous silicon film (thickness: 54 nm) containing hydrogen without being exposed to the atmosphere. Are stacked. Alternatively, the base insulating film 212 may be stacked using a silicon oxide film, a silicon nitride film, or a silicon oxide film containing nitrogen. For example, a film in which a silicon nitride film containing oxygen is stacked with a thickness of 50 nm and a silicon oxide film containing nitrogen is stacked with a thickness of 100 nm may be formed as the base insulating film 212. Note that the silicon oxide film containing nitrogen or the silicon nitride film containing oxygen functions as a blocking layer for preventing diffusion of impurities such as alkali metal from the glass substrate.

  Next, the amorphous silicon film is crystallized by a solid phase growth method, a laser crystallization method, a crystallization method using a catalytic metal, or the like, so that a semiconductor film having a crystal structure (crystalline semiconductor film), for example, polycrystalline A silicon film is formed. Here, a polycrystalline silicon film is obtained by a crystallization method using a catalytic element. A solution containing 10 ppm of nickel in terms of weight is added to the surface of the amorphous silicon film using a spinner. Instead of adding with a spinner, a method of spreading nickel element over the entire surface by sputtering may be used. Next, heat treatment is performed for crystallization to form a semiconductor film having a crystal structure (here, a polycrystalline silicon film). Here, after heat treatment (500 ° C., 1 hour), heat treatment for crystallization (550 ° C., 4 hours) is performed to obtain a polycrystalline silicon film.

  Next, the oxide film on the surface of the polycrystalline silicon film is removed with dilute hydrofluoric acid or the like. Thereafter, laser beam irradiation is performed to increase the crystallization rate and repair defects remaining in the crystal grains.

  Note that when an amorphous silicon film is crystallized by a laser crystallization method to obtain a crystalline semiconductor film, or after obtaining a semiconductor film having a crystal structure, laser irradiation is performed to repair defects remaining in crystal grains. When performing, the laser irradiation method described below may be used.

Laser irradiation can be performed using a continuous wave laser beam (CW laser beam) or a pulsed laser beam (pulse laser beam). The laser beam that can be used here is a gas laser such as an Ar laser, a Kr laser, or an excimer laser, single crystal YAG, YVO ₄ , forsterite (Mg ₂ SiO ₄ ), YAlO ₃ , GdVO ₄ , or polycrystalline ( (Ceramics) YAG, Y ₂ O ₃ , YVO ₄ , YAlO ₃ , GdVO ₄ with one or more of Nd, Yb, Cr, Ti, Ho, Er, Tm, Ta added as dopants A laser oscillated from one or more of laser, glass laser, ruby laser, alexandrite laser, Ti: sapphire laser, copper vapor laser, or gold vapor laser as a medium can be used. By irradiating the fundamental wave of such a laser beam and the second to fourth harmonic laser beams of these fundamental waves, a crystal having a large grain size can be obtained. For example, a second harmonic (532 nm) or a third harmonic (355 nm) of an Nd: YVO ₄ laser (fundamental wave 1064 nm) can be used. Energy density of the laser is about 0.01 to 100 MW / cm ² (preferably 0.1 to 10 MW / cm ²⁾ is required. Then, irradiation is performed at a scanning speed of about 10 to 2000 cm / sec.

Note that single crystal YAG, YVO ₄ , forsterite (Mg ₂ SiO ₄ ), YAlO ₃ , GdVO ₄ , or polycrystalline (ceramic) YAG, Y ₂ O ₃ , YVO ₄ , YAlO ₃ , GdVO ₄ , dopants Nd, Yb, Cr, Ti, Ho, Er, Tm, and Ta, a laser that uses one or a plurality of types added as a medium, Ar laser, Kr laser, or Ti: sapphire laser It is also possible to oscillate pulses at an oscillation frequency of 10 MHz or more by performing Q switch operation or mode synchronization. When the laser beam is oscillated at an oscillation frequency of 10 MHz or more, the semiconductor film is irradiated with the next pulse during the period from when the semiconductor film is melted by the laser to solidification. Therefore, unlike the case of using a pulse laser having a low oscillation frequency, the solid-liquid interface can be continuously moved in the semiconductor film, so that crystal grains continuously grown in the scanning direction can be obtained.

  When ceramic (polycrystal) is used as the medium, it is possible to form the medium in a free shape in a short time and at low cost. When a single crystal is used, a cylindrical medium having a diameter of several millimeters and a length of several tens of millimeters is usually used. However, when ceramic is used, a larger one can be made.

  Since the concentration of dopants such as Nd and Yb in the medium that directly contributes to light emission cannot be changed greatly regardless of whether it is a single crystal or a polycrystal, there is a certain limit to improving the laser output by increasing the concentration. However, in the case of ceramic, since the size of the medium can be remarkably increased as compared with the single crystal, the output is greatly improved.

  Further, in the case of ceramic, a medium having a parallelepiped shape or a rectangular parallelepiped shape can be easily formed. When a medium having such a shape is used to cause oscillation light to travel in a zigzag manner inside the medium, the oscillation optical path can be made longer. As a result, amplification is increased and oscillation can be performed with high output. Further, since the laser beam emitted from the medium having such a shape has a quadrangular cross-sectional shape at the time of emission, it is advantageous for shaping into a linear beam as compared with a round beam. By shaping the emitted laser beam using an optical system, it is possible to easily obtain a linear beam having a short side length of 1 mm or less and a long side length of several mm to several m. Become. In addition, by irradiating the medium with the excitation light uniformly, the linear beam has a uniform energy distribution in the long side direction.

  By irradiating the semiconductor film with this linear beam, the entire surface of the semiconductor film can be annealed more uniformly. When uniform annealing is required up to both ends of the linear beam, it is necessary to devise measures such as shielding the energy attenuation portion using a slit.

  Note that in the case where laser irradiation is performed in the air or an oxygen atmosphere, an oxide film is formed on the surface by laser beam irradiation.

  Next, in addition to the oxide film formed by the laser beam irradiation, the surface is treated with ozone water for 120 seconds to form a barrier layer made of an oxide film having a total thickness of 1 to 5 nm. This barrier layer is formed to remove a catalyst element added for crystallization, for example, nickel (Ni) from the film. Here, the barrier layer is formed using ozone water, but the surface of the semiconductor film having a crystal structure is oxidized by a method of oxidizing the surface of the semiconductor film having a crystal structure by irradiation with ultraviolet light in an oxygen atmosphere or the oxygen plasma treatment. The barrier layer may be formed by depositing an oxide film of about 1 to 10 nm by a method, plasma CVD method, sputtering method or vapor deposition method. Further, the oxide film formed by laser beam irradiation may be removed before forming the barrier layer.

Next, an amorphous silicon film containing an argon element serving as a gettering site is formed with a thickness of 10 to 400 nm, here 100 nm, over the barrier layer by a sputtering method. Here, the amorphous silicon film containing an argon element is formed using a silicon target in an atmosphere containing argon. In the case where an amorphous silicon film containing an argon element is formed using a plasma CVD method, the film formation conditions are as follows: the flow ratio of monosilane to argon (SiH ₄ : Ar) is 1:99, and the film formation pressure is 6.665 Pa. The RF power density is 0.087 W / cm ² and the film formation temperature is 350 ° C.

  Thereafter, the catalyst element is removed (gettering) by performing a heat treatment for 3 minutes in a furnace heated to 650 ° C. As a result, the concentration of the catalytic element in the semiconductor film having a crystal structure is reduced. A lamp annealing apparatus may be used instead of the furnace.

  Next, the amorphous silicon film containing an argon element which is a gettering site is selectively removed using the barrier layer as an etching stopper, and then the barrier layer is selectively removed with dilute hydrofluoric acid. Note that during gettering, nickel tends to move to a region with a high oxygen concentration, and thus it is desirable to remove the barrier layer made of an oxide film after gettering.

  Note that in the case where the semiconductor film is not crystallized using a catalytic element, the above-described barrier layer formation, gettering site formation, heat treatment for gettering, gettering site removal, barrier layer removal, etc. This step is unnecessary.

  Next, after forming a thin oxide film with ozone water on the surface of the obtained semiconductor film having a crystalline structure (for example, a crystalline silicon film), a mask made of resist is formed using a first photomask, and a desired film is formed. Semiconductor films (referred to as “island semiconductor regions” in this specification) 231 and 232 separated into island shapes are formed by etching into a shape (see FIG. 11A). After the island-shaped semiconductor region is formed, the resist mask is removed.

Next, if necessary, a small amount of impurity element (boron or phosphorus) is doped in order to control the threshold voltage of the TFT. Here, an ion doping method in which diborane (B ₂ H ₆ ) is plasma-excited without mass separation is used.

  Next, the oxide film is removed with an etchant containing hydrofluoric acid, and at the same time, the surfaces of the island-shaped semiconductor regions 231 and 232 are washed, and then an insulating film containing silicon as a main component to be the gate insulating film 213 is formed. Here, a silicon oxide film containing nitrogen (composition ratio: Si = 32%, O = 59%, N = 7%, H = 2%) with a thickness of 115 nm is formed by a plasma CVD method.

  Next, after a metal film is formed over the gate insulating film 213, gate electrodes 234 and 235, wirings 214 and 215, and a terminal electrode 250 are formed (see FIG. 11B).

  Further, as the gate electrodes 234 and 235, the wirings 214 and 215, and the terminal electrode 250, titanium (Ti), tungsten (W), tantalum (Ta), molybdenum (Mo), neodymium (Nd), cobalt (Co), zirconium ( Zr), zinc (Zn), ruthenium (Ru), rhodium (Rh), palladium (Pd), osmium (Os), iridium (Ir), platinum (Pt), aluminum (Al), gold (Au), silver ( Ag), an element selected from copper (Cu), or a single layer film made of an alloy material or a compound material containing the element as a main component, or a nitride thereof such as titanium nitride, tungsten nitride, tantalum nitride, A single layer film made of molybdenum nitride can be used.

  Further, a laminated film may be used instead of the single layer film. For example, as the gate electrodes 234 and 235, the wirings 214 and 215, and the terminal electrode 250, a film in which tantalum nitride and tungsten (W) are stacked by 30 nm and 370 nm, respectively, may be used.

  Next, an impurity imparting one conductivity type is introduced into the island-shaped semiconductor regions 231 and 232, so that the source region or drain region 237 of the TFT 105 and the source region or drain region 238 of the TFT 104 are formed. Since n-channel TFTs are formed in this embodiment mode, n-type impurities such as phosphorus (P) and arsenic (As) are introduced into the island-shaped semiconductor regions 231 and 232 (see FIG. 11C).

  Next, after forming a first interlayer insulating film (not shown) including a silicon oxide film by CVD with a thickness of 50 nm, a step of activating the impurity element added to each island-like semiconductor region is performed. This activation process is performed by a rapid thermal annealing method (RTA method) using a lamp light source, a method of irradiating a YAG laser or an excimer laser from the back surface, a heat treatment using a furnace, or a combination thereof. By different methods.

  Next, a second interlayer insulating film 216 including a silicon nitride film containing hydrogen and oxygen is formed with a thickness of 10 nm, for example.

  Next, a third interlayer insulating film 217 made of an insulating material is formed over the second interlayer insulating film 216 (see FIG. 12A). As the third interlayer insulating film 217, an insulating film obtained by a CVD method can be used. In this embodiment, in order to improve adhesion, a silicon oxide film containing nitrogen formed with a thickness of 900 nm is formed as the third interlayer insulating film 217.

  Next, heat treatment (300 to 550 ° C. for 1 to 12 hours, for example, in a nitrogen atmosphere at 410 ° C. for 1 hour) is performed to hydrogenate the island-shaped semiconductor film. This step is performed in order to terminate dangling bonds of the island-shaped semiconductor film with hydrogen contained in the second interlayer insulating film 216. The island-shaped semiconductor film can be hydrogenated regardless of the presence of the gate insulating film 213.

  Further, as the third interlayer insulating film 217, an insulating film using siloxane and a stacked structure thereof can be used. Siloxane has a skeleton structure with a bond of silicon (Si) and oxygen (O). As a substituent, an organic group containing at least hydrogen (for example, an alkyl group or an aromatic hydrocarbon) is used. A fluoro group may be used as a substituent. Alternatively, an organic group containing at least hydrogen and a fluoro group may be used as a substituent.

  In the case where an insulating film using siloxane and a stacked structure thereof are used as the third interlayer insulating film 217, a heat treatment for hydrogenating the island-shaped semiconductor film is performed after the second interlayer insulating film 216 is formed. Next, a third interlayer insulating film 217 can be formed.

  Next, a resist mask is formed, and the first interlayer insulating film, the second interlayer insulating film 216 and the third interlayer insulating film 217 or the gate insulating film 213 are selectively etched to form contact holes. Then, the resist mask is removed.

  Note that the third interlayer insulating film 217 may be formed as necessary. When the third interlayer insulating film 217 is not formed, the first interlayer insulating film and the second interlayer insulating film 216 are formed after the second interlayer insulating film 216 is formed. The second interlayer insulating film 216 and the gate insulating film 213 are selectively etched to form contact holes.

  Next, after a metal laminated film is formed by sputtering, a mask made of a resist is formed, and the metal film is selectively etched to form a wiring 284, a connection electrode 285, a terminal electrode 281 and a source electrode or drain electrode of the TFT 104. 282, a source electrode or a drain electrode 283 of the TFT 105 is formed (see FIG. 12B).

  In FIG. 12B, the wiring 284, the connection electrode 285, the terminal electrode 281, the source or drain electrode 282 of the TFT 104, and the source or drain electrode 283 of the TFT 105 are formed from a single-layer conductive film.

  As such a single layer, a titanium film (Ti film) is preferable from the viewpoints of heat resistance and electrical conductivity. Further, in place of the titanium film, tungsten (W), tantalum (Ta), molybdenum (Mo), neodymium (Nd), cobalt (Co), zirconium (Zr), zinc (Zn), ruthenium (Ru), rhodium (Rh) ), Palladium (Pd), osmium (Os), iridium (Ir), platinum (Pt), or a single layer film made of an alloy material or a compound material containing the element as a main component, or these A single layer film made of a nitride such as titanium nitride, tungsten nitride, tantalum nitride, or molybdenum nitride can be used. By forming the wiring 284, the connection electrode 285, the terminal electrode 281, the source electrode or drain electrode 282 of the TFT 104, and the source electrode or drain electrode 283 of the TFT 105 as a single layer film, the number of depositions can be reduced in the manufacturing process. It becomes possible.

  FIG. 12C illustrates the case where a protective electrode is provided for the wiring 219, the connection electrode 220, the terminal electrode 251, the source or drain electrode 241 of the TFT 104, and the source or drain electrode 242 of the TFT 105.

  First, the lower conductive films of the wiring 219, the connection electrode 220, the terminal electrode 251, the source electrode or drain electrode 241 of the TFT 104, and the source electrode or drain electrode 242 of the TFT 105 are a refractory metal film and a low resistance metal film (aluminum alloy). Or a pure aluminum structure). Here, the lower layer conductive film of the wiring 219, the connection electrode 220, the terminal electrode 251, the source or drain electrodes 241 and 242 is formed by sequentially stacking a titanium film (Ti film), an aluminum film (Al film), and a Ti film. A layer structure is adopted.

  Further, a protective electrode 218, a protective electrode 245, a protective electrode 248, and a protective electrode are provided so as to cover the wiring 219, the connection electrode 220, the terminal electrode 251, the source or drain electrode 241 of the TFT 104, and the source or drain electrode 242 of the TFT 105, respectively. 246 and a protective electrode 247 are formed.

  When the photoelectric conversion layer 103 formed later is etched, the wiring 219 is protected by the protective electrode 218 that covers the wiring 219. The material of the protective electrode 218 is preferably a conductive material whose etching rate is lower than that of the photoelectric conversion layer 103 with respect to a gas (or etchant) for etching the photoelectric conversion layer 103. In addition, the material of the protective electrode 218 is preferably a conductive material that does not react with the photoelectric conversion layer 103 to form an alloy. Note that the other protective electrode 245, the protective electrode 248, the protective electrode 246, and the protective electrode 247 are also formed using the same material and manufacturing process as the protective electrode 218.

  For example, after forming a conductive metal film (such as titanium (Ti) or molybdenum (Mo)) that hardly reacts with a photoelectric conversion layer (typically amorphous silicon) that is formed later, A protective electrode 218 that covers the wiring 219 is formed by selectively etching a conductive metal film. Here, a 200-nm-thick Ti film obtained by sputtering is used. Similarly, the connection electrode 220, the terminal electrode 251, the source electrode or drain electrode 241 of the TFT 104, and the source electrode or drain electrode 242 of the TFT 105 are also covered with a conductive metal film, and protective electrodes 245, 248, 246, and 247 are respectively formed. It is formed. Accordingly, the conductive metal film also covers the side surface of the electrode where the second Al film is exposed, and the conductive metal film can prevent diffusion of aluminum atoms into the photoelectric conversion layer.

  Next, the photoelectric conversion layer 103 including the p-type semiconductor layer 103p, the i-type semiconductor layer 103i, and the n-type semiconductor layer 103n is formed over the third interlayer insulating film 217.

  The p-type semiconductor layer 103p may be formed by forming an amorphous silicon film containing an impurity element belonging to Group 13 such as boron (B) by a plasma CVD method.

  In FIG. 13A, the wiring 284 is in contact with the lowermost layer of the photoelectric conversion layer 103, which is the p-type semiconductor layer 103p in this embodiment.

  In the case of forming a protective electrode, the wiring 219 and the protective electrode 218 are in contact with the lowermost layer of the photoelectric conversion layer 103, in this embodiment mode, the p-type semiconductor layer 103p.

  After the p-type semiconductor layer 103p is formed, an i-type semiconductor layer 103i and an n-type semiconductor layer 103n are further formed in order. Thus, the photoelectric conversion layer 103 including the p-type semiconductor layer 103p, the i-type semiconductor layer 103i, and the n-type semiconductor layer 103n is formed.

  As the i-type semiconductor layer 103i, for example, an amorphous silicon film may be formed by a plasma CVD method. As the n-type semiconductor layer 103n, an amorphous silicon film containing an impurity element of 15 group, for example, phosphorus (P) may be formed, or an impurity element of 15 group may be introduced after the amorphous silicon film is formed. Good.

  Further, as the p-type semiconductor layer 103p, the i-type semiconductor layer 103i, and the n-type semiconductor layer 103n, not only an amorphous semiconductor film but also a semi-amorphous semiconductor film may be used.

  Next, a sealing layer 224 made of an insulating material (for example, an inorganic insulating film containing silicon) is formed over the entire surface with a thickness (1 μm to 30 μm) to obtain the state shown in FIG. Here, a silicon oxide film containing nitrogen having a thickness of 1 μm is formed as the insulating material film by a CVD method. Adhesion is improved by using an insulating film formed by CVD.

  Next, after the sealing layer 224 is etched to provide openings, terminal electrodes 221 and 222 are formed by sputtering. The terminal electrodes 221 and 222 are laminated films of a titanium film (Ti film) (100 nm), a nickel film (Ni) film (300 nm), and a gold film (Au film) (50 nm). The fixing strength of the terminal electrode 221 and the terminal electrode 222 thus obtained exceeds 5N, and has a sufficient fixing strength as a terminal electrode.

  Through the above steps, the terminal electrode 221 and the terminal electrode 222 that can be connected by soldering are formed, and the structure shown in FIG. 13B is obtained.

  Next, a plurality of optical sensor chips are cut out individually. A large amount of optical sensor chips (2 mm × 1.5 mm) can be manufactured from one large-area substrate (for example, 600 cm × 720 cm).

  A cross-sectional view of one cut out optical sensor chip (2 mm × 1.5 mm) is shown in FIG. 14A, a bottom view thereof is shown in FIG. 14B, and a top view thereof is shown in FIG. 14A to 14C, the same reference numerals are used for portions that are the same as those in FIG. In FIG. 14A, the total film thickness including the substrate 210, the element formation region 291, the terminal electrode 221 and the terminal electrode 222 is 0.8 ± 0.05 mm.

  In order to reduce the total film thickness of the optical sensor chip, the substrate 210 may be thinned by CMP processing or the like, and then individually cut with a dicer to cut out a plurality of optical sensor chips.

In FIG. 14B, one electrode size of the terminal electrodes 221 and 222 is 0.6 mm × 1.1 mm, and the electrode interval is 0.4 mm. In FIG. 14C, the area of the light receiving portion 292 is 1.57 mm ² . In addition, the amplifier circuit portion 293 is provided with about 100 TFTs.

  Finally, the obtained optical sensor chip is mounted on the mounting surface of the substrate 260. Note that solder 264 and 263 are used to connect the terminal electrode 221 and the electrode 261 and the terminal electrode 222 and the electrode 262, respectively, and a solder paste is previously formed on the electrodes 261 and 262 of the substrate 260 by a screen printing method or the like. Then, after the solder and the terminal electrode are in contact with each other, the solder reflow process is performed for mounting. The solder reflow process is performed, for example, in an inert gas atmosphere at a temperature of about 255 ° C. to 265 ° C. for about 10 seconds. In addition to solder, bumps formed of metal (gold, silver, etc.) or bumps formed of conductive resin can be used. Moreover, you may mount using lead-free solder in consideration of an environmental problem (refer FIG. 10).

  As described above, a photoelectric conversion device including the photoelectric conversion layer 103 and a semiconductor device including the current mirror circuit 111 can be obtained.

  The light 200 enters from the substrate 210 as indicated by an arrow and reaches the photoelectric conversion layer 103.

  According to this embodiment mode, a semiconductor device including a photoelectric conversion device in which reduction in photosensitivity is suppressed can be obtained.

  Note that this embodiment may be combined with other embodiments if necessary.

[Embodiment 2]
In this embodiment, an example in which an amplifier circuit is formed using a p-channel TFT will be described with reference to FIGS. Note that the same components as those in Embodiment Mode 1 are denoted by the same reference numerals, and each may be created based on the production steps described in Embodiment Mode 1.

  In the case where the amplifier circuit, for example, the current mirror circuit 203 is formed using the p-channel TFTs 201 and 202, an impurity imparting one conductivity type to the island-shaped semiconductor region of Embodiment 1 is used as a p-type impurity such as boron ( What is necessary is just to replace with B).

  FIG. 9 shows an equivalent circuit diagram of the photosensor of this embodiment and FIG. 15 shows a cross-sectional view when the current mirror circuit 203 is formed by p-channel TFTs 201 and 202.

  9 and 15, the terminal electrode 221 is electrically connected to the n-type semiconductor layer 103 n of the photoelectric conversion layer 103 and the p-channel TFT 201, and the terminal electrode 222 is electrically connected to the p-channel TFT 202. The p-channel TFT 201 is electrically connected to the anode side electrode of the photoelectric conversion layer 103. The photoelectric conversion layer 103 is obtained by sequentially stacking an n-type semiconductor layer 103n, an i-type semiconductor layer 103i, and a p-type semiconductor layer 103p on a second electrode (anode side electrode) electrically connected to the p-channel TFT 201. The first electrode (cathode side electrode) may be formed.

  Alternatively, a photoelectric conversion layer in which the stacking order is reversed may be used. After sequentially stacking a p-type semiconductor layer, an i-type semiconductor layer, and an n-type semiconductor layer on the first electrode (cathode side electrode), a p-channel type is formed. A second electrode (electrode on the anode side) that is electrically connected to the TFT 201 may be formed.

  The light 200 enters from the substrate 210 as indicated by an arrow and reaches the photoelectric conversion layer 103.

  As shown in FIG. 15, p-type impurities such as boron (B) are introduced into the island-shaped semiconductor regions of the p-channel TFTs 201 and 202, and the p-channel TFT 201 has a source region or a drain region 271, A source region or drain region 272 is formed in the p-channel TFT 202.

  The wiring 284, the connection electrode 285, the terminal electrode 281, the source electrode or drain electrode 283 of the TFT 201, and the source electrode or drain electrode 282 of the TFT 202 are each formed using a single-layer conductive film according to the description in Embodiment 1. Wiring and electrodes are formed.

  12C, instead of the wiring 284, the connection electrode 285, the terminal electrode 281, and the source or drain electrode 283 of the TFT 201 and the source or drain electrode 282 of the TFT 202, the wiring 219 and its protective electrode 218, a connection electrode 220 and its protective electrode 245, a terminal electrode 251 and its protective electrode 248, a source electrode or drain electrode 242 and its protective electrode 247 of the TFT 201, and a source electrode or drain electrode 241 and its protective electrode 246 of the TFT 202 are formed. May be. Each manufacturing method is based on the first embodiment.

  According to this embodiment mode, a semiconductor device including a photoelectric conversion device in which reduction in photosensitivity is suppressed can be obtained.

  Note that this embodiment may be combined with other embodiments if necessary.

[Embodiment 3]
In this embodiment, an example of an amplifier circuit, an optical sensor, and a manufacturing method thereof, which are formed using bottom-gate TFTs, is described with reference to FIGS. 16 (A) to 16 (E) and FIGS. 17 (A) to 17 (D). This will be described with reference to FIG. In addition, the same thing as Embodiment 1- Embodiment 2 is shown with the same code | symbol.

  First, the base insulating film 212 and the metal film 311 are formed over the substrate 210 (see FIG. 16A). In this embodiment, for example, a film in which tantalum nitride and tungsten (W) are stacked by 30 nm and 370 nm is used as the metal film 311.

  In addition to the above, as the metal film 311, titanium (Ti), tungsten (W), tantalum (Ta), molybdenum (Mo), neodymium (Nd), cobalt (Co), zirconium (Zr), zinc (Zn) , Ruthenium (Ru), rhodium (Rh), palladium (Pd), osmium (Os), iridium (Ir), platinum (Pt), aluminum (Al), gold (Au), silver (Ag), copper (Cu) Or a single layer film made of an alloy material or a compound material containing the element as a main component, or a single layer film made of these nitrides, for example, titanium nitride, tungsten nitride, tantalum nitride, or molybdenum nitride Can be used.

  Note that the metal film 311 may be formed directly on the substrate 210 without forming the base insulating film 212 on the substrate 210.

  Next, gate electrodes 312 and 313, wirings 214 and 215, and a terminal electrode 250 are formed using the metal film 311 (see FIG. 16B).

  Next, a gate insulating film 314 that covers the gate electrodes 312 and 313, the wirings 214 and 215, and the terminal electrode 250 is formed. In this embodiment mode, an insulating film containing silicon as a main component, for example, a silicon oxide film containing nitrogen with a thickness of 115 nm by a plasma CVD method (composition ratio Si = 32%, O = 59%, N = 7%, H = 2%), the gate insulating film 314 is formed.

  Next, island-shaped semiconductor regions 315 and 316 are formed over the gate insulating film 314. The island-shaped semiconductor regions 315 and 316 may be formed using a material and a manufacturing process similar to those of the island-shaped semiconductor regions 231 and 232 described in Embodiment 1 (see FIG. 16C).

  After the island-shaped semiconductor regions 315 and 316 are formed, a mask 318 is formed so as to cover regions other than the source region or drain region 321 of the TFT 301 and the source region or drain region 322 of the TFT 302, and an impurity imparting one conductivity type Is introduced (see FIG. 16D). As an impurity of one conductivity type, phosphorus (P) or arsenic (As) is used as an n-type impurity when forming an n-channel TFT, and as a p-type impurity when forming a p-channel TFT. Boron (B) may be used. In this embodiment mode, phosphorus (P) which is an n-type impurity is introduced into the island-shaped semiconductor regions 315 and 316, the channel region between the source region or the drain region 321 of the TFT 301 and the source region and the drain region, and the TFT 302 A channel formation region is formed between the source or drain region 322 and the source and drain regions.

  Next, the mask 318 is removed, and a first interlayer insulating film, a second interlayer insulating film 216, and a third interlayer insulating film 217 (not shown) are formed (see FIG. 16E). The materials and manufacturing steps of the first interlayer insulating film, the second interlayer insulating film 216, and the third interlayer insulating film 217 may be based on the description in Embodiment Mode 1.

  Next, contact holes are formed in the first interlayer insulating film, the second interlayer insulating film 216, and the third interlayer insulating film 217, a single-layer metal film is formed, and the metal film is selectively etched. Thus, the wiring 284, the connection electrode 285, the terminal electrode 281, the source or drain electrode 341 of the TFT 301, and the source or drain electrode 342 of the TFT 302 are formed (see FIG. 17A).

  In addition, the wiring 284, the connection electrode 285, the terminal electrode 281, the source or drain electrode 341 of the TFT 301, and the source or drain electrode 342 of the TFT 302 may be formed using a stacked film instead of a single-layer conductive film. . An example in which these are formed using a stacked film is shown in FIG.

  In FIG. 17B, instead of the wiring 284, the connection electrode 285, the terminal electrode 281 and the source or drain electrode 341 of the TFT 301 and the source or drain electrode 342 of the TFT 302, the wiring 219 and its protective electrode 218 are connected. An electrode 220 and its protective electrode 245, a terminal electrode 251 and its protective electrode 248, a TFT 301 source or drain electrode 331 and its protective electrode 336, and a TFT 302 source or drain electrode 332 and its protective electrode 337 are formed.

  Through the above steps, bottom-gate TFTs 301 and 302 can be manufactured. A current mirror circuit 303 can be formed by the bottom gate TFTs 301 and 302.

  Next, the photoelectric conversion layer 103 including the p-type semiconductor layer 103p, the i-type semiconductor layer 103i, and the n-type semiconductor layer 103n is formed over the third interlayer insulating film 217 (see FIG. 17C). Embodiment 1 to Embodiment 2 may be referred to for the material, the manufacturing process, and the like of the photoelectric conversion layer 103.

  Next, a sealing layer 224 and terminal electrodes 221 and 222 are formed (see FIG. 17D). The terminal electrode 221 is connected to the n-type semiconductor layer 100n, and the terminal electrode 222 is formed in the same process as the terminal electrode 221.

  Further, a substrate 260 having electrodes 261 and 262 is mounted with solder 263 and 264. Note that the electrode 261 on the substrate 260 is mounted on the terminal electrode 221 with solder 264. The electrode 262 of the substrate 260 is mounted on the terminal electrode 222 with solder 263 (see FIG. 18).

  The light 200 enters from the substrate 210 as indicated by an arrow and reaches the photoelectric conversion layer 103.

  Note that even when the semiconductor device having the structure illustrated in FIG. 17B is used, a semiconductor device similar to the semiconductor device illustrated in FIG. 18 can be manufactured according to the manufacturing steps described above.

  According to this embodiment mode, a semiconductor device including a photoelectric conversion device in which reduction in photosensitivity is suppressed can be obtained.

  Note that this embodiment may be combined with other embodiments if necessary.

[Embodiment 4]
In this embodiment mode, a battery used as a power source is illustrated in FIGS. 27, 28A to 28B, 29A to 29E, FIG. 30, FIG. 31, FIG. 33 will be described below.

  In this specification, a device including a battery, an antenna, a circuit for charging the battery with an electromotive force generated by electromagnetic waves received by the antenna, and a medium for charging the electromotive force is also referred to as an RF battery or a wireless battery.

  In this specification, a battery is called a secondary battery or a storage battery, and stores electrical energy obtained from an external power source in the form of chemical energy, and takes it out again as necessary. Refers to the device. The capacitor is a device in which two insulated conductors are provided, and one of the two conductors has a positive charge and the other has a negative charge, whereby charges are stored by an attractive force between the electricity.

  Note that in this specification, the battery is a battery that can recover the continuous use time by charging. As the battery, although it varies depending on the application, it is preferable to use a battery formed in a thin sheet shape or a cylindrical shape having a small diameter, for example, a lithium battery, preferably a lithium polymer battery using a gel electrolyte, or a lithium ion battery. By using a battery or the like, the size can be reduced. Of course, any rechargeable battery may be used, such as a nickel metal hydride battery, a nickel cadmium battery, an organic radical battery, a lead storage battery, an air secondary battery, a nickel zinc battery, or a silver zinc battery. In addition, a large-capacity capacitor may be used.

  As a large-capacity capacitor that can be used as the battery of this embodiment, it is desirable that the opposing area of the electrodes be large. It is preferable to use an electrolytic double layer capacitor using an electrode material having a large specific surface area such as activated carbon, fullerene, or carbon nanotube. Capacitors have a simpler structure than batteries and can be easily made thin and laminated. The electric double layer capacitor is suitable because it has a power storage function, is hardly deteriorated even when the number of charge / discharge cycles is increased, and is excellent in quick charge characteristics.

  The battery of this embodiment can be used as, for example, the power supply 101 in FIG.

  In FIG. 27, the RF battery 401 includes a battery 407, a charging circuit 413, a charging control circuit 414, an internal antenna circuit 411, and a rectifying circuit 412. An external antenna circuit 415 is provided outside the RF battery 401. The internal antenna circuit 411 receives a radio signal generated by the external antenna circuit 415. A signal received by the internal antenna circuit 411 is input to the rectifier circuit 412 and converted into direct current. The charging circuit 413 generates a current based on the electric power of the rectifier circuit 412 and charges the battery 407. The charging control circuit 414 monitors the battery 407 so as not to be overcharged, and controls the charging circuit 413 to suppress the charging amount when the charging amount increases. Note that the charging circuit 413 can be constituted by, for example, a voltage control circuit (also referred to as a regulator) and a switch circuit. Note that the charge control circuit may be omitted by using a diode for the switch circuit. The voltage control circuit may be a voltage and current control circuit or a constant current source circuit.

  Note that as the internal antenna circuit 411 and the external antenna circuit 415, for example, an antenna circuit 503 including an antenna 501 and a resonance capacitor 502 as shown in FIG. The rectifier circuit 412 may be a circuit that converts an AC signal induced by electromagnetic waves received by the internal antenna circuit 411 and the external antenna circuit 415 into a DC signal. For example, as shown in FIG. 28B, a diode 504, a diode 505, and a smoothing capacitor 506 can be used.

  Note that as a wireless signal received by the internal antenna circuit 411 in this embodiment, for example, a signal in a frequency band such as 125 kHz, 13.56 MHz, 915 MHz, or 2.45 GHz can be used. Of course, the frequency of the signal received by the internal antenna circuit is not limited to this. For example, the sub-millimeter wave is 300 GHz to 3 THz, the millimeter wave is 30 GHz to 300 GHz, the microwave is 3 GHz to 30 GHz, and the ultra-high frequency is 300 MHz. Any frequency of ~ 3 GHz, 30 MHz to 300 MHz which is an ultrashort wave, 3 MHz to 30 MHz which is a short wave, 300 kHz to 3 MHz which is a medium wave, 30 kHz to 300 kHz which is a long wave, and 3 kHz to 30 kHz which is an ultralong wave can be used.

  A signal transmitted and received between the internal antenna circuit 411 and the external antenna circuit 415 is a signal obtained by modulating a carrier wave. The modulation method of the carrier wave may be analog modulation or digital modulation, and may be any of amplitude modulation, phase modulation, frequency modulation, and spread spectrum. Desirably, amplitude modulation or frequency modulation is used. Also, as radio signals, radio wave bands of mobile phone relay stations (800-900 MHz band, 1.5 GHz, 1.9-2.1 GHz band, etc.), radio waves oscillated from mobile phones, radio clock radio waves (40 kHz, etc.) It is also possible to use noise (60 Hz, etc.) of household AC power supply, signals received randomly from other readers / writers, and the like. Further, by providing a plurality of antenna circuits using antennas having different lengths and shapes as the internal antenna circuit 411, various wireless signals can be used for charging the battery 407.

  In addition, the antennas provided in the internal antenna circuit 411 and the external antenna circuit 415 are provided with a length and a shape that can easily receive these radio signals. In the case of receiving a plurality of these radio waves, it is preferable to provide a plurality of antenna circuits including antennas having different lengths and shapes.

  Further, the shape of the antenna provided in the internal antenna circuit 411 or the external antenna circuit 415 is not particularly limited. That is, as a signal transmission method applied to the internal antenna circuit 411 or the external antenna circuit 415, an electromagnetic coupling method, an electromagnetic induction method, a microwave method, or the like can be used. The transmission method may be selected by the practitioner in consideration of the intended use, and an antenna having an optimal length and shape may be provided in accordance with the transmission method.

  For example, when an electromagnetic coupling method or an electromagnetic induction method (for example, 13.56 MHz band) is applied as a transmission method, a conductive film functioning as an antenna is formed in a ring shape (for example, an electromagnetic induction due to a change in electric field density). , Loop antenna) and spiral (eg, spiral antenna, helical antenna).

  In addition, when a microwave method (for example, UHF band (860 to 960 MHz band), 2.45 GHz band, or the like) is applied as a transmission method, a conductive function that functions as an antenna in consideration of the wavelength of an electromagnetic wave used for signal transmission. The length and shape of the film may be set as appropriate, and the conductive film functioning as an antenna can be formed, for example, in a linear shape (for example, a dipole antenna) or a flat shape (for example, a patch antenna). Further, the shape of the conductive film functioning as an antenna is not limited to a linear shape, and may be provided in a curved shape, a meandering shape, or a combination thereof in consideration of the wavelength of electromagnetic waves.

  Here, examples of the shape of the antenna provided in the internal antenna circuit 411 or the external antenna circuit 415 are illustrated in FIGS. For example, as shown in FIG. 29A, a structure in which one antenna 523 is provided around a circuit element 522 provided with various circuits and the like may be employed. Note that the circuit element 522 indicates an element obtained by removing the internal antenna circuit 411 or the external antenna circuit 415 from each element of a semiconductor device capable of wireless communication.

  In addition, as illustrated in FIG. 29B, a structure in which a circuit element 522 provided with various circuits and the like is surrounded by a thin antenna 523 may be employed. Alternatively, as illustrated in FIG. 29C, a circuit element 522 provided with various circuits or the like may be provided, and the shape of an antenna 523 for receiving high-frequency electromagnetic waves may be employed. In addition, as shown in FIG. 29D, a circuit element 522 provided with various circuits and the like may be provided, and the antenna 523 may have a shape of 180 degrees omnidirectional (same reception is possible from any direction). In addition, as illustrated in FIG. 29E, an antenna 523 that is elongated in a rod shape may be used for the circuit element 522 provided with various circuits and the like. The internal antenna circuit 411 or the external antenna circuit 415 can be used by combining antennas of these shapes.

  In addition, in FIGS. 29A to 29E, the connection between the circuit element 522 provided with various circuits and the antenna 523 is not particularly limited. For example, a method may be employed in which the circuit element 522 provided with a circuit or the like is connected to the antenna 523 using wire bonding connection or bump connection, or a part of the circuit element 522 is attached to the antenna 523 as an electrode. . In this method, the circuit element 522 can be attached to the antenna 523 by using an ACF (anisotropic conductive film). Further, the length required for the antenna 523 differs depending on the frequency used for reception. For example, when the frequency is 2.45 GHz, a half wavelength (about 60 mm) may be used when a half-wave dipole antenna is provided, and a quarter wavelength (about 30 mm) may be used when a monopole antenna is provided.

  Note that the internal antenna circuit 411 may have a multiband antenna structure capable of receiving electromagnetic waves in a plurality of frequency bands. For example, as shown in FIG. 30, the internal antenna circuit may be formed by a plurality of antenna circuits. In the structure shown in FIG. 30, a first antenna circuit 1705a, a second antenna circuit 1705b, a third antenna circuit 1705c, a circuit element 1702 having a control circuit, and a battery 1703 are provided over a substrate 1701. Yes. Note that the first antenna circuit 1705a, the second antenna circuit 1705b, the third antenna circuit 1705c, and the control circuit provided in the circuit element 1702 are electrically connected. Reference numeral 1706 denotes a transmitter for transmitting electromagnetic waves for charging the battery, and is provided in a display unit or the like.

  The electromagnetic waves received by the first antenna circuit 1705a, the second antenna circuit 1705b, and the third antenna circuit 1705c are input to the battery 1703 through the rectifier circuit in the control circuit formed in the circuit element 1702, and the battery 1703 is supplied. Is charged.

  Here, an example is shown in which an electromagnetic wave transmitted from the transmitter 1706 is received by the first antenna circuit 1705a and an external wireless signal 1707 is received by the second antenna circuit 1705b and the third antenna circuit 1705c. Yes. Further, the connection relationship between the first antenna circuit 1705a, the second antenna circuit 1705b, and the third antenna circuit 1705c is not particularly limited. For example, all antennas may be electrically connected, May be provided independently without being electrically connected.

  Note that the lengths and shapes of the antennas of the first antenna circuit 1705a, the second antenna circuit 1705b, and the third antenna circuit 1705c used for charging the battery 1703 are not limited to the structure illustrated in FIG. Here, an example is shown in which linear antennas (dipole antennas) having different lengths are provided as the antennas of the second antenna circuit 1705b and the third antenna circuit 1705c. For example, a dipole antenna and a coiled antenna are provided. May be used in combination, or a dipole antenna and a patch antenna may be used in combination. In this manner, by providing a plurality of antennas having different lengths and shapes as the antenna used for charging the battery 1703, various wireless signals can be received, so that charging efficiency can be improved. In particular, by providing a combination of antennas having different shapes such as a patch antenna and a dipole antenna (for example, a folded dipole antenna is provided around the patch antenna), a limited space can be used effectively. In this embodiment mode, an example in which three antenna circuits 1705a, 1705b, and 1705c are provided is described, but the present invention is not limited to this, and a configuration in which one antenna circuit or three or more antenna circuits is provided may be employed.

  For example, as a signal transmitted and received between the first antenna circuit 1705a and the transmitter 1706, a signal in a frequency band such as 125 kHz, 13.56 MHz, 915 MHz, and 2.45 GHz can be used. Is set. Of course, the frequency of the signal transmitted and received between the first antenna circuit 1705a and the transmitter 1706 is not limited to this. For example, the submillimeter wave is 300 GHz to 3 THz, the millimeter wave is 30 GHz to 300 GHz, and the microwave is 3 GHz. -30 GHz, 300 MHz to 3 GHz which is an ultra high frequency wave, 30 MHz to 300 MHz which is an ultra high frequency wave, 3 MHz to 30 MHz which is a short wave, 300 kHz to 3 MHz which is a medium wave, 30 kHz to 300 kHz which is a long wave, and 3 kHz to 30 kHz which is an ultra long wave Can also be used. A signal transmitted and received between the first antenna circuit 1705a and the transmitter 1706 is a signal obtained by modulating a carrier wave. The modulation method of the carrier wave may be analog modulation or digital modulation, and may be any of amplitude modulation, phase modulation, frequency modulation, and spread spectrum. Desirably, amplitude modulation or frequency modulation is used.

  In addition, as an external wireless signal 1707 received by the antennas of the second antenna circuit 1705b and the third antenna circuit 1705c, for example, the radio wave band (800 to 900 MHz band, 1.5 GHz, 1.9 of a mobile phone relay station) ~ 2.1GHz band), radio waves oscillated from mobile phones, radio clock radio waves (40 kHz, etc.), household AC power supply noise (60 Hz, etc.), other readers / writers, etc. Radio waves can be used. By receiving an external wireless signal and charging the battery wirelessly, a battery charger or the like for charging the battery is not required separately, so that the battery can be manufactured at a lower cost. In addition, as illustrated in FIG. 30, by providing a plurality of antenna circuits using antennas having different lengths and shapes, various wireless signals can be used for charging the battery 1703. The antennas provided in the second antenna circuit 1705b and the third antenna circuit 1705c may have a shape and a length that facilitate reception of these radio signals. In FIG. 30, the first antenna circuit 1705a is configured to receive electromagnetic waves from the transmitter 1706. However, the present invention is not limited to this, and all the antenna circuits receive external wireless signals and charge the battery. It is good.

  FIG. 30 shows an example in which a plurality of antenna circuits 1705a, 1705b, 1705c, a circuit element 1702, and a battery 1703 are provided on the same substrate 1701, but the structure is not limited to that shown in FIG. May be provided on separate substrates.

  Next, a configuration example of a thin film battery as the battery 407 illustrated in FIG. 27 will be described. In this embodiment, a configuration example of a battery in the case of using a lithium ion battery is shown in FIG.

FIG. 31 is a schematic cross-sectional view of a thin film battery. First, a current collector thin film 7102 to be an electrode is formed over the substrate 7101. The current collector thin film 7102 is required to have good adhesion to the negative electrode active material layer 7103 and low resistance, and aluminum, copper, nickel, vanadium, or the like can be used. Next, a negative electrode active material layer 7103 is formed over the current collector thin film 7102. In general, vanadium oxide (V ₂ O ₅ ) or the like is used. Next, a solid electrolyte layer 7104 is formed over the negative electrode active material layer 7103. In general, lithium phosphate (Li ₃ PO ₄ ) or the like is used. Next, a positive electrode active material layer 7105 is formed over the solid electrolyte layer 7104. Generally, lithium manganate (LiMn ₂ O ₄ ) or the like is used. Lithium cobaltate (LiCoO2) or lithium nickel oxide (LiNiO ₂₎ may be used. Next, a current collector thin film 7106 to be an electrode is formed over the positive electrode active material layer 7105. The current collector thin film 7106 is required to have good adhesion to the positive electrode active material layer 7105 and low resistance, and aluminum, copper, nickel, vanadium, or the like can be used. Note that a lithium ion battery has no memory effect and can take a larger amount of current than a nickel cadmium battery or a lead battery.

  The thin film layers of the current collector thin film 7102, the negative electrode active material layer 7103, the solid electrolyte layer 7104, the positive electrode active material layer 7105, and the current collector thin film 7106 may be formed using a sputtering technique or a vapor deposition technique. May be used. The thickness of each of the current collector thin film 7102, the negative electrode active material layer 7103, the solid electrolyte layer 7104, the positive electrode active material layer 7105, and the current collector thin film 7106 is preferably 0.1 μm to 3 μm.

  Next, the operation during charging and discharging will be described below. At the time of charging, lithium is released from the positive electrode active material layer 7105 as ions. The lithium ions are absorbed by the negative electrode active material layer 7103 through the solid electrolyte layer 7104. At this time, electrons are emitted from the positive electrode active material layer 7105 to the outside.

  Further, during discharge, lithium is released from the negative electrode active material layer 7103 as ions. The lithium ions are absorbed by the positive electrode active material layer 7105 through the solid electrolyte layer 7104. At this time, electrons are emitted from the negative electrode active material layer 7103 to the outside. In this way, the thin film secondary battery operates.

  Note that by forming the current collector thin film 7102, the negative electrode active material layer 7103, the solid electrolyte layer 7104, the positive electrode active material layer 7105, and the current collector thin film 7106 again, charging and discharging with higher power is possible. This is preferable.

  Since the battery of this embodiment is a thin film with a thickness of about 10 μm or less and is a chargeable / dischargeable battery, a small and lightweight semiconductor device can be manufactured by using the battery of this embodiment. .

  When a rechargeable battery is used as a battery, it is generally necessary to control charging and discharging. In other words, it is necessary to perform charging while monitoring the charging status so as not to overcharge when charging. In this embodiment, a circuit for performing charge control will be described. FIG. 32 is a block diagram of the charging circuit 413, the charging control circuit 414, and the battery 407 shown in FIG.

  In the example shown in FIG. 32, the charging circuit 413 includes a constant current source circuit 425 and a switch circuit 426, and is electrically connected to the charging control circuit 414 and the battery 407. Note that the charging circuit illustrated in FIG. 32 is an example, and the present invention is not limited to such a configuration, and may have other configurations. In the present embodiment, the battery 407 is charged with a constant current. However, the battery 407 may be switched to a constant voltage charge in the middle instead of charging only with a constant current. Another method that does not use a constant current may be used. Further, a transistor constituting the following circuit may be a thin film transistor, a transistor on a single crystal substrate, or an organic transistor.

  FIG. 33 shows the circuit of FIG. 32 in more detail. The operation will be described below. The constant current source circuit 425, the switch circuit 426, and the charge control circuit 414 use the high potential power line 976 and the low potential power line 977 as power lines. In FIG. 33, the low-potential power supply line 977 is used as the GND line. However, the potential is not limited to the GND line and may be another potential.

  The constant current source circuit 425 includes transistors 952 to 961 and resistors 951 and 962. Current flows from the high potential power supply line 976 to the transistors 952 and 953 through the resistor 951, so that the transistors 952 and 953 are turned on.

  The transistors 954, 955, 956, 957, and 958 constitute a feedback type differential amplifier, and the gate potential of the transistor 952 is substantially the same as the gate potential of the transistor 956. The drain current of the transistor 961 is a value obtained by dividing the difference potential between the gate potential of the transistor 957 and the low potential power supply line 977 by the resistance value of the resistor 962. The current is input to a current mirror circuit including transistors 959 and 960, and an output current of the current mirror circuit is supplied to the switch circuit 426. The constant current source circuit 425 is not limited to this configuration, and other configurations may be used.

  The switch circuit 426 includes a transmission gate 965 and inverters 963 and 964, and controls whether or not the current of the constant current source circuit 425 is supplied to the battery 407 according to an input signal of the inverter 964. The switch circuit is not limited to this configuration, and other configurations may be used.

  The charge control circuit 414 includes transistors 966 to 974 and a resistor 975. Current flows from the high potential power supply line 976 to the transistors 973 and 974 through the resistor 975, so that the transistors 973 and 974 are turned on. The transistors 968, 969, 970, 971, and 972 constitute a differential comparator. When the gate potential of the transistor 970 is lower than the gate potential of the transistor 971, the drain potential of the transistor 968 is substantially equal to the potential of the high potential power supply line 976, and when the gate potential of the transistor 970 is higher than the gate potential of the transistor 971, The drain potential of 968 is substantially equal to the source potential of the transistor 970.

  When the drain potential of the transistor 968 is substantially equal to the high potential power supply line 976, the charge control circuit 414 outputs low through a buffer including the transistors 967 and 966. When the drain potential of the transistor 968 is substantially equal to the source potential of the transistor 970, the charge control circuit 414 outputs high through a buffer including the transistors 967 and 966.

  When the output of the charge control circuit 414 is low, current is supplied to the battery 407 via the switch circuit 426. When the output of the charge control circuit 414 is high, the switch circuit 426 is turned off (OFF) and no current is supplied to the battery 407. Since the gate of the transistor 970 is electrically connected to the battery 407, charging is stopped when the battery 407 is charged and its potential exceeds the threshold value of the comparator of the charge control circuit 414. In this embodiment mode, the threshold value of the comparator is set by the gate potential of the transistor 973. However, the threshold value is not limited to this value and may be another potential. Generally, the set potential is appropriately determined depending on the application and battery performance. Note that the configuration of the battery charging circuit is not limited to this configuration.

[Embodiment 5]
In this embodiment, examples in which the photoelectric conversion device obtained according to the present invention is incorporated into various electronic devices will be described. Examples of electronic devices to which the present invention is applied include computers, displays, mobile phones, and televisions. Specific examples of these electronic devices are shown in FIGS. 19, 20A to 20B, 21A to 21B, 22 and 23. FIG.

  FIG. 19 shows a cellular phone, which includes a main body (A) 701, a main body (B) 702, a housing 703, operation keys 704, an audio input unit 705, an audio output unit 706, a circuit board 707, a display panel (A) 708, and a display. A panel (B) 709, a hinge 710, a light-transmitting material portion 711, and a photoelectric conversion element 712 are included. The present invention can be applied to the photoelectric conversion element 712.

  The photoelectric conversion element 712 detects light transmitted through the light-transmitting material portion 711, performs brightness control of the display panel (A) 708 and the display panel (B) 709 in accordance with the detected illuminance of external light, or performs photoelectric conversion. The illumination of the operation key 704 is controlled in accordance with the illuminance obtained by the element 712. Thereby, current consumption of the mobile phone can be suppressed.

  20A and 20B illustrate another example of a mobile phone. 20A and 20B, 721 is a main body, 722 is a housing, 723 is a display panel, 724 is an operation key, 725 is an audio output unit, 726 is an audio input unit, and 727 and 728 are photoelectric conversions. It is an element.

  In the cellular phone illustrated in FIG. 20A, the luminance of the display panel 723 and the operation key 724 can be controlled by detecting external light using the photoelectric conversion element 727 provided in the main body 721.

  In addition, in the cellular phone illustrated in FIG. 20B, a photoelectric conversion element 728 is provided inside the main body 721 in addition to the structure in FIG. The luminance of the backlight provided in the display panel 723 can also be detected by the photoelectric conversion element 728.

  FIG. 21A illustrates a computer, which includes a main body 731, a housing 732, a display portion 733, a keyboard 734, an external connection port 735, a pointing device 736, and the like.

  FIG. 21B shows a display device such as a television receiver. This display device includes a housing 741, a support base 742, a display portion 743, and the like.

  FIG. 22 shows a detailed structure in the case where a liquid crystal panel is used as the display portion 733 provided in the computer in FIG. 21A and the display portion 743 of the display device in FIG.

  A liquid crystal panel 762 illustrated in FIG. 22 is incorporated in a housing 761, and includes substrates 751a and 751b, a liquid crystal layer 752 sandwiched between the substrates 751a and 751b, polarization filters 755a and 755b, a backlight 753, and the like. Yes. In the housing 761, a photoelectric conversion element formation region 754 including a photoelectric conversion element is formed.

  The photoelectric conversion element formation region 754 manufactured using the present invention senses the amount of light from the backlight 753, and the information is fed back to adjust the luminance of the liquid crystal panel 762.

  FIG. 23A and FIG. 23B are diagrams showing an example in which the optical sensor of the present invention is incorporated in a camera, for example, a digital camera. FIG. 23A is a perspective view seen from the front side of the digital camera, and FIG. 23B is a perspective view seen from the rear side. In FIG. 23A, the digital camera includes a release button 801, a main switch 802, a finder window 803, a flash 804, a lens 805, a lens barrel 806, and a housing 807.

  In FIG. 23B, a viewfinder eyepiece window 811, a monitor 812, and operation buttons 813 are provided.

  When the release button 801 is pressed down to the half position, the focus adjustment mechanism and the exposure adjustment mechanism are operated, and when the release button 801 is pressed down to the lowest position, the shutter button is opened.

  A main switch 802 switches on / off the power of the digital camera when pressed or rotated.

  The viewfinder window 803 is an apparatus for confirming a shooting range and a focus position from the viewfinder eyepiece window 811 shown in FIG.

  The flash 804 is arranged at the upper front of the digital camera, and emits auxiliary light at the same time that the release button is pressed and the shutter button is opened when the subject brightness is low.

  The lens 805 is disposed in front of the digital camera. The lens includes a focusing lens, a zoom lens, and the like, and constitutes a photographing optical system together with a shutter button and a diaphragm (not shown). In addition, an imaging element such as a CCD (Charge Coupled Device) is provided behind the lens.

  The lens barrel 806 moves the lens position in order to focus the focusing lens, the zoom lens, and the like. During photographing, the lens barrel 805 is extended to move the lens 805 forward. Further, when carrying the camera, the lens 805 is moved down to be compact. In the present embodiment, the structure is such that the subject can be zoomed by extending the lens barrel. However, the present invention is not limited to this structure, and the structure of the imaging optical system in the housing 807 is not limited. It may be a digital camera capable of zooming without extending the cylinder.

  The viewfinder eyepiece window 811 is provided on the upper rear surface of the digital camera, and is a window provided for eye contact when confirming the photographing range and the focus position.

  The operation buttons 813 are various function buttons provided on the rear surface of the digital camera, and include a setup button, a menu button, a display button, a function button, a selection button, and the like.

  When the optical sensor of the present invention is incorporated in the camera shown in FIGS. 23A and 23B, the optical sensor can detect the presence and intensity of light, thereby adjusting the exposure of the camera. Can do.

  The optical sensor of the present invention can be applied to other electronic devices such as a projection television and a navigation system. In other words, it can be used for any object that needs to detect light.

  Note that this embodiment may be combined with other embodiments if necessary.

  In this example, FIGS. 24 and 25 show the relationship between the illuminance E and the photocurrent I when the film thickness of the conductive film forming the source electrode or the drain electrode of the TFT 104 in FIG. 1 is changed.

FIG. 24 is a graph showing the relationship between the illuminance E (horizontal axis) and the voltage V _gate (vertical axis) applied to the gate electrode. The film thickness of the source electrode or drain electrode is 0.052Ω / □, 0 A comparison is made between those formed to have a resistance ratio of .52Ω / □, 5.2Ω / □, 52Ω / □, and 520Ω / □ (resistance ratio: 0.01, 0.1, 1, 10, 100).

  FIG. 25 is a graph showing the relationship between the illuminance E (horizontal axis) and the magnification (vertical axis), and the magnification is a differential value of the photocurrent I in FIG.

  24 and 25, the white diamonds have a resistance ratio of 0.01 (sheet resistance: 0.052 Ω / □), and the white squares have a resistance ratio of 0.1 (sheet resistance: 0.52 Ω / □) and white. The triangle represents the resistance ratio 1 (sheet resistance: 5.2 Ω / □), the white circle represents the resistance ratio 10 (sheet resistance: 52 Ω / □), and the black square represents the resistance ratio 100 (sheet resistance: 520 Ω / □). ing.

  As shown in FIGS. 24 and 25, the resistance value of the source electrode or the drain electrode is low, 0.052Ω / □, 0.52Ω / □, 5.2Ω / □ (resistance ratio: 0.01, 0.1 In 1), the rate of reduction of the photocurrent I is small even when the illuminance E increases. However, it can be seen that, at 52Ω / □, 520Ω / □ (resistance ratio: 10, 100) where the resistance value of the source electrode or the drain electrode is high, the illuminance E increases greatly.

  From the above, it can be seen that if a parasitic resistance occurs in the TFT 104 on the reference side of the current mirror circuit, the output photocurrent decreases. As a result, the range of light intensity to be sensed is reduced. Therefore, the configuration of the present invention is useful because it can suppress the generation of parasitic resistance and prevent the light sensitivity from decreasing.

  According to the present invention, a semiconductor device or a photoelectric conversion device that can suppress a decrease in photosensitivity can be manufactured. Further, by incorporating the semiconductor device or the photoelectric conversion device of the present invention, it is possible to obtain an electric device with high stability and reliability of circuit operation.

1 is a circuit diagram of a semiconductor device of the present invention. 1 is a block diagram of a semiconductor device of the present invention. 1 is a circuit diagram of a semiconductor device. The figure which shows the relationship between the voltage _Vgate concerning a gate electrode, and the photocurrent I. The figure which shows the relationship between the illumination intensity E and the photocurrent I. 1 is a circuit diagram of a semiconductor device of the present invention. 1 is a circuit diagram of a semiconductor device of the present invention. 1 is a circuit diagram of a semiconductor device of the present invention. 1 is a circuit diagram of a semiconductor device of the present invention. Sectional drawing of the semiconductor device of this invention. 9 is a cross-sectional view illustrating a manufacturing process of a semiconductor device of the present invention. 9 is a cross-sectional view illustrating a manufacturing process of a semiconductor device of the present invention. 9 is a cross-sectional view illustrating a manufacturing process of a semiconductor device of the present invention. 1 is a top view of a semiconductor device of the present invention. Sectional drawing of the semiconductor device of this invention. 9 is a cross-sectional view illustrating a manufacturing process of a semiconductor device of the present invention. 9 is a cross-sectional view illustrating a manufacturing process of a semiconductor device of the present invention. 9 is a cross-sectional view illustrating a manufacturing process of a semiconductor device of the present invention. The figure which shows the apparatus which mounted the semiconductor device of this invention. The figure which shows the apparatus which mounted the semiconductor device of this invention. The figure which shows the apparatus which mounted the semiconductor device of this invention. The figure which shows the apparatus which mounted the semiconductor device of this invention. The figure which shows the apparatus which mounted the semiconductor device of this invention. The figure which shows the relationship between the illumination intensity E and the photocurrent I when changing the film thickness of the electrically conductive film which forms a source electrode or a drain electrode. The figure which shows the relationship between the illumination intensity E and magnification when changing the film thickness of the electrically conductive film which forms a source electrode or a drain electrode. 1 is a block diagram of a semiconductor device of the present invention. The block diagram which shows the battery of this invention. The circuit diagram contained in the battery of this invention. The top view of the circuit contained in the battery of this invention. The figure which shows the circuit contained in the battery of this invention. Sectional drawing of the battery of this invention. The block diagram which shows the circuit contained in the battery of this invention. The circuit diagram contained in the battery of this invention.

Explanation of symbols

100 photoelectric conversion layer 100i i-type semiconductor layer 100n n-type semiconductor layer 100p p-type semiconductor layer 101 power supply 103 photoelectric conversion layer 103i i-type semiconductor layer 103n n-type semiconductor layer 103p p-type semiconductor layer 104 TFT
105 TFT
105a TFT
105i TFT
111 current mirror circuit 118a circuit 118b circuit 118i circuit 119a terminal 119b terminal 119i terminal 120a terminal 120b terminal 120i terminal 121a terminal 121b terminal 121i terminal 122 current mirror circuit 123 circuit 124 terminal 141 electrode 142 electrode 144 wiring 145 wiring 146 wiring 146a wiring 146b wiring 146c wiring 146d wiring 147 wiring 201 TFT
202 TFT
203 current mirror circuit 204 circuit 210 substrate 212 base insulating film 213 gate insulating film 214 wiring 215 wiring 216 insulating film 217 insulating film 218 protective electrode 219 wiring 220 connecting electrode 221 terminal electrode 222 terminal electrode 224 sealing layer 231 island-like semiconductor region 232 Island-like semiconductor region 234 Gate electrode 235 Gate electrode 237 Source region or drain region 238 Source region or drain region 241 Source electrode or drain electrode 242 Source electrode or drain electrode 245 Protection electrode 246 Protection electrode 247 Protection electrode 248 Protection electrode 250 Terminal electrode 251 Terminal electrode 260 Substrate 261 Electrode 262 Electrode 263 Solder 264 Solder 271 Source region or drain region 272 Source region or drain region 281 Terminal electrode 282 Source electrode Other drain electrode 283 the source or drain electrode 284 interconnect 285 connecting electrode 291 element forming region 292 light receiving section 293 amplifying circuit unit 301 TFT
302 TFT
303 current mirror circuit 311 metal film 312 gate electrode 313 gate electrode 314 gate insulating film 315 island semiconductor region 316 island semiconductor region 318 mask 321 source region or drain region 322 source region or drain region 331 source electrode or drain electrode 332 source electrode Or drain electrode 336 protective electrode 337 protective electrode 341 source electrode or drain electrode 342 source electrode or drain electrode 401 RF battery 407 battery 411 internal antenna circuit 412 rectifier circuit 413 charging circuit 414 charging control circuit 415 external antenna circuit 425 constant current source circuit 426 Switch circuit 501 Antenna 502 Resonance capacitance 503 Antenna circuit 504 Diode 505 Diode 506 Smoothing capacitance 522 Circuit element 523 An Na 701 body (A)
702 Body (B)
703 Case 704 Operation key 705 Audio input unit 706 Audio output unit 707 Circuit board 708 Display panel (A)
709 Display panel (B)
710 Hinge 711 Translucent material portion 712 Photoelectric conversion element 712 Photoelectric conversion element 721 Main body 722 Case 723 Display panel 724 Operation key 725 Audio output portion 726 Audio input portion 727 Photoelectric conversion element 728 Photoelectric conversion element 731 Main body 732 Case 733 Display Part 734 Keyboard 735 External connection port 736 Pointing device 741 Case 742 Support base 743 Display part 751a Substrate 751b Substrate 752 Liquid crystal layer 753 Backlight 754 Photoelectric conversion element formation region 755a Polarization filter 755b Polarization filter 761 Case 762 Liquid crystal panel 801 Release button 802 Main switch 803 Viewfinder window 804 Flash 805 Lens 806 Lens barrel 807 Case 811 Viewfinder eyepiece window 812 Monitor 813 Operation button 951 Resistance 952 Transition Transistor 954 transistor 955 transistor 955 transistor 956 transistor 957 transistor 958 transistor 959 transistor 960 transistor 961 transistor 962 resistor 963 inverter 964 inverter 965 transmission gate 966 transistor 967 transistor 968 transistor 969 transistor 970 transistor 971 transistor 972 transistor 973 transistor 974 transistor 975 resistor 976 Potential power line 977 Low potential power line 1001 Power source 1003 Photodiode 1004 TFT
1005 TFT
1006 Parasitic resistance 1011 Current mirror circuit 1701 Substrate 1702 Circuit element 1703 Battery 1705a Antenna circuit 1705b Antenna circuit 1705c Antenna circuit 1706 Transmitter 1707 Radio signal 7101 Substrate 7102 Current collector thin film 7103 Negative electrode active material layer 7104 Solid electrolyte layer 7105 Positive electrode active material layer 7106 Current collector thin film _RL Load resistance

Claims (19)

A photoelectric conversion element;
A current mirror circuit that has a thin film transistor for reference and a thin film transistor on the output side, and amplifies the output of the photoelectric conversion element;
A power source having a high potential electrode and a low potential electrode;
Have
The reference thin film transistor and the output side thin film transistor are n-type thin film transistors,
One of a source electrode and a drain electrode of the reference thin film transistor is electrically connected to the high potential electrode through the photoelectric conversion element,
One of a source electrode and a drain electrode of the thin film transistor on the output side is electrically connected to the high potential electrode,
The other of the source electrode and the drain electrode of the reference thin film transistor is electrically connected to the low potential electrode,
The other of the source electrode and the drain electrode of the output side thin film transistor is electrically connected to the low potential electrode,
The semiconductor device according to claim 1, wherein the thin film transistor on the reference side is disposed closer to the low potential electrode than the thin film transistor on the output side. In Claim 1, the gate electrode of the thin film transistor on the output side is electrically connected to one of the gate electrode of the thin film transistor on the reference side and the source electrode and drain electrode of the thin film transistor on the reference side,
One of the source electrode and the drain electrode of the thin film transistor on the reference side is electrically connected to one of the source electrode and the drain electrode of the thin film transistor on the output side via the photoelectric conversion element,
The other of the source electrode and the drain electrode of the thin film transistor on the reference side is electrically connected to the other of the source electrode and the drain electrode of the thin film transistor on the output side. A photoelectric conversion element;
A current mirror circuit that has a thin film transistor for reference and a thin film transistor on the output side, and amplifies the output of the photoelectric conversion element;
A power source having a high potential electrode and a low potential electrode;
Have
The reference thin film transistor and the output side thin film transistor are n-type thin film transistors,
One of a source electrode and a drain electrode of the reference thin film transistor is electrically connected to the high potential electrode through the photoelectric conversion element,
One of a source electrode and a drain electrode of the thin film transistor on the output side is electrically connected to the high potential electrode,
The other of the source electrode and the drain electrode of the reference thin film transistor is electrically connected to the low potential electrode,
The other of the source electrode and the drain electrode of the output side thin film transistor is electrically connected to the low potential electrode,
A semiconductor device, wherein a current path between the reference-side thin film transistor and the low-potential electrode is shorter than a current path between the output-side thin film transistor and the low-potential electrode. The gate electrode of the output side thin film transistor is electrically connected to one of the gate electrode of the reference side thin film transistor and the source electrode and the drain electrode of the reference side thin film transistor according to claim 3,
One of the source electrode and the drain electrode of the thin film transistor on the reference side is electrically connected to one of the source electrode and the drain electrode of the thin film transistor on the output side via the photoelectric conversion element,
The other of the source electrode and the drain electrode of the thin film transistor on the reference side is electrically connected to the other of the source electrode and the drain electrode of the thin film transistor on the output side. A photoelectric conversion element;
A current mirror circuit that has a thin film transistor for reference and a plurality of thin film transistors on the output side, and amplifies the output of the photoelectric conversion element;
A power source having a high potential electrode and a low potential electrode;
Have
The reference thin film transistor and the plurality of output-side thin film transistors are n-type thin film transistors,
One of a source electrode and a drain electrode of the reference thin film transistor is electrically connected to the high potential electrode through the photoelectric conversion element,
One of the source electrode and the drain electrode of the plurality of output side thin film transistors is electrically connected to the high potential electrode,
The other of the source electrode and the drain electrode of the reference thin film transistor is electrically connected to the low potential electrode,
The other of the source electrode and the drain electrode of the plurality of output side thin film transistors is electrically connected to the low potential electrode,
The reference side thin film transistor is disposed closer to the low potential electrode than each of the plurality of output side thin film transistors. The gate electrode of the plurality of output-side thin film transistors is electrically connected to one of the gate electrode of the reference-side thin film transistor and the source electrode and the drain electrode of the reference-side thin film transistor according to claim 5,
One of the source electrode and the drain electrode of the reference-side thin film transistor is electrically connected to one of the source electrode and the drain electrode of the plurality of output-side thin film transistors via the photoelectric conversion element,
The other of the source electrode and the drain electrode of the thin film transistor on the reference side is electrically connected to the other of the source electrode and the drain electrode of the plurality of thin film transistors on the output side. A photoelectric conversion element;
A current mirror circuit that has a thin film transistor for reference and a plurality of thin film transistors on the output side, and amplifies the output of the photoelectric conversion element;
A power source having a high potential electrode and a low potential electrode;
Have
The reference thin film transistor and the plurality of output-side thin film transistors are n-type thin film transistors,
One of a source electrode and a drain electrode of the reference thin film transistor is electrically connected to the high potential electrode through the photoelectric conversion element,
One of the source electrode and the drain electrode of the plurality of output side thin film transistors is electrically connected to the high potential electrode,
The other of the source electrode and the drain electrode of the reference thin film transistor is electrically connected to the low potential electrode,
The other of the source electrode and the drain electrode of the plurality of output side thin film transistors is electrically connected to the low potential electrode,
2. A semiconductor device according to claim 1, wherein a current path between the reference-side thin film transistor and the low-potential electrode is shorter than a current path between each of the plurality of output-side thin film transistors and the low-potential electrode. The gate electrode of the plurality of output-side thin film transistors is electrically connected to one of the gate electrode of the reference-side thin film transistor and the source electrode and the drain electrode of the reference-side thin film transistor according to claim 7,
One of the source electrode and the drain electrode of the reference-side thin film transistor is electrically connected to one of the source electrode and the drain electrode of the plurality of output-side thin film transistors via the photoelectric conversion element,
The other of the source electrode and the drain electrode of the thin film transistor on the reference side is electrically connected to the other of the source electrode and the drain electrode of the plurality of thin film transistors on the output side. A photoelectric conversion element;
A current mirror circuit that has a thin film transistor for reference and a thin film transistor on the output side, and amplifies the output of the photoelectric conversion element;
A power source having a high potential electrode and a low potential electrode;
Have
The reference thin film transistor and the output thin film transistor are p-type thin film transistors,
One of a source electrode and a drain electrode of the reference thin film transistor is electrically connected to the high potential electrode,
One of a source electrode and a drain electrode of the thin film transistor on the output side is electrically connected to the high potential electrode,
The other of the source electrode and the drain electrode of the reference thin film transistor is electrically connected to the low potential electrode through the photoelectric conversion element,
The other of the source electrode and the drain electrode of the output side thin film transistor is electrically connected to the low potential electrode,
The semiconductor device according to claim 1, wherein the thin film transistor on the reference side is disposed closer to the high potential electrode than the thin film transistor on the output side. The gate electrode of the thin film transistor on the output side is electrically connected to the other of the gate electrode of the thin film transistor on the reference side and the source electrode and drain electrode of the thin film transistor on the reference side.
One of the source electrode and the drain electrode of the reference side thin film transistor is electrically connected to one of the source electrode and the drain electrode of the output side thin film transistor,
The other of the source electrode and the drain electrode of the reference side thin film transistor is electrically connected to the other of the source electrode and the drain electrode of the output side thin film transistor through the photoelectric conversion element. . A photoelectric conversion element;
A current mirror circuit that has a thin film transistor for reference and a thin film transistor on the output side, and amplifies the output of the photoelectric conversion element;
A power source having a high potential electrode and a low potential electrode;
Have
The reference thin film transistor and the output thin film transistor are p-type thin film transistors,
One of a source electrode and a drain electrode of the reference thin film transistor is electrically connected to the high potential electrode,
One of a source electrode and a drain electrode of the thin film transistor on the output side is electrically connected to the high potential electrode,
The other of the source electrode and the drain electrode of the reference thin film transistor is electrically connected to the low potential electrode through the photoelectric conversion element,
The other of the source electrode and the drain electrode of the output side thin film transistor is electrically connected to the low potential electrode,
A semiconductor device, wherein a current path between the reference-side thin film transistor and the high-potential electrode is shorter than a current path between the output-side thin film transistor and the high-potential electrode. The gate electrode of the thin film transistor on the output side is electrically connected to the other of the gate electrode of the thin film transistor on the reference side and the source electrode and drain electrode of the thin film transistor on the reference side.
One of the source electrode and the drain electrode of the reference side thin film transistor is electrically connected to one of the source electrode and the drain electrode of the output side thin film transistor,
The other of the source electrode and the drain electrode of the reference side thin film transistor is electrically connected to the other of the source electrode and the drain electrode of the output side thin film transistor through the photoelectric conversion element. . A photoelectric conversion element;
A current mirror circuit that has a thin film transistor for reference and a plurality of thin film transistors on the output side, and amplifies the output of the photoelectric conversion element;
A power source having a high potential electrode and a low potential electrode;
Have
The reference thin film transistor and the plurality of output-side thin film transistors are p-type thin film transistors,
One of a source electrode and a drain electrode of the reference thin film transistor is electrically connected to the high potential electrode,
One of the source electrode and the drain electrode of the plurality of output side thin film transistors is electrically connected to the high potential electrode,
The other of the source electrode and the drain electrode of the reference thin film transistor is electrically connected to the low potential electrode through the photoelectric conversion element,
The other of the source electrode and the drain electrode of the plurality of output side thin film transistors is electrically connected to the low potential electrode,
The semiconductor device according to claim 1, wherein the reference side thin film transistor is disposed closer to the high potential electrode than each of the plurality of output side thin film transistors. The gate electrode of the plurality of output-side thin film transistors is electrically connected to the other of the gate electrode of the reference-side thin film transistor and the source electrode and the drain electrode of the reference-side thin film transistor.
One of the source electrode and the drain electrode of the reference side thin film transistor is electrically connected to one of the source electrode and the drain electrode of the plurality of output side thin film transistors,
The other of the source electrode and the drain electrode of the thin film transistor on the reference side is electrically connected to the other of the source electrode and the drain electrode of the plurality of thin film transistors on the output side via the photoelectric conversion element. Semiconductor device. A photoelectric conversion element;
A current mirror circuit that has a thin film transistor for reference and a plurality of thin film transistors on the output side, and amplifies the output of the photoelectric conversion element;
A power source having a high potential electrode and a low potential electrode;
Have
The reference thin film transistor and the plurality of output-side thin film transistors are p-type thin film transistors,
One of a source electrode and a drain electrode of the reference thin film transistor is electrically connected to the high potential electrode,
One of the source electrode and the drain electrode of the plurality of output side thin film transistors is electrically connected to the high potential electrode,
The other of the source electrode and the drain electrode of the reference thin film transistor is electrically connected to the low potential electrode through the photoelectric conversion element,
The other of the source electrode and the drain electrode of the plurality of output side thin film transistors is electrically connected to the low potential electrode,
2. A semiconductor device according to claim 1, wherein a current path between the reference side thin film transistor and the high potential electrode is shorter than a current path between each of the plurality of output side thin film transistors and the high potential electrode. The gate electrode of the plurality of output-side thin film transistors is electrically connected to the other of the gate electrode of the reference-side thin film transistor and the source electrode and the drain electrode of the reference-side thin film transistor according to claim 15,
One of the source electrode and the drain electrode of the reference side thin film transistor is electrically connected to one of the source electrode and the drain electrode of the plurality of output side thin film transistors,
The other of the source electrode and the drain electrode of the thin film transistor on the reference side is electrically connected to the other of the source electrode and the drain electrode of the plurality of thin film transistors on the output side via the photoelectric conversion element. Semiconductor device. A photoelectric conversion element;
A current mirror circuit that amplifies the output of the photoelectric conversion element and has at least two thin film transistors;
A high potential power source electrically connected to each of the thin film transistors;
A low potential power source electrically connected to each of the thin film transistors;
Have
Among the thin film transistors, a reference-side thin film transistor is disposed near the low-potential power source. A photoelectric conversion element;
Amplifying the output of the photoelectric conversion element, a reference side thin film transistor, and a current mirror circuit having a plurality of output side thin film transistors;
A high-potential power supply electrically connected to each of the reference-side thin film transistor and the plurality of output-side thin film transistors;
A low-potential power source electrically connected to each of the reference-side thin film transistor and the plurality of output-side thin film transistors;
The semiconductor device according to claim 1, wherein the thin film transistor on the reference side is disposed closer to the low potential power source than each of the thin film transistors on the output side. In claim 17 or claim 18,
The gate electrode of the output side thin film transistor is electrically connected to one of the gate electrode of the reference side thin film transistor and the source electrode or drain electrode of the reference side thin film transistor,
One of a source electrode or a drain electrode of the reference side thin film transistor is electrically connected to one of a source electrode or a drain electrode of the output side thin film transistor,
2. The semiconductor device according to claim 1, wherein the other of the source electrode and the drain electrode of the reference-side thin film transistor is electrically connected to the other of the output-side source electrode and the drain electrode.

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