JP2008108887A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of performing resin sealing in a chip scale package in size being substantially the same as the two-dimensional size of a composite semiconductor device even concerning the composite semiconductor device having the semiconductor device where a main electric current flows in the thickness direction of a semiconductor substrate. <P>SOLUTION: The semiconductor device includes: p-type well regions 3 selectively formed on an n-type drift layer 2 on an n-type low resistance semiconductor substrate 1; n-type source regions 4 selectively formed on the p-type well regions 3; gate insulating films 5 and gate electrodes 6 which are formed on the surface of the p-type well regions 3 held between the n-type drift layer 2 and the surfaces of the n-type source regions 4; and an n-type drain region 9 arranged on the surface being the same as that of the p-type well regions 3 and separated at desired distance. The desired distance is set in the semiconductor device, so as to allow the electric resistance of the electron to be the smallest when passing the low resistance semiconductor substrate 1 and reaching the drain region 9, in a case where the electron passing a channel is made to flow from the source regions 4 toward the drain region 9 by way of the drift region 2 at turning-on time. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor element in which a main current flows in the thickness direction of a semiconductor substrate, that is, a semiconductor element incorporating a vertical semiconductor device, and more particularly to a semiconductor device incorporating a vertical MOSFET.

  FIG. 13 shows a cross-sectional view of a main part of a MOSFET portion of a semiconductor device in which a conventional vertical MOSFET is integrated and built in the same semiconductor substrate. FIG. 14 is a top view showing a state in which the upper half of the sealing resin is removed in order to clearly show the inside of the structure in which this semiconductor device is sealed with resin according to the prior art. Similarly, FIG. 15 shows a vertical cross-sectional view when resin sealing is performed by a CSP (Chip Scale Package) method.

First, of the semiconductor device according to the prior art shown in FIG. 13, a vertical MOSFET portion, the high-resistance n formed on one surface of a low-resistance n ⁺ semiconductor substrate 1 ^- p-well region in a surface layer of the drift layer 2 3, an n ⁺ source region 4 is selectively formed on the surface layer of the p well region 3, and the p well region 3 sandwiched between the surface of the n ⁻ drift layer 2 and the surface of the n ⁺ source region 4 is formed. surface of the gate electrode 6 is provided via the gate insulating film 5, further a source electrode 7 made of a metal electrode film in contact with the common provided on the surface of the n ⁺ source region 4 and the p-well region 3, n ⁺ substrate 1 The other surface is provided with a drain electrode 8 made of a metal electrode film. When this vertical MOSFET is turned on, the current flows from the drain electrode 8 to the drain region 1, the drift region 2, the p-well region 3 portion (n channel—not shown) immediately below the gate electrode, and the source region 7. This is a conventional normal vertical MOSFET structure.

  When a semiconductor device incorporating such a conventional vertical MOSFET structure in the same semiconductor substrate is resin-sealed, as shown in a top view of FIG. 14, one pin provided in the resin package 100 is electrically connected. On the metal die pad 101 connected to the semiconductor device, a semiconductor device in which the vertical MOSFET is formed on the same semiconductor substrate, that is, the back surface of the IC chip 102 is brought into contact, and the pin needs to be a drain electrode terminal of the vertical MOSFET. . The back surface of the IC chip 102 and the die pad 101 are connected and fixed via solder. A plurality of pins (electrode terminals) 104 are arranged around the IC chip, one end side is fixed in the package 100 and the other end side protrudes from the package for external connection, and provided on the surface of the IC chip 102. Some of the IC pads 103 are formed by resin sealing after being configured to be conductively connected by bonding wires.

  On the other hand, in the resin-encapsulated semiconductor device by the conventional CSP method shown in the sectional view of FIG. 15, the back surface 202 side of the IC chip 200 is up in this drawing, and the front surface 201 side where a plurality of IC pads 203 are provided is down. An insulating film 204 is formed on the IC chip surface 201 excluding the plurality of IC pads 203, a metal post pedestal 205 is formed on the insulating film 204, and each post pedestal is conductively connected to each IC pad 203. A cylindrical metal post 206 is formed on the post pedestal 205, and solder bumps 207 are formed on each post 206 to serve as input / output pins. Finally, the resin from the top of the insulating film 204 to the height of the post 206 is covered with resin 208 and sealed with a resin, thereby obtaining a CSP type semiconductor device. In the CSP, the solder bumps 207 at all locations serve as input / output pins (electrode terminals) of the IC chip 200. The two-dimensional size of the package of this CSP type semiconductor device is almost the same as the chip size. Further, since the back surface 202 of the IC chip 200 is not conductively connected to the electrode terminals (pins) and is exposed without being covered with the resin, the thickness of the package is also the height of the input / output pins. A resin thickness of a minute is necessary, but other thicknesses can be minimized.

As a composite semiconductor device in which a MOSFET is built in the same semiconductor substrate, an intelligent switch device having a built-in lateral MOSFET is known (Patent Document 1).
JP 2005-136290 A (summary)

  However, the resin package shown in FIG. 14 that is required when resin-sealing an IC chip incorporating the conventional vertical MOSFET as shown in FIG. 13 reduces the occupied space and further downsizes the package. However, it is difficult to further reduce the size as it is. If the CSP method is applied, the size can be reduced. However, since the conventional vertical MOSFET needs to use both the front and back surfaces of the IC chip as electrodes, the conventional CSP resin as shown in FIG. It is difficult to obtain a sealed body.

  The present invention has been made in view of the above points, and an object of the present invention is a composite semiconductor device having a vertical semiconductor element in which the main current flows in the thickness direction of the semiconductor substrate on the same semiconductor substrate. Another object of the present invention is to provide a semiconductor device that can be resin-sealed in a chip scale package that is substantially the same as the two-dimensional size of the semiconductor substrate of the composite semiconductor device.

  According to the first aspect of the present invention, the other conductivity type well region selectively formed on the surface layer of the one conductivity type drift layer on the one main surface of the one conductivity type low resistance semiconductor substrate, One conductivity type source region selectively formed on the surface layer of the other conductivity type well region, and the other conductivity type well region surface sandwiched between the one conductivity type drift layer surface and the one conductivity type source region surface In a semiconductor device comprising: a gate electrode formed on a gate insulating film thereon; and a one-conductivity-type drain region disposed on the same surface as the other-conductivity-type well region and spaced apart by a required distance. When a voltage equal to or higher than the threshold voltage is applied, electrons pass from the source region to the drain region through the channel formed in the surface of the other conductivity type well region immediately below the gate insulating film. In the semiconductor device, the required distance is set to be the smallest when the electrical resistance received by the electrons passes through the one-conductivity type low-resistance semiconductor substrate to the drain region. The object of the invention is achieved.

According to the second aspect of the present invention, it is preferable that the bottom of the drain region is not in contact with the one-conductivity type low-resistance semiconductor substrate. .
According to a third aspect of the present invention, the bottom of the drain region is preferably in contact with the one-conductivity type low-resistance semiconductor substrate. .

According to a fourth aspect of the present invention, the semiconductor device according to any one of the first to third aspects, wherein the thickness of the one-conductivity type low-resistance semiconductor substrate is 50 μm or more. More preferably.
According to the invention described in claim 5, the metal thin film is in ohmic contact with the other main surface of the one-conductivity-type low-resistance semiconductor substrate. The semiconductor device described in one item is also desirable.

According to the invention described in claim 6, the chip scale which is resin-sealed by exposing the other main surface of the semiconductor device according to any one of claims 1 to 5. It is also preferable that the package is a chip scale package of a semiconductor device in which a heat sink is provided on the exposed surface of the semiconductor device.
According to the seventh aspect of the present invention, the number of drain electrodes is larger than that of the source electrode in order to reduce the electric resistance component due to the current flowing in the one-conductivity type low-resistance semiconductor substrate in parallel with the main surface. 5. The semiconductor device according to claim 1, wherein the same number of drain electrodes as the source electrodes are provided with solder bumps, and the remaining drain electrodes are connected by metal wiring. It is more preferable to use a chip scale package of a semiconductor device connected to the solder bumped drain electrode.

  According to the present invention, it is possible to provide a semiconductor device that is resin-sealed in a chip scale package that is substantially the same as the two-dimensional size of the semiconductor substrate, even if it is a composite semiconductor device having vertical semiconductor elements in the same semiconductor substrate. it can.

Hereinafter, an embodiment of a semiconductor device according to the present invention will be described in detail with reference to the drawings. The present invention is not limited to the description of the examples described below unless it exceeds the gist.
1 is a cross-sectional view of a main part of a vertical MOSFET according to a first embodiment of the present invention, FIG. 2 is a cross-sectional view of a main part of an IC chip according to the first embodiment of the present invention, and FIG. 3 is a second embodiment according to the present invention. FIG. 4 is a cross-sectional view of the main part of the vertical MOSFET according to the second embodiment of the present invention, and FIG. 5 is a cross-sectional view of the main part of the vertical MOSFET according to the third embodiment of the present invention. 6 is a cross-sectional view of the main part of the vertical MOSFET according to the third embodiment of the present invention, FIG. 7 is a transparent top view of the CSP resin sealing body according to the third embodiment of the present invention, and FIG. 8 is a third embodiment of the present invention. FIG. 9 is a cross-sectional view of an essential part of a vertical MOSFET according to Example 4 of the present invention, FIG. 10 is a cross-sectional view of a CSP resin encapsulant according to Example 5 of the present invention, and FIG. 12 is a perspective top view of a CSP resin encapsulant according to Example 6 of the present invention, and FIG. 12 is an example of the present invention. It is a cross-sectional view of a IC chip.

  FIG. 1 is a cross-sectional view of a main part of a semiconductor substrate of a vertical MOSFET portion built in the same semiconductor substrate as a composite semiconductor device (hereinafter referred to as an IC chip) according to a first embodiment. In the first embodiment, a semiconductor device that can be resin-sealed by the CSP method that is miniaturized to the same size as the chip size even when an IC chip incorporating such a vertical semiconductor device is used will be described. A semiconductor device according to the present invention is characterized in that a source electrode and a drain electrode are provided on the surface side of a vertical MOSFET portion built in an IC chip in order to enable resin sealing by the CSP method. . Further, in addition, although the vertical MOSFET according to the present invention has a configuration in which the source electrode and the drain electrode are separately formed on the same surface side of the semiconductor substrate, the main current is the thickness of the semiconductor substrate. The direction, that is, the drain-source high resistance region (drift region) is configured to flow in the vertical direction. In this respect, the drain electrode and the source electrode are similarly provided on the same surface side of the semiconductor substrate of the MOSFET, but the main current is between the drain and source, and the high resistance region (drift region) of the semiconductor substrate is parallel to the main surface. This is different from so-called lateral MOSFETs that flow in different directions.

Next, the vertical MOSFET according to the first embodiment illustrated in FIG. 1 will be described. Low resistance n ^{+ A} p ⁻ well region 3 is selectively formed in the surface layer of the high resistance n ⁻ drift region 2 disposed on the substrate 1, and n is selectively formed in the surface layer of the p ⁻ well region 3. ⁺ Source region 4 is formed. On the surface of the p ⁻ well region 3 sandwiched between the surface of the n ⁻ drift region 2 and the surface of the n ⁺ source region 4, a gate electrode 6 made of conductive polysilicon or the like via a gate insulating film (oxide film) 5. And a source electrode 7 made of a metal film such as Al—Si connected to the surfaces of the n ⁺ source region 4 and the p ⁻ well region 3 in common. An n ⁺ drain region 9 is formed on the surface of the n ⁻ drift region 2 that is separated from the end of the surface on the side where an n channel (not shown) is formed immediately below the gate insulating film on the surface of the p ⁻ well region 3. Place. A metal film such as Al—Si is brought into ohmic contact with the surface of the n ⁺ drain region 9 as the drain electrode 10. At this time, the bottom of the n ⁺ drain region 9 formed from the surface of the drift region 2 toward the inside is not connected to the low resistance n ⁺ substrate 1, but the main current 20 is supplied from the drain electrode 10 to the n ⁺ drain. It is configured to flow through the bottom of region 9 to the low resistance n ⁺ substrate. Subsequently, the main current 20 flows in the low resistance n ⁺ substrate in a direction parallel to the main surface, and flows in the n ⁻ drift region 2 in the thickness direction toward the surface. Then, the p ⁻ well region 3, the n ⁺ drain region 9 and the n ⁺ source region 4 pass through the n channel formed on the surface of the p ⁻ well region 3 and enter the n ⁺ source region 4 and the main current 20 is passed to the source electrode 7. If the distance between the drift regions is increased and the lateral resistance between them is set to be greater than the resistance in the thickness direction (vertical direction), the semiconductor device incorporating the vertical semiconductor device Even so, it is possible to package by a conventional CSP resin sealing method as shown in FIG.

However, in the vertical MOSFET shown in FIG. 1 according to the first embodiment, a current may flow from the source electrode 7 to the drain electrode 10 in the negative direction depending on the application. The drain current 30 flowing in the negative direction is indicated by a thick line in FIG. In this case, a drain leakage current 40 is generated which flows into the NMOSFET region 50 of the adjacent low-voltage circuit beyond the bottom of the n ⁺ drain region 9 at a predetermined ratio in the negative direction drain current. When this drain leakage current 40 becomes large, there may be a problem that the NMOSFET 50 malfunctions or is destroyed. When this problem is concerned, it is preferable to use a vertical MOSFET having the configuration of the second embodiment shown below.

FIG. 3 is a cross-sectional view of the semiconductor substrate of the vertical MOSFET portion according to the second embodiment. The configuration of the vertical MOSFET according to the second embodiment is a failure caused by the drain leakage current 40 flowing into the NMOSFET region 50 of the adjacent low voltage circuit when the negative current 30 of FIG. 2 described in the first embodiment flows. This is a configuration for avoiding the problem. The difference between the vertical MOSFET shown in FIG. 1 and FIG. 3 is that the bottom of the n ⁺ drain region 9 reaches the low resistance n ⁺ substrate 1 and is connected in the vertical MOSFET shown in FIG. . With this configuration, it is possible to completely prevent the generation of the drain leakage current 40 even in applications where the negative current 30 described with reference to FIG. 2 flows.

In the vertical MOSFET shown in FIG. 3 according to the second embodiment, the main current flows from the drain electrode 10 to the low resistance n ⁺ substrate 1, the drift region 2, the n channel, and the source, as in the main current path 20 indicated by the thick line in FIG. 4. It flows to the source electrode 7 through the region 4. However, in the case of the n ⁺ substrate 1 having a sheet resistance of about several Ω / □, the drain current 20 cannot be ignored if the on-resistance of the vertical MOSFET increases when the flowing distance is long. Therefore, in applications that require a large drain current 20, heat generated by the on-resistance of the vertical MOSFET is generated in a local region on the back surface of the IC chip with respect to the entire surface of the IC chip. It can be a big problem in terms of diffusion and radiation.

FIG. 5 is a sectional view of the semiconductor substrate of the vertical MOSFET portion according to the third embodiment. The third embodiment can solve the case where the sheet resistance of the n ⁺ substrate 1 cannot be ignored in an application requiring a large capacity drain current, which may cause a problem in the second embodiment shown in FIG. This is a configuration of a vertical MOSFET. The difference between the vertical MOSFETs shown in FIGS. 3 and 5 is that the vertical MOSFET shown in FIG. 5 is different from the configuration of FIG. 3 in that two n ⁺ drain regions 9 are arranged with respect to the MOS gate structure. . However, the n ⁺ drain region 9 may not be separated into two but may have a configuration surrounding the MOS gate structure. According to this structure, the drain current 20 flowing through the vertical MOSFET, minute current path in parallel to n ⁺ substrate 1 on the main surface as shown by a bold line 20 in FIG. 6 is approximately as compared with the case of FIG. 4 The resistance of the n ⁺ substrate 1 is reduced equivalently.

  On the other hand, there is a demerit when there are a plurality of drain electrodes 9. A perspective top view of the IC chip when the vertical MOSFET of the third embodiment is resin-sealed by the conventional CSP method is shown in FIG. As described above, there are two drain electrode pads 13 of the same vertical MOSFET on both sides of the source electrode pad 12 indicated by a broken line in the vertical MOSFET portion in the IC chip 11. The total number of output solder bumps 15 connected to the drain electrode pads 13 of these two vertical MOSFETs is the same as the current flowing from the drain electrode to the source electrode, so that the connection is made to the source electrode pad 12 of the vertical MOSFET. It is sufficient if it is the same as the total number of solder bumps 15 that are applied. However, in Example 3, the total number of output solder bumps 15 connected to the drain electrode pad 13 is larger than the total number of solder bumps 15 connected to the source electrode pad 12. It is useless. This is a disadvantage.

  FIG. 8 is a cross-sectional view of the IC chip 11 according to the third embodiment corresponding to FIG. The IC chip 11 includes a vertical MOSFET section as shown in FIGS. 7 and 8 and a control circuit section 14 configured within a two-dot chain line. As shown in FIG. A lateral N-channel MOSFET 50, a lateral P-channel MOSFET 60, a lateral diode 70 formed in the substrate, a lateral diode 80 formed of polysilicon on a semiconductor substrate, a resistor 90, and the like are included. Reference numeral 15 in FIG. 7 is a solder bump, a chain line with a reference numeral 16 is one pad of the control circuit unit, and a reference numeral 17 is a wiring connecting the solder bump 15 and the pad 16.

FIG. 9 is a sectional view of the semiconductor substrate of the vertical MOSFET portion according to the fourth embodiment. The fourth embodiment has a configuration for further reducing the on-resistance of the vertical MOSFET according to the third embodiment. The difference between FIG. 9 according to the fourth embodiment and the vertical MOSFET of FIG. 5 according to the third embodiment is that a metal thin film 8 is provided on the front surface (rear surface side) of the n ⁺ substrate 1 in FIG. . With the configuration of the vertical MOSFET shown in FIG. 9, the drain current 20 shown in FIG. 6 mainly flows through the metal thin film 8 having a smaller sheet resistance of about 0.01 Ω / □, which is smaller in resistance than the n ⁺ substrate 1. Therefore, the on-resistance of the vertical MOSFET can be greatly reduced. Furthermore, the heat generated in the local region due to the on-resistance of the vertical MOSFET is diffused to the entire surface of the IC chip through the metal thin film 8 provided on the back surface of the IC chip, and the effect based on the heat radiation function radiating into the air from the entire surface is also achieved. Have. The vertical MOSFET shown in FIG. 9 according to the above description does not exhibit its effect only when applied to the fourth embodiment. In the first and second embodiments, the metal thin film 8 is provided on the back surface of the IC chip. If applied, the same effect can be obtained.

  Example 5 will be described using the cross-sectional view of the CSP shown in FIG. The CSP resin package shown in the fifth embodiment has the same outer diameter as that of the conventional CSP resin package described with reference to FIG. 15, but each of the vertical types of the first, second, third, and fourth embodiments described above. The configuration differs in that the IC chip 210 including the MOSFET is resin-sealed by the CSP method and the heat sink 209 is disposed in close contact with the surface exposed on the back surface of the IC chip. As a result, the heat radiation function of the package is further improved, and the allowable loss can be greatly increased.

  Example 6 will be described. FIG. 11 is a transparent top view of the IC chip 11 resin-sealed by the CSP method showing a configuration that eliminates the disadvantages of the IC chip resin-sealed by the CSP method shown in FIG. In the sixth embodiment, the total number of solder bumps 15 connected to the drain electrode pad 13 described in the third embodiment is reduced to be the same as the total number of solder bumps connected to the source electrode pad 12. An example of the configuration to be performed will be described. As shown in FIG. 11, when the solder bump 15 and the drain electrode pad 13 of the vertical MOSFET are connected by the wiring 17, as shown by the new wiring 18, the drain electrode pad 13 of the vertical MOSFET in two locations is 1 The drain electrode pad 13 of the vertical MOSFET and the solder bump 15 are connected to each other, and the drain electrode pad 13 of the other vertical MOSFET is connected to the new wiring 18. With this configuration, the number of solder bumps 15 connected to the drain electrode pad of the vertical MOSFET and the number of solder bumps 15 connected to the source electrode pad 12 are the same, and the number of solder bumps 15 required for the vertical MOSFET. Can be reduced. The sixth embodiment can be applied to a vertical MOSFET having a plurality of drain electrode pads 13.

  FIG. 12 is a cross-sectional view of the IC chip 11 according to the sixth embodiment corresponding to FIG. This IC chip 11 includes the vertical MOSFET portion shown in FIGS. 11 and 12 and the control circuit portion 14 configured within the same two-dot chain line as in FIG. As shown in FIG. 12, the control circuit unit 14 includes a lateral N-channel MOSFET 50, a lateral P-channel MOSFET 60, a lateral diode 70, a lateral diode 80 formed of polysilicon on the semiconductor substrate, a resistor 90, and the like. It has.

Example 7 will be described with reference to FIGS. 16 and 17. Example 7 is a specific numerical explanation regarding the reduction of the resistance component of the n ⁺ substrate among the on-resistance components of the vertical MOSFETs shown in FIGS. 6 and 9, respectively. As shown in FIG. 16, when the distance between the n ⁺ drain region 9 is x, the depth of the vertical MOSFET region is y, the thickness of the n ⁺ substrate 1 is t, and the resistivity of the n ⁺ substrate 1 is ρ. , N ⁺ on-resistance component R (n ⁺ ) of substrate 1 is

It is represented by
Further, regarding the vertical MOSFET shown in FIG. 9, when the thickness of the metal thin film 8 is t _M and the resistivity of the metal thin film 8 is ρ _M , the on-resistance component R of the n ⁺ substrate 1 including the metal thin film 8 ( n ⁺ ) '

It is represented by
17, ^{n +} resistivity ρ, for example 5 m [Omega · cm of the substrate 1, ^{n +} drain region 9 between the distance x, for example 1500 .mu.m, vertical MOSFET region when the depth y example the 2500 [mu] m ^{n +} substrate 1 FIG. 4 is a relationship diagram between a thickness t and an on-resistance component R (n ⁺ ). According to FIG. 17, it can be seen that if the thickness t of the n ⁺ substrate 1 is 50 μm or more, the on-resistance component of the n ⁺ substrate 1 can be 150 mΩ or less. Furthermore, when the resistivity ρ _M of the metal thin film 8 is 0.003 mΩ · cm and the thickness t _M of the metal thin film 8 is 3 μm, for example, the on-resistance component of the n ⁺ substrate 1 can be reduced to 1.5 mΩ or less. I understand.

  As described above, according to the first to seventh embodiments, even in a composite semiconductor device (IC chip) having a vertical MOSFET in which the main current flows in the thickness direction of the semiconductor substrate on the same semiconductor substrate, It becomes possible to manufacture a small CSP that can be resin-sealed as a chip scale package that is almost the same as the two-dimensional size of the semiconductor substrate.

It is principal part sectional drawing of the vertical MOSFET concerning Example 1 of this invention. It is principal part sectional drawing of the IC chip concerning Example 1 of this invention. It is principal part sectional drawing of the vertical MOSFET concerning Example 2 of this invention. It is principal part sectional drawing of the vertical MOSFET concerning Example 2 of this invention. It is principal part sectional drawing of the vertical MOSFET concerning Example 3 of this invention. It is principal part sectional drawing of the vertical MOSFET concerning Example 3 of this invention. It is a see-through | perspective top view of the CSP resin sealing body concerning Example 3 of this invention. It is sectional drawing of the IC chip concerning Example 3 of this invention. . It is principal part sectional drawing of the vertical MOSFET concerning Example 4 of this invention. It is sectional drawing of the CSP resin sealing body concerning Example 5 of this invention. It is a see-through | perspective top view of the CSP resin sealing body concerning Example 6 of this invention. It is sectional drawing of the IC chip concerning Example 6 of this invention. It is principal part sectional drawing of the conventional vertical MOSFET. It is a see-through | perspective top view of the resin sealing body of the conventional IC chip. Sectional drawing of the conventional CSP resin sealing body It is a perspective sectional view of a vertical MOSFET according to Example 7 of the present invention. It is a related figure of the thickness of n ⁺ board | substrate of the vertical MOSFET concerning Example 7 of this invention, and an ON-resistance component.

Explanation of symbols

1 n ⁺ substrate 2 n ^- drift region 3 p ^- well region 4 n ⁺ source region 5 gate insulating film 6 gate electrode 7 source electrode 8 metal thin film 9 n ⁺ drain region 10 drain electrode 11 IC chip 12 source electrode pad 13 drain electrode Pad 14 Control circuit section 15 Solder bump 17, 18 Wiring 20 Main current path 30 Main current path 209 Heat sink 210 IC chip.

Claims (7)

Another conductivity type well region selectively formed in the surface layer of the one conductivity type drift layer on one main surface of the one conductivity type low resistance semiconductor substrate, and selectively formed in the surface layer of the other conductivity type well region A gate electrode formed on a surface of the other conductivity type well region sandwiched between the surface of the one conductivity type drift layer and the surface of the one conductivity type source region via a gate insulating film; In a semiconductor device comprising one conductivity type drain region disposed on the same surface and spaced apart by a required distance from the other conductivity type well region, other than immediately below the gate insulating film when a voltage higher than a threshold voltage is applied to the gate electrode When electrons flow from the source region to the drain region through the channel formed in the surface of the conductivity type well region, the required distance is received by the electron. Vertical semiconductor device, characterized in that the gas resistance is set to be smallest when the exit to the drain region through the one conductivity type low-resistance semiconductor substrate. 2. The vertical semiconductor device according to claim 1, wherein a bottom of the drain region is not in contact with the one conductivity type low resistance semiconductor substrate. 2. The vertical semiconductor device according to claim 1, wherein the bottom of the drain region is in contact with the one-conductivity type low-resistance semiconductor substrate. 4. The vertical semiconductor device according to claim 1, wherein a thickness of the one-conductivity-type low-resistance semiconductor substrate is 50 μm or more. 4. The vertical semiconductor device according to claim 1, wherein a metal film is in ohmic contact with the other main surface of the one-conductivity-type low-resistance semiconductor substrate. 6. A chip scale package in which the other main surface of the vertical semiconductor device according to any one of claims 1 to 5 is exposed and resin-sealed, and a heat sink is provided on the exposed surface of the vertical semiconductor device. A chip scale package of a vertical semiconductor device characterized by the above. 5. The drain electrode according to claim 1, wherein the number of drain electrodes is larger than the number of source electrodes in order to reduce an electrical resistance component due to a current flowing in parallel to the main surface in the one-conductivity type low-resistance semiconductor substrate. In the vertical semiconductor device, the same number of drain electrodes as the source electrodes are provided with solder bumps, and the remaining drain electrodes are connected by metal wiring and connected to the solder bumped drain electrodes. Chip scale package for semiconductor devices.