JP2008107962A - Electronic equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce power consumption in a power saving mode in electronic equipment including a circuit which receives the supply of power supply voltage and operates on the basis of a clock signal. <P>SOLUTION: The electric equipment is provided with a power supply part, a clock signal generation part, an arithmetic processing circuit including an arithmetic processing core part, and a power saving control part for controlling shift processing between a normal mode and a power saving mode. In the case of shifting the normal mode to the power saving mode, the power saving control part validates a clock frequency down signal to the clock signal generation part, and after the lapse of the first time, validates a voltage down signal to the power supply part. When the clock frequency down signal is validated, the clock signal generation part gradually changes the frequency of a clock supplied to the arithmetic processing circuit from the first frequency to the second frequency lower than the first frequency. When the voltage down signal is validated, the voltage to be supplied to the arithmetic processing core part of the arithmetic processing circuit is dropped from the first voltage to the second voltage lower than the first voltage. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to an electronic device including a circuit which is supplied with a power supply voltage and operates based on a clock signal.

  An electronic device such as a printing apparatus is equipped with a controller board for controlling the electronic device. The controller board is an integrated circuit developed for specific applications such as CPU (Central Processing Unit) that performs arithmetic processing, RAM (Random Access Memory) that stores data, ROM (Read Only Memory), and communication processing control. A certain ASIC (Application Specific Integrated Circuit) or the like is arranged.

  A CPU, an ASIC, and the like are supplied with a power supply voltage from a power supply unit provided in the electronic device, and operate based on a clock signal generated by a clock generation circuit.

  2. Description of the Related Art Conventionally, when processing is not performed in an electronic device for a certain period of time, a transition is made to a power saving mode and power supply to peripheral portions such as a hard disk and a print engine is stopped.

Further, in Patent Document 1, in order to further reduce power consumption, in the power saving mode, the frequency of the clock signal supplied to a portion where power supply cannot be stopped can be lowered to a value lower than normal. Are listed.
JP 2003-84858 A

  Patent Document 1 focuses on reducing the frequency of a clock signal supplied to a portion where power supply cannot be stopped, but in recent years, further power saving has been demanded. Further reduction of power consumption in the power saving mode is desired.

  An object of the present invention is to reduce power consumption in a power saving mode in an electronic device including a circuit which is supplied with a power supply voltage and operates based on a clock signal.

In order to solve the above problems, according to the present invention,
An electronic device including a power supply unit, a clock signal generation unit, an arithmetic processing circuit including an arithmetic processing core unit, and a power saving control unit that controls transition processing between a normal mode and a power saving mode,
The power saving control unit enables a clock frequency down signal for the clock signal generation unit at the time of transition to a power saving mode, and after a first time has passed, enables a voltage down signal for the power supply unit,
When the clock frequency down signal becomes valid, the clock signal generation unit gradually changes the frequency of the clock supplied to the arithmetic processing circuit from a first frequency to a second frequency lower than the first frequency,
When the voltage down signal becomes valid, the power supply unit drops the voltage supplied to the arithmetic processing core unit of the arithmetic processing circuit from the first voltage to a second voltage lower than the first voltage. Is provided.

  In the present invention, in the power saving mode, in addition to lowering the clock frequency, the voltage supplied to the arithmetic processing core unit is reduced, so that the power consumption in the power saving mode can be reduced.

  Here, it is preferable that the first time is longer than the time for the clock signal generator to change the clock signal from the first frequency to the second frequency.

  By reducing the supply voltage after the clock frequency has been reliably reduced, it is possible to prevent the arithmetic processing core unit from malfunctioning when shifting to the power saving mode.

The power saving control unit invalidates the voltage down signal for the power supply unit upon returning to the normal mode, and invalidates the clock frequency down signal for the clock signal generation unit after a second time has elapsed. ,
When the clock frequency down signal becomes invalid, the clock signal generation unit gradually changes the frequency of the clock supplied to the arithmetic processing circuit from a second frequency to a higher first frequency,
When the voltage down signal becomes invalid, the power supply unit can increase the voltage supplied to the arithmetic processing core unit of the arithmetic processing circuit from the second voltage to a higher first voltage.

  Thereby, it is possible to return to the normal mode.

  Here, it is desirable that the second time is longer than a time during which the voltage supplied from the power supply unit to the arithmetic processing core unit of the arithmetic processing circuit is changed from the second voltage to the first voltage.

  By returning the clock frequency after the supply voltage has been reliably recovered, it is possible to prevent malfunction of the arithmetic processing core unit when returning to the normal mode.

  Embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a block diagram showing a configuration of a printing apparatus to which the present invention is applied. However, the present invention is not limited to a printing apparatus, and can be widely applied to electronic devices in general.

  As shown in the figure, the printing apparatus 100 includes a CPU 10, a data transfer control circuit (ASIC) 20, a clock generation circuit 30, a ROM 40, an SDRAM 45, a power supply unit 50, an operation panel control unit 60, an EEPEOM 70, a USB I / F 80, printing. An engine 90 is provided. The CPU 10, the ASIC 20, the clock generation circuit 30, the ROM 40, the SDRAM 45, and the EEPEOM 70 are arranged on the controller board.

  The CPU 10 is a control circuit that integrally controls each unit in the printing apparatus 100. The CPU 10 has a CPU core 11 that mainly performs arithmetic processing. Portions other than the CPU core 11 of the CPU 10 perform interface processing for returning from the power saving mode.

  The ASIC 20 is connected to the ROM 40, the SDRAM 45, the operation panel control unit 60, the EEPROM 70, the USB I / F 80, and the print engine 90, and stores the print data transmitted from the host PC via the USB I / F 80 in the SDRAM 45. Also, a process of transferring the image data developed on the SDRAM 45 to the print engine 90 is performed.

  Here, the operation panel control unit 60 is a circuit that performs display control of an operation panel provided in the printing apparatus, operation input control from a user, and the like. The EEPROM 70 is a non-volatile memory that records operating conditions of the printing apparatus 100 set by the user, usage status information of the printing apparatus 100, and the like. The USB I / F 80 is a circuit for receiving print data from a host PC connected by a USB cable. The print engine 90 is a unit that actually performs printing on paper.

  The ASIC 20 includes an ASIC core 22 that mainly performs data transfer processing, and a power saving control unit 21 that performs power saving control processing of the printing apparatus 100. The power saving control unit 21 includes a counter 21 a that is used when shifting to the power saving mode and when returning to the normal mode. The counter 21a can be realized in software or hardware. Details of the power saving control process performed by the power saving control unit 21 will be described later. The power saving control unit 21 may be included in the CPU 10.

  Further, the ASIC 20 supplies the power supply voltage supplied from the power supply unit 50 to the ROM 40, SDRAM 45, operation panel control unit 60, EEPROM 70, and USB I / F 80.

  Here, the voltage that the power supply unit 50 supplies to the CPU 10 and the ASIC 20 will be described.

  In the present embodiment, the power supply unit 50 supplies the CPU 10 with a core power supply voltage and a 3.3V voltage that is always ON. The core power supply voltage is 1.3 V in the normal mode. The core power supply voltage is supplied to the CPU core 11, and the always-on 3.3 voltage is supplied to a portion of the CPU 10 other than the CPU core 11.

  In this embodiment, the core power supply voltage is lowered to 1.25 V in the power saving mode. Thereby, the power consumption in the power saving mode in the CPU core 11 can be reduced.

  Further, the power supply unit 50 supplies the ASIC 20 with a core power supply voltage, a 3.3 voltage that is always ON, and a 3.3 V voltage that is controlled to be turned ON / OFF. The core power supply voltage is 1.3 V in the normal mode. The core power supply voltage is supplied to the ASIC core 22, and the always-on 3.3 voltage is supplied to a portion other than the ASIC core 22 of the ASIC 20.

  As described above, the core power supply voltage is lowered to 1.25 V in the power saving mode. Thereby, the power consumption in the power saving mode in the ASIC core 22 can be reduced.

  The 3.3V voltage for which ON / OFF is controlled is a voltage at which power supply from the power supply unit 50 is stopped in the power saving mode. This voltage is supplied from the power supply unit 50 to the ASIC 20, but is not used by the ASIC 20 itself, but is supplied from the ASIC 20 to the ROM 40 and the SDRAM 45. That is, voltage supply to the ROM 40 and the SDRAM 45 is stopped in the power saving mode. The power supply unit 50 may directly supply a voltage to the ROM 40 and the SDRAM 45 without using the ASIC 20.

  On the other hand, a 3.3V voltage that is always ON is supplied to the operation panel control unit 60, the EEPROM 70, and the USB I / F 80 via the ASIC 20. The operation panel controller 60 and the USB I / F 80 are supplied with a constantly ON voltage in order to accept an operation on the operation panel from the user that triggers a return from the power saving mode and a print instruction from the host PC. ing. Further, the EEPROM 70 is used for recording data at the time of shifting to the power saving mode, and whether the power saving mode is set based on the recorded data (whether the supply voltage is lowered or the clock frequency is lowered). Since it is used for determination, a voltage that is always ON is supplied.

  The power saving control unit 21 of the ASIC 20 shifts the printing apparatus 100 to the power saving mode when a predetermined condition is satisfied, for example, when the printing apparatus 100 does not perform processing for a certain period. At this time, the core power supply voltage of 1.3 V supplied from the power supply unit 50 to the CPU 10 and the ASIC 20 is lowered to 1.25 V, and the 3.3 V voltage for controlling ON / OFF supplied to the ASIC 20 is stopped. Specifically, the core voltage / 3.3 V voltage down control signal, which is a control signal line for the power supply unit 50, is validated.

  When the core voltage / 3.3 V voltage down control signal becomes valid, the power supply unit 50 sets the core power supply voltage to 1.25 V and stops the 3.3 V voltage to be controlled ON / OFF. The voltage transition may be performed in one step or a plurality of steps, or may be continuously changed.

  The clock generation circuit 30 includes a transmission circuit 31 and a frequency control circuit 32. The clock generation circuit 30 generates a clock signal and supplies it to the CPU 10, the ASIC 20, and the SRRAM 45. The transmission circuit 31 is a circuit that uses a crystal resonator and outputs a predetermined frequency signal. The frequency control circuit 32 outputs a 100 MHz clock signal or a 66 MHz clock signal based on the predetermined frequency signal output from the transmission circuit 31 and the frequency down control signal from the ASIC 20.

  The 100 MHz clock signal is output in the normal mode of the printing apparatus 100, and the 66 MHz clock signal is output in the power saving mode of the printing apparatus 100. That is, the power saving control unit 21 of the ASIC 20 invalidates the frequency down control signal in the normal mode and validates the frequency down control signal in the power saving mode.

  In the transition from the normal mode to the power saving mode, if the clock frequency is lowered from 100 MHz to 66 MHz all at once, the CPU 10, the ASIC 20, etc. may not be able to follow. For this reason, in this embodiment, the frequency is gradually lowered. For example, although 100 MHz has a period of 10 ns, the period is increased from 10 ns to 10 ps at a time, and it takes about 5 μs to finally shift to 66 MHz of one period 15 ns.

  In addition, the frequency is gradually increased when returning from the power saving mode to the normal mode. That is, the period is shortened by 10 ps from 15 ns, and a time of about 5 μs is taken, and finally, the period is shifted to 100 MHz of 10 ns.

  Next, processing of the power saving control unit 21 at the time of transition from the normal mode to the power saving mode will be described with reference to the flowchart of FIG.

  When the power is turned on, the printing process, etc., the printing apparatus 100 operates in the normal mode (S101). In the normal mode, both the core voltage / 3.3 V voltage down control signal and the frequency down control signal are disabled.

  Therefore, in the normal mode, the power supply unit 50 supplies 1.3 V as the core power supply voltage for the CPU 10 and the ASIC 20, and the 3.3 V voltage for which ON / OFF is controlled for the ASIC 20 supplies 3.3 V in the ON state. . The clock generation circuit 30 supplies a 100 MHz clock signal to the CPU 10, the ASIC 20, and the SDRAM 45. As a result, the CPU 10, the ASIC 20, the ROM 40, and the SDRAM 45 perform normal operations.

  After that, when the condition for shifting to the power saving mode is satisfied, for example, when the standby state continues for a certain time (S102: Y), the power saving control unit 21 shifts to the power saving mode as described below. Perform processing.

  In the transition process to the power saving mode, first, the power saving control unit 21 of the ASIC 20 validates the frequency down control signal to the clock generation circuit 30 (S103). As a result, the frequency control circuit 32 of the clock generation circuit 30 gradually reduces the clock frequency to 66 MHz. When the transition to 66 MHz is completed, for example, the fact that the transition has been completed is recorded in the EEPROM 70.

  Further, the power saving control unit 21 of the ASIC 20 starts counting by the internal counter 21a at the same time that the frequency down control signal is validated. The internal counter 21a counts, for example, a first count time that takes into account the time required to lower the clock frequency from 100 MHz to 66 MHz and the time to stabilize at 66 MHz. The first count time is determined in advance.

  When the counter 21a counts up the first count time (S104: Y), the power saving control unit 21 of the ASIC 20 enables the core voltage / 3.3V voltage down control signal for the power supply unit 50 (S105). . As a result, the power supply unit 50 reduces the 1.3 V core power supply voltage supplied to the CPU core 11 and the ASIC core 22 to 1.25 V, and the ON / OFF supplied to the ROM 40 and the SDRAM 45 via the ASIC 20 is controlled. Stop the 3.3V voltage.

  That is, in the present embodiment, the supply voltage is lowered after the clock frequency is reliably lowered. Thereby, it is possible to prevent malfunctions of the CPU 10, the ASIC 20, the SDRAM 45, and the like when shifting to the power consumption mode.

  When the supply voltage drop is completed, for example, the fact that the voltage drop is completed is recorded in the EEPROM 70.

  Further, the power saving control unit 21 of the ASIC 20 starts counting by the internal counter 21 a at the same time that the core voltage / 3.3 V voltage down control signal is validated. For example, the internal counter 21a counts the second count time in consideration of the time to decrease the core power supply voltage to 1.25V and stop the 3.3V voltage for which ON / OFF is controlled. This second count time can be determined in advance.

  When the counter 21a counts up the second count time (S106: Y), the printing apparatus 100 operates in the power saving mode (S107).

  In the power saving mode, the power supply unit 50 supplies 1.25V as the core power supply voltage to the CPU 10 and the ASIC 20, and the 3.3V voltage for controlling ON / OFF to the ASIC 20 is turned off and the supply is stopped. The clock generation circuit 30 supplies a 66 MHz clock to the CPU 10, ASIC 20, and SDRAM 45.

  FIG. 3 is a timing diagram showing changes in internal signals in the transition process from the normal mode to the power saving mode.

  This figure shows changes in the clock signal, the frequency down control signal, the core voltage / 3.3 V voltage down control signal, the core power supply voltage, and the 3.3 V voltage to be controlled ON / OFF. Further, the state of the counter 21a and the change of the power mode are also shown for reference.

  In the normal mode, the frequency down control signal and the core voltage / 3.3 V voltage down control signal are invalid. As a result, the clock signal operates at 100 MHz, the core power supply voltage is 1.3 V, and the 3.3 V voltage whose ON / OFF is controlled operates at 3.3 V.

  At t1, the transition condition to the power saving mode is satisfied, and the transition period to the power saving mode is entered. First, the frequency down control signal becomes valid, and the counter 21a starts counting the first count time.

  As a result of the frequency down control signal becoming effective, the frequency of the clock signal gradually decreases and shifts to 66 MHz at t2.

  When the counter 21a counts up the first count time at t3, the core voltage / 3.3V voltage down control signal becomes valid, and the counter 21a starts counting the second count time.

  As a result of the core voltage / 3.3 V voltage down control signal becoming effective, the core power supply voltage shifts to 1.25 V, and the 3.3 V voltage to be controlled ON / OFF shifts to 0 V.

  When the counter 21a counts up the second count time at t4, the transition to the power saving mode is completed.

  Next, processing of the power saving control unit 21 at the time of returning to the normal mode from the transition to the power saving mode or the power saving mode will be described with reference to the flowchart of FIG. Note that the return to the normal mode from the transition to the power saving mode is when the request for the return to the normal mode occurs during the transition to the power saving mode, that is, before the transition to the power saving mode is completed. .

  At the time of shifting to the power saving mode or the power saving mode (S201), when a request for returning to the normal mode, for example, an operation on the operation panel from the user or a print instruction from the host PC is received (S202: Y), First, it is determined whether or not the core power supply voltage is lowered to 1.25 V (S203). This can be determined by referring to the EEPROM 70, for example.

  As a result, when the core power supply voltage is down to 1.25V (S203: Y), the core voltage / 3.3V voltage down control signal is invalidated (S204). As a result, the power supply unit 50 raises the core power supply voltage of 1.25V supplied to the CPU core 11 and the ASIC core 22 to 1.3V, and ON / OFF supplied to the ROM 40 and the SDRAM 45 via the ASIC 20 is controlled. Increase 3.3V voltage to 3.3V. When the increase of the supply voltage is completed, for example, the fact that the voltage increase is completed is recorded in the EEPROM 70.

  In addition, the power saving control unit 21 of the ASIC 20 invalidates the core voltage / 3.3 V voltage down control signal, and at the same time, starts counting by the internal counter 21 a. For example, the internal counter 21a raises the core power supply voltage to 1.3V, and the third count time considering the time to raise the 3.3V voltage, which is controlled to be stopped ON / OFF, to 3.3V. Shall be counted. The third count time is determined in advance. Note that the same value as the second count time may be used. Then, it waits for the counter 21a to count up (S205).

  On the other hand, when the core power supply voltage is not lowered to 1.25V (S203: N), that is, when a return request is made before the core power supply voltage is lowered, the core voltage power supply is maintained at 1.3V. To do. However, when the core voltage / 3.3 V voltage down control signal is valid, it is invalidated.

  When the core power supply voltage is not lowered to 1.25 V (S203: N), or when the counter 21a is incremented (S205: Y), it is determined whether or not the clock frequency is lowered to 66 MHz (S206). This can be determined by referring to the EEPROM 70, for example.

  As a result, when the clock frequency is down to 66 MHz (S206: Y), the frequency down control signal is invalidated (S207). As a result, the frequency control circuit 32 of the clock generation circuit 30 gradually increases the clock frequency to 100 MHz. When the transition to 100 MHz is completed, for example, the fact that the transition has been completed is recorded in the EEPROM 70.

  In addition, the power saving control unit 21 of the ASIC 20 starts counting by the internal counter 21a at the same time as invalidating the frequency down control signal. The internal counter 21a counts, for example, a fourth count time that takes into account the time required to increase the clock frequency from 66 MHz to 100 MHz and the time required to stabilize at 100 MHz. The fourth count time is determined in advance. Note that the same value as the first count time may be used. Then, it waits for the counter 21a to count up (S208).

  On the other hand, when the clock frequency is not lowered to 66 MHz (S206: N), that is, when a return request is made before the clock frequency is lowered, the clock frequency is maintained at 100 MHz. However, if the clock frequency down control signal is enabled, it is disabled.

  When the clock frequency is not lowered to 66 MHz (S206: N), or when the counter 21a counts up (S208: Y), the return to the normal mode is completed (S209).

  As a result, the power supply unit 50 supplies 1.3 V as the core power supply voltage to the CPU 10 and the ASIC 20, and the 3.3 V voltage for controlling ON / OFF to the ASIC 20 supplies 3.3 V in the ON state. The clock generation circuit 30 supplies a 100 MHz clock to the CPU 10, the ASIC 20, and the SDRAM 45. As a result, the CPU 10, the ASIC 20, the ROM 40, and the SDRAM 45 perform normal operations.

  As described above, in this embodiment, the clock frequency is restored after the supply voltage is reliably restored. As a result, malfunctions of the CPU 10, ASIC 20, SDRAM 45, etc. when returning to the normal mode can be prevented.

  In general, the power consumption of an integrated circuit is proportional to the square of voltage × clock frequency × capacitance (+ leakage current when active). For example, when the clock frequency is lowered from 100 MHz to 66 MHz without changing the voltage, the power consumption is reduced by 34%. On the other hand, when the voltage is decreased from 1.3 V to 1.25 V without changing the clock frequency, the power consumption is reduced by 7.5%. In the present embodiment, since both are used, about 40% of power consumption can be reduced.

  In addition, 100 MHz and 66 MHz used as the frequency of the clock signal are examples, and are not limited to these values. In addition, 1.3 V and 1.25 V used as the core power supply voltage and 3.3 V used as the supply voltage are examples, and are not limited to these values.

FIG. 2 is a block diagram illustrating a configuration of a printing apparatus. The flowchart explaining the process of the power saving control part at the time of transfer to power saving mode. The timing diagram which shows the change of the internal signal at the time of transfer to power saving mode. The flowchart explaining the process of the power saving control part at the time of return to normal mode.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... CPU, 11 ... CPU core, 20 ... ASIC, 21 ... Power saving control part, 22 ... ASIC core, 30 ... Clock generation circuit, 31 ... Transmission circuit, 32 ... Frequency control circuit, 40 ... ROM, 45 ... SDRAM, DESCRIPTION OF SYMBOLS 50 ... Power supply unit, 60 ... Operation panel control part, 70 ... EEPROM, 80 ... USB I / F, 90 ... Print engine, 100 ... Printing apparatus

Claims (8)

An electronic device including a power supply unit, a clock signal generation unit, an arithmetic processing circuit including an arithmetic processing core unit, and a power saving control unit that controls transition processing between a normal mode and a power saving mode,
The power saving control unit enables a clock frequency down signal for the clock signal generation unit at the time of transition to a power saving mode, and after a first time has passed, enables a voltage down signal for the power supply unit,
When the clock frequency down signal becomes valid, the clock signal generation unit gradually changes the frequency of the clock supplied to the arithmetic processing circuit from a first frequency to a second frequency lower than the first frequency,
When the voltage down signal becomes valid, the power supply unit drops the voltage supplied to the arithmetic processing core unit of the arithmetic processing circuit from the first voltage to a second voltage lower than the first voltage. . The electronic device according to claim 1,
The electronic apparatus according to claim 1, wherein the first time is longer than a time during which the clock signal generator changes the clock signal from the first frequency to the second frequency. The electronic device according to claim 1,
A storage device to which a clock is supplied from the clock signal generator;
The power supply unit stops the voltage supplied to the storage device when the voltage down signal becomes valid. The electronic device according to claim 1,
A data transfer control circuit including a data transfer core unit;
When the clock frequency down signal becomes valid, the clock signal generation unit gradually changes the frequency of the clock supplied to the data transfer control circuit from a first frequency to a second frequency lower than the first frequency,
The power supply unit drops the voltage supplied to the data transfer core unit of the data transfer control circuit from the first voltage to a lower second voltage when the voltage down signal becomes valid. machine. The electronic device according to claim 1,
The power saving control unit invalidates the voltage down signal for the power supply unit upon returning to the normal mode, and after the second time has elapsed, invalidates the clock frequency down signal for the clock signal generation unit,
When the clock frequency down signal becomes invalid, the clock signal generation unit gradually changes the frequency of the clock supplied to the arithmetic processing circuit from a second frequency to a higher first frequency,
The power supply unit increases the voltage supplied to the arithmetic processing core unit of the arithmetic processing circuit from the second voltage to a higher first voltage when the voltage down signal becomes invalid. . The electronic device according to claim 5,
The electronic apparatus according to claim 1, wherein the second time is longer than a time during which the voltage supplied from the power supply unit to the arithmetic processing core unit of the arithmetic processing circuit is changed from the second voltage to the first voltage. The electronic device according to claim 5,
A storage device to which a clock is supplied from the clock signal generator;
The electronic apparatus according to claim 1, wherein the power supply unit resumes voltage supply to the storage device when the voltage down signal becomes invalid. The electronic device according to claim 5,
A data transfer control circuit including a data transfer core unit;
When the clock frequency down signal becomes invalid, the clock signal generation unit gradually changes the frequency of the clock supplied to the data transfer control circuit from a second frequency to a higher first frequency,
The power supply unit increases a voltage supplied to a data transfer core unit of the data transfer control circuit from a second voltage to a higher first voltage when the voltage down signal becomes invalid. machine.

Images