JP2008103875A - Synthetic d/a converter and magnetic resonance imaging device by it - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a D/A converter holding down a cost, being operated at a high speed and having a high accuracy and a high resolution by using the D/A converter obtaining high speed operation at a low cost and having the small number of bits. <P>SOLUTION: The D/A converter has a first D/A converter inputting N1 bits of N bits digital data N from an MSB to the LSB side and an accuracy compensating-value memory storing preset digital compensating values NcN to each of the digital data N while using the digital data N of the N bits as an address and outputting the digital compensating values NcN at least N2=(N-N1+2) bits corresponding to the digital data N by inputting the digital data N. The D/A converter further has a second D/A converter at N2 bits connected to an output from the accuracy compensating-value memory and an amplifier amplifying the output from the first D/A converter at an amplification factor of 2<SP>(N-N1)</SP>. The D/A converter further has an adder adding the output from the amplifier and the output from the second D/A converter. A synthetic D/A converter uses the result of the output from the adder as the analog converting value of the digital input data N. A magnetic resonance imaging device consists of the synthetic D/A converter. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a gradient magnetic field power supply device that drives a gradient magnetic field coil of a magnetic resonance imaging apparatus (MRI apparatus), and in particular, a high-precision, high-resolution D / A (digital / analog) converter that constitutes this power supply. Regarding technology.

  In a magnetic resonance imaging apparatus (MRI apparatus), for example, a static magnetic field magnet or a static magnetic field coil that generates a static magnetic field, a gradient magnetic field coil for generating a gradient magnetic field superimposed on the static magnetic field, and a high-frequency magnetic field are generated. A high-frequency coil and an applied current at which these magnetic field generating coils have a predetermined magnetic field intensity and a coil drive power supply device that controls the timing are provided. Furthermore, since the strength of the magnetic field and the temporal stability of these coils influence the image quality of the obtained image, control by a digital value is generally performed (see, for example, Patent Document 1 and Patent Document 2). In particular, in driving a gradient magnetic field coil, it is required to control a large current with high accuracy, for example, with accuracy of about 0/00 (per mill). The excitation current converted into an analog value by the amplifier and amplified through the current amplifier is applied to the coil.

  As for D / A converters (conversion circuits) that convert digital values into analog values, conventionally, D / A converters of 16 bits or less and low bits and relatively high speeds are offered to the market. It is generally popular.

  On the other hand, with the advancement of industrial technology, the need for multi-bit D / A converters has increased. For example, as described above, high-precision, high-resolution D / A conversion is possible when driving a gradient coil of a medical MRI diagnostic apparatus. It is required to operate the vessel with high stability and high speed. Such a multi-bit high-precision, high-resolution D / A converter can realize a high-speed, high-resolution D / A converter with an extension of the conventional technology in terms of circuit configuration, but the selection of performance Advanced technology is required for adjusting the characteristics and characteristics, and as a result, it is very expensive, and its use is limited for general consumer use.

  High-speed, high-resolution D / A conversion function that converts higher-order data to analog and D / A conversion function that converts lower-order data to analog as a technology to realize a multi-bit D / A converter at low cost The small bit D / A converters are shared and realized in combination (for example, see Patent Document 3 and Patent Document 4). Even in these cases, there is a limit to speeding up the full bit conversion by operating the delay circuit and the latch means.

Also, since the D / A converter basically guarantees only the accuracy of 1/2 LSB, the linearity of the analog output result cannot achieve the desired resolution due to the accumulation of these errors. For example, as shown in FIG. 7 (a), an 8-bit digital data input signal D is shared by an upper 4-bit D / A converter A71 and a lower 4-bit A / D converter B72. Then, the output of the higher order D / A converter A71 is amplified to a voltage corresponding to the higher order bit output by the amplifier 73 and added to the output of the lower order A / D converter B72 by the adder 74. It also occurs in a typical configuration that operates as a D / A converter C75. The analog output value should be an ideal D / A output value 81 so that a part of the analog output value is enlarged and displayed in FIG. 7B, and conversion output error portions 82a, 82b for each upper bit, and In stepped output including lower / upper D / A conversion output error 83, the output characteristic (actual D / A output value) 81a is a result of conversion with irregularities, resulting in reduced output linearity. There is also a problem.
JP-A-5-3863. Japanese Patent Application Laid-Open No. 11-318855. Japanese Patent Laid-Open No. Hei 8-195567. Japanese Patent Laid-Open No. 4-68820.

  The problem to be solved is that, in order to obtain an MRI apparatus with improved image quality performance, a high-speed, high-resolution D / A converter, which is an extension of the prior art, is used in the drive power source of the gradient magnetic field coil. The higher the resolution, the more the cost increases, and the higher the cost of the device itself. In addition, since the D / A converter basically guarantees only an accuracy of 1/2 LSB, when a plurality of low-cost low-bit D / A converters are combined, the linearity of the output result due to variations in performance characteristics And the desired resolution and accuracy cannot be achieved.

  The present invention has been made in view of the above-described conventional problems, and generally uses a small-bit D / A converter that is inexpensive and capable of high-speed operation. An object of the present invention is to provide a magnetic resonance imaging apparatus which provides a D / A converter at a reduced cost, and includes this high-accuracy and high-resolution D / A converter to improve the image quality of MRI.

In order to achieve the above object, a composite D / A converter according to claim 1 of the present invention is a first D / A converter in which N1 bit is inputted from MSB to LSB side of N-bit digital data N; A preset digital compensation value NcN for each of the digital data N is stored with the N-bit digital data N as an address, and at least N2 = (N−N1 + 2) corresponding to the input of the digital data N ) An accuracy compensation value memory for outputting this digital compensation value NcN of bits, an N2-bit second D / A converter connected to the output of the accuracy compensation value memory, and an output of the first D / A converter 2 ^(N−N1) and an adder that adds the output of the amplifier and the output of the second D / A converter, and outputs the output result of the adder. Provided is an analog conversion value of digital input data N.

Furthermore, in the composite D / A converter according to claim 2 of the present invention, the digital compensation value NcN is inputted with N-bit digital data N, and is a reference D / D that performs high-precision, high-resolution quantization analog conversion. With respect to the A converter and the conversion reference value output from the reference D / A converter, an output of the first D / A converter to be compensated for the digital data N is amplified by the amplifier with an amplification factor 2 ^{(N− N1)} , a subtracter for subtracting the output of the adder for adding the amplification result and the output of the second D / A converter as a zero value, and the output of the subtractor are input. The compensation value A / D converter that outputs the digital compensation value NcN, the N2 bit digital compensation value NcN output from the compensation value A / D converter, the digital data N of the accuracy compensation value memory as the memory address, You Compensation value generating / writing means comprising a data writing means for recording in a recording area to be generated and recorded for each digital value of the input data N is provided. .

  In order to achieve the above object, a magnetic resonance imaging apparatus according to claim 3 of the present invention is adapted to generate a magnetic resonance signal from a subject radiated by a gradient magnetic field generated by a gradient magnetic field coil driven by a gradient magnetic field coil power supply unit. A magnetic resonance imaging apparatus for reconstructing an image of the subject based on the gradient magnetic field coil power supply unit, a gradient magnetic field data generation unit controlled by a control computer unit for generating digital time sequence data; The combined D / A converter that converts the digital time sequence data into a quantized analog value by including the accuracy compensation value memory, and a current that amplifies the quantized analog value to a level that is an excitation current of the gradient coil. An amplifier is provided.

  Furthermore, in the magnetic resonance imaging apparatus according to claim 4 of the present invention, the combined D / A converter of the gradient coil power supply unit generates the combined D / A by the accuracy compensation value memory generated and recorded by the compensation value generation / writing means. What is provided with the A converter is provided.

  According to the present invention, since a plurality of low-cost and high-speed D / A converters are combined to perform conversion based on preset accuracy compensation data, multi-bit high-resolution that operates at high speed and high accuracy. The D / A converter can be provided at low cost. In addition, the magnetic resonance imaging apparatus that drives the magnetic field coil by the multi-bit high-resolution D / A converter that operates at high speed and with high accuracy can capture MRI images at high speed and with high resolution.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 5 is a diagram showing a configuration of a magnetic resonance imaging apparatus (MRI apparatus) according to the present embodiment. The MRI apparatus shown in FIG. 5 includes a static magnetic field magnet 51, a gradient magnetic field coil 52, a gradient magnetic field coil drive power supply unit 53, a bed 54, a bed control unit 55, RF coil units 56a, 56b and 56c, a transmission unit 57, and a selection circuit. 58, a receiving unit 59, a control computer unit 61, a storage unit 62, an input unit 64, and a display unit 63 connected to the control computer unit 61. The gradient coil drive power supply unit 53 is a gradient magnetic field data generation unit 53c that generates digital information related to the drive of the gradient magnetic field coil 52 in response to an instruction from the control computer unit 61, and a D / A that converts this digital information into an analog value. The converter 53b includes a current amplifier 53a that converts the analog value into an excitation current of the gradient magnetic field coil 52.

  The static magnetic field magnet 51 has a hollow cylindrical shape and generates a uniform static magnetic field in the internal space. For example, a permanent magnet or a superconducting magnet is used as the static magnetic field magnet 51.

  The gradient coil 52 has a hollow cylindrical shape and is disposed inside the static magnetic field magnet 51. The gradient coil 52 is a combination of three types of coils corresponding to the X, Y, and Z axes orthogonal to each other. The gradient coil 52 generates a gradient magnetic field in which the above three types of coils are individually supplied with current from the gradient coil drive power supply unit 53 and the magnetic field strength is inclined along the X, Y, and Z axes. To do. The Z-axis direction is, for example, the same direction as the static magnetic field. The gradient magnetic fields of the X, Y, and Z axes correspond to, for example, the slice selection gradient magnetic field Gs, the phase encoding gradient magnetic field Ge, and the readout gradient magnetic field Gr, respectively. The slice selection gradient magnetic field Gs is used to arbitrarily determine an imaging section. The phase encoding gradient magnetic field Ge is used to change the phase of the magnetic resonance signal in accordance with the spatial position. The readout gradient magnetic field Gr is used for changing the frequency of the magnetic resonance signal in accordance with the spatial position.

  The subject 60 is inserted into the cavity (imaging port) of the gradient magnetic field coil 52 while being placed on the top 54 a of the bed 54. The couch 54 is driven by the couch controller 55 and moves the couchtop 54a in the longitudinal direction (left-right direction in FIG. 5) and up-down direction. Usually, the bed 54 is installed so that the longitudinal direction is parallel to the central axis of the static magnetic field magnet 51.

  The RF coil unit 56a is configured by housing one or more coils in a cylindrical case. The RF coil unit 56 a is disposed inside the gradient magnetic field coil 52. The RF coil unit 56a receives a high frequency pulse (RF pulse) from the transmission unit 57 and generates a high frequency magnetic field.

  The RF coil units 56b and 56c are placed on the top board 54a, built in the top board 54a, or attached to the subject 60. And at the time of imaging | photography, it inserts in the cavity of the gradient magnetic field coil 52 with the subject 60. FIG. Each of the RF coil units 56 b and 56 c uses an array coil including a plurality of element coils, and receives a magnetic resonance signal radiated from the subject 60. The output signals of the element coils are individually input to the selection circuit 58.

  The transmission unit 57 includes an oscillation unit, a phase selection unit, a frequency conversion unit, an amplitude modulation unit, and a high frequency power amplification unit. The oscillation unit generates a high-frequency signal having a resonance frequency unique to the target nucleus in the static magnetic field. The phase selection unit selects the phase of the high-frequency signal. The frequency conversion unit converts the frequency of the high-frequency signal output from the phase selection unit. The amplitude modulation unit modulates the amplitude of the high-frequency signal output from the frequency modulation unit, for example, according to a sync function. The high frequency power amplification unit amplifies the high frequency signal output from the amplitude modulation unit. As a result, the transmission unit 57 supplies an RF pulse corresponding to the Larmor frequency to the RF coil unit 56a.

  The selection circuit 58 selects some of the multiple magnetic resonance signals output from the RF coil units 56b and 56c. Then, the selection circuit 58 gives the selected magnetic resonance signal to the reception unit 59. Which channel is selected is instructed by the control computer unit 61.

  The receiving unit 59 includes a plurality of processing systems including a pre-stage amplifier, a phase detector, and an analog / digital converter. The magnetic resonance signals selected by the selection circuit 58 are input to the processing systems of these multiple channels. The pre-stage amplifier amplifies the magnetic resonance signal. The phase detector detects the phase of the magnetic resonance signal output from the preamplifier. The analog-digital converter converts the signal output from the phase detector into a digital signal. The receiving unit 59 outputs a digital signal obtained by each processing system.

  The control computer unit 61 includes a CPU, a memory, and the like (not shown), and comprehensively controls the MRI apparatus according to the present embodiment, and functions as an interface unit, a data collection unit, a reconstruction unit, and a control unit. It is comprised. The interface unit inputs and outputs signals exchanged between the connected units such as the gradient coil drive power supply unit 53, the bed control unit 55, the transmission unit 57, the reception unit 59, and the selection circuit 58. The data collection unit collects digital signals output from the reception unit 59 and stores the collection result, that is, magnetic resonance signal data, in the storage unit 62. The reconstruction unit performs post-processing, that is, reconstruction such as Fourier transform, on the magnetic resonance signal data stored in the storage unit 62 to obtain spectrum data or image data of a desired nuclear spin in the subject 60. .

  The storage unit 62 stores magnetic resonance signal data and spectrum data or image data for each patient.

  The display unit 63 displays various information such as spectrum data or image data under the control of the control unit of the control computer unit 61. A display device such as a liquid crystal display can be used as the display unit 63.

  The input unit 64 receives various commands and information inputs from the operator. The input unit 64 can appropriately use a pointing device such as a mouse or a trackball, a selection device such as a mode change switch, or an input device such as a keyboard.

  The above is the overall configuration of the MRI apparatus according to the present embodiment. A feature of the present embodiment is that the gradient magnetic field coil drive power supply unit 53 converts multi-bit digital information related to the drive of the gradient magnetic field coil 52 into an analog value related to an excitation current that acquires MRI data at high speed with high image quality. D / A converter 53b. Below, the high-precision and high-speed D / A converter which comprises the gradient coil drive power supply part 53 is demonstrated in detail.

(First embodiment)
FIG. 1A is a functional circuit block diagram showing a configuration of a D / A converter to which N-bit digital data is input according to the present embodiment. FIG. 5B is a block diagram showing a configuration of a compensation data setting device that creates compensation value data of an accuracy compensation value memory provided in the D / A converter of the present embodiment.

  The details of the configuration of the D / A converter of this embodiment are shown in FIG. 1A or the detailed circuit configuration of FIG. 2, as shown in FIG. The first D / A converter 11 (111) to which N1 bit is input, the amplifier 13 (113) for amplifying the analog voltage after conversion, and the digital signal N having the same input N bit are input, and the preset accuracy is set. An accuracy compensation value memory 15 (115) for outputting the compensation data N2, a second D / A converter 12 (112) to which the accuracy compensation data N2 of this output is input as N2 bit data from the lower LSM, and an amplifier 13 (113) and an adder 14 (114) for adding the output of the second D / A converter 12 (112). In order to distinguish the D / A converter of this embodiment formed by this configuration from the first and second D / A converters 11 and 12 (111 and 112), hereinafter, the combined D / A converter 10 It is called.

  In this configuration, the (2 + n) bits on the LSB side of the corresponding N1 bits of the first D / A converter 11 and the (2 + n) bits on the MSB side of the corresponding N2 bits of the second D / A converter 12 are input N bits. In the middle of the digital signal, 2 + n bits that overlap with at least 2 bits are allocated and allocated (where n is an integer including 0). That is, an allocation that satisfies the relationship N = N1-2−n + N2 (where n is an integer including 0) is allocated to the conversion bits of the first and second D / A converters.

  The accuracy compensation value memory 15 provided in the present embodiment shown in FIG. 1A is stored in the compensation value data by the compensation data setting device 30 whose detailed circuit configuration is shown in FIG. Preset and recorded. The set accuracy compensation value memory 15 (115) is supplied to the second D / A converter 12 (112) in response to the N-bit digital input of the composite D / A converter 10 (110) of the present application. It functions as a data converter that outputs digital compensation data consisting of N2 bits corresponding to the input.

  In the embodiment of the compensation data setting device 30 shown in FIG. 1B or FIG. 3, the input of the high-resolution D / A converter 21 (121) that outputs a high-precision reference value for D / A conversion The connection is the same as the digital input of the composite D / A converter 10 of the present embodiment, which is the target for setting the compensation data in the compensation value memory 15, that is, the digital input data N. The output of the high resolution D / A converter 21 (121) is input to the subtractor 22 (122).

  On the other hand, as shown in FIG. 1B or FIG. 3, the target composite D / A converter sets the output of the second D / A converter 12 (112) to zero without inputting it to the adder 14. , The compensation setting dedicated connection for connecting only the amplification result obtained by amplifying the output of the first D / A converter 11 (111) corresponding to the MSB side bit by the amplifier 13 (113) to the adder 14 (114) The D / A converter 20 is configured. The output of the D / A converter 20 with this compensation setting dedicated connection configuration is input to the subtraction side terminal, which is another input of the subtractor 22 (122).

  Therefore, the output of the subtractor 22 (122) of the compensation data setting device 30 is the quantized analog reference value output from the high-precision high-resolution D / A converter 21 (121) for the N-bit digital input N, and It becomes a difference value from the analog value of the conversion result of the D / A converter 20 of the compensation setting connection, that is, the first D / A converter 11 (111) including the amplification corresponding to the digit of the data. The subtraction result analog value of the subtractor 22 (122) is input to the compensation value A / D converter 23 (123) and converted into N2 bit digital compensation data corresponding to the difference value. Further, a data writer 24 (124) for writing the N2-bit digital compensation data of the conversion result into a predetermined address area related to the digital input N of the accuracy compensation value memory 15 (115) is provided.

  All digital values of all N bits 0 to 1 are sequentially input to the input of the compensation data setting device 30 configured as described above. For each digital value input, a subtracter 22 (122) which is a conversion result difference between the high-precision high-resolution D / A converter 21 (121) and the first D / A converter 11 (111) to be corrected. Is input to the compensation value A / D converter 23 (123), and the output digital data of N2 bits is output as N2 bit compensation value data corresponding to each of the N bit input values. The data writer 24 (124) writes and stores it in the accuracy compensation value memory 15 (115).

  In the following description, N = 6, N1 = N2 = 4, and n = 0 in order to simplify and understand the description, that is, a 6-bit D / A converter is composed of two 4-bit D / A converters. Will be described with reference to FIG. 3 which is configured as the composite D / A converter 10 of the present invention. A part of the list of real examples is illustrated in FIG. 4, and the embodiment will be described with reference to this.

  The compensation value data written to the accuracy compensation value memory 115 by the compensation data setting device 30 with N-bit input is, for example, 6-bit digital data as shown in FIG. N is input to the high-resolution D / A converter 121 of the conversion reference device, and converted into a 64-stage quantized analog value to generate a reference value. That is, each digital value of input N: input digital value 41 in FIG. 4 is sequentially input to the high resolution D / A converter 121 shown in FIG. 1B that outputs the standard value analog value 42 of D / A conversion. Is done. With this input 41, a quantized analog value Na 42 serving as a reference corresponding to the input digital N is output from the high resolution D / A converter 121 and input to the subtractor 122.

  In the example of the real value in FIG. 4, the output of each D / A converter includes an allowable error within 1/2 LSB in the actual machine, but the analog value display example is quantized to avoid complexity. The analog value is used as an example. Further, it is assumed that there is no error in the quantization of the analog value Na42 serving as a reference outputted from the high resolution D / A converter 121, and the error in the conversion of the first D / A converter 111 and the subsequent amplification compared with this reference. Also, in the illustration of FIG.

  On the other hand, an accuracy compensation value memory 115 that is a target for setting compensation data is provided, the connection to input the output of the second D / A converter 112 to the adder 114 is cut off, and the upper bit N1 (4 bits) 43 is supported. Similarly to the high-resolution D / A converter 121, the input of the D / A converter 20 configured by the connection dedicated to the compensation setting that connects only the amplified output of the first D / A converter 111 to the adder 114 is also used. , Input N: digital values of input digital value 41 are sequentially input.

Then, the output of the adder 114 of the D / A converter 20 connected exclusively for compensation setting, that is, the output 43 of the amplifier 113 is input to the subtraction side terminal of the subtractor 122. The first D / A converter 111 receives the MSB side 4 bits 43 of the input N, and the amplifier 113 is set with an amplification factor of 4 (= 2 ² ) times corresponding to the LSB side 2 bits. Therefore, the output of the D / A converter 20 adder 114 connected only for compensation setting, which is not connected to one addition terminal, that is, the subtraction terminal of the subtractor 22 has an N1-bit quantized analog signal for every two LSB changes. The values 44, 0, 4, 8,... 56, 60 are input.

However, the D / A converter generally only compensates for the conversion accuracy of ½ LSM, and when the output of the first D / A converter 111 is amplified, an output of ½ LSB × amplification factor at the maximum. An error occurs, and 0, 4, 8,... 56, 60 of the quantized analog value 44 are analog values each including an error of this conversion. For example, in the case of N = 6, N1 = N2 = 4, and n = 0 exemplified here, an error equal to or less than 1/2 LSB × 2 ² = 2 bits on the N2 bit side is included. For example, in the example of the data in FIG. 4, the error 45 of the analog output value is indicated by the count value n by the analog value of the quantization unit corresponding to the LSB data 1 of the D / A converter 10. The A output value 46 in the figure is the output of the adder 14, that is, the input to the subtraction terminal. In the high-precision D / A converter 121, the data value shown in the column of the quantized analog value 44 in FIG. 4 should be the same, but the conversion accuracy of the D / A converter 111 and the accuracy caused by the amplification are lowered as it is. As a result, the result as shown in the column of the A output value 46 in the figure is obtained, and the D / A converter 20 is inferior in accuracy in linearity and resolution.

  The subtraction result output 47 of the subtracter 122 outputs the difference between the conversion reference value and the D / A conversion value including these higher-order conversion errors, so that an analog value including these corrections is output. Is done.

  The analog value output from the subtractor 122 is input to the A / D converter 123 that outputs N2 bits having the same number of bits as the input to the second D / A converter 112, for example, 4 bits in this example. .

  For the digital value 48 output from the A / D converter 123, the data writer 124 uses, for example, the input digital value 41 of the accuracy compensation value memory 15 as a predetermined memory address for each digital value of N-bit input. Write as compensation data in the area, store and save. All digital values of all N bits from 0 to 1 are written sequentially, and the compensation data 48 for all input digital values is completed in the accuracy compensation value memory 15.

  The D / A converter 10 (110) of the present embodiment shown in FIG. 1A or FIG. 2 which is a detailed circuit configuration diagram is paired with the first D / A converter 11 (111). Then, the compensation data is written by the compensation data setting device 30 described above and combined with the accuracy compensation value memory 15 (115), and the second D / A converter 12 (112) is further added, and the output is added to the adder 14 ( 114).

  Details of the operation and operation of the D / A converter 110 (10) of this embodiment will be described with reference to FIG. That is, similarly to the description of the compensation data setting device 30 described above, the input N is 6 bits (D0 to D5), and the first and second D / A converters 111 and 112 (11 and 12) are each 4 bits. A more specific circuit configuration including an input D / A converter will be exemplified. The accuracy compensation value memory 115 in this example forms a pair with the first D / A converter 111 by connecting the compensation data setting device shown in FIG. 4 bits of the accuracy compensation data is written and set in advance.

  Upper (MSB) 4 (N1) -bit data D2, D3, D4, and D5 of the digital input N are input to the first D / A converter 111, and the converted quantized analog value is converted to the first D / A converter 111. Is output from. This output includes an error equal to or less than 1/2 LSM of the D / A converter which is allowed as a range of accuracy guarantee of the first D / A converter 111. This conversion result is input to the amplifier 113, amplified by an amplification factor of 4 corresponding to the lower 2 bits not converted by the first D / A converter 111, and the output is input to the adder 114.

  On the other hand, all the bit data D0, D1, D2, D3, D4, D5 of the digital input N consisting of 6 bits are input to the accuracy compensation value memory 115, for example, the bit data D0, D1, D2, D3, The accuracy compensation value memory 115 is operated using D4 and D5 as data search destination addresses, and 4-bit accuracy compensation data written in advance at the corresponding address is read out and input to the second D / A converter 112. The

  The 4 (N2) -bit data inputted to the second D / A converter 112 is inputted N-bit data D0, D1, D2, D3, D4, D5 by connecting the compensation data setting device described above. Digital data of a difference value between a reference quantized analog value by the high-precision D / A converter and a conversion result value of the first D / A converter 111. Therefore, the quantized analog output of the second D / A converter 112 is an unconverted value of the first D / A converter 111 with respect to the reference conversion value of the N-bit data D0, D1, D2, D3, D4, D5. It becomes a quantized analog value to be supplemented. In this supplement, guarantee data including data for correcting a reduction in guarantee accuracy by the amplifier 113 is generated as a result value of the D / A conversion.

  The output of the second D / A converter 112 is input to the adder 114 together with the output of the amplifier 113. The output of the adder 114 is the high-resolution D / A of the above-described compensation data setting device used as a reference for the conversion output. An analog value corresponding to the quantized analog output value of the converter 21 is output, and a high-precision and high-resolution D / A converter can be provided throughout the 6-bit D / A converter 10.

  According to the present embodiment, the compensation data setting device stores, in the accuracy compensation value memory, correction data of the LSB side D / A conversion value with respect to the reference conversion value by the reference D / A converter with high resolution and high accuracy in advance. Records are saved. When digital data to be converted is input, the D / A converter that converts the LSB side outputs an analog value corresponding to the correction data, and is added to the output of the D / A converter on the MSB side. A conversion analog value that is the same value as the output of the reference D / A converter can be output, and it can be configured by a low-speed, low-speed D / A converter, so that it can be operated at high speed, high resolution, and high accuracy. A multi-bit D / A converter can be provided at a low cost.

(Second Embodiment)
FIG. 6 is a block diagram showing a configuration of the gradient coil drive power supply unit 53 of the magnetic resonance imaging apparatus (MRI apparatus) shown in FIG. 5 according to the second embodiment of the present invention. The D / A converter 53b of the gradient coil drive power supply unit 53 of the magnetic resonance imaging apparatus according to this embodiment is the same as the D / A converter 10 shown in FIG. 1A according to the first embodiment described above. Composed. In the accuracy compensation value memory 15 of the D / A converter 53b mounted in the MRI apparatus of this embodiment, the compensation value data is previously set and recorded by the compensation data setting device 30 shown in FIG. It is a thing.

  In the gradient magnetic field coil drive power supply unit 53 mounted on the MRI apparatus of this embodiment, as shown in FIG. 6, information on the gradient magnetic field formed corresponding to the X, Y, and Z axes from the control computer unit 61. Are first input to the gradient magnetic field data generation unit 53c. In this gradient magnetic field data generation unit 53c, a time sequence of digital data of a magnetic field that is inclined along each of the X, Y, and Z axes is generated based on the input information, and the digital data is converted into D for each axis. / A converter 53b (10) respectively. In FIG. 6, for example, the data input to the D / A converter 53b (10) is 20 bits, and this is input to the 12-bit first and second D / A converters 11 and 12, and the 20-bit input. In the case of conversion to an analog value by the accuracy compensation value memory 15, the number of digital lines (bits) and the analog lines are exemplified by [A].

  For example, 12 bits on the MSB side of the digital data input to the D / A converter 53b (10) are input to the first D / A converter 11, and all 20 bits of the input digital data are input to the accuracy compensation value memory 15. Entered.

The converted analog value of 12 bits on the MSB side of the digital data output from the first D / A converter 11 corresponds to the number of bits shared by the second D / A converter 12, for example, 8 bits in the example of FIG. Therefore, the amplification factor is input to the amplifier 13 with 2 ⁸ = 256, and the output is input to the adder 14.

  On the other hand, the accuracy compensation value memory 15 to which 20-bit digital data is input reads 12-bit accuracy compensation data corresponding to the input, and the accuracy compensation data is converted into the 12-bit second D / A converter 12. The analog value of the conversion result by the second D / A converter 12 is input to the other addition terminal of the adder 14.

  The addition result of the two analog values by the adder 14 is input to the current amplifier 53a and amplified to a current value level corresponding to the excitation current of the gradient magnetic field coil 52. Supplied as a magnetic field coil 52).

  According to the present embodiment, the drive power source of the gradient magnetic field coil of the magnetic resonance imaging apparatus (MRI apparatus) is paired with a plurality of low-bit input D / A converters and a set of the D / A converters operating at high speed. Equipped with a D / A converter that converts multi-bits composed of an accuracy compensation value memory that has previously recorded compensation data into analog values with high accuracy and high speed, so that multi-bit digital data with high resolution and excellent linearity The excitation signal data obtained by the above can be converted into an analog value at high speed and with high accuracy, and the image quality of the resulting MR image can be improved. In addition, since the low-bit D / A converter and the memory that are configured can be obtained at low cost, a magnetic resonance imaging apparatus (MRI apparatus) with reduced cost can be provided.

1 is a functional circuit block diagram showing a configuration of a D / A converter according to a first embodiment of the present application, and a configuration diagram of a compensation data setting device that creates compensation value data of an accuracy compensation value memory included in the present embodiment. The detailed circuit block diagram of the D / A converter of 1st Embodiment of this application. The circuit block diagram of the compensation data setting apparatus which produces the compensation value data of this embodiment. The chart which showed a part of real number example of D / A conversion in this embodiment. The figure which shows the structure of the magnetic resonance imaging apparatus which concerns on 2nd Embodiment of this application. The block diagram of the gradient magnetic field coil drive power supply part which concerns on 2nd Embodiment of this application. The block diagram of the conventional multi-bit D / A converter and the schematic diagram showing its accuracy degradation.

Explanation of symbols

10, 53b ... composite D / A converter,
11, 111 ... 1st D / A converter,
12, 112 ... 2nd D / A converter,
13, 113... Amplifier,
14, 114 ... adders,
15, 115 ... accuracy compensation value memory,
20: D / A converter dedicated for compensation setting,
21, 121... High resolution D / A converter,
22, 122 ... subtractor,
23, 123 ... compensation value A / D converter,
24, 124 ... data writer,
30: Compensation data setting device,
51 ... Static magnetic field magnet,
52 ... Gradient magnetic field coil,
53... Gradient coil drive power supply,
53a ... current amplifier,
53b ... Composite D / A converter,
53c ... Gradient magnetic field data generation 54 ... Sleeper,
54a ... top plate,
55 ... Bed control unit,
56a, 56b, 56c ... RF coil unit,
57... Transmitter
58... Selection circuit,
59... Receiver
60 ... subject,
61 ... Control computer section,
62 ... storage unit,
63 ... display part,
64: Input unit.

Claims (4)

A first D / A converter in which N1 bits are input from the MSB of the N-bit digital data N to the LSB side;
A preset digital compensation value NcN for each of the digital data N is stored with the N-bit digital data N as an address, and at least N2 = (N−N1 + 2) corresponding to the digital data N is input by the input of the digital data N. An accuracy compensation value memory for outputting this digital compensation value NcN of bits;
An N2 bit second D / A converter connected to the output of the accuracy compensation value memory;
An amplifier for amplifying the output of the first D / A converter with an amplification factor of 2 ^(N−N1) ;
An adder for adding the output of the amplifier and the output of the second D / A converter;
A combined D / A converter characterized in that the output result of the adder is an analog conversion value of the digital input data N. The digital compensation value NcN stored in the accuracy compensation value memory is:
A reference D / A converter that receives N-bit digital data N and performs high-precision, high-resolution quantization analog conversion;
With respect to the conversion reference value output from the reference D / A converter, the output of the first D / A converter to be compensated for the digital data N is amplified by the amplifier with an amplification factor of 2 ^(N−N1). A subtracter for subtracting the output of the adder for adding the amplification result and the output of the second D / A converter as a zero value;
A compensation value A / D converter that receives the output of the subtractor and outputs a digital compensation value NcN of N2 bits;
Data writing means for recording the N2-bit digital compensation value NcN output from the compensation value A / D converter in a recording area having the digital data N of the accuracy compensation value memory as a memory address;
2. The combined D / A converter according to claim 1, wherein each of the digital values of the input data N is generated and recorded by a compensation value generating / writing means comprising: A magnetic resonance imaging apparatus for reconstructing an image related to a subject based on a magnetic resonance signal from the subject radiated by a gradient magnetic field generated by a gradient coil driven by a gradient coil power supply unit,
The gradient coil power source is
A gradient magnetic field data generation unit controlled by a control computer unit for generating digital time sequence data;
The combined D / A converter according to claim 1, which converts the digital time sequence data into a quantized analog value.
A current amplifier that amplifies the quantized analog value to a level that is an excitation current of the gradient coil;
A magnetic resonance imaging apparatus comprising: A combined D / A converter that converts the digital time sequence data of the gradient magnetic field coil power supply unit into a quantized analog value,
3. A magnetic resonance imaging apparatus comprising a combined D / A converter that generates and records data in the accuracy compensation value memory by means of generating and writing compensation values according to claim 2.