JP2010142531A - Magnetic resonance imaging apparatus - Google Patents

Abstract

The present invention provides a magnetic resonance imaging apparatus capable of preventing a reduction in image quality of an MRI image by preventing an increase in accumulated error during D / D conversion.
When N (> M) -bit digital data is generated, the lower (NM) bits of the N-bit digital data are truncated to be converted into upper M-bit digital data. When (NM) bit digital data is integrated at every conversion, and the integrated value reaches the maximum value of the lower (NM) bits + 1 or more, the lower (NM) bit maximum from the integrated value. After subtracting the value +1, a new integration is performed, and the integration value reaches the maximum value +1 or more of the lower (N−M) bits. Thereafter, the data generation unit generates N-bit digital data, and the upper M bits. When converted into digital data, the numerical value 1 is added to the converted M-bit digital data.
[Selection] Figure 2

Description

  The present invention relates to a magnetic resonance imaging apparatus, and in particular, converts digital data into analog data, outputs analog data as an excitation current, and generates a gradient magnetic field in which the magnetic field strength is changed stepwise by the excitation current. The present invention relates to a magnetic resonance imaging apparatus having a magnetic field coil.

  In a magnetic resonance imaging apparatus, when a gradient magnetic field and an electromagnetic wave having a frequency in a predetermined range corresponding to the gradient magnetic field are added to a subject, a specific nucleus having a magnetic rotation ratio related to the strength of the magnetic field and the frequency of the electromagnetic wave is obtained. Resonates (MR phenomenon). For example, the position of a hydrogen nucleus can be identified from the frequency at the time of resonance, and an MRI image of the subject can be obtained from information on the position of the hydrogen nucleus. The MR phenomenon may or may not occur depending on the frequency of the electromagnetic wave, the type of atomic nucleus, and the strength of the magnetic field. The relationship between the magnetic field strength B, the gyromagnetic ratio (constant specific to the nucleus) γ, and the resonance frequency ω can be expressed by the equation (ω = γB).

  For example, as a conventional technique, a data generation unit that generates N-bit digital data, and an N-bit D / A conversion that converts the generated N-bit digital data into analog data and outputs the analog data as an excitation current And a magnetic resonance imaging apparatus having a gradient magnetic field coil for generating a gradient magnetic field by the input excitation current. When N bits are 16 bits, the 16-bit D / A converter has the advantage of being fast and inexpensive.

  The resolution of the current is determined by the resolution of the D / A converter. Therefore, the 16-bit D / A converter cannot meet the demand for higher current resolution.

  In order to meet the demand for high current resolution, N bits are set to 20 bits and a 20-bit D / A converter is used. As a result, a high current resolution can be obtained, and a gradient magnetic field can be generated with high accuracy, whereby the position of the nucleus can be known with high accuracy, and the image quality of the MRI image can be improved.

  Further, when the advantage of high speed and low cost and high current decomposition are required, as a conventional technique (for example, Patent Document 1), 20-bit digital data generated by a data generation unit is converted into upper 16 by a selector. Dividing into 16 bits and lower 16 bits, upper 16 bits are converted to analog data by the first 16-bit D / A converter, and lower 16 bits are converted to analog data by the second 16-bit D / A converter There is a magnetic resonance imaging apparatus that adds an output value of a first D / A converter and an output value of a second D / A converter by an adder.

  When errors are accumulated when D / D conversion is performed from 20-bit digital data to 16-bit digital data, deterioration of the image quality of the MRI image can be prevented by suppressing the accumulated error from increasing. I understand.

  Furthermore, it is convenient for users and manufacturers to enable an upgrade from a magnetic resonance imaging apparatus having a 16-bit D / A converter to a magnetic resonance imaging apparatus having a 20-bit D / A converter with a simple configuration. .

JP 2008-153928 A

  However, in the latter prior art described in Patent Document 1, a selector that divides 20-bit digital data into upper 16 bits and lower 16 bits and a first 16-bit D / A converter with upper 16 bits. There is a problem that many configurations such as an adder for adding the output value and the output value of the lower 16-bit second 16-bit D / A converter are required.

  The present invention solves the above-described problem, and includes a configuration for converting multi-bit digital data to analog data, and converting multi-bit digital data to small-bit digital data and then converting to analog data. The magnetic field that can prevent the deterioration of the image quality of the MRI image by preventing the cumulative error when converting the multi-bit digital data into the low-bit digital data is prevented. An object is to provide a resonance imaging apparatus.

In order to solve the above problems, the present invention accumulates errors when converting lower digital (N−M) bits of N-bit digital data into upper M-bit digital data, and the accumulated error is predetermined. In this case, attention was paid to preventing the accumulated error from becoming larger than a predetermined amount by including it in the upper M-bit digital data.
Specifically, according to a first aspect of the present invention, a data generation unit that generates N-bit digital data, and a D that converts the generated N-bit digital data into upper M-bit digital data smaller than N bits. / D converter, D / A converter that converts the converted upper M-bit digital data into analog data, and outputs the analog data as an excitation current, and generates a gradient magnetic field by the input excitation current In the magnetic resonance imaging apparatus, the D / D converter includes a subordinate (NM) of the N-bit digital data when the data generation unit generates the N-bit digital data. ) By rounding down the bits, the fraction processing unit converts the digital data of the upper M bits, and the fraction processing unit rounds down the bits. The digital data of the lower (NM) bits is integrated at each conversion, and when the integrated value reaches the maximum value of the lower (NM) bits + 1 or more, the lower (NM) from the integrated value. After subtracting the maximum bit value +1, the integration unit newly adds, and the integration value reaches the maximum value +1 of the lower (NM) bits, and then the data generation unit performs the N-bit digital And a data adding unit that adds a numerical value of 1 to the converted M-bit digital data when the fraction processing unit converts the digital data to the M-bit digital data. An imaging device.
According to a second aspect of the present invention, there is provided a data generation unit for generating N-bit digital data, and a D / D for converting the generated N-bit digital data into upper M-bit digital data having fewer than N bits. A converter; a D / A converter that converts the converted upper M-bit digital data into analog data and outputs the analog data as an excitation current; and a gradient that generates a gradient magnetic field by the input excitation current In the magnetic resonance imaging apparatus having a magnetic field coil, the D / D converter, when the data generator generates the N-bit digital data, the lower (NM) bits of the N-bit digital data Is rounded down to the upper M-bit digital data, and the fraction processing unit When digital data of (N−M) bits is integrated, and the integrated value reaches a predetermined value that is smaller than the maximum value of (N−M) bits, the lower order (N− M) a subtracting unit that newly accumulates after subtracting the maximum bit value +1, and the fraction processing unit reaches a predetermined value or more, and the data generating unit includes the N bits. And an addition unit that adds a numerical value 1 to the converted M-bit digital data when the fraction processing unit converts the digital data into the M-bit digital data. An imaging device.
Further, according to a third aspect of the present invention, a data generation unit that generates N-bit digital data, and a D / D that converts the generated N-bit digital data into higher-order M-bit digital data that is smaller than N bits. A converter; a D / A converter that converts the converted upper M-bit digital data into analog data and outputs the analog data as an excitation current; and a gradient that generates a gradient magnetic field by the input excitation current In the magnetic resonance imaging apparatus having a magnetic field coil, the D / D converter, when the data generator generates the N-bit digital data, the lower (NM) bits of the N-bit digital data The fraction processing unit for converting the digital data into the upper M bits and the data generation unit An adder for adding the lower-order (NM) bit digital data rounded down by the fraction processing unit to the next generated N-bit digital data, This is a magnetic resonance imaging apparatus.
Furthermore, a fourth aspect of the present invention is a data generation unit that generates N-bit digital data, and a D / D that converts the generated N-bit digital data into higher-order M-bit digital data smaller than N bits. A converter; a D / A converter that converts the converted upper M-bit digital data into analog data and outputs the analog data as an excitation current; and a gradient that generates a gradient magnetic field by the input excitation current In the magnetic resonance imaging apparatus having a magnetic field coil, the D / D converter, when the data generator generates the N-bit digital data, the lower (NM) bits of the N-bit digital data The fraction processing unit for converting the digital data into the upper M bits and the data generation unit When the next Tal data is generated, a subtracting unit for subtracting the upper M-bit digital data converted by the fraction processing unit from the N-bit digital data generated next, and the subtracting unit subtracts And a summing unit that sums up the subtracted digital data and outputs the summed digital data to the fraction processing unit.

  According to the first aspect of the present invention, the lower (NM) bit digital data rounded down by the fraction processing unit is integrated, and the integrated lower (NM) bit digital data is accumulated as an error. . When the accumulated lower limit (NM) bit maximum value +1 or more is reached, and then the generated N-bit digital data is converted to M-bit digital data, the M-bit digital data has a numerical value 1 Therefore, it is possible to suppress the accumulated error from increasing. Thereby, it is possible to prevent the image quality of the MRI image from being deteriorated.

  Further, when the accumulated value reaches or exceeds the maximum value of the lower (NM) bits, the maximum value of the lower (NM) bits + 1 is subtracted from the accumulated value, and then the new value is accumulated. While the generated error is small, the accumulated error can be reduced. From this point as well, it is possible to prevent deterioration of the image quality of the MRI image.

  According to the first embodiment described above, the accumulated error is always lower than the numerical value obtained by integrating the N-bit digital data, and the brightness of the image quality of the MRI image is always offset, for example, lower, so that the image quality of the MRI image is further improved. It will be a hindrance when letting

  On the other hand, according to the second embodiment of the present invention, when the integrated value reaches a predetermined value or more which is smaller than the maximum value of (N−M) bits, the generated N bits When the digital data is converted to M-bit digital data, the numerical value 1 is added to the M-bit digital data, so the accumulated error may be higher or lower than the numerical value obtained by integrating the N-bit digital data. For example, the image quality of the MRI image can be further improved without causing the brightness of the image quality of the MRI image to be shifted slightly lower or higher.

  According to the third aspect of the present invention, when the data generation unit next generates N-bit digital data, the N-bit bits that are truncated to the next generated N-bit digital data. Since the adding unit adds the digital data, it is possible to suppress an increase in accumulated error with a simple configuration. In addition, it is possible to prevent deterioration of the image quality of the MRI image.

  Further, according to the fourth aspect of the present invention, when N-bit digital data is generated next, the subtracting unit subtracts and subtracts M-bit digital data from the next generated N-bit digital data. At this time, since the subtracted digital data is integrated and the integrated digital data is output to the fraction processing unit, it is possible to suppress an increase in accumulated error with the same simple configuration. Thereby, it is possible to prevent the image quality of the MRI image from being deteriorated.

[First Embodiment]
(Constitution)
A configuration of a magnetic resonance imaging apparatus (MRI apparatus) according to a first embodiment of the present invention will be described with reference to FIG. FIG. 1 is a configuration diagram of an MRI apparatus.

  First, the gradient coil drive power supply unit 10 constituting the MRI apparatus will be described. The gradient coil drive power supply unit 10 includes a data generation unit 11 that generates N-bit digital data, and a D / D converter 12 that converts the generated N-bit digital data into M-bit digital data smaller than N bits. A D / A converter 13 that converts the converted M-bit digital data into analog data, a current amplifying unit 14 that outputs the analog data as an excitation current, and a gradient that generates a gradient magnetic field by the input excitation current A magnetic field coil 22. An MRI apparatus having a gradient coil drive power supply unit 10 is shown in FIG.

  Next, the D / D converter 12 will be described in more detail with reference to FIG. FIG. 2 is a configuration diagram of the D / D converter.

  The D / D converter 12 includes a fraction processing unit 121 that converts the low-order 4 bits of the 20-bit digital data into 16-bit digital data when the data generation unit 11 generates 20-bit digital data. The subtractor 122 that outputs the lower 4 bits of digital data rounded down by the fraction processing unit 121. The output lower 4 bits of the digital data are accumulated at every conversion, and the lower 4 bits of the accumulated digital data When the most significant bit data is rounded up, the lower 4-bit digital data rounded down by the fraction processing unit 121 is returned to the numerical value 0 and then newly accumulated, and the accumulated lower 4-bit digital data The most significant bit data is rounded up, and then the data generation unit 11 performs 20-bit digital data. Generates has when rounding unit 121 is converted into 16-bit digital data, an adder 124 for adding the number 1 to the converted 16-bit digital data, and a delay unit 125.

  Note that the subtraction unit 122, the integration unit 123, and the addition unit 124 may or may not be included in the fraction processing unit 121. A fraction processing unit 121 including the adding unit 124 is shown in FIG.

  The adder 124 truncates without adding to the 16-bit digital data if the output of the accumulator 123 is 0x0000F (maximum value of lower 4 bits), or 0x00010 (maximum of lower 4 bits if it is 0x00010 or higher). (Value + 1) is added to the 16-bit digital data (the numerical value 1 is added to the 16-bit digital data). By providing the delay unit 125, the result output from the integration unit 123 is used for the next determination by the addition unit 124 as to whether or not to round up.

  Next, the overall configuration of the MRI apparatus will be described with reference to FIG.

  The MRI apparatus shown in FIG. 1 includes a gradient magnetic field coil drive power supply unit 10, a static magnetic field magnet 21, a gradient magnetic field coil 22, a bed 24, a bed control unit 25, RF coil units 26a, 26b, and 26c, a transmission unit 27, and a selection circuit 28. , Receiving unit 29 and control computer unit 31, storage unit 32 connected to control computer unit 31, input unit 34, and display unit 33.

  In addition, the gradient coil drive power supply unit 10 is a data generation unit 11 that generates digital information related to the drive of the gradient coil 22 in response to an instruction from the control computer unit 31, and converts the digital data into digital data with a small number of bits. The / D converter 12 includes a D / A converter 13 that converts the digital data into an analog value and outputs the analog value to the gradient coil 22 as an excitation current.

  The static magnetic field magnet 21 has a hollow cylindrical shape and generates a uniform static magnetic field in the internal space. For example, a permanent magnet or a superconducting magnet is used as the static magnetic field magnet 21.

  The gradient coil 22 has a hollow cylindrical shape and is disposed inside the static magnetic field magnet 21. The gradient magnetic field coil 22 is a combination of three types of coils corresponding to the X, Y, and Z axes orthogonal to each other. The gradient coil 22 generates a gradient magnetic field in which the above three types of coils are individually supplied with current from the gradient coil drive power supply unit 10 and the magnetic field strength is inclined along the X, Y, and Z axes. To do. The Z-axis direction is, for example, the same direction as the static magnetic field. The gradient magnetic fields of the X, Y, and Z axes respectively correspond to, for example, a slice selection gradient magnetic field, a phase encoding gradient magnetic field, and a readout gradient magnetic field. The slice selection gradient magnetic field is used to arbitrarily determine an imaging section. The phase encoding gradient magnetic field is used to change the phase of the magnetic resonance signal in accordance with the spatial position. The readout gradient magnetic field is used to change the frequency of the magnetic resonance signal in accordance with the spatial position.

  The subject P is inserted into the cavity (imaging port) of the gradient coil 22 while being placed on the top 24 a of the bed 24. The couch 24 is driven by the couch controller 25 and moves the top plate 24a in the longitudinal direction (left-right direction in FIG. 1) and up-down direction. Usually, the bed 24 is installed so that the longitudinal direction is parallel to the central axis of the static magnetic field magnet 21.

  The RF coil unit 26a is configured by housing one or more coils in a cylindrical case. The RF coil unit 26 a is disposed inside the gradient magnetic field coil 22. The RF coil unit 26a receives a high frequency pulse (RF pulse) from the transmission unit 27 and generates a high frequency magnetic field.

  The RF coil units 26b and 26c are placed on the top plate 24a, built in the top plate 24a, or attached to the subject P. And at the time of imaging | photography, it inserts in the cavity of the gradient magnetic field coil 22 with the subject P. Each of the RF coil units 26b and 26c uses an array coil including a plurality of element coils, and receives a magnetic resonance signal emitted from the subject P. The output signals of the element coils are individually input to the selection circuit 28.

  The transmission unit 27 includes an oscillation unit, a phase selection unit, a frequency conversion unit, an amplitude modulation unit, and a high frequency power amplification unit. The oscillation unit generates a high-frequency signal having a resonance frequency unique to the target nucleus in the static magnetic field. The phase selection unit selects the phase of the high-frequency signal. The frequency conversion unit converts the frequency of the high-frequency signal output from the phase selection unit. The amplitude modulation unit modulates the amplitude of the high-frequency signal output from the frequency modulation unit, for example, according to a sync function. The high frequency power amplification unit amplifies the high frequency signal output from the amplitude modulation unit. As a result, the transmitter 27 supplies an RF pulse corresponding to the Larmor frequency to the RF coil unit 26a.

  The selection circuit 28 selects some of the multiple magnetic resonance signals output from the RF coil units 26b and 26c. Then, the selection circuit 28 gives the selected magnetic resonance signal to the reception unit 29. Which channel is selected is instructed by the control computer unit 31.

  The receiving unit 29 includes a plurality of processing systems including a pre-stage amplifier, a phase detector, and an analog / digital converter. Magnetic resonance signals selected by the selection circuit 28 are input to the processing systems of these multiple channels. The pre-stage amplifier amplifies the magnetic resonance signal. The phase detector detects the phase of the magnetic resonance signal output from the preamplifier. The analog-digital converter converts the signal output from the phase detector into a digital signal. The receiving unit 29 outputs a digital signal obtained by each processing system.

  The control computer unit 31 includes a CPU, a memory, and the like (not shown), and comprehensively controls the MRI apparatus according to the present embodiment, and functions as an interface unit, a data collection unit, a reconstruction unit, and a control unit. It is comprised. The interface unit inputs and outputs signals exchanged between the connected units such as the gradient coil drive power supply unit 10, the bed control unit 25, the transmission unit 27, the selection circuit 28, and the reception unit 29. The data collection unit collects digital signals output from the reception unit 29 and stores the collection result, that is, magnetic resonance signal data, in the storage unit 32. The reconstruction unit performs post-processing, that is, reconstruction such as Fourier transform, on the magnetic resonance signal data stored in the storage unit 32, and obtains spectrum data or image data of a desired nuclear spin in the subject P. Obtainable.

  The storage unit 32 stores magnetic resonance signal data and spectrum data or image data for each patient.

  The display unit 33 displays various information such as spectrum data or image data under the control of the control unit of the control computer unit 31. As the display unit 33, a display device such as a liquid crystal display can be used.

  The input unit 34 receives various commands and information input from the operator. The input unit 34 can appropriately use a pointing device such as a mouse or a trackball, a selection device such as a mode change switch, or an input device such as a keyboard.

(Operation)
Next, the operation of the D / D converter 12 that has received 20-bit digital data will be described with reference to FIG. FIG. 3 is an explanatory diagram showing an example of the data value of each part in the D / D converter 12. In order to simplify the description, the 20-bit digital data is assumed to be constant.

  It is assumed that the digital data 0x11464 generated by the data generation unit 11 is input to the fraction processing unit 121 at time t0. If the output of the accumulating unit 123 is 0x00000 in the initial state, the fraction processing unit 121 rounds down, and the fraction processing unit 121 outputs 0x1146. The output 0x1146 is input to the D / A converter 13. The accumulating unit 123 stores an output 0x00004 (= 0x11464-0x1146) of the subtracting unit 122.

  At time t1, next, when the data generation unit 11 generates the digital data 0x11464, the output is 0x0000F or less of the integration unit 123, and therefore is rounded down by the fraction processing unit 121, and the output of the fraction processing unit 121 is 0x1146. The output 0x1146 is input to the D / A converter 13. At this time, 0x00008 (= 0x00004 + 0x00004) is stored in the integration unit 123.

  Even at time t2, when the data generation unit 11 next generates the digital data 0x11464, the output of the integration unit 123 is 0x0000F or less, so the fraction processing unit 121 rounds down, and the output of the fraction processing unit 121 becomes 0x1146. The output 0x1146 is input to the D / A converter 13. At this time, 0x0000C (= 0x00008 + 0x00004) is stored in the integrating unit 123.

  Even at time t3, when the data generation unit 11 next generates the digital data 0x11464, the output from the integration unit 123 is 0x0000F or less, so the fraction processing unit 121 rounds down, and the output from the fraction processing unit 121 becomes 0x1146. The output 0x1146 is input to the D / A converter 13. At this time, 0x00010 (= 0x0000C + 0x00004) is stored in the integrating unit 123.

  At time t4, next, when the data generation unit 11 generates the digital data 0x11464, the output of the integration unit 123 is 0x00010 or more, so the rounding unit 121 rounds up, and the addition unit 124 adds the rounded up 0x00010 to 16-bit digital data. Add to 0x1146 (add 1 to 16-bit digital data 0x1146). 0x1147 (= 0x00010 + 0x1146) is input to the D / A converter 13 from the fraction processing unit 121. At this time, 0xFFFF4 (= 0x11464-0x1147) is added to the integration unit 123. The accumulating unit 123 stores 0x00004 (= 0x00010 + 0xFFFF4). As a result, when the lower 4-bit digital data is rounded up, the accumulating unit 123 subtracts the 4-bit maximum value + 1 (= 0x00010) from the accumulated value, and then newly accumulates 0x00004.

  The operation from time t5 to time t8 is shown in FIG. As can be seen from the operation from time t1 to time t8, the operation from time t5 to time t8 is the same as the operation from time t1 to time t4. That is, the D / D converter 12 according to the first embodiment repeats the operation from time t1 to time t4.

  In FIG. 3, the output of the integrating unit 123 represents the accumulated error. As described for the operation of the D / D converter 12, when the accumulated error due to truncation exceeds a specified threshold value, the operation is performed to reduce the accumulated error. Therefore, errors do not continue to accumulate.

  As a result, an increase in accumulated error when converting 20-bit digital data into 16-bit digital data is suppressed, and deterioration of the image quality of the MRI image can be prevented. FIG. 4 shows the generated 20-bit digital data and 16-bit digital data close to the 20-bit digital data. FIG. 4 is an explanatory diagram showing the output data of the D / D converter 12 in a graph.

[Second Embodiment]
(Constitution)
A configuration of the D / D converter 12 according to the second embodiment of the present invention will be described. The configuration of the D / D converter 12 of the second embodiment is basically the same as the configuration of the D / D converter 12 of the first embodiment shown in FIG. Hereinafter, a configuration different from the D / D converter 12 of the first embodiment will be described. The components other than the D / D converter 12 are the same as those in the first embodiment, and the description of each component is omitted.

When the data generation unit 11 generates 20-bit digital data, the D / D converter 12 according to the second embodiment converts the lower 4 bits of the 20-bit digital data into 16-bit digital data. A fraction processing unit 121 for conversion and an integration unit 123 for integrating the lower 4 bits of digital data rounded down by the fraction processing unit 121 are included.
The fraction processing unit 121 is the time when the integration value of the integration unit reaches a predetermined value or more that is smaller than the maximum value of (N−M) bits, and the data generation unit 11 performs 20-bit digital data. When the fraction processing unit 121 converts to 16-bit digital data, the adder 124 adds a numerical value 1 to the converted 16-bit digital data.

  In the first embodiment, the addition unit 124 adds the numerical value 1 to the converted 16-bit digital data (0x1146) when the accumulated lower-order 4-bit digital data is greater than or equal to the maximum value +1 (becomes 0x00010). (0x1146 + 0x00010).

  On the other hand, in the second embodiment, the integration value of the integration unit is converted when it reaches or exceeds a predetermined value that is smaller than the maximum value of (N−M) bits (when 0x00008). The adding unit 124 adds the numerical value 1 to the 16-bit digital data (0x1146) (0x1146 + 0x00010).

(Operation)
Next, the operation of the D / D converter 12 that has received 20-bit digital data will be described with reference to FIG. FIG. 5 is an explanatory diagram showing an example of the data value of each part in the D / D converter 12. In order to simplify the description, the 20-bit digital data is assumed to be constant.

  Assume that digital data 0x11464 is input at time t0. If the output of the integrating unit 123 is 0x00000 in the initial state, the fraction processing unit 121 rounds down and the output is 0x1146. This is input to the D / A converter 13. The accumulating unit 123 stores an output 0x00004 (= 0x11464-0x1146) of the subtracting unit 122.

  At time t1, since the output of the accumulating unit 123 is 0x00008 or less, it is rounded down by the fraction processing unit 121 and 0x1146 is input to the D / A converter 13. At this time, 0x00008 (= 0x00004 + 0x00004) is stored in the integration unit 123.

  At time t2, since the output of the integrating unit 123 is 0x00008 or more, the rounding unit 121 rounds up, and the adding unit 124 adds the rounded up 0x00010 to the 16-bit digital data 0x1146 (the numerical value 1 is added to the 16-bit digital data 0x1146). to add). 0x1147 (= 0x00010 + 0x1146) is input to the D / A converter 13 from the fraction processing unit 121. At this time, 0xFFFF4 (= 0x11464-0x1147) is added to the integration unit 123. The accumulating unit 123 stores 0xFFFFC (= 0x00008 + 0xFFFF4).

  At time t3, since the output of the accumulating unit 123 is 0x00008 or less, it is rounded down by the fraction processing unit 121 and 0x1146 is input to the D / A converter 13. At this time, 0x00000 (= 0xFFFFC + 0x00004) is stored in the integration unit 123.

  At time t4, similarly to time t0, the output of the accumulating unit 123 is 0x00008 or less, so it is rounded down by the fraction processing unit 121 and 0x1146 is input to the D / A converter 13. At this time, 0x00004 (= 0x00000 + 0x00004) is stored in the integration unit 123.

  Thereafter, at time t5, as with time t1, the output of the accumulating unit 123 is 0x00008 or less, so the rounding unit 121 rounds down and 0x1146 is input to the D / A converter 13. At this time, 0x00008 (= 0x00004 + 0x00004) is stored in the integration unit 123.

  At time t6, since the output of the accumulating unit 123 is equal to or greater than 0x00008 at time t2, it is rounded up by the fraction processing unit 121, and the adding unit 124 adds the rounded up 0x00010 to the 16-bit digital data 0x1146 (the numerical value 1 is 16 bits To the digital data 0x1146). 0x1147 (= 0x00010 + 0x1146) is input to the D / A converter 13 from the fraction processing unit 121. At this time, 0xFFFF4 (= 0x11464-0x1147) is added to the integration unit 123. The accumulating unit 123 stores 0xFFFFC (= 0x00008 + 0xFFFF4).

  As can be seen from the description of the operation from time t1 to time t6, the D / D converter 12 according to the second embodiment repeats the operation from time t0 to time t2 with the operation at time t3 interposed therebetween. .

  Here, if the output of the integration unit 123 reaches 0x00008, which is the specified threshold value, the output of the D / D converter 12 becomes 0x00147 (= 0x00010 + 0x1146), so that the accumulated error is obtained by integrating 20-bit digital data. Above or below the numerical value. Thereby, for example, the image quality of the MRI image can be further improved without causing the brightness of the image quality of the MRI image to be shifted slightly lower or higher. FIG. 6 shows 20-bit digital data and 16-bit digital data that exceeds or falls below the 20-bit digital data. FIG. 6 is an explanatory diagram showing the output data of the D / D converter in a graph.

[Third Embodiment]
(Constitution)
A configuration of a D / D converter 12 according to a third embodiment of the present invention will be described with reference to FIG. FIG. 7 is a configuration diagram of the D / D converter 12. The components other than the D / D converter 12 are the same as those in the first embodiment, and the description of each component is omitted.

  When the data generation unit 11 generates 20-bit digital data, the D / D converter 12 according to the third embodiment converts the lower 4 bits of the 20-bit digital data into 16-bit digital data. When the fraction processing unit 121 to be converted and the data generation unit 11 next generate 20-bit digital data, the lower-order 4-bit digital data truncated by the fraction processing unit 121 into the next generated 20-bit digital data. And an adding unit 124 for adding data.

  In addition, it has a subtractor 122 that subtracts the 16-bit digital data converted by the fraction processor 121 from the 20-bit digital data input to the fraction processor 121. The subtractor 122 subtracts the 16-bit digital data from the 20-bit digital data to generate lower 4 bits of digital data.

  Note that the lower 4 bits of digital data may be generated by extracting the lower 4 bits of the 20-bit digital data.

  In addition, a delay unit 125 is included. By providing the delay unit 125, the result output from the subtraction unit 122 is added with the lower 4 bits of digital data when the data generation unit 11 next generates 20 bits of digital data.

(Operation)
Next, the operation of the D / D converter 12 that has received 20-bit digital data will be described with reference to FIG. FIG. 8 is an explanatory diagram showing an example of the data value of each part in the D / D converter 12. In order to simplify the description, the 20-bit digital data is assumed to be constant.

  It is assumed that the digital data 0x11464 generated by the data generation unit 11 is input to the addition unit 124 at time t0. If the output of the delay unit 125 is 0x00000 in the initial state, the output of the adder unit 124 is 0x11464. The output 0x11464 of the adding unit 124 is rounded down by the fraction processing unit 121, and the output of the fraction processing unit 121 is 0x1146. The output 0x1146 of the fraction processing unit 121 is input to the D / A converter 13. The output of the subtractor 122 is 0x00004 (= 0x11464-0x11460).

  At time t1, the output 0x00004 of the subtraction unit 122 that has passed through the delay unit 125 is added to the digital data 0x11464 generated by the data generation unit 11 by the addition unit 124, and the output of the addition unit 124 is 0x11468 (= 0x11464 + 0x00004) and is rounded down by the fraction processing unit 121, and the output of the fraction processing unit 121 is 0x1146. The output 0x1146 of the fraction processing unit 121 is input to the D / A converter 13. The output of the subtracting unit 122 is 0x00008 (= 0x11468-0x11460).

  Next, at time t2, the output 0x00008 of the subtractor 122 that has passed through the delay unit 125 is added to the digital data 0x11464 generated by the data generator 11 by the adder 124, and the output of the adder 124 is 0x1146C (= 0x11468 + 0x00004) and is rounded down by the fraction processing unit 121, and the output of the fraction processing unit 121 is 0x1146. The output 0x1146 of the fraction processing unit 121 is input to the D / A converter 13. The output of the subtracting unit 122 is 0x0000C (= 0x1146C-0x11460).

  At time t3, next, the output 0x0000C of the subtraction unit 122 that has passed through the delay unit 125 is added to the digital data 0x11464 generated by the data generation unit 11 by the addition unit 124, and the output of the addition unit 124 is 0x11470 (= 0x1146C + 0x00004) and rounded down by the fraction processing unit 121, and the output of the fraction processing unit 121 becomes 0x1147. The output 0x1147 of the fraction processing unit 121 is input to the D / A converter 13. The output of the subtractor 122 is 0x00000 (= 0x11470-0x11470).

  At time t4, the result is the same as time t0. That is, next, the output 0x00000 of the subtraction unit 122 that has passed through the delay unit 125 is added to the digital data 0x11464 generated by the data generation unit 11 by the addition unit 124, and the output of the addition unit 124 becomes 0x11464. The output 0x11464 of the adding unit 124 is rounded down by the fraction processing unit 121, and the output of the fraction processing unit 121 is 0x1146. The output 0x1146 of the fraction processing unit 121 is input to the D / A converter 13. The output of the subtractor 122 is 0x00004 (= 0x11464-0x11460).

  As can be seen from the operation from time t0 to time t4, the D / D converter 12 according to the third embodiment repeats the operation from time t0 to time t3.

  In FIG. 8, the lower 4 bits of data truncated by the fraction processing unit 121 represent the accumulated error. As described above, the operation of the D / D converter 12 operates so that the cumulative error becomes 0 when the most significant 4 bits of data are rounded up. Therefore, errors do not continue to accumulate.

  As a result, an increase in accumulated error when converting 20-bit digital data into 16-bit digital data is suppressed, and deterioration of the image quality of the MRI image can be prevented. Further, a simple configuration in which the subtracting unit 122 and the delay unit 125 are provided can be achieved.

  FIG. 9 shows 20-bit digital data generated by the data generation unit 11 and 16-bit digital data close to the 20-bit digital data. FIG. 9 is an explanatory diagram showing the output data of the D / D converter 12 in a graph.

[Fourth Embodiment]
(Constitution)
A configuration of a D / D converter 12 according to a fourth embodiment of the present invention will be described with reference to FIG. FIG. 10 is a configuration diagram of the D / D converter 12. About each structure other than the D / D converter 12, it is the same as each structure of 1st Embodiment, and description of those each structure is abbreviate | omitted.

  When the data generation unit 11 generates 20-bit digital data, the D / D converter 12 according to the fourth embodiment converts the lower 4 bits of the 20-bit digital data into 16-bit digital data. When the fraction processing unit 121 to be converted and the data generation unit 11 next generate 20-bit digital data, 16-bit digital data converted by the fraction processing unit 121 from the next generated 20-bit digital data A subtracting unit 122 that subtracts the subtracted digital data, and a subtracting unit 122 that accumulates the subtracted digital data and outputs the integrated digital data to the fraction processing unit 121 when the subtracting unit 122 subtracts the subtracted digital data.

  In addition, a delay unit 125 is included. By providing the delay unit 125, when the data generation unit 11 next generates 20-bit digital data, the result output from the fraction processing unit 121 is subtracted.

(Operation)
Next, the operation of the D / D converter 12 that has received 20-bit digital data will be described with reference to FIG. FIG. 11 is an explanatory diagram showing an example of the data value of each part in the D / D converter 12. In order to simplify the description, the 20-bit digital data is assumed to be constant.

  It is assumed that the digital data 0x11464 generated by the data generation unit 11 is input to the subtraction unit 122 at time t0. If the output of the delay unit 125 is 0x00000 in the initial state, the output of the subtraction unit 122 is 0x11464. The output of the integrating unit 123 is 0x11464. The output 0x11464 of the accumulating unit 123 is rounded down by the fraction processing unit 121, and the output of the fraction processing unit 121 becomes 0x1146. The output 0x1146 of the fraction processing unit 121 is input to the D / A converter 13. At this time, the accumulated error is a value 0x00004 obtained by subtracting the output 0x1146 of the fraction processing unit 121 from the output 0x11464 of the integration unit 123.

  Next, at time t1, the output 0x1146 of the fraction processing unit 121 that has passed through the delay unit 125 is subtracted from the digital data 0x11464 generated by the data generation unit 11 by the subtraction unit 122, and the output of the subtraction unit 122 is 0x00004. (0x11464-0x1146). The output of the integration unit is 0x11468 (= 0x11464 + 0x00004). The output 0x11468 of the accumulating unit 123 is rounded down by the fraction processing unit 121, and the output of the fraction processing unit 121 becomes 0x1146. The output 0x1146 of the fraction processing unit 121 is input to the D / A converter 13. At this time, the accumulated error is a value 0x00008 obtained by subtracting the output 0x1146 of the fraction processing unit 121 from the output 0x11468 of the integrating unit 123.

  At time t2, next, the output 0x1146 of the fraction processing unit 121 that has passed through the delay unit 125 is subtracted by the subtraction unit 122 with respect to the digital data 0x11464 generated by the data generation unit 11, and the output of the subtraction unit 122 is 0x00004. (0x11464-0x1146). The output of the integration unit is 0x1146C (= 0x11468 + 0x00004). The output 0x1146C of the accumulating unit 123 is rounded down by the fraction processing unit 121, and the output of the fraction processing unit 121 becomes 0x1146. The output 0x1146 of the fraction processing unit 121 is input to the D / A converter 13. At this time, the accumulated error is a value 0x0000C obtained by subtracting the output 0x1146 of the fraction processing unit 121 from the output 0x1146C of the integration unit 123.

  Next, at time t3, the output 0x1146 of the fraction processing unit 121 that has passed through the delay unit 125 is subtracted from the digital data 0x11464 generated by the data generation unit 11 by the subtraction unit 122, and the output of the subtraction unit 122 is 0x00004. (0x11464-0x1146). The output of the integration unit is 0x11470 (= 0x1146C + 0x00004). The output 0x11470 of the accumulating unit 123 is rounded down by the fraction processing unit 121, and the output of the fraction processing unit 121 becomes 0x1147. The output 0x1147 of the fraction processing unit 121 is input to the D / A converter 13. At this time, the accumulated error is a value 0x00000 obtained by subtracting the output 0x1147 of the fraction processing unit 121 from the output 0x11470 of the integration unit 123.

  Next, at time t4, the output 0x1147 of the fraction processing unit 121 that has passed through the delay unit 125 is subtracted from the digital data 0x11464 generated by the data generation unit 11 by the subtraction unit 122, and the output of the subtraction unit 122 is 0xFFFF4 (0x11464-0x1147). The output of the integration unit is 0x11464 (= 0x11470 + 0xFFFF4). The output 0x11464 of the accumulating unit 123 is rounded down by the fraction processing unit 121, and the output of the fraction processing unit 121 becomes 0x1146. The output 0x1146 of the fraction processing unit 121 is input to the D / A converter 13. At this time, the accumulated error is a value 0x00004 obtained by subtracting the output 0x1146 of the fraction processing unit 121 from the output 0x11464 of the integration unit 123.

  Next, at time t5, the output 0x1146 of the fraction processing unit 121 that has passed through the delay unit 125 is subtracted from the digital data 0x11464 generated by the data generation unit 11 by the subtraction unit 122, and the output of the subtraction unit 122 is 0x00004. (0x11464-0x1146). The output of the integration unit is 0x11468 (= 0x11464 + 0x00004). The output 0x11468 of the accumulating unit 123 is rounded down by the fraction processing unit 121, and the output of the fraction processing unit 121 becomes 0x1146. The output 0x1146 of the fraction processing unit 121 is input to the D / A converter 13. At this time, the accumulated error is a value 0x00008 obtained by subtracting the output 0x1146 of the fraction processing unit 121 from the output 0x11468 of the integrating unit 123. This is the same as the operation at time t1.

  As can be seen from the operation from time t0 to time t5, the D / D converter 12 according to the fourth embodiment repeats the operation from time t1 to time t4.

  In FIG. 11, the accumulated error is expressed as a value obtained by subtracting the output of the fraction processing unit from the output value of the integrating unit 123. As described for the operation of the D / D converter 12, the operation is performed so that the accumulated error becomes zero at every fixed time. Therefore, errors do not continue to accumulate. Thereby, it is possible to prevent the image quality of the MRI image from being deteriorated.

  In each of the above embodiments, if the D / D converter 12 is configured by a field programmable gate array, a 16-bit D / A converter can be converted to a 20-bit D / A conversion by exchanging ROM (read-only memory). It can be easily replaced with a vessel. As a result, it is possible to provide a gradient magnetic field system that can easily cope with an upgrade requiring high current resolution.

  In the embodiment, the M bit is 16 bits and the N bit is 20 bits. However, in the present invention, it is sufficient that M bits is smaller than N bits (M <N). For example, M bits may be 18 bits and N bits may be 24 bits. Further, although the D / A converter 13 and the current amplifying unit 14 are provided separately, the D / A converter 13 may include the current amplifying unit 14.

1 is a configuration diagram of a magnetic resonance imaging apparatus (MRI) according to a first embodiment of the present invention. It is a block diagram of a D / D converter. It is explanatory drawing which shows an example of the data value of each part in a D / D converter. It is explanatory drawing which shows the output data of a D / D converter with a graph. It is explanatory drawing which shows an example of the data value of each part in the D / D converter which concerns on 2nd Embodiment of this invention. It is explanatory drawing which shows the output data of a D / D converter with a graph. It is a block diagram of the D / D converter which concerns on 3rd Embodiment of this invention. It is explanatory drawing which shows an example of the data value of each part in a D / D converter. It is explanatory drawing which shows the output data of a D / D converter with a graph. It is a block diagram of the D / D converter which concerns on 4th Embodiment of this invention. It is explanatory drawing which shows an example of the data value of each part in a D / D converter.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Gradient magnetic field coil drive power supply part 11 Data generation part 12 D / D converter 13 D / A converter 14 Current amplification part 121 Fraction processing part 122 Subtraction part 123 Accumulation part 124 Addition part 125 Delay part 21 Static magnetic field magnet 22 Gradient magnetic field 22 Coil 24 Bed 24a Top plate 25 Bed control unit 26a, 26b, 26c RF coil unit 27 Transmission unit 28 Selection circuit 29 Reception unit 31 Control computer unit 32 Storage unit 33 Display unit 34 Input unit

Claims (5)

A data generation unit for generating N-bit digital data, a D / D converter for converting the generated N-bit digital data into upper M-bit digital data smaller than N bits, and the converted upper M bits In a magnetic resonance imaging apparatus, comprising: a D / A converter that converts digital data into analog data and outputs the analog data as an excitation current; and a gradient magnetic field coil that generates a gradient magnetic field using the input excitation current ,
The D / D converter is:
When the data generation unit generates the N-bit digital data, a fraction processing unit that converts the lower (NM) bits of the N-bit digital data into the upper M-bit digital data by truncating the N-bit digital data;
The lower (NM) bit digital data rounded down by the fraction processing unit is integrated every time the conversion is performed, and when the integrated value reaches the maximum value of the lower (NM) bits + 1 or more, the integrated value An accumulation unit for newly accumulating after subtracting the maximum value +1 of the lower (NM) bits from +1,
The integrated value reaches the maximum value of the lower (N−M) bits + 1 or more, and thereafter, the data generation unit generates the N-bit digital data, and the fraction processing unit converts the digital data to the M-bit digital data. An adding unit that adds a numerical value 1 to the converted upper M-bit digital data;
A magnetic resonance imaging apparatus comprising: A data generation unit for generating N-bit digital data, a D / D converter for converting the generated N-bit digital data into upper M-bit digital data smaller than N bits, and the converted upper M bits In a magnetic resonance imaging apparatus, comprising: a D / A converter that converts digital data into analog data and outputs the analog data as an excitation current; and a gradient magnetic field coil that generates a gradient magnetic field using the input excitation current ,
The D / D converter is:
When the data generation unit generates the N-bit digital data, a fraction processing unit that converts the lower (NM) bits of the N-bit digital data into the upper M-bit digital data by truncating the N-bit digital data;
When digital data of lower (NM) bits rounded down by the fraction processing unit is integrated, and the integrated value is smaller than the maximum value of (NM) bits and reaches a predetermined value or more An integration unit for newly integrating after subtracting the maximum value +1 of the lower order (NM) bits from the integrated value;
Have
When the fraction processing unit reaches the predetermined value or more, the data generation unit generates the N-bit digital data, and the fraction processing unit converts the digital data to the upper M bits. A magnetic resonance imaging apparatus comprising: an adder that adds a numerical value 1 to the converted upper M-bit digital data. A data generation unit for generating N-bit digital data, a D / D converter for converting the generated N-bit digital data into upper M-bit digital data smaller than N bits, and the converted upper M bits In a magnetic resonance imaging apparatus, comprising: a D / A converter that converts digital data into analog data and outputs the analog data as an excitation current; and a gradient magnetic field coil that generates a gradient magnetic field using the input excitation current ,
The D / D converter is:
When the data generation unit generates the N-bit digital data, a fraction processing unit that converts the lower (NM) bits of the N-bit digital data into the upper M-bit digital data by truncating the N-bit digital data;
When the data generation unit next generates the N-bit digital data, the N-bit digital data rounded down by the fraction processing unit to the N-bit digital data generated next. An adder for adding
A magnetic resonance imaging apparatus comprising: A data generation unit for generating N-bit digital data, a D / D converter for converting the generated N-bit digital data into upper M-bit digital data smaller than N bits, and the converted upper M bits In a magnetic resonance imaging apparatus, comprising: a D / A converter that converts digital data into analog data and outputs the analog data as an excitation current; and a gradient magnetic field coil that generates a gradient magnetic field using the input excitation current ,
The D / D converter is:
When the data generation unit generates the N-bit digital data, a fraction processing unit that converts the lower (NM) bits of the N-bit digital data into the upper M-bit digital data by truncating the N-bit digital data;
When the data generation unit next generates the N-bit digital data, the upper M-bit digital data converted by the fraction processing unit is subtracted from the next generated N-bit digital data. A subtraction unit;
When the subtraction unit subtracts, the integration unit that integrates the subtracted digital data and outputs the integrated digital data to the fraction processing unit;
A magnetic resonance imaging apparatus comprising:   5. The magnetic resonance imaging apparatus according to claim 1, wherein the D / D converter includes a field programmable gate array.

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