JP2008103624A - Packaging method of semiconductor chip - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a new packaging method of a semiconductor chip which can attain the high performance and the miniaturization of semiconductor equipment by particularly laminating semiconductor chips in order to narrow a mounting area. <P>SOLUTION: At least one through hole is formed at the semiconductor chip, and then, an adhesive layer is attached to the rear side of the semiconductor chip. After that, a substrate for package in which at least one metal pin is standingly provided is prepared, the semiconductor chip and the substrate for package are stuck to each other so that the metal pin is inserted into the through hole so as to wind up a part of the adhesive layer, and that a part of the adhesive layer infills a clearance between the metal pin and the through hole. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor chip mounting method.

  In recent years, with the increase in performance and miniaturization of electronic devices, a plurality of semiconductor chips are arranged in a single package to form a multi-chip package, thereby increasing the functionality and size of the semiconductor device. Is planned. The multi-chip package includes a plurality of semiconductor chips arranged in a plane and a plurality of semiconductor chips stacked in the thickness direction. A multi-chip package in which semiconductor chips are arranged in a plane requires a large mounting area, and therefore contributes little to downsizing of electronic devices. For this reason, development of stacked MCPs in which semiconductor chips are stacked has been actively conducted.

  From this point of view, in Japanese Patent Application Laid-Open No. 2001-127241, a plurality of semiconductor chips are stacked, a through hole is formed in a straight line with respect to these stacked bodies, a conductive shaft is inserted into the through hole, and a chip electrode is formed. A method of mounting a semiconductor chip configured to be electrically connected to a portion is disclosed.

  In Japanese Patent Laid-Open No. 2001-135785, a plurality of semiconductor chips are prepared, through holes are formed in each semiconductor chip, and metal pins are inserted into the through holes so as to be electrically connected to the chip electrode portion. After that, a method of aligning and stacking these semiconductor chips and mounting the semiconductor chips is disclosed.

  However, in the method described in Japanese Patent Laid-Open No. 2001-127241, a silicon oxide film is formed on the inner wall surface of the through hole in order to insulate the through hole of the semiconductor chip from the conductive shaft. In Japanese Patent Laid-Open No. 2001-135785, an insulating resin is interposed between the through hole and the metal pin in order to insulate the through hole of the semiconductor chip from the metal pin.

Therefore, in such a conventional technique, an operation for separately forming a semiconductor chip and a conductive shaft or a metal pin inserted into the through hole to form an insulation is required. In addition, when the silicon oxide film or the insulating resin as described above is interposed, the opening diameter of the through hole needs to be set to a certain extent depending on the amount of the interposed film. Therefore, the proportion of the through-holes in the semiconductor chip is increased, which is contrary to the demand for downsizing the semiconductor chip.
JP 2001-127241 A JP 2001-135785 A

  The present invention provides a novel semiconductor chip mounting method capable of reducing the mounting area, in particular by stacking and mounting semiconductor chips, and improving the performance and miniaturization of semiconductor devices. With the goal.

In order to achieve the above object, one embodiment of the present invention provides:
Forming at least one through hole in the semiconductor chip;
Attaching an adhesive layer to the back side of the semiconductor chip;
Preparing a package substrate on which at least one metal pin is erected;
Bonding the semiconductor chip and the package substrate through the adhesive layer,
The step of bonding the semiconductor chip and the package substrate through the adhesive layer includes the metal pin winding a part of the adhesive layer into the through hole, and a part of the adhesive layer being the metal pin and the The present invention relates to a semiconductor chip mounting method, wherein the semiconductor chip is inserted so as to bury a gap with a through hole.

  As described above, according to one embodiment of the present invention, in order to reduce the mounting area, a novel semiconductor chip capable of achieving high performance and miniaturization of a semiconductor device, in particular, by stacking and mounting semiconductor chips. Can be provided.

  Hereinafter, other features and advantages of the present invention will be described based on the best mode for carrying out the invention.

  FIGS. 1 to 5 are process diagrams in an example of a semiconductor chip mounting method of the present invention, and FIGS. 6 to 8 are explanatory views showing an enlarged state in one process of the mounting method.

  First, as shown in FIG. 1, a semiconductor wafer 11 such as silicon (Si) is prepared, and a scrub line 12 for cutting a chip is formed on the main surface. Next, as shown in FIG. 2, a plurality of through holes 13 are formed in a region defined by the scrub line 12 of the semiconductor wafer 11. The through hole 13 can be formed using means such as a water laser cutter.

  The water laser cutter is a technique for performing fine processing by irradiating a laser beam simultaneously with a load of water pressure, and by using such a technique, the opening diameter of the through hole 13 is about 50 μm to 100 μm. It can be very small. Even if the thickness of the semiconductor wafer is increased to about 100 μm, the through hole 13 having the above-described opening diameter can be formed.

  In FIGS. 1 and 2, only the region defined by the scrub line 12 of the semiconductor wafer 11 is shown, but actually extends far beyond the region shown.

  1 and 2, the plurality of through holes 13 are formed on the line, but can be formed so as to be arranged in an arbitrary form according to the application.

  Next, as shown in FIG. 3, the semiconductor wafer 11 is cut along the scrub line 12 to form the semiconductor chip 11, and then an adhesive layer 14 is formed (attached) on the back surface of the semiconductor chip 11. As the adhesive layer 14, an adhesive film such as epoxy, polyimide, polyethylene, and acrylic can be used.

  In FIG. 3 and subsequent figures, for simplification, the reference numeral 11 indicating the semiconductor wafer is used together with the semiconductor chip.

  In this example, although not particularly illustrated, an insulating layer such as silicon oxide is formed by performing an operation such as oxidation on the main surface of the semiconductor chip 11 or performing a film forming process such as CVD. A metal wiring electrically connected to the metal pins shown below is appropriately formed on the insulating layer.

  Next, as shown in FIG. 4, a package substrate 21 is prepared, and a plurality of metal pins 22 are formed so as to stand on the main surface. The package substrate 21 can be made of, for example, glass epoxy resin, and the metal pins 22 are fixed thereon using solder or the like and are erected.

  Since the metal pin 22 is inserted into the through hole 13 of the semiconductor chip 11 as will be described later, the diameter of the metal pin 22 needs to be smaller than the opening diameter of the through hole 13, and the length of the metal pin 22 is within the through hole 13. After being completely inserted into the semiconductor chip 11, the length is set such that it can be electrically contacted with the metal wiring formed on the main surface of the semiconductor chip 11. Further, since the metal pins 22 are respectively inserted into the corresponding through holes 13, it is necessary to arrange them so as to correspond to the arrangement of the through holes 13.

  Moreover, the metal pin 22 is comprised from the metal material which exhibits electrical conductivity, such as gold | metal | money, silver, copper, aluminum, for example.

  Next, as shown by the arrows in FIG. 4, the semiconductor chip 11 is lowered so that the metal pins 22 erected on the package substrate 21 are inserted into the through holes 13 of the semiconductor chip 11. The chip 11 and the package substrate 21 are bonded together via the adhesive layer 14. As a result, as shown in FIG. 5, the metal pins 22 provided on the package substrate 21 penetrate through the through holes 13 of the semiconductor chip 11 and are electrically connected to the metal wiring formed on the main surface of the semiconductor chip 11. Mounting is done in contact with

  Although not particularly shown in this example, the semiconductor chip mounted as shown in FIG. 5 can be appropriately sealed with resin for protection.

  6 to 8, the process of inserting the metal pins 22 formed on the package substrate 21 in the mounting process into the through hole 13 of the semiconductor chip 11 will be described.

  First, as shown in FIG. 6, when the metal pin 22 comes into contact with the adhesive layer 14 formed on the back surface of the semiconductor chip 11, the contact portion becomes depressed, and when the insertion of the metal pin 22 further proceeds, FIG. As shown, the metal pin 22 penetrates the adhesive layer 14 and enters the through hole 13. At this time, the metal pin 22 is wound around a portion of the adhesive layer 14 in the vicinity of the through hole, and is inserted into the through hole 13 together with the wound portion 14A. Thereafter, the winding portion 14 </ b> A comes into close contact with the side surface of the metal pin 22 and is similarly introduced into the through hole 13 as the metal pin 22 is inserted into the through hole 13.

  As a result, after the entire metal pin 22 is inserted into the through-hole 13, as shown in FIG. 8, there is a winding portion 14A of the adhesive layer 14 in the gap between the through-hole 13 and the metal pin 22. Thus, electrical conduction of the semiconductor chip 11 through the through hole 11A can be avoided.

  In the present invention, the tip 22A of the metal pin 22 in the package substrate 21 can be made of a low melting point conductive material such as solder. In this case, a heating operation is performed after mounting as shown in FIGS. 5 and 8, and as shown in FIG. 9, the tip 22 </ b> A is heated and melted and flattened to ensure electrical connection with the metal wiring 15. Can be made to do.

  The tip portion 22A of the metal pin 22 can be made of a material such as solder as described above, but the melting point of the material is about 270 ° C., and it is preferable to appropriately select a material that does not melt during mounting. .

  FIG. 10 is a modification of the above specific example. In FIG. 10, groove processing is performed on the package substrate 21 to form a plurality of grooves 21 </ b> A. The plurality of grooves 21 </ b> A are formed so as to correspond to the positions of the through holes 13 of the semiconductor chip 11. In this case, fixing the metal pin 22 to be inserted into the through hole 13 of the semiconductor chip 11 can be facilitated by fixing the metal pin 22 to the groove 21A with solder or the like and standing upright. The positioning of the metal pin 22 with respect to the through hole 13 can be facilitated.

  Accordingly, the metal pin 22 can be inserted almost completely linearly into the through hole 13, the portion 14 </ b> A where the adhesive layer 14 is wound is partially broken, and the semiconductor chip 11 and the metal pin 22 are electrically connected. Can be avoided.

  11 and 12 are configuration diagrams showing another example of the semiconductor chip mounting method of the present invention. In addition, about the component same as or similar to FIGS. 1-9 regarding the said specific example, it represents using the same reference number.

  In this example, the above-described steps shown in FIGS. 1 to 9 are defined as one cycle, and this cycle is first performed once to produce a semiconductor chip element A as shown in FIGS. 11 and 12. The cycle is performed once more to produce a semiconductor chip element B as shown in FIGS. Thereafter, alignment is performed so that the upper and lower portions of the metal pins 22 of each semiconductor chip element are in contact with each other, and the semiconductor pins are bonded and fixed via the adhesive layer 14.

  In this example, the package substrate is removed from the semiconductor chip element A. However, the above-described alignment and adhesion fixing are performed by leaving the package substrate and newly forming an adhesive layer between the chip elements A and B. Can be implemented.

  13 to 15 are configuration diagrams showing other examples of the semiconductor chip mounting method of the present invention. Also in this example, the same reference numerals are used for the same or similar components as those in FIGS.

  In this example, first, according to the steps shown in FIGS. 1 to 3, the semiconductor chip 11 having the through-hole 13 formed therein is connected to each other through the adhesive layer 14 formed on the back surface of the upper semiconductor chip. Align and bond and fix so that they match. As a result, a semiconductor chip stacked body C as shown in FIG. 13 is produced.

  Next, a package substrate 21 as shown in FIG. 4 is prepared, the semiconductor chip laminated body shown in FIG. 13 is lowered instead of the semiconductor chip 11 shown in FIG. 4, and the metal pins 22 constitute the semiconductor chip laminated body C. It is inserted sequentially into each through hole of the upper and lower semiconductor chips.

  As a result, as shown in FIG. 14, first, the metal pin 22 penetrates the adhesive layer 14 of the lower semiconductor chip 11 and is inserted into the through hole 13 while winding a part of the adhesive layer 14. Thereafter, the adhesive layer 14 of the upper semiconductor chip 11 is reached, penetrates through the adhesive layer 14, and is inserted into the through hole 13 while being partly wound. Finally, as shown in FIG. 15, the through-holes in the upper semiconductor chip and the lower semiconductor chip of the semiconductor chip stacked body C are embedded in the enveloping portion 14 </ b> A of the adhesive layer 14 with the respective semiconductor chips. As a result, electrical insulation between the upper and lower semiconductor chips 11 and the metal pins 22 is ensured.

  Also in this example, the tip portion 22A of the metal pin 22 can be made of a low melting point conductive material such as solder. In this case, as shown in FIG. 15, the front end portion 22 </ b> A can be heated and melted to be flattened, and electrical contact with the metal wiring 15 can be ensured.

  While the present invention has been described in detail based on the above specific examples, the present invention is not limited to the above specific examples, and various modifications and changes can be made without departing from the scope of the present invention.

  For example, in the specific examples related to FIGS. 11 and 12 and the specific examples related to FIGS. 13 to 15, the semiconductor chips are stacked in two layers. The number of stacked layers is the required performance and miniaturization of semiconductor devices. Depending on the request, the number can be any number of 3 or more.

It is a figure which shows the first process in an example of the mounting method of the semiconductor chip of this invention. It is a figure which shows the next process of the process shown in FIG. It is a figure which shows the next process of the process shown in FIG. FIG. 4 is a diagram showing a step subsequent to the step shown in FIG. 3. It is a figure which shows the next process of the process shown in FIG. It is explanatory drawing which expands and shows the state in 1 process of the said mounting method. Similarly, it is explanatory drawing which expands and shows the state in one process of the said mounting method. Similarly, it is explanatory drawing which expands and shows the state in one process of the said mounting method. It is a figure which shows the following preferable process of the process shown in FIG. It is a figure which shows the modification of the said mounting method. It is a figure which shows one process in the other example of the mounting method of the semiconductor chip of this invention. FIG. 12 is a diagram showing a step subsequent to the step shown in FIG. 11. It is a figure which shows one process in the other example of the mounting method of the semiconductor chip of this invention. FIG. 14 is a diagram showing a step subsequent to the step shown in FIG. 13. FIG. 15 is a diagram showing a step subsequent to the step shown in FIG. 14.

Explanation of symbols

11 Semiconductor chip (semiconductor wafer)
12 Scrub line 13 Through hole (for semiconductor chip) 14 Adhesive layer 15 Metal wiring 21 Package substrate 22 Metal pin (standing on package substrate)

Claims (5)

Forming at least one through hole in the semiconductor chip;
Attaching an adhesive layer to the back side of the semiconductor chip;
Preparing a package substrate on which at least one metal pin is erected;
Bonding the semiconductor chip and the package substrate through the adhesive layer,
The step of bonding the semiconductor chip and the package substrate through the adhesive layer includes the metal pin winding a part of the adhesive layer into the through hole, and a part of the adhesive layer being the metal pin and the A semiconductor chip mounting method, wherein the semiconductor chip is inserted so as to bury a gap with a through hole. Forming a groove by performing groove processing at a position corresponding to a position where the through hole of the semiconductor chip is formed in the package substrate;
Forming the metal pin so as to stand in the groove formed on the package substrate,
2. The semiconductor chip mounting method according to claim 1, wherein the metal pins on the package substrate are inserted substantially linearly into the through holes of the semiconductor chip. A conductive material having a low melting point is provided at the tip of the metal pin of the package substrate,
After the metal pin of the package substrate is inserted into the through-hole of the semiconductor chip, the conductive material is heated and melted so that the wiring formed on the main surface of the semiconductor substrate and the metal pin are The method for mounting a semiconductor chip according to claim 1, further comprising a step of electrically conducting the semiconductor chip.   A plurality of steps in the mounting method according to any one of claims 1 to 3 is defined as one cycle, and the cycle is repeated a plurality of times, whereby the package substrate bonded through the semiconductor chip and the adhesive layer is used. The semiconductor chip element is laminated, and a plurality of the semiconductor chips into which the metal pins are inserted are laminated so that the inside of the through hole is embedded in a part of the adhesive layer. The mounting method of the semiconductor chip as described in any one of 1-3. A semiconductor chip mounting method comprising:
Preparing a plurality of semiconductor chips;
Forming at least one through hole for each semiconductor chip;
Laminating the plurality of semiconductor chips so that the through-holes formed in each semiconductor chip coincide with each other, and forming a semiconductor chip laminate,
Attaching an adhesive layer to at least the back surface of the semiconductor chip laminate;
Preparing a package substrate on which at least one metal pin is erected;
The semiconductor chip laminate and the package substrate are inserted in each through-hole of each semiconductor chip so that the metal pin wraps a part of the adhesive layer, and a part of the adhesive layer is the metal. A step of bonding through the adhesive layer so as to embed a gap between the pin and the through hole of each semiconductor chip;
A method of mounting a semiconductor chip, comprising:

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