JP2008103601A - Method for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technology which can enhance the operation efficiency of a prober in the prober having a continuous fail check function. <P>SOLUTION: A probe inspection is executed in a chip region to be inspected in a semiconductor wafer to be inspected (S103). As a result, in the case of failure determination (S104), a quality result of the chip region at the same coordinates of the semiconductor wafer which has been already measured is obtained (S105). In the chip region at the same coordinates of the semiconductor wafer which has been already measured, if failure determination is made (S106), a failure of the chip region to be inspected is regarded as a failure caused by regionality, and a continuous fail count is not incremented even if the failure determination is made in the chip region to be inspected. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a manufacturing technique of a semiconductor device, and more particularly to a technique that is effective when applied to an inspection process for determining whether an integrated circuit formed on a semiconductor wafer is good or bad on a chip area basis.

  In Japanese Patent Laid-Open No. 2001-102417 (Patent Document 1), coordinates (positions) of non-defective chips on a semiconductor wafer are stored in a storage means, and when defective chips are continuously generated a predetermined number of times, they are detected. A technique is described in which the coordinates of a non-defective chip in the storage means are selected and the semiconductor wafer and the probe card are moved relative to each other so that the chip is at the test position to perform the retest. After that, if the result of the retest is a non-defective product, the next chip after the continuous defective product is tested, and if the result of the retest is a defective product, relief processing for the probe card is performed.

Japanese Patent Application Laid-Open No. 08-340027 (Patent Document 2) discloses a step of performing electrical measurement by sequentially bringing a probe needle into contact with each chip in a semiconductor wafer to be measured, and a defective chip as a result of measurement in this step. In the case where a predetermined number is continued, a technique is described that includes a step of returning to a non-defective chip measured before these consecutive defective chips and sequentially contacting the probe needle again to perform electrical measurement. According to this technique, when defective chips continue as a result of measurement, the measurement is performed again by returning to the non-defective chip before the defective chip, so that the reliability of the measurement result can be improved.
JP 2001-102417 A Japanese Patent Laid-Open No. 08-340027

  After the integrated circuit is formed on the semiconductor wafer, an inspection (hereinafter referred to as a probe inspection) is performed to determine whether the integrated circuit is good or defective in each chip area. In this probe inspection, a semiconductor wafer is mounted on a wafer stage by a prober that includes a wafer stage, a wafer transfer device (loader), and a control unit. Then, the probe needle is brought into contact with the position of the pad formed in each chip region of the semiconductor wafer. The probe needle is formed on a probe card in which a plurality of probe needles are arranged at predetermined intervals. A probe card having a different probe needle arrangement pattern depending on the type of semiconductor wafer to be measured is used as one of the test jigs. From this probe card, signal lines corresponding to all probe needles come out, and these signal lines are connected to a tester.

  A pre-programmed signal waveform is input from the tester to the pad formed in the chip area while the probe needle is in contact with the pad formed in the chip area. Then, a constant signal waveform is output from other pads formed in the same chip region. By reading this output signal waveform with a tester, it is determined whether the integrated circuit formed in the chip region is good or bad.

  Normally, if a prober or probe card, which is a prober, functions properly, the integrated circuit formed on the chip area of the semiconductor wafer is judged as good or bad, and the probe test results are accurately integrated. It reflects the circuit characteristic failure. However, a failure determination may be made due to a failure of the prober itself or a failure of a test jig attached to the prober. In other words, although the integrated circuit to be inspected is normal, an erroneous determination may be made in the probe inspection due to a defect in a prober or a test jig as a measuring device. If an erroneous defect determination is made in the probe inspection, it is determined as a defective product even though it is a non-defective product, and normal inspection cannot be performed. Therefore, the prober has a continuous fail check function as a function for reducing the number of chip areas erroneously determined due to a defect of the prober itself or a defect of the test jig. The continuous fail check function is a function for forcibly stopping the prober by assuming that a defect in the prober or the test jig has occurred when a defect determination is made in a predetermined number of continuous chip regions. According to this continuous fail check function, it is possible to suppress erroneous defect determination caused by a problem of a prober or a test jig. A function currently set as the continuous fail check function will be described.

  First, basic functions will be described. As described above, the function to set the number of defects to be determined in the continuous chip area, and forcibly stop the prober when the defect determination is made in the chip area that is more than the set number in the actual probe inspection. There is. That is, the number of defective judgments in consecutive chip areas is counted as a continuous fail count, and the prober is stopped when the continuous fail count exceeds the set number. In this function, the prober is simply stopped when a failure is determined in a continuous chip area of a set number or more, and the failure determination is an erroneous failure determination due to a characteristic failure of the original integrated circuit itself or a failure of the prober itself. I do n’t know if For this reason, even if the characteristic failure of the original integrated circuit itself occurs continuously over the set number, the prober is forcibly stopped, and there is a problem that the operating rate of the probe inspection process is lowered. . That is, there is a problem that the number of times the prober is forcibly stopped increases even when it is not necessary to stop the prober.

  As a function for improving this problem, there is a function for presetting a chip area that is not subject to continuous fail check. For example, it is conceivable to exclude the row of chip regions formed on the outermost periphery of the semiconductor wafer from the continuous fail check. In other words, the chip region formed on the outermost periphery of the semiconductor wafer takes into consideration that the characteristic failure of the integrated circuit is likely to occur. According to this function, the characteristic failure of the chip area itself formed on the outermost periphery can be excluded from the continuous fail count, and it is possible to reduce the forced stop of the prober even when it is not necessary to stop. Similarly, the same effect can be obtained by selecting a row instead of a column of chip regions formed on the outermost periphery of the semiconductor wafer. However, this function is based on the premise that it is known in advance that a defective characteristic of the integrated circuit will occur in the target matrix. Therefore, it is difficult to specify a chip area in which a characteristic defect occurs reliably in a chip area formed in an area other than the outermost periphery, so the function of setting a chip area that is not subject to continuous fail check is not much. There is no effect.

  Further, as a function for improving the above-mentioned problems, there is a continuous fail checkback function. For example, it is assumed that the defect determination is performed more than the set number in the chip area continuous after the non-defective chip area. The failure determination performed at this time cannot be determined as a failure in the characteristics of the integrated circuit formed in the chip region or an erroneous failure determination due to a defect in the prober itself or the test jig. Therefore, the probe inspection is again performed in the chip region where the non-defective product is determined. As a result, if the non-defective product is determined again in the chip area where the non-defective product is determined, it can be understood that there is no defect in the prober and the test jig. In this case, the probe inspection is continued without stopping the prober. In other words, if more than the set number of defects are determined in the continuous chip area, the chip area determined to be non-defective is probed again, and the characteristics of the integrated circuit in which the continuous defect determination is formed in the chip area. It is possible to determine whether it is a failure or an erroneous failure determination due to a failure of the prober itself or the test jig itself.

  However, since the probe inspection is performed again by bringing the probe needle into contact with the pad in the chip area determined to be non-defective, the probe mark formed on the pad becomes large, and there is a problem that the reliability of the pad is lowered. . In addition, when the number of defective determinations in the probe inspection process increases, the number of times of remeasurement of the chip area that has been determined to be non-defective increases, and the throughput of the probe inspection process decreases.

  In addition to the functions described above, a method of dividing the chip area defect determination in the probe inspection into several categories is conceivable. In this case, it is effective if the characteristic classification of the integrated circuit can be distinguished from the erroneous defect determination caused by the prober or the test jig by the categorization, but in reality, it is difficult to categorize in this way.

  As described above, the presently provided functions of the continuous fail check function have been described. However, the setting contents include a function for determining the set number of continuous fail counts, a function for categorizing the target defect determination, and a continuous fail check. Various functions can be set, such as the function to set the area to exclude, but all of them are set in advance, and the characteristics of the integrated circuit formed in the chip area or the defect of the prober or test jig It is not possible to distinguish whether it is a false defect judgment caused by. For this reason, even if the characteristic failure of the integrated circuit itself occurs continuously, there is a problem that the prober is forcibly stopped because it is subject to continuous fail check. That is, with the current continuous fail check function, it is difficult to improve the operation efficiency of the prober while effectively preventing the erroneous defect determination caused by the prober and the test jig. Further, although there is a function of re-inspecting the chip area determined to be non-defective, there is a problem in that the reliability of the pad and the throughput of the probe inspection process are reduced as described above.

  An object of the present invention is to provide a technique capable of improving the operation efficiency of a prober in a prober having a continuous fail check function.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  According to a method of manufacturing a semiconductor device according to the present invention, an integrated circuit and a pad electrically connected to the integrated circuit are formed in a plurality of chip regions on a semiconductor wafer, and then the semiconductor wafer is mounted on a prober, and a probe is mounted on the pad. A step of performing an electrical characteristic test on the integrated circuit in units of the chip area by bringing a needle into contact therewith is provided. In addition, the present invention relates to a method of manufacturing a semiconductor device in which the prober is stopped when a continuous fail count indicating that a defect is detected in a predetermined number of consecutive chip regions exceeds a set number. Here, (a) a step of storing the pass / fail judgment result in the chip region of the semiconductor wafer that has already been inspected, and (b) the chip region that is the inspection target of the semiconductor wafer that is the inspection target. And a step of performing an electrical characteristic inspection. When a defect is detected in the chip area that is the inspection target of the semiconductor wafer that is the inspection target, it is determined that the defect is in the chip area at the same coordinate position of the semiconductor wafer that has already been inspected. In some cases, the continuous fail count is not increased even if the chip area to be inspected is defective.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  In the probe inspection process using a prober having a continuous fail check function, unnecessary stoppage of the prober can be reduced, and the operation efficiency of the prober can be improved.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

(Embodiment 1)
The probe inspection in the first embodiment will be described with reference to the drawings. FIG. 1 is a diagram showing a schematic configuration of a test system used in probe inspection according to the first embodiment. In FIG. 1, the test system 1 according to the first embodiment includes a prober 2, a probe card 3, and a tester 4.

  The prober 2 is a pad formed in a chip region of a semiconductor wafer in order to efficiently inspect the electrical characteristics of an integrated circuit such as an IC (Integrated Circuit) or an LSI (Large Scale Integration) formed on the semiconductor wafer. The probe needle (contact needle) is automatically brought into contact with the test needle 4 so that the electrical characteristics can be inspected by the tester 4 connected to the probe needle. It also has a function that makes it possible to identify a chip area that the tester has determined to be defective. Specifically, the prober 2 includes a wafer stage 5, a transfer unit 7, and a control unit 8. The wafer stage 5 is configured to arrange the semiconductor wafer 6, and the position of the arranged semiconductor wafer 6 can be adjusted. The position adjustment of the semiconductor wafer 6 is performed under the control of the control unit 8. By adjusting the position of the semiconductor wafer 6 placed by the wafer stage 5, the probe needle 3 a formed on the probe card 3 on the pad formed in the chip area to be inspected of the semiconductor wafer 6. Can be in contact.

  The transfer unit 7 is configured to be able to transfer a wafer carrier (not shown) in which, for example, a plurality (one lot) of semiconductor wafers 6 are stored, and one semiconductor from the wafer carrier. The wafer 6 is taken out, and the taken-out semiconductor wafer 6 can be placed on the wafer stage 5.

  The control unit 8 is configured to control the overall operation of the prober 2, and controls the position adjustment operation of the wafer stage 5, the transfer operation of the semiconductor wafer 6 by the transfer unit 7, and the like. The control unit 8 is composed of, for example, a CPU (Central Processing Unit) of a computer. That is, the prober 2 is equipped with a computer. Furthermore, the control unit 8 also has a continuous fail check function described later.

  A semiconductor wafer 6 is disposed on the wafer stage 5 of the prober 2, and a probe card 3 for bringing the probe needle 3 a into contact with the semiconductor wafer 6 is disposed on the semiconductor wafer 6. A plurality of probe needles 3 a formed on the probe card 3 are provided corresponding to pads formed on the chip region of the semiconductor wafer 6, respectively. That is, the probe needle 3 a is provided for each of the plurality of pads formed in the chip region of the semiconductor wafer 6. Since the position of the pad is different in the case of the semiconductor wafer 6 having a different product, the probe card 3 is replaced for each product. Therefore, it can be said that the probe card 3 is a test jig for performing probe inspection.

  The probe needle 3a formed on the probe card 3 is electrically connected to the tester 4, and the signal waveform from the tester 4 is input to the integrated circuit including the pad via the probe needle 3a. Similarly, the signal waveform output from the integrated circuit is input to the tester 4 via the probe needle 3a. The tester 4 is configured so as to be able to judge the quality of the integrated circuit formed in the chip region of the semiconductor wafer 6.

  An operation of performing a probe inspection using the test system 1 configured as described above will be described. The probe needle 3a of the probe card 3 is brought into contact with a pad formed in a chip region to be inspected of the semiconductor wafer 6. Then, in a state where the probe needle 3a is in contact with the pad, a signal waveform programmed in advance in the tester 4 is input from the tester 4 to the pad via the probe needle 3a. Then, the signal waveform input from the pad is processed by an integrated circuit formed inside the semiconductor wafer 6, and then a constant signal waveform is output from another pad formed in the same chip region. A constant signal waveform output from another pad is input to the tester 4 via the probe needle 3a. When the tester 4 receives a certain signal waveform, it analyzes it to determine whether the integrated circuit is good or bad. Thereafter, the same inspection is repeated for all chip regions formed on the semiconductor wafer 6. In this way, the quality of the integrated circuit formed in each chip region of the semiconductor wafer 6 can be inspected.

  Normally, if the prober 2 or the probe card 3 as a test jig functions normally, the integrated circuit formed in the chip area of the semiconductor wafer 6 is judged as good / bad, and the result of the probe inspection is It accurately reflects the defective characteristics of the integrated circuit. However, a failure determination may be made due to a failure of the prober 2 itself or a failure of a test jig attached to the prober. In other words, although the integrated circuit to be inspected is normal, an erroneous defect determination may be made in the probe inspection due to a defect in the prober 2 or the test jig as a measuring device. If an erroneous defect determination is made in the probe inspection, it is determined as a defective product even though it is a non-defective product, and normal inspection cannot be performed. Therefore, the prober 2 has a continuous fail check function as a function for reducing the number of chip areas erroneously determined due to a defect of the prober itself or a defect of the test jig. This continuous fail check function is a function that the control unit 8 of the prober 2 has. The basic function of the continuous fail check is to set the number of defective judgments in the continuous chip area, and in the actual probe inspection, if the defective judgment is made in the continuous chip area more than the set number, the prober 2 is turned on. This function forcibly stops. That is, the number of defective judgments in continuous chip areas is counted as a continuous fail count, and the prober 2 is stopped when the continuous fail count exceeds the set number. However, with this function alone, the prober 2 is simply stopped when a failure determination is made in a continuous chip area of a set number or more. The failure determination is a characteristic failure of the original integrated circuit itself or a failure of the prober itself. I don't know if it's wrong or bad. For this reason, since the prober 2 is forcibly stopped even if the characteristic failure of the original integrated circuit itself continuously occurs over the set number, the operation rate of the probe inspection process is lowered. is there. That is, there is a problem that the number of times the prober 2 is forcibly stopped increases even when it is not necessary to stop the prober 2.

  Therefore, in the first embodiment, the prober 2 is forcibly stopped even if characteristic failures of the original integrated circuit itself continuously occur in excess of the set number, assuming the basic function of the continuous fail check function described above. We have invented a new additional function that can reduce this. Before explaining the additional function that is the feature of the present invention, the preconditions will be described.

  In a pre-process for forming a MISFET (Metal Insulator Semiconductor Field Effect Transistor) or multilayer wiring on a semiconductor wafer, each process is often performed on a plurality of semiconductor wafers under the same conditions (same semiconductor manufacturing apparatus). For example, one lot of semiconductor wafers may be processed by the same semiconductor manufacturing apparatus. In this case, for example, when a defect is formed on a semiconductor wafer due to a defect of a certain semiconductor manufacturing apparatus, it is conceivable that the same defect occurs in the semiconductor wafer started by the semiconductor manufacturing apparatus. For example, if a patterning defect occurs due to an abnormality in the exposure apparatus used in the photolithography process, it is considered that this patterning defect appears in the same manner on all semiconductor wafers that have been started by the exposure apparatus in which the abnormality has occurred. That is, when a defect occurs in a specific area of a certain semiconductor wafer, there is a high possibility that a defect occurs in the same area in other semiconductor wafers. This defect is called, for example, a region-related defect. It is considered that such region-related defects often appear in the previous step of forming an integrated circuit on a semiconductor wafer. Of course, in the previous process, not all defects are caused by regionality, but it can be said that it is appropriate from the characteristics of the previous process that many integrated circuit failures are caused by regionality.

  In the present invention, attention is paid to the fact that, in the so-called pre-process performed before the probe inspection, the characteristic failure of the integrated circuit is often a region-related failure. If a defect is determined in a continuous chip area of the semiconductor wafer and the continuous fail count exceeds the set number, the prober is forcibly stopped as a problem with the prober or test jig. However, when the failure determination is a failure inherent in the integrated circuit, there is no problem with the prober or the test jig, and it is not necessary to forcibly stop the prober. That is, when the defect determination in the chip area is based on the defect of the integrated circuit itself, it is not necessary to add (increment) the continuous fail count.

  Here, paying attention to the fact that the failure of the integrated circuit itself is often a region-related failure, in the present invention, the failure of the integrated circuit itself and the error failure based on the failure of the prober or the test jig are considered. The distinction is characteristic. That is, when a defect determination is made in a chip area to be inspected of a semiconductor wafer to be inspected, first, a determination result of a chip area at the same coordinate of a measured semiconductor wafer that has already undergone probe inspection Refer to As a result, when the defect determination is made in the chip region at the same coordinate of the measured semiconductor wafer, this defect is regarded as a region-related defect. As a result, the cause of the defect in the chip area to be inspected of the semiconductor wafer to be inspected is determined to be a defect in the integrated circuit itself, and is not determined to be due to a defect in the prober or test jig. The Therefore, the continuous fail count is not added. This is one of the features of the present invention. On the other hand, when the normal determination (OK determination) is made in the chip region at the same coordinate of the measured semiconductor wafer, the defect due to the region property is not considered. Since it is impossible to determine whether the defect of the chip area to be inspected at this time is a defect of the integrated circuit itself or an error due to a defect of a prober or a test jig, a continuous fail count is added. As described above, according to the present invention, when a region-related failure occurs, the continuous fail count is not added. And the unnecessary forced prober stop can be reduced. Therefore, the operation efficiency of the prober can be improved while the continuous fail check function is functioning.

  Next, the structure which implement | achieves the additional function of this invention mentioned above is demonstrated. FIG. 2 is a functional block diagram mainly showing a configuration related to the continuous fail check function of the control unit 8 included in the prober 2 (see FIG. 1). As shown in FIG. 2, the control unit 8 and the tester 4 are configured to be able to communicate with each other. The tester 4 has a pass / fail judgment unit 41. When the pass / fail judgment unit 41 receives (inputs) a signal indicating that the probe needle is in contact with the pad formed in the chip region of the semiconductor wafer from the control unit 8, it is formed in the chip region to be inspected. The probe inspection of the integrated circuit is performed. Specifically, it has a function of outputting a pre-programmed signal waveform from the quality determination unit 41 of the tester 4 to the pad via the probe needle 3a. Then, a certain signal waveform output from another pad in the same chip area through the integrated circuit is input, and this is analyzed to determine whether the integrated circuit is good or bad. Then, the pass / fail result of the chip area to be inspected is output to the prober 2.

  The control unit 8 includes a pass / fail result storage unit 81, a measurement result acquisition unit 82, a measurement result determination unit 83, a comparison unit 84, a continuous fail count addition unit 85, a continuous fail count determination unit 86, and a prober stop unit 87. .

  The pass / fail result storage unit 81 is configured to store pass / fail results relating to the chip area of the measured semiconductor wafer that has already been inspected, and is configured by, for example, a nonvolatile memory or a hard disk. The pass / fail result storage unit 81 may be configured to store pass / fail results in all chip regions of the measured semiconductor wafer, such as wafer map data. (No) You may make it memorize | store the chip | tip area | region where the determination is made. Whichever storage method is used, the pass / fail judgment is stored in association with the coordinate position of the chip region on the semiconductor wafer. When only the chip area for which the defect determination is made is stored, it is determined that the chip area at the coordinate position that is not stored is determined to be normal.

  The measurement result acquisition unit 82 is configured to input the determination result in the chip region that is the inspection target of the semiconductor wafer that is the inspection target from the pass / fail determination unit 41 in the tester 4. This determination result is associated with the position coordinates of the chip area to be inspected. That is, it is possible to know at which position of the chip region of the semiconductor wafer to be inspected the determination result.

  The measurement result determination unit 83 is configured to determine whether the determination result acquired by the measurement result acquisition unit 82 is a normal (good) determination or a defective (not) determination.

  The comparison unit 84, when the determination result of the measurement result determination unit 83 is a failure determination, that is, when the probe inspection result of the chip region to be inspected of the semiconductor wafer to be inspected is a failure determination The pass / fail result stored in the pass / fail result storage unit 81 is acquired. Specifically, the pass / fail result of the chip area having the same coordinates as the chip area to be inspected of the semiconductor wafer to be inspected is retrieved and acquired from the chip area of the already measured semiconductor wafer. And when the quality result of the chip area | region of the acquired same coordinate is bad, it is comprised so that the defect of the chip | tip area | region used as to-be-inspected object may be judged as area property origin defect.

  Here, as the measured semiconductor wafer, for example, a semiconductor wafer included in the same lot as the semiconductor wafer to be inspected can be selected. This is because semiconductor wafers in the same lot are highly likely to be processed by the same semiconductor manufacturing apparatus in the previous process, and there is a high possibility that a defect due to area characteristics has occurred. That is, by selecting a semiconductor wafer that has already been measured and included in the same lot, it becomes easy to find a defect in an integrated circuit based on a region-related defect. In particular, among the semiconductor wafers included in the same lot, it is desirable to select the semiconductor wafer that has been subjected to the pre-process treatment immediately before the semiconductor wafer to be inspected as the measured semiconductor wafer. This is because a semiconductor wafer that has undergone a probe inspection immediately before is most likely to manifest when a region-related defect has occurred. That is, even when a semiconductor wafer of the same lot is selected as a measured semiconductor wafer, a predetermined number of semiconductor wafers may be interposed between the semiconductor wafer to be inspected. At this time, if a region-related defect occurs due to a defect in the semiconductor manufacturing apparatus from a semiconductor wafer later than the semiconductor wafer selected as the measured semiconductor wafer, the region-related defect occurs in the semiconductor wafer selected as the measured semiconductor wafer. It may not occur. On the other hand, if the semiconductor wafer immediately before the semiconductor wafer to be inspected is selected as the measured semiconductor wafer, this can be minimized.

  The continuous fail count adding unit 85 is configured to adjust a continuous fail count indicating the number of defective determinations in continuous chip regions based on the determination result of the comparison unit 84. Specifically, as a result of the comparison unit 84, if the defect determination is made even in the chip area at the same coordinate of the already measured semiconductor wafer, the defect is determined to be an area-related defect. That is, it is determined that the integrated circuit itself is defective, and is not determined to be erroneous based on a problem with a prober or a test jig. In such a case, the continuous fail count adding unit 85 is configured not to add the continuous fail count even if a failure is determined in the chip area to be inspected. On the other hand, as a result of the comparison unit 84, when the normal determination is made in the chip area at the same coordinate of the already measured semiconductor wafer, it is determined that the defect is not due to area characteristics, and the defect determination is made in the chip area to be inspected. A continuous fail count is added. Further, when normal determination is made in the chip area to be inspected, the continuous fail count is cleared (set to 0).

  The continuous fail count determination unit 86 is configured to determine whether or not the continuous fail count exceeds a preset number. The prober stop unit 87 is configured to forcibly stop the prober when the continuous fail count exceeds the preset number set by the continuous fail count determination unit 86.

  The prober according to the first embodiment is configured as described above, and the operation thereof will be described below with reference to FIGS.

  First, as a premise, it is assumed that the semiconductor wafer probe inspection is performed several times, and the good / bad result storage unit 81 shown in FIG.

  As shown in FIG. 3, first, a wafer carrier storing a lot of semiconductor wafers is prepared (S101). The semiconductor wafer housed in the wafer carrier is formed with integrated circuits and pads that are electrically connected to the integrated circuits in units of chip areas. Then, one semiconductor wafer to be inspected is taken out of the wafer carrier by the transporter of the prober, and the semiconductor wafer to be inspected is mounted on the wafer stage (S102). Subsequently, the position of the wafer stage is adjusted by the control unit 8, and the probe needle is brought into contact with the pad formed in the chip region to be inspected. When the probe needle normally contacts the pad, the control unit 8 outputs the information to the tester. When the quality determination unit 41 of the tester 4 inputs this information, the probe inspection is started. Specifically, the programmed signal waveform is input from the tester 4 to the pad via the probe needle. Then, the signal waveform input from the pad is processed by an integrated circuit inside the chip area to be inspected, and then a constant signal waveform is output from another pad formed in the same chip area. Is done. The constant signal waveform output from the other pad is input to the pass / fail judgment unit 41 of the tester 4 via the probe needle. In the pass / fail judgment unit 41, when a certain signal waveform is inputted, it is analyzed to judge pass / fail of the integrated circuit. In this way, the chip area is measured (S103).

  Subsequently, the determination result determined by the pass / fail determination unit 41 is output to the measurement result acquisition unit 82 of the prober. When the measurement result acquisition unit 82 acquires the determination result in the chip region to be inspected, the measurement result acquisition unit 82 outputs the determination result to the measurement result determination unit 83. The measurement result determination unit 83 confirms the determination result in the chip area to be inspected (S104). When the determination result is normal determination (OK determination), the measurement result determination unit 83 outputs to the continuous fail count addition unit 85 that the determination result is normal. The continuous fail count addition unit 85 clears the continuous fail count when a determination result indicating normal determination is input (S110). That is, the continuous fail count is set to “0”. Thereafter, the determination result (normal determination) of the chip area to be inspected is stored in the pass / fail result storage unit 81 (S111).

  On the other hand, when the determination result is a failure determination (fail determination), the measurement result determination unit 83 outputs to the comparison unit 84 that the determination result is defective. When the output from the measurement result determination unit 83 is input, the comparison unit 84 accesses the pass / fail result storage unit 81. Specifically, the comparison unit 84 includes a chip region having the same coordinates as the chip region to be inspected of the semiconductor wafer to be inspected and the measured semiconductor wafer stored in the pass / fail result storage unit 81. Search from the chip area and obtain the pass / fail result (S105). When the acquired pass / fail result is a defect determination (S106), the comparison unit 84 determines that the defect in the chip area to be inspected is an area-related defect. Then, the comparison unit 84 outputs this fact to the continuous fail count addition unit 85. The continuous fail count adding unit 85 does not add the continuous fail count when a determination result indicating that the failure is due to area characteristics is input. That is, since the area-related failure is a failure of the integrated circuit itself and is not an error failure based on a failure of the prober or the test jig, the continuous fail count is not added. Thereafter, the determination result (defect determination) of the chip area to be inspected is stored in the pass / fail result storage unit 81 (S111).

  On the other hand, the comparison unit 84 is a measured semiconductor wafer in which a chip region having the same coordinates as the chip region to be inspected of the semiconductor wafer to be inspected is stored in the pass / fail result storage unit 81. Consider a case where the chip area is searched and its pass / fail result is acquired, and the acquired pass / fail result is normal determination. In this case, the comparison unit 84 determines that the defect in the chip area to be inspected is not an area-related defect. Then, the comparison unit 84 outputs this fact to the continuous fail count addition unit 85. The continuous fail count adding unit 85 adds (increases) the continuous fail count when the defect of the chip area to be inspected is not the area-related defect (S107). When the continuous fail count is added by the continuous fail count adding unit 85, the continuous fail count determining unit 86 determines whether or not the continuous fail count exceeds the set number (S108). If the continuous fail count exceeds the set number, the prober is forcibly stopped by the prober stop unit 87 (S109). On the other hand, if the continuous fail count does not exceed the set number, the prober is not stopped. Thereafter, the determination result (defect determination) of the chip area to be inspected is stored in the pass / fail result storage unit 81 (S111).

  In this way, the probe inspection of the chip area to be inspected is completed. If the probe inspection is not completed for all the chip areas on the semiconductor wafer to be inspected, the above-described operation is repeated for the next chip area (S112). Thereafter, when the probe inspection is completed in all chip regions of the semiconductor wafer to be inspected, the probe inspection is performed on the next semiconductor wafer in the same lot (S113). This is repeated until probe inspection is completed for all semiconductor wafers in the lot. When processing is completed for all semiconductor wafers in the lot (S114), the wafer carrier is unloaded from the prober.

  According to the first embodiment, since a continuous failure count is not added when a region-related failure occurs, a failure of the integrated circuit itself based on the region-related failure is determined as a misjudgment failure due to a problem of a prober or a test jig. And the unnecessary forced prober stop can be reduced. On the other hand, if the failure is not due to area characteristics, a continuous fail count is added. Therefore, the operation efficiency of the prober can be improved while the continuous fail check function is functioning. In addition, unlike the technique described in the problem to be solved, probe inspection is not performed by bringing the probe needle into contact with the pad in the chip area that has been determined to be non-defective, so that the probe mark formed on the pad becomes large. It is possible to prevent the reliability of the pad from being lowered. In addition, even if the number of defective determinations in the probe inspection process increases, it is not necessary to re-measure the chip area that has been determined to be non-defective, so that the throughput of the probe inspection process can be prevented from decreasing.

  Next, the effect in this Embodiment 1 is demonstrated with a specific example. 4 and 5 are diagrams showing wafer map data in the probe inspection. The wafer map data shown in FIGS. 4 and 5 are for semiconductor wafers included in the same lot. For example, FIG. 4 shows the first semiconductor wafer 10A in the lot, and FIG. 5 shows the second semiconductor wafer 10B. In FIG. 4, each square area indicates a chip area, and “/” indicates that normality is determined in the chip area. “A” and “B” indicate defect determination. “A” and “B” are defects of the integrated circuit itself, and represent area-related defects. That is, also in FIG. 5, “A” and “B” are judged as defective, and similar defects appear at the same coordinate positions of the semiconductor wafer 10A and the semiconductor wafer 10B. In FIG. 5, it can be seen that there is a defect “C” in addition to the area-related defect. This “C” is not a region-related defect, but is a defect of the integrated circuit itself.

  First, probe inspection in the first embodiment will be described for the semiconductor wafer 10A shown in FIG. First, it is assumed that the set number of continuous fail counts is set to “4”. A probe inspection of a continuous chip region along the direction of the arrow in FIG. 4 is performed. At this time, the semiconductor wafer 10A is first inspected among the semiconductor wafers stored in the lot. Therefore, there is no measured semiconductor wafer that has already been measured in the same lot. For this reason, the probe inspection in the first embodiment is not performed, and the continuous fail count is added as in the conventional case. That is, the continuous fail count is added even though the continuous defect “B” is an area-related defect. As a result, the prober is forcibly stopped 14 times in the semiconductor wafer 10A shown in FIG.

  Next, a probe test is performed on the second semiconductor wafer 10B shown in FIG. At this time, the first semiconductor wafer 10A exists as a semiconductor wafer that has already been measured. The pass / fail results in all the chip regions of the semiconductor wafer 10A are stored. Therefore, in the probe inspection of the second semiconductor wafer 10B, the quality result of the first semiconductor wafer 10A can be referred to. For this reason, in the probe inspection of the second semiconductor wafer 10B, it can be seen that the defect “B” is an area-related defect. In other words, when a defect “B” occurs in the chip area to be inspected of the second semiconductor wafer 10B, in the first embodiment, the chip at the same coordinate position of the first semiconductor wafer 10A. The pass / fail result of the area can be acquired. In this case, since the pass / fail result of the chip area at the same coordinate position is defective (“B”), it is understood that the defect is due to area characteristics. Since the area-related failure is a failure of the integrated circuit itself, the continuous fail count is not added in the first embodiment. As a result, in the second semiconductor wafer 10B, the prober is not forcibly stopped even if four consecutive region-related defects (“A”, “B”) are detected in the four consecutive chip regions. In the second semiconductor wafer 10B, the prober is forcibly stopped only once when “C” that is not a region-related defect is continuously detected.

  On the other hand, if the first embodiment is not applied to the second semiconductor wafer 10B, the defect caused by the region cannot be distinguished, and the prober is forcibly stopped 15 times. become. As described above, according to the first embodiment, in the second and subsequent semiconductor wafers in the same lot, it is possible to drastically reduce the unnecessary forced prober stop due to the failure of the integrated circuit itself (failure due to the region property). It can be seen that the operation efficiency of the prober can be improved.

(Embodiment 2)
In the first embodiment, the pass / fail result of the chip area having the same coordinates as the chip area to be inspected of the semiconductor wafer to be inspected is retrieved and acquired from the chip area of the already measured semiconductor wafer. . And when the quality result of the acquired chip | tip area | region of the same coordinate is unsatisfactory, it is comprised so that the defect of the chip | tip area | region used as to-be-inspected object may be judged to be area property origin defect. At this time, an example in which a semiconductor wafer included in the same lot is used as the measured semiconductor wafer has been described. In the second embodiment, an example in which a semiconductor wafer included in a different lot is used as the measured semiconductor wafer will be described. To do.

  In the first embodiment, a semiconductor wafer in the same lot is used as the measured semiconductor wafer. For this reason, when the semiconductor wafer at the head of the lot is probe-inspected, there is no measured semiconductor wafer that has already been measured, and thus the present invention cannot be applied. That is, in the semiconductor wafer at the head of the lot, even if the defect is due to regionality, the continuous fail count is added, and unnecessary forced prober stop tends to occur.

  Therefore, in the second embodiment, semiconductor wafers of different lots are used as the measured semiconductor wafers. By configuring in this way, even when the semiconductor wafer at the head of the lot is probe-inspected, the semiconductor wafer in the lot measured before this lot can be referred to as the measured semiconductor wafer. Sex-related defects can be distinguished, and unnecessary forced stop of the prober can be reduced. That is, the present invention can also be applied to the probe inspection of the semiconductor wafer at the head of the lot, and the operation efficiency of the prober can be improved.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  In the embodiment, as shown in FIG. 2, the control unit 8 of the prober is configured to have a function for realizing the present invention. However, the present invention is not limited to this. For example, the function for realizing the present invention in the tester 4 You may comprise so that it may provide.

  The present invention can be widely used in the manufacturing industry for manufacturing semiconductor devices.

It is a figure which shows the structure of the test system in Embodiment 1 of this invention. It is a functional block diagram which shows the main structures of the control part of a prober. 3 is a flowchart showing an operation of a probe inspection process in the first embodiment. It is a figure which shows an example of the wafer map data of the semiconductor wafer in the head of a lot. It is a figure which shows an example of the wafer map data of the semiconductor wafer in the 2nd sheet of a lot.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Test system 2 Prober 3 Probe card 3a Probe needle 4 Tester 5 Wafer stage 6 Semiconductor wafer 7 Transfer part 8 Control part 10A Semiconductor wafer 10B Semiconductor wafer 41 Pass / fail judgment part 81 Pass / fail result storage part 82 Measurement result acquisition part 83 Measurement result judgment part 83 84 Comparison unit 85 Continuous fail count addition unit 86 Continuous fail count judgment unit 87 Prober stop unit

Claims (5)

After forming an integrated circuit and a pad electrically connected to the integrated circuit on a plurality of chip regions on a semiconductor wafer, the chip region is mounted by mounting the semiconductor wafer on a prober and contacting a probe needle to the pad A step of performing an electrical characteristic test on the integrated circuit in units;
When a continuous fail count indicating that a defect has been detected in a predetermined number of consecutive chip regions exceeds a set number, the method for manufacturing a semiconductor device stops the prober,
(A) storing a pass / fail judgment result in a chip region of a semiconductor wafer that has already been inspected;
(B) including a step of performing an electrical characteristic inspection on a chip region to be inspected of a semiconductor wafer to be inspected,
When a defect is detected in the chip area that is the inspection target of the semiconductor wafer that is the object to be inspected, when it is determined to be defective in the chip area at the same coordinate position of the semiconductor wafer that has already been inspected, A method of manufacturing a semiconductor device, characterized in that the continuous fail count is not increased even if a chip region to be inspected is defective. After forming an integrated circuit and a pad electrically connected to the integrated circuit on a plurality of chip regions on a semiconductor wafer, the chip region is mounted by mounting the semiconductor wafer on a prober and contacting a probe needle to the pad A step of performing an electrical characteristic test on the integrated circuit in units;
When a continuous fail count indicating that a defect has been detected in a predetermined number of consecutive chip regions exceeds a set number, the method for manufacturing a semiconductor device stops the prober,
(A) storing a pass / fail judgment result in a chip region of a semiconductor wafer that has already been inspected;
(B) including a step of performing an electrical characteristic inspection on a chip region to be inspected of a semiconductor wafer to be inspected,
When a defect is detected in a chip area to be inspected of a semiconductor wafer to be inspected, when it is determined to be normal in a chip area at the same coordinate position of a semiconductor wafer that has already been inspected, A method of manufacturing a semiconductor device, wherein the continuous fail count is increased. After forming an integrated circuit and a pad electrically connected to the integrated circuit on a plurality of chip regions on a semiconductor wafer, the chip region is mounted by mounting the semiconductor wafer on a prober and contacting a probe needle to the pad A step of performing an electrical characteristic test on the integrated circuit in units;
When a continuous fail count indicating that a defect has been detected in a predetermined number of consecutive chip regions exceeds a set number, the method for manufacturing a semiconductor device stops the prober,
(A) storing a pass / fail judgment result in a chip region of a semiconductor wafer that has already been inspected;
(B) including a step of performing an electrical characteristic inspection on a chip region to be inspected of a semiconductor wafer to be inspected,
When a defect is detected in the chip area that is the inspection target of the semiconductor wafer that is the object to be inspected, when it is determined to be defective in the chip area at the same coordinate position of the semiconductor wafer that has already been inspected, Even if the chip area to be inspected is defective, the continuous fail count is not increased.
A method of manufacturing a semiconductor device, wherein a semiconductor wafer that has been inspected is used as a semiconductor wafer that has already been inspected, immediately before the semiconductor wafer to be inspected. After forming an integrated circuit and a pad electrically connected to the integrated circuit on a plurality of chip regions on a semiconductor wafer, the chip region is mounted by mounting the semiconductor wafer on a prober and contacting a probe needle to the pad A step of performing an electrical characteristic test on the integrated circuit in units;
When a continuous fail count indicating that a defect has been detected in a predetermined number of consecutive chip regions exceeds a set number, the method for manufacturing a semiconductor device stops the prober,
(A) storing a pass / fail judgment result in a chip region of a semiconductor wafer that has already been inspected;
(B) including a step of performing an electrical characteristic inspection on a chip region to be inspected of a semiconductor wafer to be inspected,
When a defect is detected in the chip area that is the inspection target of the semiconductor wafer that is the object to be inspected, when it is determined to be defective in the chip area at the same coordinate position of the semiconductor wafer that has already been inspected, Even if the chip area to be inspected is defective, the continuous fail count is not increased.
A method of manufacturing a semiconductor device, wherein a semiconductor wafer that has already been inspected is one that is included in the same lot as the semiconductor wafer to be inspected. After forming an integrated circuit and a pad electrically connected to the integrated circuit on a plurality of chip regions on a semiconductor wafer, the chip region is mounted by mounting the semiconductor wafer on a prober and contacting a probe needle to the pad A step of performing an electrical characteristic test on the integrated circuit in units;
When a continuous fail count indicating that a defect has been detected in a predetermined number of consecutive chip regions exceeds a set number, the method for manufacturing a semiconductor device stops the prober,
(A) storing a pass / fail judgment result in a chip region of a semiconductor wafer that has already been inspected;
(B) including a step of performing an electrical characteristic inspection on a chip region to be inspected of a semiconductor wafer to be inspected,
When a defect is detected in the chip area that is the inspection target of the semiconductor wafer that is the object to be inspected, when it is determined to be defective in the chip area at the same coordinate position of the semiconductor wafer that has already been inspected, Even if the chip area to be inspected is defective, the continuous fail count is not increased.
A method for manufacturing a semiconductor device, wherein a semiconductor wafer that has already been inspected is used in a different lot from the semiconductor wafer to be inspected.

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