JP2008097503A - Timing analysis circuit and timing analysis method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a timing analysis circuit reducing burden of confirming timing restriction of an actual device. <P>SOLUTION: A bus master 111 synchronizes and transmits a reference clock signal and a synchronization signal showing a prescribed pattern. A re-timing part 112 delays and transmits the synchronization signal transmitted from the bus master 111. A bus slave 121 fetches the synchronization signal transmitted from the re-timing part 112 in synchronization with the reference clock signal, and stores the fetched synchronization signal into a storage part 122. An analysis part 113 adjusts a delay amount of the re-timing part 112, and adjusts the synchronization signal stored in the storage part 122. The analysis part 113 obtains a time lag amount generated between a pattern shown by the synchronization signal stored in the storage part 122 and the prescribed pattern. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a timing analysis circuit and a timing analysis method for analyzing circuit timing.

  In an apparatus such as an electronic device, for example, a synchronous bus is very important in transferring data between devices.

  There are various types of synchronous buses depending on the control method of the synchronous bus. For example, the synchronous bus includes a CPU processor bus, a PCI bus, an ATM (Asynchronous Transfer Mode) Utopia bus, and the like.

  In synchronous communication using these synchronous buses, the transmission side transmits a synchronization signal such as a control signal in synchronization with the clock signal, and the reception side takes in the synchronization signal in synchronization with the clock signal. At this time, there is a restriction for the receiving side to capture the synchronization signal normally. Hereinafter, this constraint is referred to as a timing constraint.

  FIG. 8 is a time chart for explaining timing constraints.

  Assume that at time 801, the transmission side transmits the clock signal and the synchronization signal to the reception side in synchronization.

  The synchronization signal includes a control signal for controlling transmission / reception of data, an address signal for specifying a transmission side or a reception side, and a data signal for transferring data. There are a plurality of address signals and data signals. FIG. 8 shows the mth address signal and data signal of the plurality of address signals and data signals. The reference CLK is a clock signal.

  The transmitted clock signal and synchronization signal cause a transmission delay due to transmission until reaching the receiving side. This delay time varies depending on, for example, waveform distortion due to the wiring length and impedance of the synchronous bus.

  It is assumed that at time 802, the receiving side captures the synchronization signal in synchronization with the clock signal.

  At this time, the receiving side must satisfy timing constraints in order to capture the synchronization signal normally. Specifically, the setup time and hold time must be satisfied.

  The setup time is the minimum value of the time (setup margin) that is necessary to normally capture the synchronization signal and before the synchronization signal is captured. The hold time is the minimum value of the time (hold margin) that is required after the synchronization signal is captured, which is necessary for normally capturing the synchronization signal.

  For this reason, the designer needs to design the electronic device so as to satisfy the timing constraint. Traditionally, such a design has been labor intensive.

  Japanese Patent Application Laid-Open No. 2003-27322 describes a circuit design method capable of designing a circuit so as to satisfy timing constraints. In this circuit design method, when circuit design information is input, timing analysis of the design information is performed. When an error occurs in the timing analysis, a variable cell capable of changing the signal delay amount is adjusted, and the error is eliminated.

Thereby, even when the timing constraint is not satisfied, the design can be changed so as to satisfy the constraint, and the labor required for the design can be reduced.
JP 2003-27322 A

  It is important to perform the analysis of timing constraints not only at the design stage but also on the manufactured actual device in order to ensure the reliability of the device.

  Conventionally, in the analysis of timing constraints on an actual apparatus, the state of a signal (such as a waveform) is measured by a measuring instrument such as a logic analyzer. Further, a person obtains a timing margin (a setup margin and a hold margin) from the measured signal state and confirms whether or not the timing constraint is satisfied. For this reason, labor is required.

  The circuit design method described in Patent Document 1 has been devised to reduce the labor required for circuit design, and there is no description about the analysis of timing constraints for an actual device.

  An object of the present invention is to provide a timing analysis circuit and a timing analysis method capable of reducing labor required for analyzing timing constraints of an actual apparatus.

  To achieve the above object, a storage unit, a transmission unit that transmits a synchronization signal indicating a predetermined pattern and a reference clock signal in synchronization, a delay unit that transmits the synchronization signal with delay, and the delay The synchronization signal transmitted from the transmission unit is captured in synchronization with the reference clock signal transmitted from the transmission unit, the reception unit that stores the captured synchronization signal in the storage unit, and the delay amount of the delay unit is adjusted. Adjusting the synchronization signal stored in the storage unit, comparing the pattern indicated by the synchronization signal stored in the storage unit with the predetermined pattern, and comparing the pattern indicated by the synchronization signal with the predetermined pattern. And an analysis unit for obtaining a delay amount at which the deviation occurs.

  The timing analysis method of the present invention is a timing analysis method performed by a timing analysis circuit, a transmission step of synchronizing a synchronization signal indicating a predetermined pattern and a reference clock signal, and delaying the synchronization signal. A delay step for transmitting, a capture step for capturing the delayed and transmitted synchronization signal in synchronization with the transmitted reference clock signal, a storage step for storing the captured synchronization signal, and the synchronization An adjustment step of adjusting a delay amount of the signal to adjust the stored synchronization signal; comparing a pattern indicated by the stored synchronization signal with the predetermined pattern; and a pattern indicated by the synchronization signal; An analysis step for obtaining a delay amount that causes a deviation from a predetermined pattern.

  According to the above invention, the amount of delay that causes a shift in the pattern is obtained. The amount of delay that causes a shift in the pattern reflects the setup margin.

  Therefore, it is possible to know the setup margin without measuring the signal state. If the setup margin is known, it can be determined whether or not the timing constraint is satisfied. Therefore, it is possible to reduce the labor required for analyzing the timing constraints of the actual device.

  A receiving unit that receives the reference clock signal from the generating unit that generates the reference clock signal and transmits the reference clock signal; and the analysis unit multiplies the reference clock signal transmitted from the receiving unit. A multiplying unit that generates a plurality of multiplied clock signals and transmits the plurality of multiplied clock signals; a control unit that selects one multiplied clock signal from the plurality of multiplied clock signals transmitted from the multiplying unit; A delay generation unit that generates a delayed clock signal in synchronization with the multiplied clock signal selected by the control unit from the reference clock signal transmitted from the reception unit, and transmits the delayed clock signal. The unit transmits the synchronization signal and the reference clock signal transmitted from the reception unit in synchronization, and the delay unit transmits the synchronization signal transmitted from the transmission unit to the delay It is desirable to transmit in synchronism with the delayed clock signal transmitted from the generating unit.

  According to the above invention, the synchronization signal is transmitted in synchronization with the delayed clock signal. As a result, the synchronization signal is delayed by the delay amount of the delayed clock signal.

  For this reason, it is possible to accurately adjust the delay amount of the synchronization signal.

  In addition, it is preferable that a correction unit that transmits the reference clock signal transmitted from the transmission unit with a delay is further included, and the analysis unit adjusts a delay amount of the correction unit based on the obtained delay amount. .

  According to the above invention, the delay amount of the reference clock signal is adjusted based on the delay amount of the synchronization signal that causes a shift in the pattern.

  For this reason, the timing margin of the synchronization signal can be adjusted to a desired value.

  Further, the control unit further includes a correction unit that transmits the reference clock signal transmitted from the transmission unit in synchronization with the delay clock signal transmitted from the delay generation unit, and the control unit is based on the obtained delay amount. Preferably, the delay generator selects a multiplied clock signal that synchronizes the reference clock signal.

  According to the above invention, the reference clock signal is transmitted in synchronization with the delayed clock signal. As a result, the reference clock signal is delayed by the delay amount of the delayed clock signal.

  Therefore, it is possible to accurately adjust the delay amount of the reference clock signal.

  According to the present invention, it is possible to reduce the labor required for analyzing the timing constraint of an actual device.

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 is a block diagram showing a configuration of a timing analysis circuit according to an embodiment of the present invention.

  In FIG. 1, the timing analysis circuit includes devices 101 and 102.

  The device 101 is a data transmission device, and the device 102 is a data reception device.

  The devices 101 and 102 perform synchronous communication via the synchronous bus 103. The devices 101 and 102 are connected via a signal bus 104.

  The device 101 includes a bus master 111, a retiming unit 112, and a timing analysis function unit 113.

  The device 102 includes a bus slave 121 and a storage unit 122.

  The bus master 111 is an example of a transmission unit.

  The bus master 111 performs synchronous communication with the bus slave 121. Specifically, the bus master 111 transmits the synchronization signal and the reference clock signal to the bus slave 121 in synchronization.

  There are a plurality of synchronization signals. For example, the synchronization signal includes a control signal for controlling transmission / reception of data, an address signal for specifying a transmission destination of data, and a data signal for transferring data. Control signals include a CS signal, a WE signal, and an RE signal. The number of address signals and data signals is assumed to be m. Note that m is an integer of 1 or more.

  The bus master 111 transmits a synchronization signal for data transfer and a reference clock signal to the bus slave 121.

  In addition, when the analysis unit 113 sets the analysis mode, the bus master 111 stops transmission of a synchronization signal for data transfer. After that, when receiving a test request from the analysis unit 113, the bus master 111 transmits the next reference clock signal and a synchronization signal indicating a predetermined pattern in synchronization.

  The predetermined pattern is, for example, a repetition of 1 and 0. The predetermined pattern is not limited to repetition of 1 and 0, but can be changed as appropriate. In this embodiment, a 32-bit signal “0x55555555” consisting of repetition of 1 and 0 is used as a synchronization signal indicating a predetermined pattern. Hereinafter, a synchronization signal indicating a predetermined pattern is referred to as a test signal. The bus master 111 holds the predetermined pattern.

  The test request is information indicating that a test signal is transmitted.

  The retiming unit 112 is an example of a delay unit.

  The retiming unit 112 transmits the synchronization signal transmitted from the bus master 111 to the bus slave 121. At this time, the retiming unit 112 delays the transmitted synchronization signal and transmits it to the bus slave 121 when it is on.

  When the bus master 111 transmits a synchronization signal for data transfer, the retiming unit 112 is controlled by the analysis unit 113 so as to be turned off.

  The bus slave 121 is an example of a receiving unit.

  The bus slave 121 captures the synchronization signal transmitted from the retiming unit 112 in synchronization with the reference clock signal transmitted from the bus master 111.

  When the storage unit 122 sets the analysis mode, the bus slave 121 stops capturing the synchronization signal for data transfer. Note that the analysis unit 113 and the storage unit 122 set the analysis mode at the same time.

  Thereafter, when the bus slave 121 receives the start signal from the analysis unit 113, the bus slave 121 captures the synchronization signal transmitted from the retiming unit 112 in synchronization with the reference clock transmitted next. The start signal is a signal indicating the start of transmission of the test signal.

  At this time, the bus master 111 is transmitting a test signal. For this reason, the synchronization signal captured by the bus slave 121 is also a test signal.

  The bus slave 121 stores the acquired test signal in the storage unit 122 with identification information for specifying the test signal.

  In order for the bus slave 121 to capture the synchronization signal normally, the hold time and the setup time must be satisfied.

  When the hold time or setup time is not satisfied, the pattern indicated by the acquired synchronization signal is different from the pattern indicated by the synchronization signal transmitted by the bus master 111. For example, when the bus master 111 transmits a test signal “0x55555555”, the bus slave 121 receives a signal “0xAAAAAAAA” that is one bit different from the test signal “0x55555555”.

  The analysis unit 113 holds a predetermined pattern.

  When the analysis unit 113 sets the analysis mode for itself, the analysis unit 113 adjusts the delay amount of the retiming unit 112 and adjusts the test signal stored in the storage unit 122. Note that the analysis unit 113 holds the adjusted delay amount.

  The analysis unit 113 compares the pattern indicated by the test signal stored in the storage unit 122 with the predetermined pattern held therein, and causes a delay that causes a shift between the pattern indicated by the test signal and the predetermined pattern. Find the amount.

  For example, first, when the analysis unit 113 sets the analysis mode for itself, the analysis unit 113 adjusts the delay amount of the retiming unit 112 to the initial value. Note that the initial value is 0 in this embodiment.

  Thereafter, the analysis unit 113 repeats the following operation until a delay amount that causes a deviation between the pattern indicated by the test signal stored in the storage unit 122 and a predetermined pattern is obtained.

  Specifically, the analysis unit 113 transmits a test request to the bus master 111 and simultaneously transmits a start signal to the bus slave 121 via the signal bus 104.

  When the bus master 111 finishes transmitting the test signal, the analysis unit 113 compares the pattern indicated by the test signal stored in the storage unit 122 with the predetermined pattern held.

  If the pattern indicated by the test signal does not deviate from the predetermined pattern, the analysis unit 113 increases the delay amount of the retiming unit 112 by 1, and simultaneously transmits the test request and the start signal again.

  On the other hand, if the pattern indicated by the test signal deviates from the predetermined pattern, the analysis unit 113 shifts the delay amount of the retiming unit 112 at that time between the pattern indicated by the test signal and the predetermined pattern. Is obtained as the delay amount of the test signal in which Hereinafter, the delay amount of the test signal that causes a shift between the pattern indicated by the test signal and the predetermined pattern is referred to as a shift delay amount.

  Note that the analysis unit 113 compares the test signal with a predetermined pattern for each test signal stored in the storage unit 122 to obtain a shift delay amount.

  The shift delay amount reflects the setup margin. Therefore, it is possible to know the setup margin without measuring the signal state. If the setup margin is known, it can be determined whether or not the timing constraint is satisfied.

  In addition, it is possible to know the setup margin without measuring the wiring length and impedance of the synchronous bus 103. For this reason, this timing analysis circuit can reduce the labor required to analyze the timing constraint of the actual device regardless of the type of the synchronous bus.

  Note that the number of devices on the receiving side is only one, but there may actually be a plurality of devices. In this case, the device 101 obtains the shift delay amount for each of the plurality of receiving devices.

  Next, the configuration of the timing analysis circuit will be described in more detail.

  FIG. 2 is a block diagram showing a detailed configuration of the timing analysis circuit according to the embodiment of the present invention. In FIG. 2, the same components as those in FIG. In the following, a configuration different from the configuration described in FIG. 1 will be mainly described.

  In FIG. 2, the timing analysis circuit includes devices 101 and 102.

  Devices 1 and 2 are connected to a CPU (not shown). The device 1 is connected to the reference clock generation unit 105. The reference clock generation unit 105 generates a reference clock signal and transmits the reference clock signal to the device 101.

  The device 101 includes a bus master 111, a retiming unit 112, an analysis unit 113, a data buffer 114, and a reception unit 115. The analysis unit 113 includes a setting register 201, a multiplication unit 202, a DelayCLK generation unit 203, an analysis control unit 204, and a result storage unit 205.

  The device 102 includes a bus slave 121, a storage unit 122, and a data buffer 123. The storage unit 122 includes a setting register 211, a storage control unit 212, and a memory 213.

  When the retiming unit 112 is on, the retiming unit 112 transmits the test signal transmitted from the bus master 111 in synchronization with the delay clock signal transmitted from the DelayCLK generating unit (hereinafter referred to as delay generating unit) 203. The delayed clock signal is a signal obtained by delaying the reference clock signal. As a result, the retiming unit 112 transmits the test signal after delaying the delay amount of the delayed clock signal.

  The data buffer 114 stores data transmitted with a synchronization signal for data transfer.

  The receiving unit 115 receives the reference clock signal from the reference clock generation unit 105, and sends the reference clock signal to the bus master 111 and the analysis unit 113 (specifically, the multiplication unit 202, the delay generation unit 203, and the analysis control unit 204). Send. The bus master 111 and the analysis unit 113 receive the reference clock signal having the same phase.

  The setting register 201 and the result storage unit 205 are connected to the CPU.

  When receiving a setting signal indicating ON from the CPU, the setting register 201 sets the analysis mode for itself.

  The multiplier 202 multiplies the reference clock signal transmitted from the reception unit 115 to generate a plurality of multiplied clock signals, and transmits the plurality of multiplied clock signals to the delay generator 203. The plurality of multiplied clock signals have different delay amounts with respect to the reference clock signal. Further, the multiplication number of the multiplication unit 202 is an integer.

  The delay generation unit 203 generates a delayed clock signal by delaying the reference clock signal transmitted from the reception unit 115 based on the plurality of multiplied clock signals transmitted from the multiplication unit 202. Specifically, the delay generation unit 203 generates the delay clock signal in synchronization with the reference clock signal selected by the analysis control unit 204 among the plurality of multiplied clock signals.

  The delay generation unit 203 generates delayed clock signals having different delay amounts according to the multiplied clock signal that synchronizes the reference clock signal. The number of delay clock signals having different delay amounts that can be generated by the delay generation unit 203 is equal to the number of multiplied clock signals generated by the multiplication unit 202, that is, the multiplication number of the multiplication unit 202. For this reason, it becomes possible to finely adjust the delay amount of the test signal of the retiming unit 112 as the multiplication number increases.

  The delay generation unit 203 transmits the generated delayed clock signal to the retiming unit 112.

  The analysis control unit 204 is an example of a control unit. The analysis control unit 204 holds a predetermined pattern.

  When the setting register 201 sets the analysis mode, the analysis control unit 204 generates one multiplied clock signal from the multiple clock signals generated by the multiplication unit 202, and a multiplied clock signal in which the delay generation unit 203 synchronizes with the reference clock signal. Choose as. The analysis control unit 204 identifies the multiplied clock signal by the delay amount of the multiplied clock signal. Further, the analysis control unit 204 holds the delay amount of the selected multiplied clock signal.

  Also, the analysis control unit 204 compares the pattern indicated by the test signal stored in the storage unit 122 with a predetermined pattern held therein to obtain a shift delay amount.

  For example, first, when the setting register 201 sets the analysis mode, the analysis control unit 204 adjusts the delay amount of the retiming unit 112 to the initial value “0”. Note that the analysis control unit 204 may leave the retiming unit 112 off, or turn on the retiming unit 112 and the multiplied clock signal synchronized with the delay generation unit 203 has a delay amount of 0. May be selected as a multiple clock signal.

  Thereafter, the analysis control unit 204 repeats the following operation until the deviation delay amount is obtained.

  Specifically, the analysis control unit 204 transmits a test request to the bus master 111 and simultaneously transmits a start signal to the bus slave 121 via the signal bus 104.

  When the bus master 111 finishes transmitting the test signal, the analysis control unit 204 checks whether or not the pattern indicated by the test signal stored in the storage unit 122 is different from the predetermined pattern.

  If the pattern indicated by the test signal does not deviate from the predetermined pattern, the analysis control unit 204 selects the multiplied clock signal synchronized with the delay generation unit 203 as the multiplied clock signal with the delay amount increased by 1, and again , Send test request and start signal.

  On the other hand, if the pattern indicated by the test signal is different from the predetermined pattern, the analysis control unit 204 obtains the delay amount of the retiming unit 112 at that time as the deviation delay amount. The delay amount of the retiming unit 112 is equal to the delay amount of the multiplied clock signal synchronized with the delay generation unit 203.

  Note that the analysis control unit 204 compares the test signal with a predetermined pattern for each piece of identification information attached to the test signal stored in the storage unit 122 to obtain a shift delay amount.

  When the analysis control unit 204 obtains the shift delay amount, the analysis control unit 204 stores the shift delay amount in the result storage unit 205 as the analysis result. The analysis unit 204 stores the shift delay amount with identification information for specifying the test signal of the shift delay amount.

  When the result storage unit 205 receives a result acquisition request for acquiring an analysis result from the CPU, the result storage unit 205 transmits the stored analysis result to the CPU.

  The bus slave 121 captures the synchronization signal transmitted from the retiming unit 112 in synchronization with the reference clock signal transmitted from the bus master 111.

  If the analysis mode is not set for itself, the bus slave 121 stores the acquired synchronization signal in the data buffer 123. If the analysis mode is set for itself, the bus slave 121 receives the acquired synchronization signal (test signal). The data is stored in the memory 213 of the storage unit 122.

  When receiving a setting signal indicating ON from the CPU, the setting register 211 sets the analysis mode for itself.

  The storage control unit 212 sets the analysis mode in the bus slave 121 when the setting register 211 sets the analysis mode.

  Next, the operation will be described.

  First, the data transfer operation will be described.

  Note that the reference clock generation unit 105 generates a reference clock signal regardless of whether the analysis mode is set in the setting registers 201 and 211, and generates the reference clock signal as the bus master 111 and the multiplication unit 202. To the delay generation unit 203 and the analysis control unit 204. Further, the retiming unit 112 is off.

  The bus master 111 always receives the reference clock signal from the reception unit 115.

  The bus master 111 acquires data from the data buffer 114 and generates a data signal indicating the data. The bus master 111 transmits the data signal, control signal, and address signal and the received reference clock signal in synchronization. At this time, the bus master 111 transmits the reference clock signal to the bus slave 121 via the synchronization bus 103, and transmits the synchronization signal (data signal, control signal, and address signal) to the retiming unit 112.

  When receiving the synchronization signal, the retiming unit 112 transmits the synchronization signal to the bus slave 121 via the synchronization bus 103 without delay. This is because the retiming unit 112 is off.

  The bus slave 121 receives a reference clock signal from the bus master 111 and receives a synchronization signal from the retiming unit 112.

  The bus slave 121 captures the synchronization signal in synchronization with the reference clock signal, and stores the captured synchronization signal in the data buffer 123. Note that the synchronization signal capturing process is the same as the conventional process, and thus detailed description thereof is omitted.

  Next, the transition to the analysis mode will be described.

  It is assumed that a setting signal indicating ON is received from the CPU while the bus master 111 is transferring data to the setting registers 201 and 211.

  When the setting registers 201 and 211 receive a setting signal indicating ON from the CPU, they set the analysis mode for themselves.

  When setting the analysis mode, the setting register 201 transmits the setting signal to the analysis control unit 204.

  When the analysis control unit 204 receives the setting signal, the analysis control unit 204 transmits the setting signal to the bus master 111.

  When the bus master 111 receives the setting signal, the bus master 111 stops acquiring the data from the data buffer 114 and transmitting a synchronization signal for transferring the data, and then sets the analysis mode to itself.

  Further, when setting the analysis mode for itself, the setting register 211 transmits the setting signal to the storage control unit 212. When the storage control unit 212 receives the setting signal, the storage control unit 212 transmits the setting signal to the bus slave 121.

  When the bus slave 121 receives the setting signal, the bus slave 121 stops taking in the synchronization signal, and then sets the analysis mode to itself.

  Next, the operation in the analysis mode will be described.

  The multiplier 202 always receives the reference clock signal from the accepting unit 115.

  The multiplier 202 multiplies the reference clock signal to generate a plurality of multiplied clock signals, and transmits the plurality of multiplied clock signals to the delay generator 203.

  The delay generation unit 203 always receives the reference clock signal from the reference clock generation unit 105 and always receives the multiplied clock signal from the multiplication unit 202. Further, the delay generation unit 203 receives a select signal from the analysis control unit 204. The select signal specifies a multiplied clock signal that synchronizes the reference clock signal. In this embodiment, the select signal indicates the delay amount of the specified multiplied clock signal.

  FIG. 3 is a time chart for explaining an example of the operation of the delay generation unit 203. In FIG. 3, the multiplication number of the multiplication unit 202 is 10.

  In FIG. 3, reference CLK is a reference clock signal, multiplied CLK is a multiplied clock signal, and DLYCLK # 1 to # 9 are delayed clock signals.

  In the case of FIG. 3, since the multiplication number is 10, the number of delay clock signals with different delay amounts that can be generated by the delay generation unit 203 is 10. FIG. 3 shows nine delayed clock signals (DLYCLK # 1 to # 9) among the delay clock signals that can be generated.

  The remaining one delayed clock signal is a delayed clock signal that is generated in synchronization with the multiplied clock signal whose delay amount is “0”, and has the same phase as the reference clock signal.

  The delay generation unit 203 generates any one of the 10 delay clock signals that can be generated by synchronizing the reference clock signal with the multiplied clock signal specified by the select signal.

  Note that the multiplication unit 202 and the delay generation unit 203 perform the above operation regardless of whether the setting register 201 sets the analysis mode or the analysis mode.

  The retiming unit 112 receives a synchronization signal from the bus master 111 and receives a delayed clock signal from the delay generation unit 203.

  When the retiming unit 112 is off, the retiming unit 112 transmits the received synchronization signal to the bus slave 121 without delay.

  When the retiming unit 112 receives a switch signal indicating ON from the analysis control unit 204, the retiming unit 112 is turned ON.

  FIG. 4 is a time chart for explaining an example of the operation of the retiming unit 112 when turned on. In FIG. 4, reference CLK is a reference clock signal.

  Since retiming section 112 performs the same operation for each of the plurality of synchronization signals, in FIG. 4, the CS signal of the control signal will be described as an example, and a description of the synchronization signal different from the CS signal Is omitted. Further, it is assumed that the multiplication number of the multiplication unit 202 is 20.

  The retiming unit 112 transmits the CS signal to the bus slave 121 in synchronization with the delayed clock signal. As a result, the retiming unit 112 delays the CS signal by the delay amount of the delayed clock signal.

  In FIG. 4, since the multiplication number is 20, the delay generation unit 203 can generate delayed clock signals with 20 different delay amounts, and therefore the retiming unit 112 also has CS with 20 different delay amounts. It is possible to output a signal. In FIG. 4, CS signals with delay amounts of 0 to 3 and 19 are shown.

  After transmitting the setting signal to the bus master 111, the analysis control unit 204 adjusts the delay amount of the test signal of the retiming unit 112 to 0 thereafter. Specifically, the switch control signal indicating ON is transmitted to the retiming unit 112, and the select signal indicating the delay amount “0” is transmitted to the delay generation unit 203. Note that the analysis control unit 204 may leave the retiming unit 112 off.

  After adjusting the delay amount, the analysis control unit 204 transmits a test request to the bus master 112 and executes a test signal transfer process.

  FIG. 5 is a time chart for explaining test signal transfer processing.

  In FIG. 5, the mth address signal and data signal are shown. Further, the CS signal of the control signal is shown. Reference CLK is a reference clock signal, and START is a start signal.

  At time 501, the analysis control unit 204 transmits a start signal and a test request in synchronization with the reference clock signal. At this time, the analysis control unit 204 transmits a test request to the bus master 111 and transmits a start signal to the bus slave 121 via the signal bus 104.

  When receiving the test request at time 502, the bus master 111 transmits the next reference clock and test signal in synchronization. It is desirable that the next reference clock signal that has received the test request is designed to be a reference clock signal next to the reference clock signal that is synchronized with the start signal by the analysis control unit 204.

  At time 503, when the bus slave 121 receives the start signal, the bus slave 121 captures the test signal received from the bus master 111 in synchronization with the next reference clock signal. It is desirable that the next reference clock signal that has received the start signal is designed to be the next reference clock signal after the reference clock signal that is synchronized with the start signal by the analysis control unit 204.

  The bus slave 121 stores each of the captured test signals in the memory 213 with identification information for specifying the test signal.

  On the other hand, when the transmission of the test signal is completed, the bus slave 121 transmits an end signal indicating the end of the transmission of the test signal to the analysis control unit 204.

  When the analysis control unit 204 receives the end signal, the analysis control unit 204 acquires the test signal stored in the memory 213.

  Specifically, the analysis control unit 204 transmits an acquisition request for acquiring a test signal to the bus master 111. When receiving the acquisition request, the bus master 111 transmits a control signal indicating acquisition of the test signal to the bus slave 121 via the synchronous bus 104. When the bus slave 121 receives the control signal, the bus slave 121 acquires a test signal from the memory 213 and transmits the test signal to the bus master 111 via the synchronous bus 104 as a data signal. When the bus master 111 receives the test signal, the bus master 111 transmits the test signal to the analysis control unit 204. The analysis control unit 204 receives the test signal.

  The analysis control unit 204 checks for each test signal whether the pattern indicated by the test signal is deviated from the predetermined pattern held.

  If the pattern indicated by the test signal is different from the predetermined pattern, the analysis control unit 204 obtains the held delay amount as the shift delay amount.

  On the other hand, if the pattern indicated by the test signal does not deviate from the predetermined pattern, the analysis control unit 204 sends a select signal indicating a delay amount obtained by increasing the held delay amount by 1 to the delay generation unit 203. Send. When the retiming unit 112 is off, the analysis control unit 204 transmits a switch control signal indicating on to the retiming unit 112.

  Thereafter, the analysis control unit 204 transmits the start signal and the test request again in synchronization with the reference clock signal.

  The analysis control unit 204 repeats the above processing for all test signals until the pattern indicated by the test signal is different from the predetermined pattern.

  FIG. 6 is a time chart for explaining the timing analysis. The CS signal of the control signal will be described as an example, and description of other test signals will be omitted. In FIG. 6, CS signals with delay amounts of 0, n−1 and n are shown. Reference CLK is a reference clock signal, and START is a start signal.

  In this embodiment, the test signal transmitted by the bus master 111 is a 32-bit signal consisting of repetitions of 1 and 0. Therefore, when the bus slave 121 normally captures the test signal, it becomes “0x55555555”. If the timing constraint margin is not satisfied due to the delay by the retiming unit 112 and the phase is shifted because the data cannot be captured normally, the test signal becomes, for example, “0xAAAAAA”.

  The CS signal transmitted by the bus master 111 has a transmission delay due to waveform distortion due to the wiring length and impedance of the synchronous bus 104.

  Assume that the bus slave 121 takes in the CS signal in synchronization with the reference clock signal at time 601.

  When the CS signal delay amount of the retiming unit 112 is 0, the setup margin of the control signal is time 602.

  The setup margin decreases as the CS signal delay amount of the retiming unit 112 increases.

  It is assumed that the setup margin becomes shorter than the setup time when the CS signal delay amount of the retiming unit 112 is n. In this case, the bus slave 121 captures “0x55555555” as the CS signal when the delay amount of the retiming unit 112 is 0 to n−1, and captures “0xAAAAAA” as the CS signal when the delay amount is n.

  When the analysis control unit 204 acquires the CS signal when the delay amount is 0 to n−1, the analysis control unit 204 determines that the pattern indicated by the CS signal is not shifted from the predetermined pattern.

  On the other hand, when acquiring the CS signal when the delay amount is n, the analysis control unit 204 determines that the pattern indicated by the CS signal is different from the predetermined pattern. The analysis control unit 204 obtains the held delay amount n as a shift delay amount.

  Further, the analysis control unit 204 may obtain the following values.

  When the analysis control unit 204 obtains the deviation delay amount n, the analysis control unit 204 obtains the delay amount n−1 before the deviation delay amount. The analysis control unit 204 obtains a delay time obtained by multiplying the delay amount n−1 by the period of the multiplied clock signal as a setup margin. In this case, the analysis control unit 204 holds the cycle of the multiplied clock signal.

  The delay time actually indicates a value obtained by subtracting the setup time from the setup margin. The analysis control unit 204 may hold the setup time, and obtain a setup margin by adding the delay time to the setup time.

  The analysis control unit 204 obtains a remaining time obtained by subtracting the obtained setup margin from the period of the reference clock signal as a hold margin.

  The remaining time actually indicates a value obtained by adding the setup time to the hold margin. The analysis control unit 204 may hold the setup time and obtain a time obtained by subtracting the setup time from the remaining time as a hold margin.

  When the analysis control unit 204 obtains the shift delay amount, the setup time, and the hold time, the analysis control unit 204 stores the shift delay amount, the setup time, and the hold time in the result storage unit 205 as analysis results.

  According to the present embodiment, the bus master 111 transmits a synchronization signal indicating a predetermined pattern and a reference clock signal in synchronization. The retiming unit 112 transmits the synchronization signal transmitted from the bus master 111 with a delay. The bus slave 121 captures the synchronization signal transmitted from the retiming unit 112 in synchronization with the reference clock signal, and stores the captured synchronization signal in the storage unit 122. The analysis unit 113 adjusts the delay amount of the retiming unit 112 and adjusts the synchronization signal stored in the storage unit 122. In addition, the analysis unit 113 obtains a shift delay amount that causes a shift between the pattern indicated by the synchronization signal stored in the storage unit 122 and a predetermined pattern.

  In this case, the shift delay amount is obtained. The shift delay amount reflects the setup margin. Therefore, it is possible to know the setup margin without measuring the signal state. If the setup margin is known, it can be determined whether or not the timing constraint is satisfied. Therefore, it is possible to reduce the labor required for analyzing the timing constraints of the actual device.

  In this embodiment, the multiplication unit 202 multiplies the reference clock signal transmitted from the reception unit 115 to generate a plurality of multiplied clock signals, and transmits the plurality of multiplied clock signals. The analysis control unit 204 selects one multiplied clock signal from the plurality of multiplied clock signals generated from the multiplication unit 202. The delay generation unit 203 generates a delay clock signal by synchronizing the reference clock signal transmitted from the reception unit 115 with the selected multiplied clock signal, and transmits the delayed clock signal. The retiming unit 112 transmits the reference clock signal in synchronization with the delayed clock signal generated by the delay generating unit 203.

  In this case, the synchronization signal is transmitted in synchronization with the delayed clock signal. As a result, the synchronization signal is delayed by the delay amount of the delayed clock signal.

  For this reason, it is possible to accurately adjust the delay amount of the synchronization signal.

  Next, a timing analysis circuit capable of adjusting the delay amount of the reference clock signal will be described.

  FIG. 7 is a block diagram showing an example of a configuration of a timing analysis circuit capable of adjusting the delay amount of the reference clock signal. In the following, the configuration and operation different from the configuration or operation described in FIGS. 1 to 6 will be mainly described. In FIG. 7, the same components as those in FIG. 6 are denoted by the same reference numerals.

  7, the device 101 includes a bus master 111, a retiming unit 112, a retiming adjustment function unit 113a, a data buffer 114, and a retiming unit 701. The timing adjustment function unit (hereinafter referred to as an adjustment unit) 113a includes a setting register 201, a multiplication unit 202, a delay generation unit 203, an adjustment control unit 204a, and a result storage unit 205.

  The bus master 111 transmits the synchronization signal and the reference clock signal to the bus slave 121 in synchronization. At this time, the bus master 111 transmits the reference clock signal to the bus slave 121 via the retiming unit 701 and the synchronization bus 103.

  The delay generation unit 203 further transmits the delayed clock signal to the retiming unit 701.

  The retiming unit 701 is an example of a correction unit.

  The retiming unit 701 delays the reference clock signal transmitted from the bus master 111 and transmits the delayed reference clock signal to the bus slave 121. Specifically, the retiming unit 701 transmits the reference clock signal transmitted from the bus master 111 to the bus slave 121 in synchronization with the delayed clock signal transmitted from the delay generation unit 203.

  The bus slave 121 captures the synchronization signal transmitted from the retiming unit 112 in synchronization with the reference clock signal transmitted from the retiming unit 701.

  In addition to the processing performed by the analysis control unit 204, the adjustment control unit 204a performs the following processing.

  When the adjustment control unit 204a obtains the deviation delay amount, the adjustment control unit 204a adjusts the delay amount of the retiming unit 701 based on the obtained delay amount.

  Specifically, the adjustment control unit 204a determines whether or not the obtained delay amount is equal to or less than a predetermined threshold value.

  If the obtained delay amount is equal to or less than the threshold value, the adjustment control unit 204a obtains the delay amount of the reference clock signal transmitted by the bus master 111 based on the obtained delay amount.

  For example, the adjustment control unit 204a holds a predetermined value, and obtains a value obtained by subtracting the obtained delay amount from the predetermined value as the delay amount of the reference clock signal transmitted from the bus master 111. The predetermined value indicates a desired setup margin.

  When the adjustment control unit 204a obtains the delay amount of the reference clock signal, the adjustment control unit 204a transmits a select signal indicating the delay amount to the delay generation unit 203 so that the delay generation unit 203 synchronizes the reference clock signal. Then, the multiplied clock signal of the obtained delay amount is selected.

  In the present embodiment, the retiming unit 701 delays the reference clock signal transmitted by the bus master 111 and transmits the delayed reference clock signal. The adjustment control unit 204a adjusts the delay amount of the retiming unit 701 based on the obtained shift delay amount.

  In this case, the delay amount of the reference clock signal is adjusted based on the delay amount of the synchronization signal that causes a shift in the pattern. For this reason, the timing margin of the synchronization signal can be adjusted to a desired value.

  In this embodiment, the retiming unit 701 transmits the reference clock signal transmitted by the bus master 111 in synchronization with the delayed clock signal transmitted by the delay generation unit 203. The adjustment control unit 204a selects a multiplied clock signal with which the delay generation unit 203 synchronizes the reference clock signal based on the obtained shift delay amount.

  In this case, the reference clock signal is transmitted in synchronization with the delayed clock signal. As a result, the reference clock signal is delayed by the delay amount of the delayed clock signal. Therefore, it is possible to accurately adjust the delay amount of the reference clock signal.

  In the embodiment described above, the illustrated configuration is merely an example, and the present invention is not limited to the configuration.

  For example, the multiplication number of the multiplication unit 202 may be variable. In this case, the setting register 201 sets the multiplication number.

  In this case, when receiving a signal indicating the multiplication number from the CPU, the setting register 201 sets the multiplication number indicated by the signal to itself. Further, when setting the analysis mode for itself, the setting register 201 sets the multiplication number in the multiplication unit 202 and transmits the multiplication number to the analysis control unit 204 (or the adjustment control unit 204a).

  The multiplication unit 202 multiplies the reference clock signal received from the reception unit 115 by the set multiplication number.

  When the analysis control unit 204 receives the multiplication number, the analysis control unit 204 obtains the period of the multiplication clock signal, the delay amount of the multiplication clock signal, and the like based on the multiplication number and the period of the reference clock signal. Note that the analysis control unit 204 holds the period of the reference clock signal.

It is the block diagram which showed the structure of the timing analysis circuit of one Example of this invention. FIG. 3 is a block diagram illustrating a detailed configuration of a timing analysis circuit according to an embodiment of the present invention. It is a time chart for demonstrating an example of operation | movement of a delay production | generation part. It is a time chart for demonstrating an example of operation | movement of a retiming part. It is a time chart for demonstrating an example of the transfer operation | movement of a test signal. It is a time chart for demonstrating an example of a timing analysis. It is the block diagram which showed the structure of the timing analysis circuit of the other Example of this invention. It is a time chart for demonstrating timing restrictions.

Explanation of symbols

DESCRIPTION OF SYMBOLS 101 Device 102 Device 103 Synchronous bus 104 Signal bus 111 Bus master 112 Retiming part 113 Timing analysis function part 113a Timing adjustment function part 114 Data buffer 115 Reception part 121 Bus slave 122 Storage part 201 Setting register 202 Multiplication part 203 DelayCLK generation part 204 Analysis Control unit 204a Adjustment control unit 211 Setting register 212 Storage control unit 213 Memory 701 Retiming unit

Claims (8)

A storage unit;
A transmission unit that synchronously transmits a synchronization signal indicating a predetermined pattern and a reference clock signal;
A delay unit that delays and transmits the synchronization signal;
A synchronization unit transmitted from the delay unit is captured in synchronization with a reference clock signal transmitted from the transmission unit, and a reception unit that stores the captured synchronization signal in the storage unit;
The delay amount of the delay unit is adjusted, the synchronization signal stored in the storage unit is adjusted, the pattern indicated by the synchronization signal stored in the storage unit is compared with the predetermined pattern, and the synchronization signal is A timing analysis circuit including: an analysis unit that obtains a delay amount that causes a deviation between the pattern to be displayed and the predetermined pattern. The timing analysis circuit according to claim 1,
Receiving a reference clock signal from the generating unit for generating the reference clock signal, and including a receiving unit for transmitting the reference clock signal,
The analysis unit
Multiplying the reference clock signal transmitted from the reception unit to generate a plurality of multiplied clock signals, and a multiplying unit that transmits the plurality of multiplied clock signals;
A control unit that selects one multiplied clock signal from a plurality of multiplied clock signals transmitted from the multiplication unit;
A reference clock signal transmitted from the receiving unit, a delay clock signal is generated in synchronization with the multiplied clock signal selected by the control unit, and a delay generation unit that transmits the delayed clock signal,
The transmission unit transmits the synchronization signal and the reference clock signal transmitted from the reception unit in synchronization,
The timing analysis circuit, wherein the delay unit transmits the synchronization signal transmitted from the transmission unit in synchronization with the delay clock signal transmitted from the delay generation unit. In the timing analysis circuit according to claim 1 or 2,
A correction unit that delays and transmits the reference clock signal transmitted from the transmission unit;
The timing analysis circuit, wherein the analysis unit adjusts a delay amount of the correction unit based on the obtained delay amount. The timing analysis circuit according to claim 2,
A correction unit that transmits the reference clock signal transmitted from the transmission unit in synchronization with the delayed clock signal transmitted from the delay generation unit;
The control unit is a timing analysis circuit in which the delay generation unit selects a multiplied clock signal that synchronizes the reference clock signal based on the obtained delay amount. A timing analysis method performed by a timing analysis circuit,
A transmission step of synchronously transmitting a synchronization signal indicating a predetermined pattern and a reference clock signal;
A delay step of delaying and transmitting the synchronization signal;
Capturing the delayed and transmitted synchronization signal in synchronization with the transmitted reference clock signal;
A storing step for storing the captured synchronization signal;
An adjustment step of adjusting a delay amount of the synchronization signal to adjust the stored synchronization signal;
A timing analysis method comprising: an analysis step of comparing a pattern indicated by the stored synchronization signal with the predetermined pattern to obtain a delay amount that causes a shift between the pattern indicated by the synchronization signal and the predetermined pattern. The timing analysis method according to claim 5,
A clock receiving step of receiving a reference clock signal from a generating unit for generating the reference clock signal;
A multiplying step of multiplying the received reference clock signal to generate a plurality of multiplied clock signals;
A selection step of selecting one multiplied clock signal from the plurality of multiplied clock signals;
A delay generation step of generating a delayed clock signal in synchronization with the received multiplied clock signal, the received reference clock signal;
In the transmission step, the synchronization signal and the received reference clock signal are transmitted in synchronization with each other,
In the delay step, the transmitted synchronization signal is transmitted in synchronization with the generated delayed clock signal. In the timing analysis method according to claim 5 or 6,
A correction adjustment step of adjusting a delay amount of the transmitted reference clock signal based on the determined delay amount;
And a correction step of delaying and transmitting the transmitted reference clock signal by the adjusted delay amount. The timing analysis method according to claim 6,
A correction selection step of selecting a multiplied clock signal that synchronizes the transmitted reference clock signal based on the determined delay amount;
And a correction step of transmitting the transmitted reference clock signal in synchronization with the delayed clock signal selected in the totaling selection step.

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