JP2008097018A - Display driver and electronic equipment including display driver - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a display driver which can flexibly correspond to display characteristics of a display panel while reducing an influence exerting the display state of a display panel. <P>SOLUTION: The display driver comprises: a scanning driver 600 and a data driver 700 of driving the display panel 20; a control circuit 800; and a control register 400. The control register 400 receives a display characteristic parameter from a nonvolatile storage circuit 100 into which the display characteristic parameter corresponding to the display characteristics of the display panel 20 is written upon the initial setting and stores the display characteristic parameter. The control circuit 800 performs such a refresh operation as to read the display characteristic parameter from the nonvolatile storage circuit 100 and again write the display characteristic parameter to the control register 400 with a prescribed timing which is set in a former half period of non-display period of the display panel 20. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a display driver and an electronic device including the display driver.

  With the increase in resolution of the display panel, it has been a problem to consider the display characteristics of the display panel in order to improve the image quality of the display panel. Since display characteristics of display panels vary, a display driver that can flexibly handle various display panels is required. In addition, the higher resolution of the display panel is likely to be affected by external static electricity and the like, which may adversely affect data stored in an internal register of an electronic device or the like equipped with the display panel.

Patent Document 1 describes a display driver that solves the above problems. However, the refresh operation of the register or the like consumes a large amount of power and may adversely affect the display state of the display panel.
JP 2003-263134 A

  The present invention has been made in view of the technical problems as described above. The object of the present invention is to flexibly cope with the display characteristics of the display panel while reducing the influence on the display state of the display panel. To provide a display driver.

  The present invention includes a scan driver and a data driver for driving a display panel, an OTP circuit having a plurality of OTP (One-Time-PROM) cells, a control circuit, and a control register. A display characteristic parameter corresponding to the display characteristic of the display panel is written to the circuit, the control register stores the display characteristic parameter supplied from the OTP circuit, and each of the plurality of OTP cells has a floating gate. The control circuit outputs a read signal to the OTP circuit when reading the display characteristic parameter from the OTP circuit, and outputs a write signal when writing the display characteristic parameter to the OTP circuit. Output to the OTP circuit and the display characteristic parameter The refresh operation of writing over data again to the control register is read from the OTP circuit, related to the display driver to perform a predetermined timing set within the period of the first half of the non-display period of the display panel.

  According to the present invention, even if the power supply voltage or the like is changed by the refresh operation, the influence on the display state of the display panel can be reduced. Further, according to the present invention, since the OTP circuit includes the floating gate transistor, it is easy to incorporate the OTP circuit in the display driver. Furthermore, according to the present invention, since any display characteristic parameter can be stored in the display driver, the display driver according to the present invention can flexibly cope with various display panels.

  Each of the plurality of OTP cells according to the present invention includes a determination transistor provided between a node of a first power supply and a node of a second power supply, and the gate of the determination transistor The reference voltage may be input. Thereby, each OTP cell can output the written data correctly.

  Each of the plurality of OTP cells according to the present invention includes a first output transistor provided in series with the determination transistor between a node of the first power source and a node of the second power source. A second output transistor provided between a transistor, a first node to which a gate of the first output transistor is connected, and a node of the second power supply; A drain and a gate of the output transistor may be connected to the first node. Thereby, each OTP cell can output the data stored in each OTP cell.

  Each of the plurality of OTP cells according to the present invention includes a read transistor provided between the second node to which the drain of the floating gate transistor is connected and the first node. The read signal may be input to the gate of the read transistor. Thereby, the data stored in each OTP cell can be read.

  Each of the plurality of OTP cells according to the present invention includes a writing transistor provided between the second node and the node of the second power supply, and the gate of the writing transistor is provided. The write signal may be input. As a result, it is possible to write to any OTP cell.

  Each of the plurality of OTP cells according to the present invention includes a protection transistor provided in parallel with the floating gate transistor between the first power supply node and the second node. The control circuit may output a protection signal protecting the deterioration of the floating gate transistor to the gate of the protection transistor when reading or writing is not performed on the OTP circuit. As a result, the floating gate transistor can be protected from the disturb voltage.

  The OTP circuit according to the present invention may include a reference cell having the floating gate transistor, and the reference cell may generate the reference voltage and supply the reference voltage to the determination transistor. . Thereby, the deterioration characteristic of a reference cell can be made into the deterioration characteristic corresponding to the deterioration characteristic of an OTP circuit.

  In addition, the reference cell according to the present invention includes a third output transistor provided between the node of the first power supply and the node of the second power supply. The floating gate transistor is provided between a node to which a gate is connected and a node of the first power supply, and the current capability of the third output transistor is the first output for the OTP cell. It may be smaller than the current capability of the transistor. As a result, an optimum reference voltage can be output to the OTP circuit.

  In the non-display period, the control circuit according to the present invention performs control so that the voltage at which the scan driver drives the display panel and the voltage at which the data driver drives the display panel are the same. May be. This can reduce the influence on the display panel during the refresh operation.

  The control circuit according to the present invention may disable the refresh operation of the OTP circuit during a period in which a processor unit that controls a display driver is accessing the control circuit. Thereby, it is possible to prevent a malfunction due to a change in the power supply voltage or the like.

  The display driver according to the present invention includes a power supply circuit, the display characteristic parameter includes a contrast adjustment parameter, and the power supply circuit controls the contrast adjustment parameter written in the control register from the OTP circuit. A predetermined voltage may be output based on the contrast adjustment parameter received from the register. As a result, the power supply circuit can output an optimum driving voltage to the display panel.

  The present invention also includes a scan driver and a data driver for driving the display panel, a nonvolatile memory circuit, a control circuit, and a control register, and the nonvolatile memory circuit has a display panel display at the time of initial setting. Display characteristic parameters corresponding to characteristics are written, the control register stores the display characteristic parameters supplied from the nonvolatile memory circuit, and the control circuit reads the display characteristic parameters from the nonvolatile memory circuit In this case, the display driver may perform a refresh operation for rewriting to the control register at a predetermined timing set in a first half period of the non-display period of the display panel.

  The present invention also includes a scan driver and a data driver for driving the display panel, a nonvolatile memory circuit, a control circuit, and a control register, and the nonvolatile memory circuit has a display panel display at the time of initial setting. Display characteristic parameters corresponding to the characteristics are written, the control register stores the display characteristic parameters supplied from the nonvolatile memory circuit, reads the display characteristic parameters from the nonvolatile memory circuit, and stores them in the control register. The refresh operation to be written again is performed at a predetermined timing set in the non-display period of the display panel, and the processor unit that controls the display driver is accessing the control circuit during the period in which the nonvolatile memory circuit A display driver that disables the refresh operation may be used.

  The present invention also includes a scan driver and a data driver for driving the display panel, a nonvolatile memory circuit, a control circuit, and a control register, and the nonvolatile memory circuit has a display panel display at the time of initial setting. Display characteristic parameters corresponding to characteristics are written, the control register stores the display characteristic parameters supplied from the nonvolatile memory circuit, and the control circuit reads the display characteristic parameters from the nonvolatile memory circuit The refresh operation for rewriting to the control register is performed at a predetermined timing set in the non-display period of the display panel, and the voltage that the scan driver drives the display panel in the non-display period, and the data driver Is a display driver that controls the voltage to drive the display panel to be the same. It may be.

  The present invention also relates to an electronic device including any one of the display drivers described above, a display panel, and a processor unit that controls the display driver.

  Hereinafter, an embodiment of the present invention will be described with reference to the drawings. The embodiments described below do not unduly limit the contents of the present invention described in the claims. Also, not all of the configurations described below are essential constituent requirements of the present invention.

1. FIG. 1 is a block diagram illustrating an electro-optical device 1. The electro-optical device 1 includes an MPU (a processor unit that controls a display driver in a broad sense) 10, a display panel (a liquid crystal panel in a narrow sense) 20, and a display driver 30.

  The display driver 30 includes an OTP circuit (nonvolatile memory circuit in a broad sense) 100, a display RAM 200, a RAM control circuit 300, a control register 400, a power supply circuit 500, a scan driver 600, a data driver 700, and a control. Circuit 800. The OTP circuit 100 includes a plurality of OTP cells 130. The control circuit 800 controls the OTP circuit 100, the RAM control circuit 300, the control register 400, the power supply circuit 500, the scan driver 600, and the data driver 700 in accordance with a control signal from the MPU 10.

  The OTP circuit 100 stores, for example, a contrast adjustment parameter (display characteristic parameter in a broad sense) in accordance with a control signal from the control circuit 800. The control register 400 stores a contrast adjustment parameter according to the output of the OTP circuit 100 and the control signal of the control circuit 800. The power supply circuit 500 generates a predetermined voltage according to the contrast adjustment parameter supplied from the control register 400, and supplies the predetermined voltage to the scan driver 600 and the data driver 700. The RAM control circuit 300 controls the display RAM 200 according to the control signal from the control circuit 800. The display RAM 200 stores display data for one screen, for example, according to the control signal of the RAM control circuit 300, and outputs the display data to the data driver 700. In the following drawings, the same reference numerals have the same meaning.

2. OTP Circuit FIG. 2 is a diagram illustrating a connection relationship between the OTP circuit 100, the control register 400, and the control circuit 800. The OTP circuit 100 includes, for example, ten OTP cells 130, that is, the OTP cells OTP11 to OTP15 and the OTP cells OTP21 to OTP25. The reference cell 110 outputs a reference voltage (Reference-Voltage) to the input REF of each of the OTP11 to OTP15 and each of the OTP21 to OTP25. Each of the OTP 11 to OTP 15 and each of the OTP 21 to OTP 25 stores, for example, 1-bit information. The outputs RQ of the OTP 11 to OTP 15 and the OTP 21 to OTP 25 are connected to the control register 400, respectively. In this embodiment, each OTP11 to OTP15 is a first OTP cell group 101, each OTP21 to OTP25 is a second OTP cell group 102, and the first OTP cell group 101 and the second OTP cell group 102 are, for example, Although 5-bit data can be stored, the present invention is not limited to this. The OTP cell 130 may be configured to store, for example, 2-bit information.

  At the time of initial setting, a contrast adjustment parameter is written in at least one of the first OTP cell group 101 and the second OTP cell group 102 under the control of the control circuit 800. For example, when writing to the OTP 11, the control circuit 800 outputs a high level write signal WRS 11 to the input WR of the OTP 11. Further, the control circuit 800 writes bit information for selecting an output of the first OTP cell group 101 or the second OTP cell group 102 in the mask bit ROM 121 or the mask bit ROM 122. For example, when data stored in the second OTP cell group 102 is output to the control register 400, bit information that causes the output of the mask bit ROM 122 to be at a low level can be written to the mask bit ROM 122 at the initial setting. Good. In this embodiment, each of the mask bit ROMs 121 and 122 is composed of a floating gate transistor (nonvolatile memory element in a broad sense) having a floating gate.

  The control circuit 800 has two read modes (read mode 1 and read mode 2).

  In the read mode 1, the control circuit 800 outputs a read signal XREAD to either the first OTP cell group 101 or the second OTP cell group 102 in accordance with the bit information written in each mask bit ROM 121, 122. To do. As a result, the contrast adjustment parameter stored in either the first OTP cell group 101 or the second OTP cell group 102 is output to the control register 400.

  For example, when writing is performed only in the mask bit ROM 121, that is, when the output of the mask bit ROM 121 is at a low level and the output of the mask bit ROM 122 is at a high level, the data is stored in the first OTP cell group 101. The contrast adjustment parameter is used for contrast adjustment. Conversely, when writing is performed only to the mask bit ROM 122, that is, when the output of the mask bit ROM 121 is at a high level and the output of the mask bit ROM 122 is at a low level, the data is stored in the second OTP cell group 102. The contrast adjustment parameter is used for contrast adjustment. When the outputs of the mask bit ROMs 121 and 122 are at a low level, the contrast adjustment parameter stored in the second OTP cell group 102 is used for contrast adjustment.

  Since the bit information written in each mask bit ROM 121 and 122 is stored in the control register 400, the control circuit 800 checks the output of the control register 400, and thereby the bit information written in each mask bit ROM 121 and 122. Can be examined. As a modification, the output RQ of each mask bit ROM 121, 122 may be connected to the control circuit 800. Note that the first character X of the sign of each signal means negative logic.

  In the read mode 2, the control circuit 800 does not depend on the information stored in the mask bit ROMs 121 and 122, and can select any OTP cell from the first OTP cell group 101 or the second OTP cell group 102. A read signal XREAD can also be output to the group.

  When reading the contrast adjustment parameter from the OTP circuit 100, the control circuit 800 outputs a read signal XREAD to the OTP circuit 100. For example, the read signal XREAD is input to the input RD of the OTP 21 of the OTP circuit 100. Here, in the case of the read mode 1, the first OTP cell group 101 is selected when data is written only to the mask bit ROM 121, and when data is written only to the mask bit ROM 122 or each mask bit ROM 121, When both 122 are written, the second OTP cell group 102 is selected. In the read mode 2, an arbitrary OTP cell group is selected by the control circuit 800. The contrast adjustment parameter stored in the selected OTP cell group is used for contrast adjustment.

  As described above, in the present embodiment, the two OTP cell groups 101 and 102 can be properly used under the control of the control circuit 800. The floating gate transistor PROM of the present embodiment is an OTPROM (One-Time-PROM) that cannot be erased. However, since a plurality of OTP cell groups are provided in the OTP circuit 100, it corresponds to erroneous writing at the time of initial setting. Can do.

  In this embodiment, a 5-bit contrast adjustment parameter is stored in the OTP circuit 100 as an example, but other display characteristic parameters may be stored. For example, by changing the number of OTP cells 130, display characteristic parameters (for example, gradation information, oscillation frequency, PWM setting information, etc.) may be stored in the OTP circuit 100 in addition to the contrast adjustment parameters. As the gradation information, for example, a frame rate used in an FRC (frame rate control) driving method can be considered. Further, the setting information of the PWM may be the setting information of the rising timing of the gradation clock pulse.

  Furthermore, unique information (for example, product number, ID number, lot number, etc.) such as the electro-optical device 1 or the display driver 30 may be stored in the OTP circuit 100. Further, the reference cell 110 may be provided in each OTP cell 130.

  FIG. 3 is a diagram showing an OTP circuit 190, a control circuit 800, and a control register 400 each composed of one OTP cell group. The OTP cell group 103 in FIG. 3 includes five OTP cells 130 as an example, but is not limited to this as in the description of FIG. The reference cell 110 outputs a reference voltage (Reference-Voltage) to the input REF of each of the OTP cells OTP31 to OTP35.

  At the initial setting, the control circuit 800 writes the contrast adjustment parameter in the OTP circuit 190. When reading the contrast adjustment parameter, the control circuit 800 outputs the read signal XREAD to the input RD of each of the OTP cells OTP31 to OTP35. As a result, the OTP circuit 190 outputs the contrast adjustment parameter to the control register 400.

  In the present embodiment, a modification in which the OTP circuit 190 shown in FIG. 3 is applied instead of the OTP circuit 100 shown in FIG. 2 is also possible.

  FIG. 4 is a circuit diagram showing the OTP cell 130. FIG. 5 is a diagram showing the value of the voltage VOTP and the signal levels of the protection signal XPROT, the read signal XREAD, and the write signal WRROM in each operation (write, read, standby) with respect to the OTP cell 130.

  When neither reading nor writing is performed with respect to the OTP cell 130 of FIG. 4, that is, during standby, the control circuit 800 is active (low level) as shown in FIG. 5 at the gate electrode of the protection transistor PTR. A protection signal XPROT is output. That is, as shown in FIG. 5, the protection transistor PTR is turned on. As a result, the source and drain of the floating gate transistor PROM are set to the same potential, so that deterioration of the floating gate transistor PROM can be prevented. According to FIG. 5, the voltage VOTP is set to the standby voltage VST (for example, 3 V) during standby, but the standby voltage VST may be the voltage VSS. 4 indicates the output of the reference cell 110.

  When performing a write operation on the OTP cell 130 of FIG. 4 at the time of initial setting, the control circuit 800 sets the voltage VOTP to the write voltage VWR (for example, 7 V). Further, the control circuit 800 outputs an active (high level) write signal WRROM as shown in FIG. 5 to the gate of the write transistor WTR. As a result, the write transistor WTR is turned on as shown in FIG. The voltage VSS is, for example, 0V. That is, the voltage VWR is applied to the source of the floating gate transistor PROM, and the voltage VSS is applied to the drain of the floating gate transistor PROM. When a high voltage (write voltage VWR) is applied to the floating gate transistor PROM in this way, the PN junction in the floating gate transistor PROM is broken down and electrons are emitted. Since the emitted electrons are trapped by the gate electrode of the floating gate transistor PROM, a channel is formed in the channel region of the floating gate transistor PROM. That is, when data is written in the floating gate transistor PROM, the source and drain of the floating gate transistor PROM are electrically connected.

  In the write operation, as shown in FIG. 5, the signal level of the protection signal XPROT is set to a high level (non-active), and the protection transistor PTR is turned off. As shown in FIG. 5, the signal level of the read signal XREAD input to the gate of the read transistor RTR is set to a high level (non-active). As a result, the reading transistor RTR is turned off, and the transistors TR1 and TR2 are turned on. Since the voltage VSS is applied to the source of the transistor TR1, the voltage of the output RQ of the OTP cell 130 in FIG. 4 becomes the voltage VSS. That is, during the write operation, the voltage of the output RQ of the OTP cell 130 becomes the voltage VSS. Further, as shown in FIG. 5, since the transistor TR2 is turned on, the voltage VSS is applied to the respective gate electrodes of the first and second output transistors QTR1 and QTR2. The output transistors QTR1 and QTR2 are surely turned off.

  In the case of reading from the OTP cell 130 of FIG. 4, the control circuit 800 outputs an active (low level) read signal XREAD as shown in FIG. 5 to the gate of the read transistor RTR so as to be non-active (low level). The write signal WRROM is output to the gate of the write transistor WTR. As a result, the reading transistor RTR is turned on, and the transistor TR1, the transistor TR2, and the writing transistor WTR are turned off. The control circuit 800 outputs a non-active (high level) protection signal XPROT to the gate of the protection transistor PTR. As a result, the protection transistor PTR is turned off.

  Further, the control circuit 800 sets the voltage VOTP to the read voltage VRD (for example, 3V) as shown in FIG. Further, the output (reference voltage in a broad sense) of the reference cell 110 is supplied to the gate of the determination transistor DTR. When a write operation is performed on the floating gate transistor PROM in FIG. 4, the source and drain of the floating gate transistor PROM are electrically connected, and therefore the first and second nodes ND1 in FIG. , Current flows through ND2. That is, the first and second output transistors QTR1 and QTR2 are turned on. Since the first and second output transistors QTR1 and QTR2 are designed to have the same size, the current supply capabilities of the transistors QTR1 and QTR2 are the same. In other words, since the gates of the transistors QTR1 and QTR2 are connected to the node ND1, the on-resistance of the transistor QTR1 is reduced similarly to the transistor QTR2. Since the output of the reference cell 110 is supplied to the gate of the determination transistor DTR, the determination transistor DTR is turned on, but the output voltage of the reference cell 110 is set to a relatively high voltage. The current supply capability of the determination transistor DTR is smaller than the current supply capability of the transistor QTR1. That is, since the on-resistance of the transistor QTR1 is smaller than the on-resistance of the transistor DTR, the voltage of the output RQ of the OTP cell 130 in FIG. 4 becomes a low level voltage (a voltage slightly higher than the voltage VSS).

  However, when the floating gate transistor PROM in FIG. 4 is a floating gate transistor PROM that is not written, the source and drain of the floating gate transistor PROM are electrically non-conductive. Current does not flow through the nodes ND1 and ND2. As a result, the first and second output transistors QTR1 and QTR2 are turned off as shown in FIG. As a result, the on-resistance of the transistor QTR1 becomes sufficiently larger than the on-resistance of the transistor DTR, so that the voltage of the output RQ of the OTP cell 130 in FIG. 4 becomes a high level voltage (a voltage slightly lower than the read voltage VRD). .

  FIG. 6 is a circuit diagram of the reference cell 110. The floating gate transistor RPROM is written, for example, during product inspection. As a result, the floating gate and the source / drain of the transistor RPROM are electrically connected. The floating gate transistor RPROM has the same size and the same structure as the floating gate transistor PROM of FIG. 4, but is not limited thereto. Further, the size of the third output transistor QTR3 is configured to be smaller than the size of the first output transistor QTR1 in FIG. The size of the third output transistor QTR3 is configured to be, for example, 1/8 of the size of the first output transistor QTR1. The fourth output transistor QTR4 is configured to have the same size as the first output transistor QTR1 of FIG.

  When a write operation is performed on the reference cell 110 in FIG. 6 during product inspection, the control circuit 800 sets the voltage VOTP to the write voltage VWR (for example, 7 V) as described above. In addition, the control circuit 800 outputs an active (high level) write signal WRROM as shown in FIG. 5 to the gate of the write transistor RWTR. As a result, the write transistor RWTR is turned on as shown in FIG. The voltage VSS is, for example, 0V. That is, the voltage VWR is applied to the source of the floating gate transistor RPROM, and the voltage VSS is applied to the drain of the floating gate transistor RPROM. Thus, when a high voltage (write voltage VWR) is applied to the floating gate transistor RPROM, the PN junction in the floating gate transistor RPROM is broken down and electrons are emitted. Since the emitted electrons are trapped by the gate electrode of the floating gate transistor RPROM, a channel is formed in the channel region of the floating gate transistor RPROM. That is, when data is written in the floating gate transistor RPROM, the source and drain of the floating gate transistor RPROM are electrically connected.

  In the write operation, as shown in FIG. 5, the signal level of the protection signal XPROT is set to a high level (non-active), and the protection transistor RPTR is turned off. As shown in FIG. 5, the signal level of the read signal XREAD input to the gate of the read transistor RRTR is set to a high level (non-active). As a result, the reading transistor RRTR is turned off. The transistors TR4 and TR5 are turned on. Since the voltage VSS is applied to the source of the transistor TR4, the voltage of the output REF of the reference cell 110 in FIG. 6 becomes the voltage VSS. That is, during the write operation, the voltage of the output REF of the reference cell 110 becomes the voltage VSS. Further, as shown in FIG. 5, since the transistor TR5 is turned on, the voltage VSS is applied to the gate electrodes of the third and fourth output transistors QTR3 and QTR4. The output QTR3 and QTR4 are surely turned off.

  When the read operation is performed on the OTP cell 130 of FIG. 4, the read operation is similarly performed on the reference cell of FIG.

  When reading from the reference cell 110 in FIG. 6, the control circuit 800 outputs an active (low level) read signal XREAD as shown in FIG. 5 to the gate of the read transistor RRTR, and inactive (low level). The write signal WRROM is output to the gate of the write transistor RWTR. As a result, the reading transistor RRTR is turned on, and the transistor TR4, the transistor TR5, and the writing transistor RWTR are turned off. The control circuit 800 outputs a non-active (high level) protection signal XPROT to the gate of the protection transistor RPTR. As a result, the protection transistor RPTR is turned off.

  As described above, when performing a read operation on the OTP cell 130, the control circuit 800 sets the voltage VOTP to the read voltage VRD (for example, 3V) and sets the protection signal XPROT to a non-active (high level) signal. Set. Since the write operation is performed on the floating gate transistor RPROM in FIG. 6, the source and drain of the floating gate transistor RPROM are electrically connected, so the third and fourth nodes ND3 in FIG. , Current flows through ND4. That is, the third and fourth output transistors QTR3 and QTR4 are turned on, and a current flows between the source and drain of the third output transistor QTR3. At this time, the transistor size of the third output transistor QTR3 is configured to be 1/8 of the size of the fourth output transistor QTR4. Therefore, the current supply capability of the third output transistor QTR3 is 1/8 of the current supply capability of the output transistor QTR4. As a result, the output REF of the reference cell 110 becomes a voltage level higher than the voltage level when the transistors QTR3 and QTR4 have the same size.

  In the present embodiment, since the reference cell 110 includes the floating gate transistor RPROM having the same size and the same structure as the floating gate transistor PROM of the OTP circuit 100, the reference cell 110 has the same characteristic deterioration as that of the OTP circuit 100. Thereby, the OTP circuit 100 can store the display characteristic parameters with high accuracy. As a modification of the present embodiment, a configuration in which the reference transistor 110 is not provided with the protection transistor RPTR is also possible.

3. Refresh Operation FIG. 7 is a diagram showing the timing of a refresh operation for rewriting the contrast adjustment parameter (display characteristic parameter in a broad sense) in the control register. The reference clock CL is a synchronization signal generated by an internal oscillator or the like. In this embodiment, a non-display period is provided for each frame, but a non-display period may be provided for every two frames or every m (m is a natural number of 3 or more) frames. When the display period ends, the RAM control circuit 300 in FIG. 1 generates a display period end pulse COMEND as indicated by A1 and outputs it to the control circuit 800. Upon receiving the display period end pulse COMEND, the control circuit 800 causes the read signal XREAD to be output to the OTP circuit 100 to fall to a low level as indicated by A2 in synchronization with the reference clock CL, and thereafter, indicated by A3. Thus, the control register latch signal LPOTP output to the control register 400 is lowered to the low level. The control register 400 stores the contrast adjustment parameter from the OTP circuit 100 in accordance with the control register latch signal LPOTP.

  The fall timing of the read signal XREAD shown in A2 of FIG. 7 is only delayed by one cycle of the reference clock CL from the fall timing of the display period end pulse COMEND shown in A1. That is, in the present embodiment, the start timing of the refresh operation is set to the first half period of the non-display period, which is as early as possible after the display period ends. Note that the first half period of the non-display period is a period before the center of the non-display period indicated by A4 in FIG.

  FIG. 8 is a diagram showing the relationship between the refresh operation timing and the power supply voltage. When a read operation is performed on the OTP circuit 100, the power supply voltage in the display driver is temporarily lowered as indicated by B1 in FIG. Thereafter, the power supply voltage recovers to the voltage VDD.

  FIG. 9 is a diagram illustrating a state of the OTP cell 130 when a read operation is performed on the OTP cell 130 on which the write operation has been performed. When a read operation is performed on the OTP cell 130 in which the write operation has been performed, the read transistor RTR is turned on, and the source and drain of the floating gate and the transistor PROM are electrically connected. Transistor QTR2 is turned on. That is, a through current flows through the path indicated by C1 in FIG. As a result, the power supply voltage in the display driver 30 in FIG. 1 drops during the refresh operation. A drop in the power supply voltage may adversely affect the display state of the display panel. However, in this embodiment, since the refresh operation is performed in the first half of the non-display period as shown in FIG. 7, the power supply voltage is restored to the voltage VDD when the display period is started. Therefore, the display characteristic parameter refresh operation can be performed without adversely affecting the display state.

  FIG. 10 is a diagram showing a logic circuit 810 that sets the refresh operation to disable in the MPU access. This logic circuit 810 is included in the control circuit 800. The logic circuit 810 receives a write signal XWR and a read signal XRD from an MPU (processor unit that controls a display driver in a broad sense). Further, the read signal XREAD and the control register latch signal LPOTP output from the control circuit 800 are input to the logic circuit 810.

  The output XREAD ′ of the logic circuit 810 is input to the OTP circuit 100 as the read signal XREAD of the control circuit 800. The output LPOTP ′ of the logic circuit 810 is input to the control register 400 as the control register latch signal LPOTP of the control circuit 800.

  As described above, the control circuit 800 outputs the active (low level) read signal XREAD and the control register latch signal LPOTP in response to the display period end pulse COMEND. However, when the MPU accesses the control circuit 800, the write signal XWR or the read signal XRD becomes active (low level), and the output of the circuit NAND1 becomes high level. In this case, the outputs XREAD 'and LPOTP' are always at a high level regardless of the read signal XREAD and the control register latch signal LPOTP. That is, the refresh operation is not always performed during MPU access.

  FIG. 11 is a timing waveform diagram showing the relationship between the input signal and the output signal of the logic circuit 810 of FIG. As shown in FIG. 11, during MPU access, the outputs XREAD 'and LPOTP' are always at the high level even if the read signal XREAD and the control register latch signal LPOTP are active (low level). When MPU is accessed, power consumption increases, so that if the refresh operation is performed in parallel, there is a high possibility of causing a malfunction. The timing at which the MPU is accessed is asynchronous. However, if the logic circuit 810 of this embodiment is used, the refresh operation can be invalidated even when the MPU is accessed asynchronously.

  As a modification, the logic circuit 810 may be provided outside the control circuit 800, and the control circuit 800 may be configured not to include the logic circuit 810.

  FIG. 12 is a circuit diagram of the latch circuit 410 included in the control register 400. A plurality of latch circuits 410 are included in the control register 400. In the present embodiment, for example, twelve latch circuits 410 are included. The data input terminal XD of the latch circuit 410 is connected to each of the mask bit ROMs 121 and 122 and the outputs RQ of the OTP cells OTP11 to OTP15 and OTP21 to 25 in FIG. The reset input terminal XR is a terminal to which a low level signal is input when the output M of the latch circuit 410 is forced to be low level. For example, when a write operation is not performed on the floating gate transistor RPROM of the reference cell 110 such as when performing an inspection, the output M is forcibly set to a low level, so that a low level signal is applied to the reset input terminal XR. Entered. During normal operation, a high level signal is always input to the reset input terminal XR.

  A control register latch signal LPOTP (LPOTP ′) is input from the control circuit 800 to the clock input terminal CP. An inverted latch signal XLPOTP which is an inverted signal of the control register latch signal LPOTP (LPOTP ′) is input to the clock input terminal XCP. Each inverter CG1, CG2 has a clocked CMOS gate. For example, the inverter function of the inverter CG1 is activated when a low level signal is input to the terminal PG1 of the inverter CG1 and a high level signal is input to the terminal NG1 of the inverter CG1. That is, the inversion of the signal input to the input IN1 of the inverter CG1 is output from the output Q1. Conversely, when high level and low level signals are simultaneously input to the terminals PG1 and NG1 of the inverter CG1, the output Q1 of the inverter CG1 enters a high impedance state. The inverter CG2 performs the same operation.

  Here, consider the case where the output RQ of the mask bit ROMs 121 and 122 or the OTP cell 130 is at a high level, that is, when a high level signal is input to the data input terminal XD. When the refresh operation is performed, the control register latch signal LPOTP (LPOTP ′) input to the terminal CP becomes a low level as indicated by D1 in FIG. Then, the inverted latch signal XLPOTP input to the terminal XCP becomes high level. As a result, a low level signal is input to the terminal PG1 of the inverter CG1, and a high level signal is input to the terminal NG1, so that the inverter function of the inverter CG1 is activated. That is, since a high level signal is input to the input IN1 of the inverter CG1, a low level signal is output from the output Q1 of the inverter CG1. Since the output Q2 of the inverter CG2 is in a high impedance state, the output M of the latch circuit 410 at this time is at a low level. Further, since the high level signal input to the terminal XR and the low level signal from the output Q are input to the circuit NAND2, the circuit NAND2 outputs the high level signal to the input IN2 of the inverter CG2.

  This time, as indicated by D2 in FIG. 11, the control register latch signal LPOTP (LPOTP ′) input to the terminal CP goes to a high level, and accordingly, the inverted latch signal XLPOTP input to the terminal XCP goes to a low level. Become. Accordingly, a high level signal is input to the terminal NG2 of the inverter CG2, and a low level signal is input to the terminal PG2 of the inverter CG2, so that the inverter function of the inverter CG2 is activated. That is, since a high level signal is input from the circuit NAND2 to the input IN2 of the inverter CG2, a low level signal is output from the output Q2 of the inverter CG2. Since the output Q1 of the inverter CG1 is in a high impedance state, the output M of the latch circuit 410 at this time is at a low level.

  That is, when a high level signal is input to the data input terminal XD of the latch circuit 410, the output M of the latch circuit 410 is always at a low level. Since the same can be considered when a low level signal is input to the data input terminal XD, the output M of the latch circuit 410 is always at a high level.

  Since the output of the circuit NAND2 is held during a period when the control register latch signal LPOTP (LPOTP ′) is at a high level, that is, when CG2 is active, the portion constituted by the circuit NAND2 and the inverter CG2 is regarded as the holding circuit 411 Can do. That is, the latch circuit 410 includes an inverter function and a holding circuit 411 function.

For example, when writing is performed to the floating gate transistor PROM included in the mask bit ROM 121 of FIG. 2, the output RQ of the mask bit ROM 121 is at a low level. However, since the output RQ is input to the latch circuit 410, a high level signal is output from the output M of the latch circuit 410 via the inverter CG1 of the latch circuit 410. That is, when writing to the mask bit ROM 121 of FIG. 2 is performed, the output of the control register 400 is at a high level, so that the writing at the initial setting and the output of the control register 400 can be matched. As a result, a user who uses the display driver 30 according to the present embodiment can easily perform initial settings (such as setting a contrast adjustment parameter).
As a modification of the latch circuit 410, the inverter CG1 can be replaced with a CMOS inverter, and the holding circuit 411 can be replaced with a flip-flop circuit or the like. However, since this embodiment uses a clocked CMOS gate, The circuit scale of the circuit 410 can be reduced.

  FIG. 13 is a timing waveform diagram showing voltages applied to the pixels of the display panel. For example, in the non-display period, when the voltage MV2 is applied to the scanning line as indicated by E1 and the voltage V1 is applied to the data line as indicated by E2, the corresponding pixel is indicated by E3. Is applied with a voltage (MV2-V1, for example, -6V). In the non-display period, the scan driver 600 in FIG. 1 supplies the voltage VC to the scan lines. In the non-display period, the data driver 700 in FIG. 1 supplies the voltage VC to the data line as indicated by E4. That is, as indicated by E5, the voltage applied to the pixel in the non-display period is 0V. That is, in the non-display period, the voltage supplied to the pixel by the scan driver 600 and the voltage supplied by the data driver 700 to the data line are set to 0V. Since the voltage applied to the pixel is 0 V, the display state of the display panel is not affected at all even if the voltage drops due to the refresh operation. As described above, in the present embodiment, a refresh operation with less adverse effect on the display state is possible.

4). Effects In this embodiment, a floating gate transistor PROM (OTP: One-Time-PROM in a narrow sense) is used for the OTP circuit 100 (nonvolatile memory circuit in a broad sense). The floating gate transistor PROM can be easily manufactured by an existing process in a display driver because the gate of a normal transistor is in a floating state. That is, the manufacturing cost can be reduced. The floating gate transistor PROM used in the present embodiment may be an erasable PROM.

  In this embodiment, the refresh operation timing is set to the first half period of the non-display period. As a result, even if the power supply voltage drops due to the refresh operation, the display state of the display panel is not affected. Therefore, flickering of the screen can be suppressed and the display panel can be driven with higher image quality. As the resolution of display panels in the future increases, the influence of static electricity from the outside world will become stronger and the number of refresh operations will increase. That is, since this embodiment can reduce the influence on the display state during the refresh operation, it can exert a great effect even in a high-resolution display panel.

  Further, when the resolution of the display panel is increased, the amount of display data increases, so the number of MPU accesses increases. However, in this embodiment, the refresh operation is not performed during a period in which the MPU (processor unit for controlling the display driver in a broad sense) is accessing the control circuit 800. Although the MPU access consumes a large amount of power, the refresh operation is disabled when the MPU is accessed, so that a malfunction due to a drop in the power supply voltage can be avoided. For example, the logic circuit 810 of FIG. 10 can set the refresh operation to be disabled at the time of MPU access.

  Further, when the resolution of the display panel is increased, blurring of the screen may be noticeable when the refresh operation is performed in the non-display period. In the present embodiment, the voltage supplied to the scanning line and the voltage supplied to the data line can be set to be the same during the non-display period. That is, in the non-display period, the voltage applied to each pixel of the display panel can be 0V. As a result, the present embodiment prevents screen blurring and the like, and can drive a high-resolution display panel with higher image quality.

  Note that the present embodiment can exhibit the same effect as described above for a display panel with a low resolution. This embodiment can drive various display panels 20 (for example, TFT liquid crystal, TFD liquid crystal, simple matrix liquid crystal, organic EL panel, inorganic EL panel, etc.). Also, various drive systems (for example, MLS drive, PWM system, etc.) can be supported.

  Further, the present invention is not limited to that described in the above embodiment, and various modifications can be made. For example, terms cited as broad or synonymous terms in the description in the specification or drawings can be replaced by broad or synonymous terms in other descriptions in the specification or drawings.

1 is a block diagram showing an electro-optical device. It is a figure which shows the connection relation of an OTP circuit, a control register, and a control circuit. The figure which shows the OTP circuit comprised by one OTP cell group, the control circuit, and the control register. The circuit diagram which shows an OTP cell. The figure which shows the signal level of a protection signal, a read signal, and a write signal in each operation | movement with respect to an OTP cell. The circuit diagram of a reference cell. The figure which shows the timing of the refresh operation | movement which rewrites the contrast adjustment parameter to a control register. It is a figure which shows the relationship between the timing of refresh operation | movement, and a power supply voltage. The figure which shows the path | route of the through current which flows at the time of read-out operation | movement of the OTP cell in which write-in operation is not performed. The figure which shows the logic circuit which sets a refresh operation to disenable at the time of MPU access. FIG. 11 is a timing waveform diagram showing a relationship between an input signal and an output signal of the logic circuit of FIG. 10. The circuit diagram of the latch circuit contained in a control register. FIG. 5 is a timing waveform diagram showing voltages applied to pixels of a display panel.

Explanation of symbols

1 electro-optical device, 10 MPU (processor unit), 20 display panel,
30 display driver, 100 OTP circuit (nonvolatile memory circuit),
110 reference cell, 120 mask bit ROM, 130 OTP cell,
200 display RAM, 300 RAM control circuit, 400 control register,
500 power supply circuit, 600 scan driver, 700 data driver,
800 control circuit, DTR determination transistor,
RDR read transistor,
PROM, RPROM floating gate transistor,
PTR, RPTR protection transistor,
QTR1 first output transistor, QTR2 second output transistor QTR3 third output transistor, QTR4 fourth output transistor WTR, RWTR write transistor

Claims (5)

A scan driver and a data driver for driving the display panel;
A control circuit;
A control register,
The control register is
The display characteristic parameter corresponding to the display characteristic of the display panel is received and stored from the nonvolatile memory circuit in which the initial characteristic is written,
The control circuit includes:
A refresh operation in which the display characteristic parameter is read from the nonvolatile memory circuit and rewritten in the control register is performed at a predetermined timing set in a first half period of the non-display period of the display panel. driver. In claim 1,
The control circuit includes:
In the non-display period, the display driver is controlled so that a voltage for driving the display panel by the scanning driver and a voltage for driving the display panel by the data driver are the same. In claim 1 or 2,
The control circuit includes:
A display driver that disables the refresh operation of the nonvolatile memory device during a period in which a processor unit that controls the display driver is accessing the control circuit. In any one of Claims 1 thru | or 3,
A power circuit,
The display characteristic parameter includes a contrast adjustment parameter,
The power supply circuit is
A display driver which receives the contrast adjustment parameter written in the control register from the nonvolatile memory circuit from the control register and outputs a predetermined voltage based on the contrast adjustment parameter. A display driver according to claim 1;
A display panel;
A processor unit for controlling the display driver;
An electronic device comprising:

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