JP2008096325A - Board for diagnosing dynamic board - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve problems such as low transfer rate due to a daisy chain constitution from a serial bus connection and difficulty in detecting erroneous operation or fault in an operation state due to operation by the clock different from that used for the operation of a processor or an LSI in utilizing a previous boundary scan. <P>SOLUTION: A printed circuit board mounting a plurality of processors and various LSIs includes: a diagnosis control part comprising a means acquiring the operation state of the LSIs and a recording means for storing the acquisition results; a means for acquiring the acquisition results and the operation state of the processors; and a recording means for storing the acquisition results. Under this arrangement, the dynamic board diagnosing system is achieved by providing a means managing and storing the data at the same time axis in a time-series and an analysis means specifying the factor of fault and fault place in the operation state based on the operation state of the processors and the results acquired in the LSIs. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to an in-vehicle control board, an elevator control board, an inspection apparatus control board, and a board diagnosis system and system for a system incorporating these.

  With the recent enhancement of functionality of electronic equipment, multiple LSIs and processors (microcomputers) are mounted on a circuit board at high density. On the other hand, low-voltage and high-speed electronic components such as semiconductor integrated circuits are installed in circuit boards. Malfunction / failure is a problem. In the case of higher density, it is difficult to detect failures and evaluate them visually by touching the probe from the outside due to the appearance of a device that has a connection part represented by BGA (Ball Grid Array) on the lower surface of the package substrate. It has become. In addition, since the number of boards on which a plurality of high-performance LSIs such as processors, SoCs, FPGAs, and the like are mounted is increasing, it is difficult to identify the cause of a failure due to component failure or wiring failure from the phenomenon. In addition, the operation speed has been increased, and the frequency of intermittent failures due to poor margins in signal transfer between LSIs and processors has increased. In particular, intermittent failures such as margin failures are often affected by the operating environment, and even if you try to perform detailed failure analysis by removing the device from which the failure occurred, you cannot reproduce the failure. A lot is happening. For this reason, it is not possible to identify an essential failure / failure factor, resulting in an increase in countermeasures and maintenance man-hours.

Conventionally, in circuit board fault diagnosis / inspection, there is a digital boundary scan test according to IEEE standard 1149.1. In this method, a shift register called a cell is arranged between the internal logic and each signal pin, and a signal passing through the shift register is monitored or arbitrary data is inputted. That is, the cell functions equivalent to a test probe in a conventional in-circuit test. Furthermore, an instruction register for receiving an instruction, a bypass register for outputting input data through the shortest path, and a TAP controller (Test Access Port) for controlling boundary scan cancellation are incorporated. As a result, TDI (Test Data Select), TMS (Test Mode Select), TCK (Test Clock), TDO (Test Data Out), TST (Test Reset), and TRST (Test Reset) can be used for inter-connection tests with external circuits. The wiring connection between LSIs on the printed circuit board is inspected and diagnosed.
Also, a diagnosis / analysis method has been proposed in which the operation state of input / output pins of an LSI or a processor is displayed in real time using the boundary scan.

Japanese Patent Laid-Open No. 5-99980 JP 2005-214957 A

  The use of conventional boundary scan mainly aims to realize connection diagnosis of circuit boards in equipment with few signals, so it has a daisy chain configuration with serial bus connection, transfer speed is slow, and processor and LSI operations Because it operates with a separate clock, it is difficult to detect malfunctions and failures in the operating state. Moreover, when a processor is mounted on a circuit board and operates in cooperation with each other, it is difficult to diagnose whether the cooperative control is normal even if there is no abnormality for each processor.

  In addition, regarding an in-vehicle control board mounted on an automobile, it is difficult to identify a failure / failure location that occurs during traveling, and it is also difficult to reproduce the traveling environment during evaluation / analysis. With respect to elevators such as elevators, it is also difficult to identify a defective part at the time of cooperative control between a plurality of boards such as an overall control board and a car control board, a processor, and an LSI. Moreover, since it is difficult to stop the customer elevator for a long time for evaluation and analysis, it is difficult to identify the cause in the operation environment.

  The present invention solves the above-mentioned problems and implements on-board control that realizes board diagnosis characterized by performing fault detection, diagnosis, and analysis in real time on a control board on which a plurality of processors, logic LSIs, and the like are mounted. The present invention provides a board diagnosis method for a board, an elevator control board, an inspection apparatus control board, and these embedded systems.

The following is a brief description of an outline of typical inventions disclosed in the present application.
(1) A printed circuit board on which a plurality of processors and various LSIs are mounted,
Provided is a diagnostic control unit having means for acquiring the operating state of the LSI and means for storing the acquisition result, means for acquiring the result and the operating state of the processor, and means for storing the acquisition result, A means for managing and storing the data in time series on the same time character axis is provided, and an analysis means for specifying a failure factor and a part in the operation state based on the operation state of the processor and the result obtained by the LSI is provided. Is a printed circuit board characterized by
(2) A printed circuit board on which a plurality of processors and various LSIs are mounted,
A diagnostic control unit having means for sampling input / output signals in the LSI and means for storing the sampling result is provided, means for acquiring the result and the operating state of the processor, and means for storing the acquisition result are provided. , Provided with means for managing and storing the data in time series on the same time character axis, and provided with analysis means for identifying the failure factor and part in the operating state based on the operating state of the processor and the result obtained by the LSI It is the printed circuit board characterized by this.

  The present invention provides a diagnostic control unit having means for acquiring the operation state of the LSI and means for storing the acquisition result in a printed circuit board on which a plurality of processors and various LSIs are mounted. Further, a means for acquiring the acquisition result and the operating state of the processor and a means for storing the acquisition result are provided, and a means for managing and storing the data in time series on the same time axis is provided. Based on the operation state and the result obtained by the LSI, an analysis means for specifying a failure factor and a part in the operation state is provided to realize a dynamic board diagnosis method.

  According to the present invention, it is possible to solve the above-mentioned problems and realize a board diagnosis characterized in that a control board on which a plurality of processors, logic LSIs and the like are mounted is detected in real time in the operating state, diagnosed and analyzed. An in-vehicle control board, an elevator control board, an inspection apparatus control board, and a board diagnosis system for these embedded systems can be provided.

Hereinafter, embodiments of the present invention will be described with reference to the drawings using examples.
As an embodiment, a control board of an embedded system such as an in-vehicle control board, an elevator control board, or an inspection apparatus control board will be described as an example. FIG. 1 shows a configuration which is an embodiment of the substrate diagnosis system of the present invention.

  A board on which logic LSIs 13, 14, 15 and processors 16, 17 as main components for realizing a desired function are mounted on a printed board 18 generally used in various apparatuses, embedded devices, automobiles, and the like. In each of the logic LSIs (13, 14, 15), an operation state and input / output signals are acquired as diagnostic data, and a diagnostic control unit 11 for performing input / output control of the acquired diagnostic data is provided. 17 is provided with a test control unit 12 that acquires operation states, main register contents, error interrupt information, and the like as diagnostic data and performs input / output control of the results. Furthermore, a diagnostic processing unit 10 is provided for performing integrated control and management of diagnostic data from the logic LSIs 13, 14, 15, and processors 16, 17. The diagnostic processing unit 10 includes a diagnostic bus control unit 24 that collects diagnostic data from the logic LSI and the processor, a result storage unit 25 that stores the result, and a failure analysis unit that identifies a failure part and analyzes the cause 19 is a result output unit 26 that performs I / F control with 19 and a diagnosis timing control unit 23 that controls operation timing such as data acquisition and input / output timing of the logic LSI and processor diagnosis control unit 11 and test control unit 12. Constitute. In this embodiment, an operation clock for diagnosis control to the diagnosis control unit 11 and the test control unit 12 of the logic LSI and the processor is output from the diagnosis processing unit 10, and at a unified operation timing between the logic LSI and the processor. Perform diagnostic control.

  FIG. 2 shows a detailed configuration of the diagnostic processing unit 10. The diagnosis processing unit 10 receives a clock signal 41 from the outside, the diagnosis timing control unit 23 generates a diagnosis control timing based on the clock, and the diagnosis control unit 11 of the logic LSIs 13, 14, 15 and the processors 16, 17. The operation timing signal 31 of the test control unit 12 is output. The diagnostic bus control unit 24 transmits a diagnostic data acquisition instruction from the logic LSI or processor based on the operation timing 43 from the diagnostic timing control unit by the diagnostic bus 32 for transferring diagnostic instructions and diagnostic result data. Collect diagnostic result data. This acquisition instruction is output in consideration of the operation state sampling timing in the logic LSI or the processor. The collected diagnostic result data is stored in the diagnostic result storage unit 25. At this time, the history of the operation status acquisition instruction timing of the logic LSI and the processor and the diagnosis result data of the logic LSI and the processor are stored and managed in association with each other in the diagnosis result storage unit 25. When saving the diagnosis result, the time data of the diagnosis time management unit 46 having a circuit capable of calculating the time, such as a timer counter, is simultaneously saved. The diagnosis result output control unit 26 performs input / output timing to the failure analysis unit 19 that performs fault location identification and factor analysis on the data stored in the diagnosis result storage unit 25, bus arbitration of the input / output bus 33, and the like. In this embodiment, the diagnosis instruction and diagnostic data transfer bus is an example of a daisy chain configuration by serial bus connection, but a star connection or the like in which the diagnosis processing unit 10 is individually connected to each logic LSI or processor may be used. Further, this diagnostic bus may be constituted by a boundary scan.

  FIG. 3 shows the configuration of the logic LSI (logic LSIs 13, 14, 15 in the example of FIG. 1) and the diagnosis control unit 11. A diagnostic bus local control unit 52 for connecting to the diagnostic processing unit 10 or connecting to a logic LSI or processor other than the case where the diagnostic bus connection structure is a daisy chain and performing I / F control of diagnostic data is provided. Further, the internal status acquisition control unit 51 acquires in accordance with the operation timing signal 31 and an instruction from the diagnostic bus 32. This acquisition result is stored in the log memory 54. At that time, the acquisition timing (acquisition time) is also stored in the log memory 54. In addition, an input / output monitoring unit 53 for monitoring input / output signals of the logic LSI is provided. The input / output signal monitoring unit 53 samples a change in the input / output signal, and generates a unique eigenvalue by a logical operation in the time direction. The eigenvalue generation circuit stores all changes in input / output signals even when the diagnostic processing unit 10 collects diagnostic data intermittently. This eigenvalue generation circuit also has a method of generating an eigenvalue by performing a logical operation on a sampling result and a random number. An example of the eigenvalue generating circuit based on the combination with this random number is shown in FIG. In the example of FIG. 4, a counter composed of a shift register that is fed back by EOR. When the number of flip-flops is n, an eigenvalue is generated by integrating an input / output signal (Data Flow in the figure) with a pseudo random number generation circuit LFSR (Linear Feedback Shift Register) that counts up to 2n−1 by EOR. The essence of the present invention does not change even if both the internal status acquisition control unit 51 and the input / output signal monitoring unit 53 are provided. Further, when the diagnosis control unit 11 is implemented by boundary scan, it is realized by adding a user-defined command for the boundary scan and acquiring and controlling the internal state. In this case, the diagnosis processing unit 10 controls the acquisition timing and the input / output timing of the diagnostic bus to unify the diagnostic data acquisition timing and diagnostic bus control from the main components to be diagnosed such as all logic LSIs and processors on the board. It is characterized by controlling with time management and managing diagnostic data in time series.

  FIG. 5 shows a configuration example of the test control unit 12 in the processor. The operating state of the processor can be realized by acquiring the contents of internal general-purpose registers and status registers. The processor stores execution instructions described in the program in the instruction memory, and sequentially executes the stored instructions. In the present invention, means for monitoring and acquiring the internal state is provided separately from a program for realizing a desired function. This means is realized by a program for executing state monitoring and acquisition in addition to the above program. However, a state monitoring and acquisition circuit may be separately provided on the circuit in the processor. Alternatively, another LSI that monitors an interrupt from the processor may be provided. Here, when the state monitoring / acquiring means is provided by a program, the internal state is written from the processor core 64 to the general-purpose register or the dedicated state monitoring register (63) at a desired interval by this program. The diagnostic bus local control unit 52 acquires the internal state of the processor core 21 according to the operation timing signal 31 and the instruction from the diagnostic bus 32 based on the contents of the register 63. This acquisition result is stored in the log memory 54. At that time, the acquisition timing (acquisition time) is also stored in the log memory 54. Further, when the test control unit 12 is implemented by boundary scan, it is realized by adding a user-defined command for the boundary scan and acquiring and controlling the internal state. In this case, the diagnosis processing unit 10 controls the acquisition timing and the input / output timing of the diagnostic bus to unify the diagnostic data acquisition timing and diagnostic bus control from the main components to be diagnosed such as all logic LSIs and processors on the board. It is characterized by controlling with time management and managing diagnostic data in time series. In addition, when the boundary scan is used, the sampling result of the input / output signal can be obtained from the register 63 or the boundary scan register. In this case, the acquisition timing is also stored in the log memory 54.

  FIG. 6 shows operation timings in the embodiment shown in FIG. FIG. 6 shows the operation timing of the diagnostic operation of the logic LSI-L1 (13) and the input / output signal monitoring of the L2 (14). Output signals (Data 0 to 5 in the figure) from the logic circuit of L1 are taken into the input / output signal monitoring unit 53 to generate eigenvalues (Sig-0-0 to Sig4-4 in the figure). This result is stored in the log memory 54. At the same time, the internal state is acquired by the internal status acquisition control unit 51 and stored in the log memory 54. The output signal output from L1 is input to L3, and an eigenvalue is generated from this input result as in L1. The diagnostic processing unit 10 instructs the diagnostic bus 32 to acquire diagnostic data at a desired interval (“Read” in the figure). At this time, the command issuance timing (time) is recorded and used for managing the acquisition time of diagnostic data from each logic LSI or processor. However, the diagnosis control unit 11 and the test control unit 12 may be provided with a timer, output to the diagnosis bus 32 together with the diagnosis data, and the data acquisition time may be managed by centralized control by the diagnosis processing unit 10 or the failure analysis unit 19 or the like. .

  FIG. 7 shows an example of a control circuit for generating eigenvalues in FIG. FIG. 7A shows an example of a logic circuit of a logic LSI, which is composed of statuses [ACT1], [ACT2] and [ACT3] for executing desired processing and [IDLE] which is a wait status. FIG. 7B shows a circuit example of the diagnostic control circuit 11, and as an input signal for control, an RST signal that is an initial reset signal of the circuit, a VLD signal indicating the validity of data, and a DRST signal that initializes an eigenvalue It is. The output signal outputs an operation enable signal to an eigenvalue generation circuit (for example, the circuit shown in FIG. 4). In this example, a DRST signal is output at the time of transition from ACT3 to IDLE, which ends a series of operations in the internal logic circuit, and is used as a data reset timing of the diagnosis control unit 11. As a result, it is possible to obtain a result in which the generated eigenvalue is also associated with the operating state of the internal circuit. Further, the diagnosis control unit 11 can eliminate the influence of indefinite and invalid data by executing eigenvalue generation according to the VLD signal.

  FIG. 8 shows an example of operation timing of a diagnostic bus having a serial bus structure. In the example of FIG. 8 in which the diagnostic bus 32 has a serial bus structure, the diagnostic instruction from the diagnostic processing unit 10 propagates to L1, L3, and P1, and the operation state of each component is determined by the diagnostic control unit 11 or the test control unit 12. Obtain and output to the diagnostic bus 32. At this time, the diagnosis control unit 11 and the test control unit 12 according to the present invention input an instruction (command) related to diagnosis control in the diagnosis bus local control unit 52, input, storage, operation status acquisition, diagnosis status data 32, and pre-diagnosis result data. Output to. The output to the diagnosis bus 32 is made by adding the self-diagnosis result data to the diagnosis result data of the previous part, and sending the diagnosis result data of all parts to the diagnosis processing unit 10. As shown in FIG. 8, the diagnosis timings of all components are synchronously controlled to control the acquisition timing of the internal data and the change data of the input / output signals, which are diagnostic data.

  FIG. 9 shows an example of an analysis result display method in the failure analysis unit 19. This embodiment is intended for diagnosis of a board whose main components are the processors indicated by P1 and P2 and the logic LSI indicated by L1, L2 and L3, and the respective operation states and eigenvalues are displayed. In the present invention, since diagnosis data acquisition timings for all diagnosis targets are executed in a unified manner, the failure analysis unit 19 displays this diagnosis result on a time axis. By displaying the operation status of all components on the time axis, it is possible to easily diagnose and analyze the target board. In addition, by providing the failure analysis unit 19 with an expected value of the operation state, it is possible to detect an error as a substrate operation by comparing with the acquired result (t = 3 in the example in the figure).

  FIG. 10 shows an embodiment of the in-vehicle control board. As a main component configuration, an analog signal indicating the number of rotations is received from a logic LSI 72 that controls a control pulse to the engine or motor on a vehicle-mounted control board 71 and a connector 77 that transmits and receives signals between the engine and motor, and converted into digital data. It comprises an RD converter 73 for conversion, processors 74 and 75 for generating vehicle control and engine and motor control pulses, and a vehicle control setting storage memory 76, and is connected to the diagnosis processing unit 10 by an operation timing signal 31 and a diagnosis bus 32. The In this example, it is a star connection configuration that is individually connected to the diagnosis processing unit 10.

  FIG. 11 shows an embodiment of an elevator (elevator) according to the present invention. In this example, the elevator system is composed of an integrated control panel 81, a terminal device 82, a drive motor 83, and a car 86. In this embodiment, the diagnosis method according to the present invention is applied to the integrated control board 84, the terminal device 82, and the operation control board 85 in the car mounted on the integrated control panel 81. The operating states of the processors and logic LSI mounted on the respective boards are monitored and diagnosed, and the diagnosis results are collected on the integrated control board 84. When failure analysis is necessary, the failure analysis unit 19 is connected to the integrated control board 84 for analysis. The board for collecting the diagnosis results is not limited to the integrated control board 84. Further, the collection is not limited, and each substrate can be analyzed individually.

  FIG. 12A shows an example in which the failure analysis unit 19 is provided on the substrate. FIG. 12B shows an example in which the diagnosis processing unit 10 is provided separately from the diagnosis target board (circuit) (diagnosis control board 91 as another board). At this time, the diagnosis processing unit 10 and the failure analysis unit 19 may be integrated on the same substrate.

  As described above, it is possible to perform real-time diagnosis in the operating state of main components mounted on a substrate such as a logic LSI or a processor, and it is possible to unify operation timing (time) and diagnosis timing of each component. In addition, logic LSI operation status and I / O signal transfer confirmation and processor operation status are recorded and saved in time series, and the results are displayed in time series to monitor the operation status of the entire board, and detect and analyze errors. Can be made easier. In addition, by providing a monitoring circuit (eigenvalue generation) at the input / output pins in the logic LSI and providing means for monitoring the contents synchronously with the processor status, whether the cause of the processor state abnormality is due to an external input abnormality It is possible to determine the failure location. In addition, it is also possible to use a boundary scan standardized by IEEE as an acquisition means.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the above embodiment, and various modifications can be made without departing from the scope of the invention. Not too long. INDUSTRIAL APPLICABILITY The present invention can be used for in-vehicle control boards such as automobile engines and motors, control boards for various elevators (elevators, etc.), various boards such as semiconductor manufacturing apparatuses, inspection apparatuses, and medical apparatuses.

  According to the present invention, inter-LSI signals, status and processor status can be monitored in conjunction with the log acquisition position and time, so static failures such as connection failures and stack failures, margin shortages, external I / F factors, and cooperative operations It is possible to detect a dynamic malfunction in an operational state such as an indefinite operation due to, and to identify the cause. In addition, since malfunction factors can be identified during real-time operation in the operational state, it is possible to reduce the number of evaluation / analysis man-hours and to reduce maintenance / modification costs. In addition, since intrinsic malfunctions, failure factors, and unstable operation factors are identified, product quality and reliability can be improved, and product competitiveness can be improved. In addition, the acquisition of diagnosis results can be configured by a boundary scan chain, and in this case, it is not necessary to increase the number of signal lines for new diagnosis and analysis on the substrate when implementing the method according to the present invention.

It is the figure which showed an example of the structure of the dynamic system which concerns on embodiment of this invention. It is the figure which showed an example of the structure of the diagnostic process part which concerns on embodiment of this invention. It is the figure which showed an example of the structure of the diagnostic control part which concerns on embodiment of this invention. It is the figure which showed an example of the eigenvalue generation circuit by the pseudorandom numbers of this invention. It is the figure which showed an example of the structure of the test control part which concerns on embodiment of this invention. It is explanatory drawing of the diagnostic bus operation | movement of the diagnostic control part and diagnostic processing part of this invention. It is the figure which showed an example of the diagnostic control circuit. It is explanatory drawing of the diagnostic bus operation | movement of the diagnostic control part and diagnostic processing part of this invention. It is the figure which showed an example of the display data and data attribute of the failure analysis part of this invention. It is the figure which showed an example which applied this invention to the vehicle-mounted control board. It is the figure which showed an example which applied this invention to the elevator (elevator). It is the figure which showed the example which made the diagnostic processing part and failure analysis part of this invention another structure.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... Diagnosis processing part, 11 ... Diagnosis control part, 12 ... Test control part, 13 ... Logic LSI, 14 ... Logic LSI, 15 ... Logic LSI, 16 ... Processor, 17 ... Processor, 18 ... Board | substrate (diagnosis object board | substrate), DESCRIPTION OF SYMBOLS 19 ... Failure analysis part, 21 ... Processor core, 22 ... Register, 23 ... Diagnosis timing control part, 24 ... Diagnosis bus control part, 25 ... Result storage part, 26 ... Result output part, 27 ... Logic circuit, 31 ... Operation timing Signal 32 Diagnostic bus 33 Connection connector 34 Input / output signal (logic LSI data bus) 35 Operation state acquisition signal 41 Clock signal 42 Diagnosis result data signal 43 Diagnosis reference timing signal 44 ... diagnosis result output control signal 45 ... diagnosis result data signal 46 ... diagnosis time management unit 51 ... internal status acquisition control unit 52 Diagnostic bus local control unit, 53 ... I / O signal monitoring unit, 54 ... Log memory, 55 ... Diagnosis result data signal, 56 ... Logic LSI output data, 57 ... Eigen value data, 58 ... Logic LSI input data, 59 ... Diagnostic reference timing Signals 61... Status processing section 71 71 Onboard control board 72 72 Logic LSI (for in-vehicle use) 73 ... R / D converter 74 74 Processor 75 75 Processor 76 Memory 81 Integrated control board 82 Terminal device 83 ... Motor for driving 84 ... Integrated control board 85 ... Car operation control board 86 ... Car 91 ... Diagnostic data connector

Claims (13)

A printed circuit board on which a plurality of processors and various LSIs are mounted,
Provided is a diagnostic control unit having means for acquiring the operating state of the LSI and means for storing the acquisition result, means for acquiring the result and the operating state of the processor, and means for storing the acquisition result, A means for managing and storing the data in time series on the same time character axis is provided, and an analysis means for specifying a failure factor and a part in the operation state based on the operation state of the processor and the result obtained by the LSI is provided. Printed circuit board characterized by A printed circuit board on which a plurality of processors and various LSIs are mounted,
A diagnostic control unit having means for sampling input / output signals in the LSI and means for storing the sampling result is provided, means for acquiring the result and the operating state of the processor, and means for storing the acquisition result are provided. , Provided with means for managing and storing the data in time series on the same time character axis, and provided with analysis means for identifying the failure factor and part in the operating state based on the operating state of the processor and the result obtained by the LSI A printed circuit board characterized by that. A printed circuit board on which a plurality of processors and various LSIs are mounted,
A diagnostic control unit comprising: means for sampling an input / output signal in the LSI; means for generating a unique eigenvalue from the sampling result in a logical direction in the time direction; and means for storing the sampling result and the eigenvalue A means for acquiring the result and the operating state of the processor; a means for storing the acquisition result; a means for managing and storing the data in time series on the same time axis; and A printed circuit board provided with an analysis means for specifying a failure factor and a part in an operation state based on a result obtained by an LSI. A printed circuit board on which a plurality of processors and various LSIs are mounted,
A diagnostic control unit having means for sampling an input / output signal in the LSI, means for logically operating the sampling result and a random number to generate an eigenvalue, and means for storing the sampling result and the eigenvalue; Means for acquiring the operating state of the processor and means for storing the acquisition result, means for managing and storing the data in time series on the same time axis, and acquiring the operating state of the processor and the LSI A printed circuit board provided with an analysis means for identifying a failure factor and a part in an operation state based on a result. The printed circuit board according to any one of claims 1 to 4,
Further, a printed circuit board comprising a diagnostic processing LSI provided with means for acquiring the operating state of the processor and the operating state of the LSI, and managing and storing the acquired result data in time series on the same time axis . The printed circuit board according to claim 5,
A printed circuit board characterized in that an analysis means for specifying a failure factor and a part in an operating state is provided in the diagnostic processing LSI. The printed circuit board according to claim 6,
A printed circuit board characterized in that the diagnostic processing LSI is a separate board or a separate system from the board to be subjected to failure diagnosis. The printed circuit board according to claim 7,
A printed circuit board comprising means for acquiring an operating state of the processor and an operating state of the LSI through a dedicated bus connection. The printed circuit board according to claim 8,
A printed circuit board characterized in that the dedicated bus is configured to use a serial bus or a boundary canvas, and means for controlling operation state acquisition timing in the serial bus is provided. The printed circuit board according to claim 9,
A printed circuit board comprising means for storing all acquired data from the processor and LSI as data that can be searched in time series and means for displaying diagnosis results in time series based on the data. A dynamic board diagnostic system,
A dynamic board diagnosis system that dynamically diagnoses a board using the printed circuit board according to claim 1. A manufacturing apparatus comprising the substrate according to claim 5. An automobile comprising the substrate according to any one of claims 5 to 10.

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