JP2008092268A - Asic and image forming device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that direct radiation of electromagnetic waves emitted from interconnecting wires because an instantaneous transient current generated by a switching current (a transient through current) or the like flows through internal wiring, and indirect radiation emitted because a signal is generated by voltage drop of internal power source and an abrupt voltage change which are resulting from the instantaneous transient current and then the signal thus generated is overlapped on an IO output terminal to be output, and as a result unwanted radiation resulting from the direct and indirect radiations has reached a nonnegligible level. <P>SOLUTION: Skew adjustments of a clock inside an ASIC is performed in a distributed manner to eliminate the unwanted radiation by a system using its ASIC. Specifically, at least two or more blocks which are connected with the same clock terminal and from the terminals of which the clock skews are different from each other are formed. Then, timings to execute a clocking-on operation are allowed to be different from each other and thereby the connection with a power supply is practiced with a contact arranged astride a plurality of the blocks at least between the same power source lines. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to an ASIC designed using a synchronous clock and an image forming apparatus using the same, and more particularly to reducing unnecessary radiation caused by switching of a synchronous circuit in the ASIC.

Conventionally, in a semiconductor integrated circuit (IC) composed of a synchronous circuit and equipped with a plurality of independent functional blocks, all flip-flops connected by the same clock are examined, the delay from the clock input terminal is calculated, and the FF The clock tree is adjusted so that the clock delay from the input terminal of the clock supplied to each flip-flop is made equal to improve the operation performance (IO AC specifications, etc.). . Specifically, the design is such that the clock skew falls within a range of ± 500 PS or less.
JP 2000-307395 A JP 2004-348466 A JP-A-10-091274 Introduction to MOS LSI design (J. Maber MA Jack J. P. B. Denia, Takuo Kanno, translated by Takayasu Sakurai) Industrial Books P65-69 "CMOS applied design technique" Author Yasuji Suzuki, P72-76 Design wave magazine November 2002 issue P143 Super High-Speed MOS Device Author Supervision by Takuo Kanno Henfu Kayama P236〜P257 Super-high-speed MOS device Author Supervision by Takuo Kanno Henfu Kayama ed. P245 Figure 6.17

  However, what becomes a problem here is simultaneous switching by a gate of a buffer, an inverter or the like related to driving of the FF in the ASIC (IC).

  As ASICs are highly integrated, multiple gates can be mounted on a single chip. As a result, many logical functions can be mounted on a single chip by mounting multiple FFs.

  Conventionally, an IC having a sufficiently large IC even at 10,000 gates has recently become a normal one having 100,000 to 10 million gates, and more than that has been increasing. For this reason, as a result of an increase in the chip size, the length of the internal power supply wiring has increased, and the moment due to the switching current (transient through current) due to the switching operation of inverters and buffers for driving many FFs, etc. As a result of the direct current of electromagnetic waves from the wiring caused by the internal current flowing through the internal wiring, the resulting voltage drop of the internal power supply, and sudden voltage changes, the signal is superimposed on the IO output terminal and output. Unwanted radiation due to the indirect radiation that has occurred is at a level that cannot be ignored.

  At the same time, the simultaneous switching of the buffer such as the clock buffer and the gate of the inverter related to the simultaneous operation of the FFs inside the ASIC may cause a decrease in the circuit operation margin or cause a malfunction of the system. .

  This will be specifically described.

  First, an FF driver circuit as shown in FIG. 6B will be described with reference to FIG. 7A, which is a detailed circuit of the 6-1 to 6-2 inverter circuits.

  A CMOS inverter circuit is normally composed of a PCH MOS FET of 7-1 and an NCH MOSFET of 7-2 in FIG. 7 (a). For detailed operation, refer to Non-Patent Document 1, etc. Although omitted, as in 7-1, the source side of the PCHMOS FET is connected to VDD, the drain side is connected to the output terminal of 7-4 and the drain of the NCHMOS FET of 7-2, and the source is connected to VSS. Then, connect the gates of FETs 7-1 and 7-2 to the input terminal 7-3, and apply sufficient power to turn on both FETs 7-1 and 7-2 between VDD and VSS. When VIN is varied from 0V to VDD between the input terminal of 7-3 and VSS, the output voltage of 7-4 changes like the characteristic of Vo shown in FIG. 7B, and in this example, the maximum current is changed. When is VDD / 2 Although this value varies depending on the dimension design of PCHMOS and NCHMOS, current flows when the FETs 7-1 and 7-2 are in the ON region. If an ideal square wave is added, this transient current should be zero by nature, but the signal waveform of the actual clock cannot have a signal rise tr of 0. In addition to the charge / discharge current of the gate capacitance of the next stage, a transient current due to a through current flowing in both PCH and NCHFET flows.

  When switching in an actual ASIC, how to reduce the transient current when both the PCH MOS and NCHMOS are on is an important issue for reducing power consumption and unnecessary radiation.

  Next, FF (flip-flop) (hereinafter referred to as FF) will be described.

  By connecting the output terminal of the inverter 6-2 in FIG. 6B to φ and the output terminal of the inverter 6-1 to φ bar, and connecting them to φ and φ bars of the circuit of FIG. A DFF (D type flip-flop) (hereinafter referred to as DFF) that enables the operation of the symbol shown in FIG.

(Refer to Non-Patent Document 2 for details of the FF, and specific operations and the like are also described there, so the detailed description is omitted.)
When a clock as shown in the lower diagram of FIG. 8B is applied to the input terminal 6-4 in the FF configured as described above, the transient current such as the current waveform in the upper diagram of FIG. It flows in a range of about 0 to 0.5 nsec after each transition and after the transition.

  A clock is simultaneously input to the clock input of several thousand FFs, and a transient current having a very steep rising of several hundred mA / power supply PIN or more flows at the rising and falling edges. It is empirically known that when such a steep current (voltage) change flows in a wiring of several mm, it must be handled in a distributed constant manner. Then, the impedance changes from a fixed constant to a distributed constant, and this is nothing but loss due to radiation due to the L component or the like, that is, radiation noise in other words.

  With a fixed constant, the negligible L component changes and increases as a function of current change, and together with unwanted radiation due to L, power supply voltage fluctuations due to the effect of Ldi / dt are caused in the internal power supply, so that the ASIC Also creates instability factors. (L is an inductance component on the power supply wiring) In particular, when the wiring width is narrow, the inductance value increases, so that such a phenomenon is likely to occur.

(See Non-Patent Documents 3 and 5)
Wiring length on recent ASIC has been increasing from 5mm up to the size of more than 10 mm, the lead frame of QFP (size 256PINQFP is 28mm ² there) wiring length of the power supply, including the VDD, each VSS It can be considered that the worst reaches 10-20mm.

That is, when such a condition occurs inside the ASIC, it has been actually observed that very strong unnecessary radiation occurs when the timing of the FF simultaneous switching skew is in the range of ± 200 PS, and in the range of ± 500 PS. But it is dangerous. (If there is a distribution that causes a partially nonlinear current change)
Specifically, td = L√εr / Co
(L: wiring length, Co: speed of light, εr: relative permittivity, td (or tr): voltage and current rise time)
Since the rise td becomes stricter than the above condition, it is necessary to treat the circuit in a distributed constant manner, but no design countermeasures have been taken yet.

  As a result, the skew adjustment capability of recent layout tools has increased, and as a result, the skew of the circuit has increased by one to two orders compared to the conventional one. As a result of the simultaneous switching of FFs by tuning the skew, design conditions have entered a region where the wiring region must be handled in a distributed constant manner within the macro ASIC. Specifically, at the 10,000 gate level, it has become possible to design with FF clock timing with a skew of about several tens of PSECs.

  When such an ASIC is used, the internal wiring of the ASIC is distributed in a constant-constant manner by flowing a counselor with a steep rise of about 100PS to 300PS and current in the ASIC's internal wiring at the time of switching on / off of the FF. By entering the area that needs to be handled, the clock signal is superimposed on the IO pin due to the fluctuation and radiated to the outside as a noise component, and the unnecessary radiation level caused by the ASIC in the system device is set outside the ASIC. It has become very difficult to drop by measures such as IO.

  The cause is not only the buffers by the inverters 6-1 and 6-2, but also the four NORs constituting the FF body (this is equivalent when the set and reset terminals are fixed at L. Since it becomes an inverter, the above-mentioned transient current may flow when the FF data is inverted.

  Therefore, a technique for suppressing such unnecessary radiation is required.

  As an example, there is a technology that makes it seem that the unnecessary radiation is reduced by using the SSCG to sequentially change the spectrum. However, such means cannot eliminate the noise source essentially, and it is costly. However, extra costs will be required for noise countermeasures. Specifically, as shown in the total current diagram of the circuit shown in FIG. 5, in the case of SSCG, the peak current cycle varies with the increase / decrease of the clock cycle as in the current waveform on the top floor. Since the current peak does not change at all by increasing / decreasing, the absolute value of unnecessary radiation does not essentially change and is not an essential measure.

  There is also a proposal to divide the block and apply SSCG inside the ASIC (see Patent Document 2). Even in this case, the conditions as described above can be easily achieved by the size of the block and the method of power supply wiring etc. Realized and does not become an essential measure against unwanted radiation.

  Although it does not generate unnecessary radiation with the above intensity, it is similar in terms of changing the power supply voltage, and various measures have been taken for simultaneous switching of ASIC IO, and now it satisfies the manufacturer's design rules. However, if an additional power supply PIN is added, the problem does not occur. However, there is a problem that the problem in this patent is likely to occur even if it is created by a normal rule.

  In fact, as an IO switching countermeasure, there is an idea that the timing for each functional block in the ASIC is taken by changing the number of clock buffers to reduce the cost (see Patent Document 1). The idea of changing the timing of the I / O buffer by changing the number of stages of the clock buffer is scattered, but in the megamacro function block, the block level now has thousands to tens of thousands of FFs Many of the problems mentioned in this patent can be easily caused by only simultaneous switching within one megamacro.

  In addition, various patents have been filed regarding conventional noise caused by simultaneous switching. The cause of the noise is based on the assumption that the amount of current and the noise source are equivalent. The parameter by is essentially ignored.

  In other words, in the conventional literature, the amount of current and the amount of noise generated are explained from the standpoint of being equivalent (proportional), but in this patent, the parameters of the current rise time and the wiring length inside the ASIC are important. This is a patent for noise from the viewpoint that a point where the amount of generated noise changes discontinuously occurs.

(See Patent Document 3)
Patent Document 3 describes that the amount of current and the amount of noise generated are equivalent, and other documents are considered to be described under the same conditions in principle.

1: It has at least two or more logic blocks connected to the same clock terminal and having different clock skew distributions from the terminal,
At least two or more of the plurality of blocks are arranged across the same power supply line, and power is supplied to the power supply terminals of the FF elements included in each block by wiring means such as contacts, metal wiring, and poly-Si. With this configuration, the movement of charges between short-distance logic blocks causes an effect of reducing the transient current flowing on the long power supply line, that is, the current di / dt.

2: The gnd and vdd power supply terminals to which the external power supply of GND and VDD is connected are arranged in pairs on the opposing surface of the package or a position corresponding thereto,
Gndpad that supplies the gnd potential to asic and vddpad that supplies the potential of VDD are connected by bumps, metal wires, etc., and power is supplied to the inside of the ASIC chip from opposite ends of the ASIC chip. Therefore, the current component of the common mode is canceled (even when considered on the same power line and combined with VDD and GND), and the load for supplying current from one power supply terminal is effectively reduced and equivalent An effect of shortening the wiring length occurs.

3: In an ASIC in which a plurality of logic blocks connected to the same clock terminal and having different clock skews from the terminal are formed,
By making all the rise times tr of the current peaks caused by the simultaneous switching of ff of the individual logic blocks be about 500 nsec or more, the counselor and the current are prevented from being concentrated, and the noise is prevented from being generated.

4: There are at least two logic blocks connected to the same basic clock terminal and having different clock skews from the terminal.
It has at least one block having a clock of a different system from the clock, and the timing of turning on the clocks is different from each other,
By arranging a plurality of blocks across at least the same power supply line, charge transfer occurs between short-distance logic blocks, thereby reducing the transient current flowing on the long power supply line, that is, the current di / dt. Effect occurs.

  5: The frequency of the clock of the other system is ½ or less of the basic clock frequency, or is an intermittent clock, so that an effect of reducing noise generation occurs.

  6: Capacitance is dispersed and inserted between at least the power supply, VDD, and GND to the separated block, and an effect of suppressing unnecessary radiation more effectively occurs.

  7: The capacity is more effectively used by using resources and suppressing unnecessary radiation by using a MOS capacity forming an empty gate that is not used for ASIC control.

  8: The ASIC effectively suppresses unwanted radiation with respect to an object mounted on a QFP structure lead frame.

  9: In the ASIC, a signal lead-out portion connected to a power source such as a lead frame is made of a material having a large L component at least, thereby effectively suppressing unwanted radiation.

  10: At least one or more of the ASIC's IO terminals can be directly connected to the circuit, load, sensor, etc. outside the board where the ASIC is placed without going through a buffer. There is an effect that it is possible to simplify and reduce the cost and to constitute a stable image forming apparatus with less unnecessary radiation.

As explained above, according to the present invention,
It has at least two or more logic blocks connected to the same clock terminal and having different clock skew distribution from the terminals, and at least two or more of the plurality of blocks straddle between the same power supply lines. Since power is supplied to the power supply terminals of the FF elements included in each block by wiring means such as contacts, metal wiring, poly-Si, etc., charge movement occurs between short-distance logic blocks As a result, the transient current flowing on the long power line, that is, the rise time tr of the current can be reduced, and the unnecessary radiation source mentioned in this patent can be eliminated.

  2: The gnd and vdd power supply terminals to which the external power supply for GND and VDD is connected are arranged in pairs on the opposite side of the package or the corresponding position, and the gndpad and VDD potentials that supply the gnd potential to asic respectively. Connected to the vddpad to be supplied with bumps, metal wires, etc., and from there, power is supplied to the ASIC chip from opposite ends of the ASIC chip, canceling the common mode current component, [same power line Even when considering VDD and GND together], it is possible to effectively reduce the load supplied by a single power supply terminal and to shorten the equivalent wiring length, which is unnecessary in this patent. There is an effect that the radiation source can be eliminated.

  3: In an ASIC in which a plurality of logic blocks connected to the same clock terminal and having different clock skews from the terminals are formed, all rise times tr of current peaks caused by simultaneous switching of ff of individual logic blocks are all 500 nsec. By setting it to a degree or more, it is possible to prevent concentration of the counselor and current and to eliminate unnecessary radiation sources mentioned in this patent.

  4: There are at least two logical blocks connected to the same basic clock terminal and having different clock skews from the terminals, and at least one block having a clock of a different system from the clock. The timing at which the clock is turned on is different, and at least the same power supply line is placed across multiple blocks, so that charge transfer occurs between short-distance logic blocks. The transient current flowing through the current, that is, the rise time td (tr) of the current is reduced, and the unnecessary radiation source mentioned in this patent can be eliminated.

  5: The frequency of the clock of the separate system is ½ or less of the basic clock frequency or is an intermittent clock, so that the unnecessary radiation source mentioned in this patent can be eliminated more effectively. effective.

  6: Capacitance is dispersed and inserted at least between the power supply to the separated block, VDD and GND, thereby eliminating the unnecessary radiation source mentioned in this patent more effectively. There is an effect that can be.

  7: By using a MOS capacitor that constitutes an empty gate that is not used for ASIC control, the capacitor can be used more effectively and the unnecessary radiation source mentioned in this patent can be eliminated. effective.

  8: The ASIC effectively suppresses unnecessary radiation with respect to an object mounted on a lead frame having a QFP structure.

  9: In the ASIC, a signal lead-out portion connected to a power source such as a lead frame is made of a material having a large L component at least, thereby effectively suppressing unnecessary radiation.

  In addition, since at least one of the ASIC's IO terminals can be directly connected to a circuit, load, sensor, etc. outside the board where the ASIC is placed without using a buffer, the design of printers such as copiers is possible. There is an effect that it is possible to simplify and reduce the cost, and to construct a stable image forming apparatus with less unnecessary radiation.

(First embodiment)
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the case of a synchronous circuit, all the F / Fs are operated by one clock signal, so the load on the clock signal is considerably large. Signal rounds and falling waveform rounds tend to be large. Therefore, it is necessary to adjust the driving capability while inserting a number of buffers having different driving capabilities into the clock signal. That is, one clock is branched by adjusting the driving capability. This is the clock tree.

  In this embodiment, even in one functional block, the block configuration is separated so that a certain number of FFs enter the block, and the delay from the clock input terminal to the clock input terminal of each block (in the global buffer) ) Is distributed, and the timing is adjusted so that the timing in the block can be obtained for each block.

  At the same time, the delay value is correctly calculated so that the operations between the blocks do not overlap at the same time, and the timing is gradually adjusted so that the transient current peaks between the VDD and GND power supplies do not overlap each other.

  A specific circuit is shown in FIG. 1 and will be described.

  1 to 6 are global buffers (clock buffers having a large drive capability), which are arranged as a drive of a circuit far from the clock input terminal or as a drive buffer for each individual block in the ASIC as shown in FIG. . The 2-3 clock input terminals are connected to the input terminal of one global buffer (or a clock buffer is also acceptable) through the input pad 2-17. The output terminal of one global buffer is the input terminal of 2-6 global buffers. The output terminals of the global buffers 2-6 are connected to the input terminals of the clock buffers 7-19 and 19-2 in the blocks 20-24, respectively. (The output terminal of 2 global buffers is connected to the input terminals of 7 and 8 clock buffers in 20, and the output terminal of 3 global buffers is connected to the 9 and 10 clock buffer input terminals in 21 blocks. The output terminals of 4 global buffers are connected to the input terminals of 11, 12, 13 clock buffers in 22 blocks, and the output terminals of 5 global buffers are connected to 14, 15, 16, 17 in 23 blocks. The output terminals of 6 global buffers are connected to the input terminals of 19 and 19-2 clock buffers in 24 blocks, and the respective buffers are connected to the input terminals of the clock buffers. In consideration of the size of the load, the transition of the clock signal from L to H and H to L of the clock signal from the input terminal CLK 2-3 The dimensions are adjusted so that the imming delay is different for each block.) As for specific delay, the output signals of 2 to 6 global buffers are output at the timing as shown in FIG.

  Reference numerals 20 to 23 are blocks constituting one function by four blocks, which are designed in consideration of the scale of the FF. 20 and 21 are connected by 70 signal lines, and 21 and 22 are 73 and 22 are connected by 74 signal lines, and 20 and 23 are connected by 71 and 72 signal lines.

  In the circuits 20 to 23, a part of the interface DFF is written, but in actuality, each block is composed of up to several thousand DFFs and gate circuits (not shown) or gate circuits not shown. It is designed to guarantee the timing that satisfies the operation of the clock for each block. As interface DFFs, 25 to 30 DFFs are written in 20 blocks, 31 to 33 DFFs in 21 blocks, 34 and 35 DFFs in 22 blocks, and 36 in 23 blocks. Forty-four DFFs are shown as examples for explanation in the case of 24 blocks, 41 and 42 DFFs.

  Between each block, 70 signal lines connect 27 DFF Q output terminals and 32 DFF D input terminals, and 71 signal lines connect 28 DFF Q output terminals and 38 DFF D input terminals. The 72 signal lines connect the 30 DFF Q output terminals and the 37 DFF D input terminals. The 73 signal lines connect the 33 DFF Q output terminals and the 34 DFF D input terminals. 74 signal lines connect 35 DFF Q output terminals and 36 DFF D input terminals.

  In the 20 blocks, the input terminals 2-1 and 2-2 are directly input through the IO pads 2-20 and 2-19, respectively, and are output to the output terminals 2-7 through the 2-11 IO pads. The signal SIG4OUT is directly output to the outside.

  Similarly, signals SIG1OUT and SIG2OUT are output from the blocks 23 to the output terminals 2-7 and 2-8 through the IO pads 2-12 and 2-13, respectively.

  In the block 21, the SIG3IN signal is directly input to the 2-4 input terminals through the 2-16 IO pads.

  In the 24 block, the SIG4IN signal is directly input to the 2-5 input terminal through the 2-15 IO pad, and at the same time, the signal is directly output to the 2-9 output terminal through the 2-14 IO pad. SIG3OUT is output.

  The 24 blocks are independent functional blocks not related to other blocks.

  Each block is composed of about 3000 FFs in this embodiment, but only the minimum FF necessary for explanation is displayed in the figure.

Next, the connection, function, and operation of the clock system will be described. The connection of the clocks in the block will be described taking the example of the 23 blocks as an example. The clock buffers 14, 15, 16, and 17 are buffers having different drive capacities, and are used properly to finely adjust the timing according to the position and role of the FF. (Normally, the buffer is made of a combination of two inverters. Therefore, by changing the combination of the dimension of the previous inverter (drive capacity) and the dimension of the subsequent inverter (drive capacity), the necessary drive capacity and A buffer having a delay time can be created, and if necessary, a plurality of buffers can be combined (see Non-Patent Document 4).
14 clock buffers, 36 FFs are used as clocks for FFs that receive signals from 35 FFs of the other 22 blockchains, and are connected to the 36 clock terminals as an example. It is also connected to the clock terminals of other FFs (not shown) that need to make the timing.

  Similarly, 15 clock buffers, 37 and 38 FFs are used as FF clocks to receive signals from 28 and 30 FFs in the other 20 blocks, and are connected to the clock terminals of 37 and 38 as an example. Of course, it is also connected to other FF clock terminals (not shown) that need to have the same timing.

  Similarly, 16 clock buffers are connected to 39 FF clock terminals, and similarly, 17 clock buffers are connected to 40 FF clock terminals, and can be easily synchronized with external circuits respectively connected to external terminals. Timing has been adjusted.

  The clock buffers in the other blocks are also configured by adjusting the drive capability according to the layout position of each block and the number of FFs to be controlled. Similarly, the timing of FFs in 20 blocks is tuned with 7, 8 clock buffers, the timing of FFs in 21 blocks is tuned with 9, 10 clock buffers, and 22 FFs with 11, 12, 13 clock buffers. The timing of the FFs in the block is tuned, and the timing of the 24 blocks is tuned by the clock buffers 19 and 19-2. As an example of these timing tunings, FIG. 9 shows a timing chart.

  Actually, since the blocks 20, 21, 22, 23, and 24 are divided into small parts, the clock skew timing of the internal FF can be designed to be suppressed to a variation of ± 300 ps.

  Then, 20, 21, 22, 23, and 24 have dimensions of 1, 2, 3, 4, 5, and 6, respectively, so as to have a delay from the clock input terminal of 500 PS CLK as shown in FIG. 9 (a). By tuning the (drive capability), it is possible to design the power supply ON / OFF transient current continuously and the slope of the current rise tr (td) of each block to be small. FIG. 9B shows a graph showing the state of the total current when the block timing is adjusted as described above. Further, FIG. 10 shows a graph of current when all FFs are adjusted at a timing in the range of ± 300 PS skew as in the prior art. For the sake of simplicity, assuming that the number of FFs in the blocks 20, 21, 22, 23, and 24 is the same, if the peak current flowing in each block is P (mA), the peak current in the case of 9-3 Is 5 × P (mA), and when divided into five blocks as compared to the conventional example, the value of di / dt is about 1/5 even in the tuning within the same skew range. However, when divided into a plurality of blocks in this way, an independent functional block such as 24 that does not have an interface with other blocks does not need to consider timing tuning between the blocks, and an AC between the IO and the clock. The clock should be tuned according to the specifications.

  Specifically, the setup hold regulation of the input signal of 2-5 SIG4IN with respect to 2-3 CLK and the output delay regulation with respect to SIG3OUT of 2-9 may be adjusted.

  This block is addressed to a delay condition in consideration of the location of other blocks, and the block itself is 19, 19-2 clocks so that the arrival time of the clock varies within a skew range of ± 300 PS (600 PS range). Adjust the buffer dimensions.

If necessary, it is necessary to add and adjust a clock buffer having different drive capability and delay time in the block. (This is the same for other blocks.)
On the other hand, in the case of a functional block composed of 20 to 23, it is necessary to adjust the timing of the data interface between the blocks other than the timing of the IO with the outside of the ASIC.

  In such a part, 28 and 38 FFs, 30-37 FFs, 27-32 FFs, 33, 34 FFs, so that timing adjustment is easy (setup hold guarantee for the clock). It is possible to easily adjust the timing by not receiving a gate circuit between the FFs 35-36 and receiving the data directly by the FFs.

  For example, the 23 blocks themselves satisfy the AC specifications between the blocks 20 and 22, and at the same time, the AC specifications such as the output delay (relative to CLK) with respect to the output terminals 2-7 and 2-8. On the other hand, the delay values and drive capacity values of the clock buffers 14 to 17 are optimally calculated and arranged so that the skew is within ± 300 Ps in the block.

  That is, the delay may be tuned in the same way for other blocks.

  In consideration of the timing between the blocks 21 and 23, the 20 blocks should comply with the AC specification of the input terminal 2-1, that is, the setup and hold for the individual locks input to the CLK of the input signal of the input terminal. In addition, the delay value of the 7-8 clock buffer and the drive capability so that the AC specifications such as the output delay (relative to CLK) with respect to the output terminal 2-6 are kept within ± 300 Ps skew within the block. Determine the value by optimal calculation and place it.

  Similarly, the 21 blocks are the same.

  That is, the AC specification between the blocks 20 and 22 is satisfied, and the AC specification of the input terminal 2-4, that is, the setup and hold with respect to the clock input to the CLK of the input signal of the input terminal are maintained. In addition, while satisfying the AC specifications such as the output delay (with respect to CLK) for the output terminals 2-6, the delay values of the clock buffers 7-8 and the drive so as to be within ± 300 Ps skew within the block. The ability value is optimally calculated and determined.

  Similarly, the 22 blocks are the same.

  That is, the delay values and drive capacity values of the clock buffers 11 to 13 are optimally calculated and determined so as to be within ± 300 Ps skew within the block while satisfying the AC specifications between the blocks 21 and 23. Deploy.

  Of course, these calculations use the layout image of the block diagram of the layout of FIG. 2, and the timing when layout is performed in consideration of the line distance, wiring capacity, wiring impedance, buffer driving capability, load size, etc. is met. It is tuned as follows.

  With this configuration, assuming that there is virtually no delay time of the current on the power supply wiring and that an ideal voltage source is applied, if the current flowing through the circuit is the conventional method, the circuit shown in FIG. On the other hand, in this case, the current peak can be reduced and the rising di / dt can be reduced as shown in FIG.

  Even in this case, depending on the layout of the power source, the condition of td <L√εr / Co occurs when the apparent wiring length L increases (L: wiring length, Co: speed of light, εr: relative dielectric constant, td. : Voltage rise time) It may be necessary to handle the circuit in a distributed manner.

  If this condition is exceeded, noise will be generated discontinuously and suddenly, and in order to mitigate this, it is necessary to reduce the effective length of L.

  That is, although it is necessary to reduce di / dt, it is not a dominant physical quantity of essential noise, and tr is important. That is, it is important to reduce tr.

  For this purpose, global power supply wiring is arranged as shown in FIG.

  Details will be described.

  2, power supply input terminals, power supply PAD, global power supply wiring, and contacts for supplying power to each block are additionally described in 3-1 to 3-100. It is shown.

  Reference numerals 3-1 and 3-5 denote VDD power supply input terminals on the opposing surface in the vertical direction of the IC chip, which are connected to the internal power supply pads 3-3 and 3-7, respectively. And 3-7 are connected to each other by a global power supply line 3-19, and through the VDD signal line of MOS FET (not shown) and 3-9, 3-10 that constitute the FF and clock buffer of 20 blocks. A contact is made, and a contact is made through a VDD signal line of 3-21, 3-12, and 3-13 of FFs and clock buffers (not shown) of 21 blocks and 3-11, 3-12, and 3-13, respectively. The power is supplied.

  Reference numerals 3-2 and 3-6 denote GND power supply input terminals on the opposite side of the IC chip in the vertical direction, which are connected to the internal power supply pads 3-4 and 3-8, respectively. And 3-8 are connected to each other by a global power supply line 3-20, and through the GND signal line of MOS FET (not shown) and 3-14, 3-15 constituting the FF and clock buffer of that line and 20 blocks. A contact is made, and a contact is made through a VDD signal line of 3-13, 3-17, and 3-18 of a MOS FET constituting a FF and a clock buffer (not shown) of 21 blocks, respectively. The power is supplied.

  Similarly, 3-21 and 3-25 are VDD power supply input terminals on the opposite sides of the IC chip in the vertical direction, and are connected to the internal power supply pads 3-23 and 3-27, respectively. 3-23 and 3-27 are connected to each other by a global power supply line 3-39 and the VDD signal line of a MOS FET (not shown) that constitutes the FF and clock buffer of the block of the line and 3-29,3 Contact is made through -30, 3-31, and contact is made through VDD signal lines of MOS FETs constituting FFs and clock buffers not shown in 22 blocks and 3-32, 3-33. , Each is configured to be supplied with + power.

  Reference numerals 3-22 and 3-26 denote GND power supply input terminals on the opposite sides of the IC chip in the vertical direction, which are connected to internal power supply pads 3-24 and 3-28, respectively. And 3-28 are connected to each other by a global power supply line 3-40, and the GND signal lines of MOS FETs (not shown) constituting the FFs and clock buffers of the blocks and the blocks 3-34, 3-35, A contact is made through 3-36, and a contact is made through a VDD signal line of MOS FETs constituting FFs and clock buffers (not shown) of 23 blocks, and 3-37 and 3-38, respectively. The power is supplied.

  Reference numerals 3-41 and 3-45 denote VDD power supply input terminals on the opposing surfaces in the vertical direction of the IC chip, which are connected to the internal power supply pads 3-43 and 3-47, respectively. And 3-47 are connected to each other by a global power supply line 3-59, and the VDD signal line of MOS FET (not shown) and 3-49, 3-50, A contact is made through 3-51, and a contact is made through the VDD signal line of MOS FET constituting the FF and clock buffer (not shown) of 24 blocks and 3-52, 3-53, respectively. The power is supplied.

  Reference numerals 3-42 and 3-46 denote GND power supply input terminals on the opposite sides of the IC chip in the vertical direction, which are connected to 3-44 and 3-48 internal power supply PADs, respectively. And 3-48 are connected to each other by a global power supply line 3-60 and the GND signal lines of MOS FETs (not shown) and 3-54, 3-55, which constitute the FFs and clock buffers of the block and 23 blocks. The contact is made through 3-56, the FF of the 24 blocks (not shown) and the VDD signal line of the MOS FET constituting the clock buffer, and the contacts are taken through 3-57 and 3-58, respectively. The power is supplied.

  Reference numerals 3-61 and 3-65 denote VDD power supply input terminals on the opposite sides of the IC chip, which are connected to the internal power supply pads 3-63 and 3-67, respectively. And 3-67 are connected to each other by a global power supply line 3-79, and through the VDD signal line of MOS FET (not shown) and 3-69, 3-70 constituting the FF and clock buffer of 20 blocks. The contact is made and the contact is made through the VDD signal line 3-72 and 3-73 of the FF and clock buffer which are not shown in the block of 23 and the clock buffer, and + power is supplied to each. It is configured to be.

  Reference numerals 3-62 and 3-66 denote GND power supply input terminals on the opposite sides of the IC chip, which are connected to 3-64 and 3-68 internal power supply PADs, respectively. And 3-68 are connected to each other by a global power supply line 3-80, and through the GND signal line 3-74, 3-75 (not shown) constituting the FF and clock buffer of the line and 20 blocks. The contact is made, and the contact is made through the VDD signal line of the MOS FET constituting the FF and the clock buffer (not shown) in the block of 23, and 3-77 and 3-78, respectively, and the-power is supplied. It is configured to be.

  Reference numerals 3-81 and 3-85 denote VDD power supply input terminals on the opposite sides of the IC chip, which are connected to the internal power supply pads 3-83 and 3-87, respectively. And 3-87 are connected to each other through a global power supply line 3-99 and contacted through a VDD signal line (not shown) and 3-89 which constitute the FF and clock buffer of 21 blocks and 3-89. The 22 blocks are in contact with the FFs (not shown) of the MOSFET and the VDD signal lines of the MOS FETs constituting the clock buffer through 3-90, and the FFs and clock buffers (not shown) of the 24 blocks are configured. A contact is made through the VDD signal line 3-91 of the MOS FET to be operated, and + power is supplied to each.

  Reference numerals 3-82 and 3-86 denote GND power supply input terminals on the opposite side of the IC chip, which are connected to the internal power supply pads 3-84 and 3-88, respectively. And 3-88 are connected to each other by a global power supply line 3-100, and the line is contacted via a GND signal line (not shown) and 3-94 of the FF and clock buffer of block 21 and 3-94. The FFs and clock buffers not shown in the 22 blocks are connected to the VDD signal lines of the MOS FETs constituting the clock buffers through 3-95, and the FFs and clock buffers not shown in the 24 blocks are connected. The contact is made with the VDD signal line of the MOS FET to be configured through 3-96, and each is configured to be supplied with a-power. . 3-1, 3-2, 3-5, 3-6, 3-21, 3-22, 3-25, 3-26, 3-41, 3-42, 3-45, 3-46, 3 Reference numerals −61, 3-62, 3-65, 3-66, 3-81, 3-82, 3-85, and 3-86 denote input terminals connected to the power supply through a lead frame or the like.

  Next, the operation will be described.

  FIG. 4 shows a simplified equivalent circuit.

  Reference numerals 4-1 and 4-2 denote external power sources added to the outside of the package. The negative side of 4-1 is connected to 3-X2, and the positive side is connected to 3-X1.

  Similarly, the-side of 4-2 is connected to 3-X6, and the + side is connected to 3-X5. In this case, X is a positive even number up to MAX8 including 0.

  The terminal of 3-XX is a power input terminal as shown in FIG. 3, which is a lead frame if it is a normal QFP package, and the impedance of the lead frame is now 4-14, 4-15, The equivalent inductance value L of 4-18, 4-1 and the equivalent resistance value Rin of 4-16, 4-17, 4-20, 4-21 are shown. 14 and 4-16 are inserted in series, 4-15 and 4-17 are inserted in series with respect to 3-X2, and 4-18 and 4-20 are inserted in series with respect to 3-X5. 4-19 and 4-21 are inserted in series with respect to 3-X6.

  Between 4-16 and 4-20, the global power supply wiring of 3- (X + 1) 9 is connected (when X = 0, it means the global line of 3-19) between 4-17 and 4-21 Is connected to a global power supply wiring of 3- (X + 2) 0. When X = 0, it means 3-20 global line) 3- (X + 1) 9 global power supply wiring and 3- (X + 2) 0 global power supply wiring between FFs and clock buffers that make up the ASIC Although the power supply terminal is connected, an equivalent circuit necessary for considering a transient current is a plurality of CMOS inverters composed of MOSFETs of 4-3, 4-4 and 4-5, 4-6. What is necessary is just to consider the input capacity of the circuit and its driving gate, 4-7, 4-8, 4-9, 4-10 and the like.

  More specifically, a 4- (X + 1) 9 global power supply wiring and a 3- (X + 2) 0 global power supply wiring are composed of 4-3 PCH MOSFETs and 4-4 NCH MOSFETs. If there are N FFs in 20 buffers, they are equivalently replaced and arranged as N equivalent buffers including clock buffers, and 4-7 and 4-8 connected in series are driven at the same time. It can be considered that approximately N equivalent gate capacitors are connected.

  Similarly, between the global power supply wiring of 3- (X + 1) 9 and the global power supply wiring of 3- (X + 2) 0, there are 23 buffers composed of 4-5 PCH MOSFETs and 4-6 NCH MOSFETs. If there are M FFs, it is equivalently replaced and arranged as about M equivalent buffers, and at the same time, the equivalent gate capacities of 4-7 and 4-8 connected in series are M. You can think that they are connected.

  The gates of the MOS FETs 4-3 and 4-4 are connected to the output terminal of the clock buffer 4-11, and the input terminal thereof is connected to the clock input terminal CLK 4-13.

  Similarly, the gates of the MOSFETs 4-5 and 4-6 are connected to the output terminal of the clock buffer 4-12, and the input terminal thereof is connected to the clock input terminal CLK 4-13.

  For simplicity, it is assumed that N = M and VIN1 = VIN2.

  If the delay values of the clock buffer 4-11 and the clock buffer 4-12 are the same, the DFF arranged between the 3- (X + 1) 9 global power supply wiring and the 3- (X + 2) 0 global power supply wiring All switch simultaneously. In that case, current equal to the current flowing when the inverter composed of 44-3 and 4-4 is inverted × the number of DFFs (N + M) flows instantaneously.

In that case, the current 4-15 flowing from VIN1 and the current 4-16 flowing from 4-2 flow in opposite directions, and on the global power supply wiring of 3- (X + 1) 9 and the global power supply wiring of 3- (X + 2) 0 Thus, even if the wiring is made at the point 4-14 where the current is 0, the circuit is the same. (Also, the current in the reverse direction flows, which also has the effect of suppressing common mode noise)
In other words, by effectively connecting the power supply to the power supply terminals on the opposite surface in this way, the effective wiring length through which a large current flows can be reduced to half of the total length of the global wiring. Of course, since the delay values of the clock buffers 4-11 and 4-12 are different and the balance between the values of N and M is lost, the execution length becomes L> effective length> L / 2.
td <L√εr / Co
The effect of reducing L of the noise can be expected, and the value of td of the threshold at which noise is generated can be reduced. If the same td is used, a margin for noise can be obtained. In addition, the number of equivalent loads connected to the wiring is (N + M) / 2 when the balance becomes the smallest and the effect of suppressing the rising slope of the current also occurs.

  Next, the delay values of 4-11 (actually combining the characteristics of 1 and 2) and 4-12 (combining the characteristics of 1 and 5) are different, and the signal shown in the time chart of FIG. Consider the case of entering blocks 20 and 23.

  In this case, first, the DFFs in the 20 blocks symbolized by the MOSFETs 4-3 and 4-4 are turned on at 500 PS after the clock rises.

  These FFs have through currents of N sets of MOS FETs whose transient currents are symbolized as 4-3 and 4-4 according to the skew distribution of these 20 blocks, or capacities of 4-7 and 4-8. It flows as charging (discharging) current.

  If there is no delay difference between 4-11 and 4-12, most of the current flows only from the power sources of 4-1 and 4-2, but if there is a delay difference as in this embodiment, 20 At the same time when the FFs of the blocks are simultaneously turned ON, the charges stored in either 4-9 or 4-10 of the 23 blocks (depending on the FET conditions of 4-7 and 4-6) Since it flows as a discharge current, a very steep transient current does not flow as currents 4-15 and 4-16. At the same time, this eliminates the need for a steep counselor and current to flow through the lead frame, thereby reducing the lead frame wiring length and reducing the current rise time tr as a whole. .

  Similarly, when there is no transient current flowing in the 20 blocks at the next timing, and ff of the 23 blocks are switched simultaneously, the through currents of M sets of 4-6, 4-7, or M pieces In the case of charging 4-9 or 4-10, the rise of tr is alleviated due to the influence of the capacity of 4-7 and 4-8 (of course, N sets) of 20 blocks.

  It should be noted that such a power supply wiring can theoretically supply power if there is a single pair, but in practice, a plurality of power supplies are assigned as shown in FIG. By arranging a plurality of pair lines parallel and perpendicular to each other, the transient current can be further dispersed.

  These power supplies can be connected separately in a hierarchy, and are included in this embodiment even when arranged in the same hierarchy.

Second embodiment
A 256-pin ASIC with a QFP structure will be described. Figures related to FIGS. 15 and 16 are shown. FIG. 15 is a sketch of a QFP outline drawing.

The outer periphery of such a package is about 25 mm × 25 mm, and the chip size of the chip placed inside is usually about 5 mm ² or more.

  The wiring length drawn from VDD having such a structure to the input PAD, internal logic, and output PAD of 4-1, 4-2 and 4-3 in FIG. 16 is about 5 mm to 15 mm. However, at least the wiring on the ASIC is 5 mm or more.

  At the same time, it is considered that the wiring lengths routed from the VSS to the input PAD of 4-1, 4-2, 4-3, the internal logic, and the output PAD are equivalent.

  Under such conditions, if the adjustment of the clock skew of the ASIC is limited to about ± 300 PS, there is a possibility that the rise may be partially about 150 PS or less to about 250 PS, and the level of that level is in fact. It has been confirmed that unnecessary radiation occurs due to skew.

In the layout condition, as introduced in design wave magazine November 2002 P143,
td = L√εr / Co
(L: wiring length, Co: speed of light, εr: relative dielectric constant, td: voltage rise time)
It is known that when the rise td becomes stricter than the above condition, it is necessary to treat the circuit in a distributed constant manner.

  This means that if such a steep rise of the signal occurs, the circuit constant will change and it will become an area that needs to be handled by the distributed constant, which naturally increases unnecessary radiation from the circuit. I know.

For example, at the rise of tr = 0.2 ns, on the SiO ₂ of ASIC with εr = 3.9, it can be seen that if L is 6 mm or more, it falls within the region that must be handled by the distribution constant. In the skew range, it is inferred and actually occurs that unnecessary radiation may easily occur in an ordinary ASIC having a chip size of about 10 mm ² .

  In this case, the signal of the unnecessary radiation is applied to the VDD and VSS lines, which causes the power supply of the output PAD 4-3 to be swung, and as a result, the output signal output by the output PAD 4-3 is generated by the clock. Unnecessary radiation signals at the time of the transition are superimposed or output directly as radiation to the space.

  For this reason, the timing of such internal logic 4-2 is managed at the time of layout as in the first embodiment, and the skew is sufficiently widened so that (td> L√εr / Co is satisfied. It is possible to extinguish unwanted radiation sources (depending on conditions). Such unwanted radiation often occurs in normal ASIC (0.35u rule level), and there is a possibility that such radiation may occur due to the sum of the transient current due to normal gate charge / discharge and the through current. Even in such a case, this measure is very effective. In terms of frequency, it is particularly effective for an ASIC that operates in the range of 10 MHz to 500 MHz. When the frequency is higher than this, there is no room for sufficient skew, and it is necessary to take measures against unnecessary radiation other than this method. This is effective when using modern tools that are tuned to tightly skew even at frequencies below 10 MHz. In this case, the current tr (tr = td) in each individual block can be set to 500 nsec or more for the rise time tr for each individual current rise generated by all the divided blocks. No unnecessary radiation will occur.

  As a result of the countermeasures in the first embodiment, it is considered that the actual power supply wiring length on the chip is almost halved in the actual ASIC, and the ASIC up to 10 mm square is usually about 10 mm for practical use. Even with QFP routed by the lead frame wiring, unnecessary radiation due to the above causes can be suppressed.

At the same time, when the length of the lead frame is long, it is possible to reduce the rise tr of the current by using only the material of the lead frame used for the power supply or using a material having a large inductance such as Fe for the entire lead frame, The effect of suppressing unnecessary radiation is increased. [See Fig. 14 for lead frame characteristics]
Specifically, it is also effective to use an Fe lead frame instead of the Cu lead frame or to add Fe plating to the Cu lead frame only for the power supply terminals.

  This is because when Fe is cooked, the inductance of Fe increases 3 to 4 times, and the rise of current becomes gentle due to the effect of Ldi / dt with this inductance by the photoreceptor surface and current, and tr increases. is there.

  Next, a third embodiment will be described.

  FIG. 11 shows a third embodiment.

  11-1 to 11-5 are MOS capacitors formed by PCH MOS FETs, 11-6 to 11-10 are MOS capacitors formed by NCH MOS FETs, 11-1, 11-6, 11-2, 11-7, 11-3 and 11-8, 11-4 and 11-9, 11-5 and 11-10 are paired, and VDD supplied to the blocks 20, 21, 22, 23 and 24, respectively. Connected between GND.

  These pairs use MOSFETs for forming gates in the regions 2-34, 2-33, 2-32, 2-31, and 2-30 in FIG. 2 as capacitances.

  The individual MOSFETs have a structure in which PCH MOS has a gate and source connected to VDD and a drain connected to VSS, and NCHMOS has a structure in which a gate and source are connected to VSS and a drain connected to VDD. It has become.

  With this configuration, it is possible to add capacity to the power supply separately for each block, limit the peak of the transient current flowing through each block, and delay the rise of the current. In addition, these MOSFETs have a sea-of-gate structure uniformly in the wiring region using the MOS in the wiring region even outside the regions 2-34, 2-33, 2-32, 2-31, and 2-30. A MOS capacitor can be added to the.

  11 has a clock structure different from that of FIG. 1, and the clocks entering the 24 blocks are independent clocks different from the 2-3 CLKs, and the connection of the 6 inputs is different. ing.

  6 is connected to the output terminal of the OR circuit 11-1, one input terminal 11-2 of 11-1 is connected to the external HWRX signal, and the other input terminal 11-3 is connected to the external Connected to CSX signal.

  Next, the operation will be described.

  The CPU sets values in advance to the terminals 22-5 immediately before the operation of the ASIC in the HWRX and CSX with respect to the ASIC in FIG. 11, and adds the signals in FIG. A value is written in 42 register.

  During the operation of the entire circuit of FIG. 11, the 24 clocks are not normally rewritten.

  In some cases, the signal is periodically rewritten. In this case, the signal in FIG. 12 is generated at a period more than twice as long as the clock of CLK (8 times to 16 times more), and the CPU rewrites the data. It is also possible.

  Such a block and the blocks 21, 22 and 23 to which the power supply is connected are the same as in the first embodiment, even if the skew timing of the clock to which 24 is accessed is the same. Even when 23 clocks are input, the clock is not generated at almost all timings. Therefore, as in the first embodiment, the capacity of 44, 9 and 44 in the 24 blocks is equivalent to that of the blocks 21, 22, and 23. Charges are replenished when the current rises, and an effect is obtained that the value of tr of the current flowing through the lead frame can be suppressed. In particular, it is more effective when the clock relationship between a plurality of clocks is completely asynchronous.

  Next, a fourth embodiment will be described.

  FIG. 13 is a block diagram of the copying machine of the fifth embodiment.

  The copying machine 13-1 is usually composed of a scanner and a printer. A motor provided in the scanner and the printer is used so that information to be copied on the pressure plate is copied onto a transfer medium by an external human key operation. While transporting a medium such as paper, the position information is detected by a sensor that detects the position of the medium, and the position of the medium is accurately grasped to operate so that the information is copied. Since it is publicly known, it is omitted.

  In such a copying machine, for example, the ASIC for motor control of the ASIC 13-4 uses the technology for countermeasures against unnecessary radiation made by the configuration of this patent, and is mounted on the substrate of 13-3, and is used for the motor driver. It is stored in a place where a mounting area separated from 13-1 can be secured by a separate board from the mounted 13-2.

  A motor driver is provided on the board 13-2, and the board is placed near, for example, a paper discharge unit on which the motor is mounted. The phase signal input terminal of the driver is connected to the clock output terminal of the 13-4 ASIC through the buffer of 13-10 through the signal line of 16-6. Reference numeral 13-7 denotes a signal line for passing a driver control signal (level signal).

  Specifically, 13-6 is connected to the input terminal of the buffer 13-10 on the second substrate 13-2, and its output terminal is the motor driver 13-9 (the connection of the power supply is shown in the figure. The control output terminal 13-4 is connected to the input terminal of the buffer 13-5, and the output terminal 13-1 is not shown. It is connected to the control signal input terminal of the monitor display circuit of the operation unit of the main body. At the same time, a structure in which the print operation start signal of the operation unit 13-1 is connected to 13-4 via 13-8 will be described as an example.

  Next, the operation will be described.

  The print operation start signal information of the operation unit of the main body 13-1 is detected by the 13-4 ASIC configured on the first board through the signal line 13-8, and control information corresponding to the detected signal is displayed. -6, 13-7 to send to 13-9 motor driver.

  At the same time, 13-4 operates to return to the control circuit of the main body (not shown) that the motor start signal has been sent through the buffer 13-5.

  Such a configuration can be configured without any problem as long as it is a dual power supply type ASIC having an IO section and an internal power supply separation structure. In this case, if there is no contrivance as in the first, second, and third embodiments, radiation noise will increase and noise countermeasures will be difficult. Usually, when signals are exchanged across boards, they will be on the same board. A buffer such as 13-5 and a signal conversion circuit such as a transistor are provided to cut off noise components, thereby taking measures against noise.

  On the other hand, this noise generation source is extinguished by distributing blocks with different clock skews between the same power supply lines as in this claim, or by adding a capacitance with a MOS FET or the like constituting the gate inside the ASIC. Thus, as in 13-6 and 13-7, without using a signal conversion circuit such as a buffer or a transistor on the same substrate, wiring connection across the substrate is possible without causing unnecessary radiation. As described above, even in an ASIC in which the IO and the internal power supply are configured separately, noise is applied to the power supply unit in the internal circuit, and the threshold voltage of the internal gate fluctuates, thereby generating a clock generated by the ASIC. When subtle jitter appears in the output clock of the circuit clock, for example, if it is a CCD drive circuit or the like, there is a problem that noise is added to the image due to jitter on the clock.

  Even in such a case, it is very effective to disperse blocks having different clock skews between the same power supply wirings or to disperse capacitance between power supplies of internal blocks.

Diagram for explaining the first embodiment Layout image of the first embodiment The figure which shows the power supply wiring structure of 1st Example Equivalent circuit of the first embodiment The figure explaining the effect of an Example Detailed illustration of DFF Detailed explanation diagram of inverter Diagram explaining the current that flows as a through current of DFF Diagram showing the current that flows for each block and the total current Time chart explaining timing deviation between blocks The figure which shows a 3rd Example Diagram showing the second clock The figure which shows a 4th Example Diagram showing equivalent circuit and physical constant of lead frame Outline drawing of QFP outline drawing Diagram showing power supply configuration and interface of ASIC

Explanation of symbols

1-6 Global buffer 25-42 DFF
7-19 Clock buffer 2-11 to 2-21 IO pad
VDD, VDDINα + power supply (pin)
VSS, VSSINα-Power supply (pin)
14-1 Equivalent circuit of lead frame 6-1, 6-2 Inverter 7-1, 7-2 MOSFET
11-1 OR gate circuit

Claims (10)

It has at least two or more logic blocks connected to the same clock terminal and having different clock skew distributions from the terminal,
An ASIC characterized in that at least two or more of the plurality of blocks are arranged across the same power supply line, and power is supplied to the power supply terminals of the FF elements included in each block by wiring means. The gnd and vdd power supply terminals to which the GND and VDD external power supplies are connected are arranged in pairs on the opposite side of the package or the equivalent position, respectively.
A patent that is connected to the gndpad that supplies the gnd potential to asic and the vddpad that supplies the potential of VDD, respectively, and power is supplied to the inside of the ASIC chip from opposite ends of the ASIC chip. The ASIC according to claim 1. In an ASIC that is connected to the same clock terminal and has multiple logic blocks with different clock skews from that terminal,
An ASIC characterized in that all rise times tr of current peaks caused by simultaneous switching of ff of individual logic blocks are about 500 nsec or more. There are at least two logic blocks connected to the same basic clock terminal and having different clock skews from the terminal,
It has at least one block having a clock of a different system from the clock, and the timing of turning on the clocks is different from each other,
An ASIC characterized in that a plurality of blocks are arranged across at least the same power line.   5. The ASIC according to claim 4, wherein the frequency of the clock of the other system is ½ or less of the basic clock frequency or an intermittent clock.   6. The ASIC according to claim 1, wherein electrostatic capacity is dispersedly inserted between at least the power source, VDD, and GND for the separated block.   7. The ASIC according to claim 6, wherein a MOS capacitor that constitutes an empty gate that is not used for controlling the ASIC is used as the capacitor.   The ASIC according to any one of claims 1 to 7, wherein the ASIC is mounted on a lead frame having a QFP structure.   9. The ASIC according to claim 1, wherein a signal extraction portion connected to a power source is made of a material having an L component larger than at least an L component of Cu.   In the image forming apparatus using the ASIC according to any one of claims 1 to 9, at least one output terminal of the IO terminal of the ASIC is mounted directly or directly without mounting the ASIC. An image forming apparatus having a structure connected through a second substrate different from the object.

Images