JP2008091530A - Semiconductor device - Google Patents

Semiconductor device Download PDF

Info

Publication number
JP2008091530A
JP2008091530A JP2006269210A JP2006269210A JP2008091530A JP 2008091530 A JP2008091530 A JP 2008091530A JP 2006269210 A JP2006269210 A JP 2006269210A JP 2006269210 A JP2006269210 A JP 2006269210A JP 2008091530 A JP2008091530 A JP 2008091530A
Authority
JP
Japan
Prior art keywords
mounting substrate
semiconductor chip
semiconductor device
sealing resin
metal member
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2006269210A
Other languages
Japanese (ja)
Inventor
Yasushi Shiraishi
靖 白石
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Oki Electric Industry Co Ltd
Original Assignee
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Electric Industry Co Ltd filed Critical Oki Electric Industry Co Ltd
Priority to JP2006269210A priority Critical patent/JP2008091530A/en
Publication of JP2008091530A publication Critical patent/JP2008091530A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15172—Fan-out arrangement of the internal vias
    • H01L2924/15173—Fan-out arrangement of the internal vias in a single layer of the multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Abstract

<P>PROBLEM TO BE SOLVED: To efficiently perform radiation so as to reduce heat resistance in a semiconductor device by arranging a highly heat-conductive metallic member in contact with a mounting substrate, a semiconductor chip, and a sealing resin. <P>SOLUTION: The semiconductor chip 20 with a bump 21 arranged on one surface as an external terminal and a plurality of chip components 30 are electrically connected to a wiring circuit 11, and then, mounted on the mounting substrate 10, where the wiring circuit 11 is arranged on one main surface and the external terminal 12 to be electrically connected to the wiring circuit 11 is arranged on the other main surface, concerning the semiconductor device. A box shape metallic member 40 with one open surface is arranged on the mounting substrate 10, so as to cover the wiring circuit 11, the semiconductor chip 20, and the chip components 30 formed or mounted on the mounting substrate 10. A gap between the mounting substrate 10 and the metallic member 40 is sealed with a sealing resin 50. The box shape metallic member 40 is brought into contact with the mounting substrate 10 at the end part and contact with the semiconductor chip 20 and the sealing resin 50 on the inner surface. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は、半導体チップを基板上に実装してパッケージ化した半導体装置に関する。   The present invention relates to a semiconductor device in which a semiconductor chip is mounted on a substrate and packaged.

近年、携帯電話等に代表される小型電子機器の急速な普及により、半導体装置も薄型、小型、軽量のものが要求されるようになってきている。そこで、これらの要求に対応するために数多くの半導体装置のパッケージ構造が提案されている（例えば、特許文献１）。   In recent years, with the rapid spread of small electronic devices typified by mobile phones and the like, semiconductor devices are also required to be thin, small and light. Therefore, many package structures for semiconductor devices have been proposed to meet these requirements (for example, Patent Document 1).

そのパッケージ構造の一つとして、例えば、表面に配線回路が形成され裏面に外部端子が形成されたシリコン基板上に、片面に電極を配置した半導体チップと、その他電子部品とを実装して構成されたシリコンモジュールと呼ばれるパッケージ構造がある。   As one of the package structures, for example, a semiconductor chip in which electrodes are arranged on one side and other electronic components are mounted on a silicon substrate having a wiring circuit formed on the front surface and external terminals formed on the back surface. There is a package structure called a silicon module.

特開２００６−０１９６３６JP 2006-019636 A

しかしながら、近年の半導体チップの高集積化や高速化、またパッケージの高密度実装に伴い、単位面積当たりの熱密度が上昇し、パッケージ化された半導体装置の熱抵抗というものが無視できなくなるほど大きくなってしまうといった問題が生じている。   However, with the recent high integration and high speed of semiconductor chips and high-density packaging of packages, the heat density per unit area increases, and the thermal resistance of packaged semiconductor devices cannot be ignored. There is a problem of becoming.

そこで、本発明の課題は、上記問題に鑑み、熱抵抗を低減した半導体装置を提供することである。   In view of the above problems, an object of the present invention is to provide a semiconductor device with reduced thermal resistance.

上記課題は、以下の手段により解決される。即ち、
本発明の半導体装置は、
配線回路が形成された実装基板と、
前記配線に接続されるように前記実装基板に搭載される半導体チップと、
前記半導体チップ及び前記実装基板に接触して配設された金属部材と、
前記実装基板と前記金属基板との間隙を封止する封止樹脂と、
を備えたことを特徴としている。 The above problem is solved by the following means. That is,
The semiconductor device of the present invention is
A mounting board on which a wiring circuit is formed;
A semiconductor chip mounted on the mounting substrate to be connected to the wiring;
A metal member disposed in contact with the semiconductor chip and the mounting substrate;
A sealing resin for sealing a gap between the mounting substrate and the metal substrate;
It is characterized by having.

また、本発明の半導体装置において、前記封止樹脂の熱膨張係数は、前記実装基板の熱膨張係数と前記金属部材の熱膨張係数との間の範囲であることがよい。   In the semiconductor device of the present invention, the thermal expansion coefficient of the sealing resin is preferably in a range between the thermal expansion coefficient of the mounting substrate and the thermal expansion coefficient of the metal member.

本発明の半導体装置において、前記実装基板は、シリコン基板であることがよい。   In the semiconductor device of the present invention, the mounting substrate is preferably a silicon substrate.

本発明の半導体装置において、前記金属部材の熱伝導率は、前記実装基板、前記半導体チップ、及び前記封止樹脂の熱伝導率よりも高いことがよい。   In the semiconductor device of the present invention, the metal member preferably has a thermal conductivity higher than that of the mounting substrate, the semiconductor chip, and the sealing resin.

本発明によれば、熱抵抗を低減した半導体装置を提供することができる。   According to the present invention, a semiconductor device with reduced thermal resistance can be provided.

以下、本発明の実施形態について図面を参照して説明する。なお、実質的に同様の機能を有するものには、全図面を通して同じ符号を付して説明し、場合によってはその説明を省略することがある。   Embodiments of the present invention will be described below with reference to the drawings. In addition, what has the substantially same function is attached | subjected and demonstrated through the whole drawing, and the description may be abbreviate | omitted depending on the case.

図１は、実施形態に係る半導体装置を示す概略平面図である。図２は、実施形態に係る半導体装置を示す概略断面図である。なお、図１では、金属部材４０に覆われる配線回路１１、半導体チップ２０、チップ部品３０は実線で示している。   FIG. 1 is a schematic plan view showing the semiconductor device according to the embodiment. FIG. 2 is a schematic cross-sectional view illustrating the semiconductor device according to the embodiment. In FIG. 1, the wiring circuit 11, the semiconductor chip 20, and the chip component 30 covered with the metal member 40 are indicated by solid lines.

実施形態に係る半導体装置１００は、図１及び図２に示すように、一方の主面に配線回路１１と他方の主面に配線回路１１と電気的に接続される外部端子１２を有する実装基板１０を備えている。外部端子１２は、パッド１３及びパッド１３上に設けられたバンプ１４で構成されている。   1 and 2, the semiconductor device 100 according to the embodiment includes a wiring circuit 11 on one main surface and an external terminal 12 electrically connected to the wiring circuit 11 on the other main surface. 10 is provided. The external terminal 12 includes a pad 13 and a bump 14 provided on the pad 13.

また、実装基板１０上には、例えば片面に外部端子としてバンプ２１が設けられた半導体チップ２０（半導体チップ）と、複数（本実施形態では２つ）のチップ部品３０（電子部品）とが配線回路１１と電気的に接続されて実装されている。   In addition, on the mounting substrate 10, for example, a semiconductor chip 20 (semiconductor chip) provided with bumps 21 as external terminals on one side and a plurality (two in this embodiment) of chip components 30 (electronic components) are wired. The circuit 11 is mounted while being electrically connected.

そして、実装基板１０上に形成或いは実装された配線回路１１、半導体チップ２０、及びチップ部品３０を覆うように、例えば一面が開口した箱状の金属部材４０が実装基板１０上に配設され、実装基板１０と金属部材４０との間隙を封止樹脂５０により封止されている。   Then, for example, a box-shaped metal member 40 opened on one surface is disposed on the mounting substrate 10 so as to cover the wiring circuit 11, the semiconductor chip 20, and the chip component 30 formed or mounted on the mounting substrate 10. A gap between the mounting substrate 10 and the metal member 40 is sealed with a sealing resin 50.

この箱状の金属部材４０は、その端部が実装基板１０と接触し、その内面で半導体チップ２０及び封止樹脂５０と接触して配設されている。   The end of the box-shaped metal member 40 is in contact with the mounting substrate 10, and the inner surface of the box-shaped metal member 40 is in contact with the semiconductor chip 20 and the sealing resin 50.

このようにして、本実施形態に係る半導体装置１００は、パッケージングされており、マザーボード等の他の実装基板６０上に実装される。   Thus, the semiconductor device 100 according to the present embodiment is packaged and mounted on another mounting substrate 60 such as a mother board.

実装基板１０としては、基板に対し、めっき法、スパッタ法、リソグラフィー法、エッチング等を利用して配線回路１１を形成し、これと電気的に接続するように外部端子１２が設けて構成することができる。   As the mounting substrate 10, a wiring circuit 11 is formed on the substrate using a plating method, a sputtering method, a lithography method, etching, or the like, and an external terminal 12 is provided so as to be electrically connected thereto. Can do.

実装基板１０としては、例えば、シリコン基板、アルミ基板等に代表される金属基板、ガラス基板やガラスエポキシ基板に代表される有機樹脂基板（フレキシブルプリント基板も含む）等であってもよい。本実施形態では、実装基板としてシリコン基板を適用している。   The mounting substrate 10 may be, for example, a metal substrate typified by a silicon substrate or an aluminum substrate, an organic resin substrate (including a flexible printed circuit board) typified by a glass substrate or a glass epoxy substrate, and the like. In this embodiment, a silicon substrate is applied as the mounting substrate.

半導体チップ２０は、片面に外部端子としてバンプ２１が設けられ、外部と電気的に接続しつつ実装可能に構成されている。しかし、これに限られず、例えば、ＷＣＳＰやＭＣＰに代表されるようにパッケージング化されていてもよい。また、チップ部品３０としては、例えばコンデンサや抵抗などの直方体型の電子部品が挙げられる。   The semiconductor chip 20 is provided with bumps 21 as external terminals on one side, and can be mounted while being electrically connected to the outside. However, the present invention is not limited to this, and for example, it may be packaged as represented by WCSP or MCP. The chip component 30 may be a rectangular parallelepiped electronic component such as a capacitor or a resistor.

ここで、ＷＣＳＰ（Ｗａｆｅｒ Ｌｅｖｅｌ Ｃｈｉｐ Ｓｉｚｅ Ｐａｃｋａｇｅもしくは、Ｗａｆｅｒ Ｌｅｖｅｌ Ｃｈｉｐ Ｓｃａｌｅ Ｐａｃｋａｇｅ）は、ウエハ単位でパッケージング処理を行い個片化して得られるチップサイズとほぼ等しい外形寸法を有するパッケージである。このようなＷＣＳＰは例えば特開平９−６４０４９号に開示されている。ＭＣＰ（Ｍｕｌｔｉ Ｃｈｉｐ Ｐａｃｋａｇｅ）は、半導体チップを２次元もしくは３次元（スタック構造）敵に複数搭載したパッケージである。   Here, the WCSP (Wafer Level Chip Size Package or Wafer Level Chip Scale Package) is a package having an outer dimension substantially equal to a chip size obtained by performing packaging processing in units of wafers and singulating. Such a WCSP is disclosed in, for example, Japanese Patent Laid-Open No. 9-64049. The MCP (Multi Chip Package) is a package in which a plurality of semiconductor chips are mounted on a two-dimensional or three-dimensional (stacked structure) enemy.

金属部材４０は、例えば、金属板を屈曲して構成したり、金属材料を型成形させて構成することができる。金属部材４０の形状は、上述のように、実装基板１０、半導体チップ２０、封止樹脂５０と接触していれば特に制限はなく、例えば、２面以上が開口した箱状であってもかまわない。   The metal member 40 can be configured by, for example, bending a metal plate or molding a metal material. As described above, the shape of the metal member 40 is not particularly limited as long as it is in contact with the mounting substrate 10, the semiconductor chip 20, and the sealing resin 50. For example, the shape of the metal member 40 may be a box shape having two or more surfaces opened. Absent.

金属部材４０は、例えば、銅部材、アルミニウム部材等が挙げられる。また、金属部材４０は、実装基板１０、半導体チップ２０、及び封止樹脂よりも高い熱伝導率を有するものを選択することがよい。本実施形態では、金属部材４０として銅部材を適用している。   Examples of the metal member 40 include a copper member and an aluminum member. The metal member 40 is preferably selected to have a higher thermal conductivity than the mounting substrate 10, the semiconductor chip 20, and the sealing resin. In the present embodiment, a copper member is applied as the metal member 40.

金属部材４０としての銅部材の熱伝導率は、例えば３９５（Ｗ／ｍ・ｋ）であり、例えば、実装基板１０としてのシリコン基板の熱伝導率が１１７．５（Ｗ／ｍ・ｋ）で、半導体チップの熱伝導率が１１７．５（Ｗ／ｍ・ｋ）で、後述する封止樹脂５０としての液状エポキシ系樹脂の熱伝導率が０．８４（Ｗ／ｍ・ｋ）であることから、これらよりも高くなっている。   The thermal conductivity of the copper member as the metal member 40 is, for example, 395 (W / m · k). For example, the thermal conductivity of the silicon substrate as the mounting substrate 10 is 117.5 (W / m · k). The thermal conductivity of the semiconductor chip is 117.5 (W / m · k), and the thermal conductivity of the liquid epoxy resin as the sealing resin 50 described later is 0.84 (W / m · k). Therefore, it is higher than these.

封止樹脂５０は、例えば、液状エポキシ系樹脂、シリカなどのフィラー入りの液状エポキシ樹脂（熱膨張係数：８〜１２ｐｐｍ）等が挙げられる。   Examples of the sealing resin 50 include a liquid epoxy resin, a liquid epoxy resin containing filler such as silica (thermal expansion coefficient: 8 to 12 ppm), and the like.

封止樹脂５０は、実装基板１０と金属部材４０との間の範囲の熱膨張係数を有する材料を選択することがよい。具体的には、例えば、本実施形態では、実装基板１０としてのシリコン基板の熱膨張係数が３ｐｐｍで、金属部材４０としての銅部材の熱膨張係数が１６ｐｐｍであることから、熱膨張係数が１０ｐｐｍ前後の封止樹脂を選択することがよい。   As the sealing resin 50, a material having a thermal expansion coefficient in a range between the mounting substrate 10 and the metal member 40 is preferably selected. Specifically, for example, in this embodiment, the thermal expansion coefficient of the silicon substrate as the mounting substrate 10 is 3 ppm, and the thermal expansion coefficient of the copper member as the metal member 40 is 16 ppm. It is preferable to select the sealing resin before and after.

以上説明した本実施形態に係る半導体装置１００では、実装基板１０、半導体チップ２０及び封止樹脂５０よりも熱伝導率が高い金属部材４０が、当該実装基板１０、半導体チップ２０及び封止樹脂５０と接触して配設されている。このため、金属部材４０によって、半導体チップ２０で発生する熱を直接、並びに、実装基板１０及び封止樹脂５０を介して効率的に放熱でき、半導体装置の熱抵抗を低減させることができる。   In the semiconductor device 100 according to the present embodiment described above, the metal member 40 having higher thermal conductivity than the mounting substrate 10, the semiconductor chip 20, and the sealing resin 50 corresponds to the mounting substrate 10, the semiconductor chip 20, and the sealing resin 50. Is arranged in contact with. For this reason, the metal member 40 can efficiently dissipate heat generated in the semiconductor chip 20 directly and through the mounting substrate 10 and the sealing resin 50, thereby reducing the thermal resistance of the semiconductor device.

加えて、封止樹脂５０の熱膨張係数を実装基板１０の熱膨張係数と金属部材４０の熱膨張係数との間の範囲にする、具体的には、例えば、封止樹脂５０の熱膨張係数を実装基板の熱膨張係数よりも高く、金属部材４０の熱膨張係数よりも小さい値とすることで、長期に渡り半導体装置を使用しても、昇温による部材の膨張に起因する部材間の離間が防止され、各部材同士の密着（接着）が保たれ、継続して金属部材４０による上記放熱が実現される。   In addition, the thermal expansion coefficient of the sealing resin 50 is set to a range between the thermal expansion coefficient of the mounting substrate 10 and the thermal expansion coefficient of the metal member 40. Specifically, for example, the thermal expansion coefficient of the sealing resin 50 is used. By setting the value to be higher than the thermal expansion coefficient of the mounting substrate and smaller than the thermal expansion coefficient of the metal member 40, even if the semiconductor device is used for a long time, the members between the members due to the expansion of the temperature due to the temperature rise Separation is prevented, adhesion (adhesion) between the members is maintained, and the heat dissipation by the metal member 40 is continuously realized.

なお、上記実施形態では、半導体チップ２０と複数のチップ部品３０とが実装基板１０に実装した形態を説明したが、これに限定されず、例えば、半導体チップ２０のみを実装基板１０に実装した形態であってもよいし、複数の半導体チップ２０を実装基板１０に実装した形態であってもよい。   In the above embodiment, the form in which the semiconductor chip 20 and the plurality of chip components 30 are mounted on the mounting substrate 10 has been described. However, the present invention is not limited to this. For example, the form in which only the semiconductor chip 20 is mounted on the mounting substrate 10. It may be a form in which a plurality of semiconductor chips 20 are mounted on the mounting substrate 10.

また、上記実施形態は、限定的に解釈されるものではなく、本発明の要件を満足する範囲内で実現可能であることは、言うまでもない。   Further, the above embodiment is not construed in a limited manner, and it goes without saying that it can be realized within the range satisfying the requirements of the present invention.

実施形態に係る半導体装置を示す概略平面図である。1 is a schematic plan view showing a semiconductor device according to an embodiment. 実施形態に係る半導体装置を示す概略断面図である。1 is a schematic cross-sectional view showing a semiconductor device according to an embodiment.

符号の説明Explanation of symbols

１０ 実装基板
１１ 配線回路
１２ 外部端子
１３ パッド
１４ バンプ
２０ 半導体チップ
２１ バンプ
３０ チップ部品
４０ 金属部材
５０ 封止樹脂
６０ 他の実装基板
１００ 半導体装置 10 mounting substrate 11 wiring circuit 12 external terminal 13 pad 14 bump 20 semiconductor chip 21 bump 30 chip component 40 metal member 50 sealing resin 60 other mounting substrate 100 semiconductor device

Claims (4)

配線回路が形成された実装基板と、
前記配線に接続されるように前記実装基板に搭載される半導体チップと、
前記半導体チップ及び前記実装基板に接触して配設された金属部材と、
前記実装基板と前記金属基板との間隙を封止する封止樹脂と、
を備えた半導体装置。 A mounting board on which a wiring circuit is formed;
A semiconductor chip mounted on the mounting substrate to be connected to the wiring;
A metal member disposed in contact with the semiconductor chip and the mounting substrate;
A sealing resin for sealing a gap between the mounting substrate and the metal substrate;
A semiconductor device comprising: 前記封止樹脂の熱膨張係数は、前記実装基板の熱膨張係数と前記金属部材の熱膨張係数との間の範囲である請求項１に記載の半導体装置。   The semiconductor device according to claim 1, wherein a thermal expansion coefficient of the sealing resin is in a range between a thermal expansion coefficient of the mounting substrate and a thermal expansion coefficient of the metal member. 前記実装基板は、シリコン基板である請求項１又は２に記載の半導体装置。   The semiconductor device according to claim 1, wherein the mounting substrate is a silicon substrate. 前記金属部材の熱伝導率は、前記実装基板、前記半導体チップ、及び前記封止樹脂の熱伝導率よりも高い請求項１〜３のいずれか１項に記載の半導体装置。   4. The semiconductor device according to claim 1, wherein a thermal conductivity of the metal member is higher than a thermal conductivity of the mounting substrate, the semiconductor chip, and the sealing resin.
JP2006269210A 2006-09-29 2006-09-29 Semiconductor device Pending JP2008091530A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2006269210A JP2008091530A (en) 2006-09-29 2006-09-29 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2006269210A JP2008091530A (en) 2006-09-29 2006-09-29 Semiconductor device

Publications (1)

Publication Number Publication Date
JP2008091530A true JP2008091530A (en) 2008-04-17

Family

ID=39375401

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006269210A Pending JP2008091530A (en) 2006-09-29 2006-09-29 Semiconductor device

Country Status (1)

Country Link
JP (1) JP2008091530A (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0258357A (en) * 1988-08-24 1990-02-27 Hitachi Ltd Pin grid array type semiconductor device
JPH0823049A (en) * 1994-07-08 1996-01-23 Hitachi Chem Co Ltd Semiconductor package
JP2000022052A (en) * 1998-06-30 2000-01-21 Casio Comput Co Ltd Semiconductor device and its manufacture
JP2004014870A (en) * 2002-06-07 2004-01-15 Taiyo Yuden Co Ltd Circuit module and its producing method

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0258357A (en) * 1988-08-24 1990-02-27 Hitachi Ltd Pin grid array type semiconductor device
JPH0823049A (en) * 1994-07-08 1996-01-23 Hitachi Chem Co Ltd Semiconductor package
JP2000022052A (en) * 1998-06-30 2000-01-21 Casio Comput Co Ltd Semiconductor device and its manufacture
JP2004014870A (en) * 2002-06-07 2004-01-15 Taiyo Yuden Co Ltd Circuit module and its producing method

Similar Documents

Publication Publication Date Title
US10546844B2 (en) Stack package and method of manufacturing the stack package
US10204848B2 (en) Semiconductor chip package having heat dissipating structure
US11728232B2 (en) Semiconductor package having a stiffener ring
US7714451B2 (en) Semiconductor package system with thermal die bonding
JP2012138473A (en) Mounting structure for semiconductor device and electronic component
CN111627871A (en) Semiconductor package
JP2004071670A (en) Ic package, connecting structure and electronic apparatus
JP2008305838A (en) Semiconductor device and mounting structure thereof
JP2006196709A (en) Semiconductor device and manufacturing method thereof
KR20060105403A (en) Package structure having circuit and composite substrate
JP2007095860A (en) Semiconductor device
US7310224B2 (en) Electronic apparatus with thermal module
JP4919689B2 (en) Module board
US11502020B2 (en) Electronic device having a chip package module
EP3751603A2 (en) Semiconductor package with a heat sink bonded to a semiconductor chip with a bonding layer and to a molding material with a thermal interface material
JP2005332918A (en) Electronic apparatus
US20090072373A1 (en) Packaged integrated circuits and methods to form a stacked integrated circuit package
JP2018182175A (en) Power semiconductor module
JP2008091530A (en) Semiconductor device
US10366906B2 (en) Electronic package and its package substrate
US20160005674A1 (en) Integrated circuit assembly and integrated circuit packaging structure
JP2016219535A (en) Electronic circuit device
JP2020188082A (en) Semiconductor package
JP2008140979A (en) Package-type semiconductor device
JP2020167181A (en) Electronic apparatus

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20080815

A711 Notification of change in applicant

Free format text: JAPANESE INTERMEDIATE CODE: A712

Effective date: 20081210

RD03 Notification of appointment of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7423

Effective date: 20090203

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20101101

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20101109

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20110111

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20110201