JP2008085864A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the amount of control information related to restructure of circuit structure in a semiconductor device, the circuit structure of which can be dynamically restructured. <P>SOLUTION: The semiconductor device which has a control data memory 24 that stores configuration data and an operator 26 includes a plurality of calculation parts 22, the circuit structure of which can be restructured corresponding to the configuration data, and a configuration memory 13A that stores structure specifying data to output the configuration data from the control data memory. In the configuration memory, the configuration data are not stored, but only information to output the configuration data from the control data memory is stored to supply the configuration data. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device whose circuit configuration can be dynamically reconfigured.

  Conventionally, a semiconductor device such as an LSI is generally designed to arrange an AND gate (logical product operation circuit), an OR gate (logical sum operation circuit), and wiring related to them so as to execute a predetermined process as a required specification. A semiconductor device is manufactured that is determined in the process and capable of executing processing according to the required specifications. That is, when a desired function is to be realized in a conventional semiconductor device, a circuit configuration (logic configuration) is designed in units of gates (gate level), and a semiconductor device that realizes the function is manufactured. Yes.

  However, since the circuit configuration of the semiconductor device is fixed in the design process, it is necessary to perform all of the design and manufacture each time a process according to a different required specification is performed due to a specification change or the like. . Therefore, much labor and time are required, and the development cost is high.

  As one method for solving this problem, there is a reconfigurable semiconductor device called a reconfigurable LSI that can change the process of reconfiguring and executing logic even after manufacturing. This reconfigurable semiconductor device has a plurality of arithmetic units that can receive a control signal (configuration information) from the CPU and change functions. The arithmetic unit is configured by appropriately combining a shifter, an ALU (arithmetic logic unit), a selector, and the like, and receives processing information from the CPU, and executes processing by reconfiguring the logic accordingly. It is possible to change.

  In the reconfigurable semiconductor device described above, the CPU directly controls a plurality of arithmetic units, and the processing speed is low. For example, when processing to be executed by a plurality of arithmetic units is changed based on an interrupt from a certain arithmetic unit, the CPU receives an interrupt from the arithmetic unit, calls and executes an interrupt processing routine, and then executes the processing. Configuration information corresponding to the routine processing result is supplied to a plurality of arithmetic units. This interrupt process requires a time corresponding to several tens of clocks. Therefore, in the above-described reconfigurable semiconductor device, the processing speed is low, and the processing to be executed by the arithmetic unit cannot be changed dynamically (in units of clocks).

  As one method for solving this problem, the present applicant has proposed a reconfigurable semiconductor device having a configuration shown in FIG. FIG. 10 is a diagram illustrating a configuration example of a reconfigurable semiconductor device proposed by the present applicant. The semiconductor device is equivalent to a CPU with respect to change control of a circuit configuration (logical configuration) instead of the CPU. A functional sequencer is provided.

  The sequencer (control unit) 1 comprehensively controls the semiconductor device in accordance with an instruction from the outside (for example, a processor connected via the external bus 3). The circuit configuration of the arithmetic processing unit 2 (Including logical configuration) is managed and control is performed to dynamically change it. Since the sequencer 1 dynamically changes the circuit configuration of the arithmetic processing unit 2 according to the application, the arithmetic processing unit 2 can supply a control signal from the sequencer 1 including configuration data (configuration information). Are connected to each functional unit via a signal line.

  The sequencer 1 includes a state control circuit 11, a state register 12, and a configuration memory 13F. The state control circuit 11 is a configuration data and fixed value data for shifting the state (circuit configuration) of the arithmetic processing unit 2 to the next state based on a predetermined sequence set in advance, a state transition instruction signal from the arithmetic processing unit 2, or the like. Is read from the configuration memory 13F, and a read timing is generated. The configuration memory address is generated by the state control circuit 11 with reference to information indicating the current state held in the state register 12. Also, the information held in the state register 12 is updated when transitioning to the next state.

  The configuration memory 13F stores configuration data for setting the circuit configuration of the arithmetic processing unit 2 and fixed value data. All configuration data and fixed value data are written in advance to the configuration memory 13F from the outside before the operation starts, and are held as a set of data for each state. Configuration data and fixed value data stored in the configuration memory 13 </ b> F are read according to control by the state control circuit 11 and output to the arithmetic processing unit 2. Details of the contents of the configuration memory 13F will be described later.

  The arithmetic processing unit 2 includes a selector / register (bus) 21, an arithmetic unit 22-i, and a data memory 23-j. Note that i and j are subscripts, i = 1 to N (N is an arbitrary number), and j = 1 to M (M is an arbitrary number).

  The selector / register 21 is controlled by configuration data supplied from the sequencer 1. The selector / register 21 is connected to the arithmetic units 22-1 to 22-N and the data memories 23-1 to 23-M, respectively, and exchanges data with the arithmetic units 22-i and the data memory 23-j. In other words, the selector / register 21 has a network function for connecting the arithmetic units 22-1 to 22-N and the data memories 23-1 to 23-M so that they can communicate with each other.

  Specifically, the selector / register 21 supplies data to the arithmetic unit 22-i, supplies write data to and from the data memory 23-j, and is read according to the configuration data. Receive data supply. Further, the selector / register 21 has a register that temporarily holds the output (calculation result) and the like of the calculation unit 22-i. From the data held in the register according to the configuration data or other than that The supplied data can be selectively output.

Each arithmetic unit 22-i includes a register 25 and an arithmetic unit (ALU) unit 26.
The register 25 includes a configuration register 25A and a fixed value register 25B that temporarily hold configuration data and fixed value data supplied from the sequencer 1, respectively.

  The ALU unit 26 is configured using a shift circuit (shifter), an ALU (arithmetic logic unit), a selector, and the like (hereinafter, for convenience of explanation, these are simply referred to as an arithmetic unit without being distinguished from each other). The ALU unit 26, specifically, a plurality of arithmetic units (or one) constituting the ALU unit may be selected and determined as appropriate according to the application to be used.

  In the ALU unit 26, the operation mode of the arithmetic units and the connection between the arithmetic units are set for each ALU unit 26 based on the configuration data CD held in the configuration register 25A. That is, the ALU unit 26 can change the circuit configuration in accordance with the configuration data CD in units of this, and includes addition, multiplication, bit operation, logical operation (AND, OR, EOR, etc.), etc. Each arithmetic unit is controlled so as to realize a desired function (perform predetermined processing).

  For example, in the case of a shift circuit, a shift amount, an arithmetic shift process, a logical shift process, a mask process for a predetermined bit after the shift process, and the like are controlled. For example, if the ALU is configured using an AND circuit, an OR circuit, or the like, the circuit (calculation) function of the entire ALU is controlled by appropriately combining them. In the case of a selector, which input is output from among a plurality of inputs is controlled. Furthermore, the connections among these shift circuits, ALUs, selectors, and the like are controlled.

  The ALU unit 26 receives the first input data DT1 supplied from the selector / register 21, and the second input data DT2 or fixed value register 25B supplied from the selector / register 21 according to the configuration data. One of the fixed value data CVD held in is input, a predetermined calculation is performed using them, and the calculation result is output. The output of the ALU unit 26 can be output as it is, but is also configured to be fed back based on the configuration data. For example, the output can be accumulated and standardized and output.

  Each data memory 23-j is a memory that stores data related to processing in the arithmetic processing unit 2.

  FIG. 11 is a diagram for explaining the contents of the configuration memory 13F shown in FIG. 10, in which configuration data and fixed value data corresponding to each state are stored as described above. In FIG. 11, CDi is configuration data, and CVDi is fixed value data. Note that i is a subscript, and i = 1 to N (N is an arbitrary number). In FIG. 11, only the value of the fixed value data CVDi is shown, and the value of the configuration data CDi is not shown.

  The configuration data CDi and the fixed value data CVDi are supplied to the arithmetic unit 22-i and temporarily held in the configuration register 25 when the k-th (k = 1 to 128 natural number) state is set. That is, configuration data and fixed value data related to a circuit configuration FUNCk for realizing a desired circuit function in the arithmetic processing unit 2 are a set of configuration data CD1 to CDN arranged in the row direction in FIG. And fixed value data CVD1 to CVDN. Although not shown in FIG. 11, the configuration memory 13F stores configuration data for controlling the selector / register 21 in addition to the configuration data related to the arithmetic unit 22-i.

  As described above, by providing the sequencer 1 instead of the CPU, a reconfigurable semiconductor device can perform so-called dynamic reconfiguration, and the circuit configuration (logic) can be dynamically reconfigured in units of clocks. it can. For example, the arithmetic processing unit 2 can perform the A function in a certain clock period and perform the B function different from the A function in the next clock period based on the configuration data (control signal) from the sequencer 1.

  However, in the reconfigurable semiconductor device shown in FIG. 10 and FIG. 11, for the arithmetic unit capable of inputting a fixed value (constant), the fixed value data is stored in the configuration memory 13F together with the configuration data and is necessary. Accordingly, it is read out and held in the configuration register 25 provided corresponding to the arithmetic unit. When the fixed value data is stored in the configuration memory 13F as described above, a fixed value data area for storing the fixed value data is provided for each arithmetic unit capable of inputting the fixed value, and all the fixed value data is stored in the configuration memory. It is necessary to save in 13F. For example, if the second input data from the selector / register 21 is 32 bits wide for an arithmetic unit capable of inputting a fixed value, a 32-bit fixed value data area for each arithmetic unit in the configuration memory 13F. Must be provided for all the states of the arithmetic processing unit 2 (hereinafter, the state is also referred to as “configuration”).

  Here, the fixed value data is set as the input of each arithmetic unit in all the states of the arithmetic processing unit 2, that is, the fixed value data is set as the input of each arithmetic unit every time the state of the arithmetic processing unit 2 is switched. rare. Therefore, the fixed value data area provided as described above wastes the storage area of the configuration memory 13F, and a large amount of memory (storage area) is required when the fixed value data is stored in the configuration memory 13F. Will be consumed.

  In view of this, the present applicant has proposed a reconfigurable semiconductor device having a configuration shown in FIG. 12 in which the storage capacity required for storing fixed value data is reduced (see Patent Document 1). FIG. 12 is a diagram showing another configuration example of the reconfigurable semiconductor device proposed by the present applicant. In FIG. 12, components having the same functions as those shown in FIG. 10 are given the same reference numerals, and redundant descriptions are omitted.

  The reconfigurable semiconductor device shown in FIG. 12 includes a sequencer 1 and an arithmetic processing unit 2 and includes fixed value memories 72-1 and 72-2 that store fixed value data in the arithmetic processing unit 2. .

The sequencer 1 includes a state control circuit 11, a state register 12, and a configuration memory 13G.
The configuration memory 13G stores configuration data for setting the circuit configuration of the arithmetic processing unit 2 and fixed value designation data. The fixed value designation data is for designating and reading fixed value data corresponding to the state of the arithmetic processing unit 2 from the fixed value data stored in the fixed value memories 72-1 and 72-2. Here, as an example, the addresses in the fixed value memories 72-1 and 72-2 are used.

  The arithmetic processing unit 2 includes, in addition to the selector / register (bus) 21, the arithmetic unit 22-i, and the data memory 23-j, fixed value memories 72-1, 72-2, a selector 73-i, and a fixed value designation. It has registers 74-1 and 74-2. Note that i and j are subscripts, i = 1 to N (N is an arbitrary number), and j = 1 to M (M is an arbitrary number).

  The fixed value memories 72-1 and 72-2 are memories for storing fixed value data. The fixed value data stored in the fixed value memories 72-1 and 72-2 is read out by the sequencer 1 based on the address values set in the fixed value designation registers 74-1 and 74-2, and the selector 73- output to i.

  The selector 73-i is fixed according to the configuration data supplied from the sequencer 1, the second input data DT 2 supplied from the selector / register 21 or the fixed value memories 72-1 and 72-2. The value data CVD is selected and output to the ALU unit 26 in the calculation unit 22-i.

  The arithmetic unit 22-i includes a configuration register 71 that temporarily holds configuration data supplied from the sequencer 1 and an ALU unit 26. Since the fixed value data is read from the fixed value memories 72-1 and 72-2 and supplied to the ALU unit 26 via the selector 73-i, the calculation unit 22-i has the fixed value register shown in FIG. 10. Not equipped.

  The configuration data and fixed value designation data stored in the configuration memory 13G, and the fixed value data stored in the fixed value memories 72-1 and 72-2 are externally received from the configuration memory 13G and the fixed value data. Each of the memories 72-1 and 72-2 is written and held in advance before the operation starts. The configuration data and the fixed value designation data are held in the configuration memory 13G as a set of data for each state.

  FIG. 13 is a diagram for explaining the contents of the configuration memory 13G and fixed value memories 72-1 and 72-2 shown in FIG. In FIG. 13, the contents equivalent to the contents of the configuration memory 13F shown in FIG. 11 are shown as an example for comparison and reference.

  FIG. 13A shows the contents of the configuration memory 13G. In FIG. 13A, CDi (i = 1 to N is a natural number) is configuration data, and CVAD1 and CVAD2 are address values in fixed value memories 72-1 and 72-2, respectively. FUNCk (natural number of k = 1 to 128) indicates a state (circuit surface) for realizing a desired circuit function in the arithmetic processing unit 2.

  FIGS. 13B and 13C show the contents of the fixed value memories 72-1 and 72-2. 13B and 13C, CVAD1 and CVAD2 are address values in the fixed value memories 72-1 and 72-2, and CVDi (i = 1 to N is a natural number) is fixed value data. FIGS. 13B and 13C show a case where fixed value data CVD1 and CVD3 are stored in the fixed value memory 72-1, and fixed value data CVD2 and CVDN are stored in the fixed value memory 72-2. .

  As shown in FIGS. 13B and 13C, when the combination of the fixed value data CVDi is the same in each of the fixed value memories 72-1 and 72-2, one set of fixed value data CVDi is obtained. Remembered. That is, the combinations of the fixed value data CVDi stored in the fixed value memory 72-1 are different from each other and are not stored redundantly. Similarly, the fixed values stored in the fixed value memory 72-2 are stored. The combinations of data CVDi are different from each other and are not stored redundantly.

  Further, as shown in FIG. 13A, in the configuration memory 13G, fixed value memories 72-1, 72 for storing a combination of configuration data CDi and fixed value data CVDi corresponding to this state. -2 address values CVAD1 and CVAD2 are stored.

  As described above, the fixed value data is stored in the fixed value memories 72-1 and 72-2 so that the combination of the fixed value data does not overlap, and the configuration memory 13 G corresponds to the configuration data and its state. The address values of fixed value memories 72-1 and 72-2 for reading fixed value data are stored. As a result, only the address values of the fixed value memories 72-1 and 72-2 need be stored in the configuration memory 13G without storing the fixed value data, so the storage capacity required for the configuration memory 13G. The configuration memory 13G can be configured with a small size memory. In addition, the fixed value memories 72-1 and 72-2 do not store fixed value data for each state, but store only one fixed value data of the same combination as one set of fixed value data. It is possible to reduce the storage capacity required to store data.

JP 2006-18453 A

  Here, in a reconfigurable semiconductor device, the number of circuit configurations that can be set by configuration data tends to be considerably smaller than the number of state transitions that can be stored in the configuration memory. For example, assuming that the number of bits of configuration data related to each arithmetic unit 22-i is 16 bits and the number of arithmetic units 22-i is 32, configuration data in one state (one circuit plane) The total number of bits is 512 bits, and there are enormous combinations of 2 to the 512th power. However, the memory capacity of an appropriate size considering the cost in the current LSI technology is about several tens of KB, and it is impossible to set all the huge combinations described above in the configuration memory.

  Further, in a reconfigurable semiconductor device, when attention is paid to the circuit configuration on a plurality of circuit surfaces when an actual application is mounted, the number of different circuit surfaces is often small. For example, with respect to the configuration data (configuration data CD1 shown in FIG. 13A) related to one arithmetic unit 22-1 in the reconfigurable semiconductor device shown in FIG. , It is very rare that the settings (configuration data) of all 128 planes are different, and there are actually only several different settings.

  The configuration data for controlling the selector / register (bus) 21 is also stored in the configuration memory. The selector / register (bus) 21 is composed of a large number of selectors and a large number of registers. The amount is enormous.

  An object of the present invention is to enable a semiconductor device capable of dynamically reconfiguring a circuit configuration to reduce the amount of control information related to the reconfiguration of the circuit configuration.

The semiconductor device of the present invention includes a plurality of arithmetic units each having a first control data memory and an arithmetic unit, and having a circuit configuration reconfigurable according to the first configuration information, and a configuration memory. First configuration information is stored in the first control data memory, and first configuration designation information for outputting the first configuration information from the first control data memory is stored in the configuration memory.
According to the present invention, the first configuration information is stored in the first control data memory in the arithmetic unit, so that the configuration memory does not have a data area for storing the first configuration information itself. Only the designation information for outputting the first configuration information from the first control data memory needs to be stored, and the amount of data to be stored can be reduced.

  According to the present invention, since the first control data memory is provided for each arithmetic unit separately from the configuration memory, the configuration information related to the reconfiguration of the circuit configuration is stored. It is not necessary to provide a data area for storing itself, and the configuration information can be supplied only by storing the designation information for outputting the configuration information from the first control data memory. Therefore, the amount of control information for reconfiguring the circuit configuration can be reduced, the storage capacity required for the configuration memory can be reduced, and the circuit scale can be reduced.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
FIG. 1 is a diagram illustrating a configuration example of a reconfigurable semiconductor device according to the first embodiment of the present invention. In FIG. 1, components having the same functions as those shown in FIG. 10 are denoted by the same reference numerals. The reconfigurable semiconductor device according to the first embodiment includes a sequencer (control unit) 1 and an arithmetic processing unit 2.

  The sequencer 1 comprehensively controls the semiconductor device in response to an instruction from the outside (for example, a processor connected via the external bus 3), and the circuit configuration (logical configuration of the arithmetic processing unit 2). Control), and control to change it dynamically. The sequencer 1 is connected to each functional unit of the arithmetic processing unit 2 via signal lines in order to dynamically change the circuit configuration of the arithmetic processing unit 2 according to the application.

  The sequencer 1 includes a state control circuit 11, a state register 12, and a configuration memory 13A. The arithmetic processing unit 2 includes a selector / register (bus) 21, an arithmetic unit 22-i, and a data memory 23-j. Each arithmetic unit 22-i includes a control data memory 24, a register 25, and An arithmetic unit (ALU) unit 26 is included. Note that i and j are subscripts, i = 1 to N (N is an arbitrary number), and j = 1 to M (M is an arbitrary number).

  The state control circuit 11 is a selector / register for shifting the state (circuit configuration) of the arithmetic processing unit 2 to the next state based on a predetermined sequence set in advance, a state transition instruction signal from the arithmetic processing unit 2, or the like. A configuration memory address for reading the configuration data and configuration designation data of the (bus) 21 from the configuration memory 13A and its read timing are generated. The configuration memory address is generated by the state control circuit 11 with reference to information indicating the current state held in the state register 12. Also, the information held in the state register 12 is updated when transitioning to the next state.

  The configuration memory 13A stores configuration data for setting the configuration of the selector / register (bus) 21 in the arithmetic processing unit 2 and configuration designation data related to the arithmetic units 22-1 to 22-N. This configuration designation data is information that can uniquely identify a set of configuration data and fixed value data in the control data memory 24 corresponding to the state of the arithmetic unit 22-i, and is stored in the control data memory 24. This is for designating and reading a set of configuration data and fixed value data corresponding to the state of the arithmetic unit 22-i from the set of configuration data and fixed value data. Hereinafter, as an example, the configuration specifying data is an address in the control data memory 24.

  The selector / register (bus) 21 controls data exchange within the arithmetic processing unit 2 and is controlled by configuration data CSRD supplied from the sequencer 1. The selector / register (bus) 21 is connected to the arithmetic units 22-1 to 22-N and the data memories 23-1 to 23-M, respectively, and transmits data between the arithmetic units 22-i and the data memory 23-j. Give and receive. In other words, the selector / register (bus) 21 has a network function for connecting the arithmetic units 22-1 to 22-N and the data memories 23-1 to 23-M so that they can communicate with each other.

  Specifically, the selector / register (bus) 21 supplies data to the arithmetic unit 22-i, supplies write data to the data memory 23-j, and reads data according to the configuration data. Receive supply of released data. Further, the selector / register (bus) 21 has a register that temporarily holds the output (calculation result) and the like of the calculation unit 22-i, and the data stored in the register according to the configuration data or Data supplied from other sources can be selectively output.

  The control data memory 24 is a memory for storing configuration data and fixed value data related to the computing unit 22-i. The control data memory 24 is a configuration data area 24A for storing configuration data and a fixed value for storing fixed value data. It has a data area 24B. Configuration data and fixed value data relating to the arithmetic unit 22-i are held in the control data memory 24 as a set of data, and are read based on the address value CADi supplied from the sequencer 1 as configuration designation data. The data (configuration data and fixed value data) CDCVD is output to the register 25.

  The register 25 includes a configuration register 25A that holds configuration data output from the control data memory 24 and a fixed value register 25B that holds fixed value data. The register 25 is for adjusting the timing of supplying the data output from the control data memory 24 to the ALU unit 26. For example, the control data memory 24 is a synchronous memory, and the output timing is the same. If adjustment is unnecessary, the register 25 may not be provided.

  The ALU unit 26 is configured by using a shift circuit (shifter), an ALU (arithmetic logic operation device), a selector, and the like (hereinafter, these are also simply referred to as an arithmetic unit without being distinguished from each other). The ALU unit 26, specifically, a plurality of arithmetic units (or one) constituting the ALU unit may be appropriately selected and determined according to the application to be used.

  In the ALU unit 26, the operation mode of the arithmetic units and the connection between the arithmetic units are set for each ALU unit 26 based on the configuration data CD held in the configuration register 25A. That is, the ALU unit 26 can change the circuit configuration in accordance with the configuration data CD with this as a unit so as to realize a desired function including addition, multiplication, bit operation, and logical operation. Each arithmetic unit and the like are controlled (to execute a predetermined process).

  For example, in the case of a shift circuit, a shift amount, an arithmetic shift process, a logical shift process, a mask process for a predetermined bit after the shift process, and the like are controlled. For example, if the ALU is configured using an AND circuit, an OR circuit, or the like, the circuit (calculation) function of the entire ALU is controlled by appropriately combining them. In the case of a selector, which input is output from among a plurality of inputs is controlled. Furthermore, the connections among these shift circuits, ALUs, selectors, and the like are controlled.

The ALU unit 26 receives the first input data DT1 supplied from the selector / register 21, and the second input data DT2 or fixed value register 25B supplied from the selector / register 21 according to the configuration data. One of the fixed value data CVD held in is input, and calculation is performed using them, and the calculation result is output. The output of the ALU unit 26 can be output as it is, but is also configured to be fed back based on the configuration data. For example, the output can be accumulated and standardized and output.
Each data memory 23-j is a memory that stores data related to processing in the arithmetic processing unit 2.

  The configuration data of the selector / register (bus) 21 stored in the configuration memory 13A, the configuration designation data of the arithmetic units 22-1 to 22-N, and the arithmetic unit 22- stored in the control data memory 24 The configuration data and fixed value data of i are written and held in advance in the configuration memory 13A and the control data memory 24 from the outside by, for example, RISC (processor) or other hardware before starting the operation.

FIG. 2 is a diagram for explaining the contents of the configuration memory 13A and the control data memory 24 shown in FIG.
FIG. 2A shows the contents of the configuration memory 13A. In FIG. 2A, CADi (i = 1 to N is a natural number) is an address value in the control data memory 24 as configuration designation data related to the corresponding arithmetic unit 22-i, and CSRD is a selector / register (bus ) 21 configuration data. FUNCk (natural number of k = 1 to 128) indicates a state (circuit surface) for realizing a desired circuit function in the arithmetic processing unit 2.

  2B and 2C show the contents of the control data memory 24 provided in the arithmetic unit 22-i, and CADi (i = 1 to N is a natural number, the same applies to CDCVDi) is controlled. It is an address value in the data memory 24, and CDCVDi is configuration data and fixed value data of the corresponding arithmetic unit 22-i. The data CDCVDi is, for example, bit combination of the configuration data CDi of the arithmetic unit 22-i and the fixed value data CVDi (“&” in the figure indicates a bit connector).

  2B and 2C show the contents of the control data memory 24 provided in the computing units 22-1 and 22-N, respectively, as an example. 2B and 2C, E1, E2, E3, E4,... And G1, G2, G3, G4,... Are the configuration data of the arithmetic units 22-1 and 22-N, and F1, F2 ,... And H1, H2, H3,.

  That is, in the reconfigurable semiconductor device according to the first embodiment, the control data memory 24 is provided in each calculation unit 22-i in the calculation processing unit 2, and the configuration data CDi of the calculation unit 22-i is fixed. Value data CVDi is stored. In the configuration memory 13A in the sequencer 1, the address value of the control data memory 24 for reading the configuration data CDi and the fixed value data CVDi from the control data memory 24 of each arithmetic unit 22-i is stored as configuration designation data. To do.

  When the state in the arithmetic processing unit 2 is switched, the configuration data CSRD of the selector / register (bus) 21 corresponding to the state and the address value CADi as the configuration designation data relating to each arithmetic unit 22-i are obtained. Read from the configuration memory 13A. The read configuration data CSRD of the selector / register (bus) 21 is supplied to the selector / register (bus) 21 and the configuration of the selector / register (bus) 21 is set. The read address value CADi is supplied to each arithmetic unit 22-i, and the configuration data CDi and the fixed value data CVDi are read from the control data memory 24 based on the address value CADi, and the register 25 The circuit configuration is reconfigured by being supplied to the ALU unit 26. In this way, a desired function is realized by the arithmetic processing unit 2.

  Here, when the combination of the configuration data CDi of the arithmetic unit 22-i and the fixed value data CVDi stored in the control data memory 24 is the same, it is stored as one set of configuration data CDi and fixed value data CVDi. The That is, the combination of the configuration data CDi and the fixed value data CVDi stored in the control data memory 24 is different from each other and is not stored redundantly.

  As described above, according to the first embodiment, the control data memory 24 for storing the configuration data and the fixed value data related to the calculation unit 22-i is provided for each calculation unit 22-i in the calculation processing unit 2. The configuration memory 13A in the sequencer 1 stores configuration designation data (address value) for reading out configuration data and fixed value data related to the arithmetic unit 22-i from the control data memory 24. When the combination of the configuration data and the fixed value data related to the arithmetic unit 22-i is the same, the control data memory 24 does not store the configuration data differently, and the control data memory 24 fixes different configuration data. A set of value data is stored and selected according to an address value which is configuration designation data.

  As a result, the storage capacity required to store the configuration data for reconfiguring the circuit configuration can be reduced. For example, the storage capacity required for the configuration memory 13A can be reduced, and the circuit scale can be reduced. . Further, when the circuit configuration that can be set by the arithmetic unit 22-i is narrowed down in advance, that is, when the number of settable configuration data CDi is narrowed down, the configuration designation for reading the configuration data from the control data memory 24 The number of bits of data can be made smaller than the number of bits of configuration data, and the storage capacity required for the entire semiconductor device can be reduced.

(Second Embodiment)
Next, a second embodiment of the present invention will be described.
In the first embodiment described above, a set of configuration data and fixed value data related to the calculation unit 22-i is stored in the control data memory 24 provided in each calculation unit 22-i. In the second embodiment described below, memories for storing configuration data and fixed value data related to the computing unit 22-i are independently arranged.

  FIG. 3 is a diagram illustrating a configuration example of a reconfigurable semiconductor device according to the second embodiment. In FIG. 3, components having the same functions as those shown in FIG. 1 are denoted by the same reference numerals, and redundant description is omitted.

  The sequencer 1 includes a state control circuit 11, a state register 12, and a configuration memory 13B. The arithmetic processing unit 2 includes a selector / register (bus) 21, an arithmetic unit 22-i, and a data memory 23-j. Each arithmetic unit 22-i includes a first control data (configuration data) memory 31, a second control data (fixed value) memory 32, a configuration register 33, a fixed value register 34, and an ALU unit 26. Have.

  The configuration memory 13B includes configuration data for setting the configuration of the selector / register (bus) 21 in the arithmetic processing unit 2, the first configuration specifying data and the second data for the arithmetic units 22-1 to 22-N. The configuration designation data is stored. The first configuration specifying data is information that can uniquely identify the configuration data in the first control data memory 31 corresponding to the state of the arithmetic unit 22-i, and is stored in the first control data memory 31. This is for designating and reading out configuration data corresponding to the state of the arithmetic unit 22-i from the stored configuration data. Similarly, the second configuration designation data (fixed value designation data) is information that can uniquely identify the fixed value data in the second control data memory 32 corresponding to the state of the computing unit 22-i. This is for designating and reading fixed value data corresponding to the state of the arithmetic unit 22-i from the fixed value data stored in the second control data memory 32. In the following, as an example, the first and second configuration designation data are addresses in the control data memories 31 and 32, respectively.

  The first control data memory 31 is a memory that stores configuration data related to the computing unit 22-i. The configuration data CD stored in the first control data memory 31 is read out based on the address value CADi supplied from the sequencer 1 as the first configuration specifying data and is output to the configuration register 33.

  The second control data memory 32 is a memory for storing fixed value data related to the calculation unit 22-i. The fixed value data CVD stored in the second control data memory 32 is read based on the address value DADi supplied from the sequencer 1 as the second configuration specifying data, and is output to the fixed value register 34.

  The configuration register 33 and the fixed value register 34 correspond to the configuration register 25A and the fixed value register 25B in the first embodiment, respectively.

  Configuration data of the selector / register (bus) 21 stored in the configuration memory 13B, first and second configuration designation data related to the arithmetic units 22-1 to 22-N, and first and second controls The configuration data and fixed value data of the arithmetic unit 22-i stored in the data memories 31 and 32, respectively, start operation from the outside to the configuration memory 13B and the first and second control data memories 31 and 32, respectively. Previously written and held in advance. Further, the configuration data of the selector / register (bus) 21 and the first and second configuration designation data related to the arithmetic units 22-1 to 22-N are held in the configuration memory 13B as a set of data for each state. Is done.

  4 is a diagram for explaining the contents of the configuration memory 13B, the first control data memory 31, and the second control data memory 32 shown in FIG. In FIG. 4, the content equivalent to the content shown in FIG. 2 is shown as an example for comparison and reference.

  FIG. 4A shows the contents of the configuration memory 13B. In FIG. 4A, CADi (i = 1 to N is a natural number) is an address value in the control data memory 31 as the first configuration specifying data related to the corresponding arithmetic unit 22-i, and DADi (i = 1 to N) is an address value in the control data memory 32 as the second configuration specifying data related to the corresponding arithmetic unit 22-i. CSRD is configuration data of the selector / register (bus) 21. FUNCk (natural number of k = 1 to 128) indicates a state (circuit surface) for realizing a desired circuit function in the arithmetic processing unit 2.

  4B to 4E show the contents of the first and second control data memories 31 and 32 provided in the computing unit 22-i. FIG. 4B shows the contents of the first control data memory 31 provided in the calculation unit 22-1, CAD1 is the address value in the first control data memory 31, and CD1 is the calculation unit 22. -1 configuration data. FIG. 4C shows the contents of the second control data memory 32 provided in the calculation unit 22-1, DAD1 is an address value in the second control data memory 32, and CVD1 is the calculation unit 22. −1 fixed value data.

  Similarly, FIG. 4D shows the contents of the first control data memory 31 provided in the arithmetic unit 22-N, where CADN is an address value in the first control data memory 31, and CDN is This is configuration data of the computing unit 22-N. FIG. 4E shows the contents of the second control data memory 32 provided in the arithmetic unit 22-N, where DADN is an address value in the second control data memory 32, and CVDN is the arithmetic unit 22. -N fixed value data.

  That is, in the reconfigurable semiconductor device according to the second embodiment, the first and second control data memories 31 and 32 are provided in each arithmetic unit 22-i in the arithmetic processing unit 2, and the arithmetic unit 22- i configuration data CDi and fixed value data CVDi are stored independently. The configuration memory 13B in the sequencer 1 includes first and second configuration data CDi and fixed value data CVDi for reading out the configuration data CDi and the fixed value data CVDi from the independent first and second control data memories 31 and 32 of each arithmetic unit 22-i. The address values of the second control data memories 31 and 32 are stored as configuration designation data.

  When the state in the arithmetic processing unit 2 is switched, the configuration data CSRD of the selector / register (bus) 21 corresponding to the state and the address value CADi as the configuration designation data related to each arithmetic unit 22-i, DADi is read from the configuration memory 13B. The read configuration data CSRD of the selector / register (bus) 21 is supplied to the selector / register (bus) 21 and the configuration of the selector / register (bus) 21 is set.

  Further, the read address values CADi and DADi are supplied to the respective arithmetic units 22-i. The configuration data CDi is read from the first control data memory 31 based on the address value CADi and supplied to the ALU unit 26 via the configuration register 33, and the second data based on the address value DADi. Fixed value data CVDi is read from the control data memory 32 and supplied to the ALU unit 26 via the fixed value register 34. In this way, the circuit configuration is reconfigured, and a desired function is realized by the arithmetic processing unit 2.

  In the first control data memory 31, configuration data CDi having the same value is not stored redundantly, but only different data is stored. Similarly, only different fixed value data is stored in the second control data memory 32, and fixed value data CDi having the same value is not stored redundantly.

  As described above, according to the second embodiment, the same effects as those of the first embodiment can be obtained, the storage capacity required to store the configuration data for reconfiguring the circuit configuration can be reduced, and the circuit scale can be reduced. Can be reduced. Since the first and second control data memories 31 and 32 are provided for each calculation unit 22-i, the configuration data related to the calculation unit 22-i and the fixed value data are stored independently. The number of combinations of configuration data and fixed value data is large, but if the number of types of configuration data and fixed value data is considered individually, the required storage capacity can be further reduced. Become.

  The configuration in the first embodiment shown in FIG. 1 and FIG. 2 and the configuration in the second embodiment shown in FIG. 3 and FIG. 4 are appropriately selected according to the application to be used. Just do it.

(Third embodiment)
Next, a third embodiment of the present invention will be described.
FIG. 5 shows the configuration of a reconfigurable semiconductor device showing the internal structure of the selector / register (bus). In FIG. 5, components having the same functions as those shown in FIGS. 1 and 10 are denoted by the same reference numerals, and redundant description is omitted.

  The selector / register (bus) 21 includes a setting information register circuit 41 that stores configuration data CSRD that is selector / register (bus) setting information supplied from the sequencer 1, and a configuration stored in the setting information register circuit 41. A selector circuit 42 that performs a desired operation based on the data is included. The setting information register circuit 41 and the selector circuit 42 are composed of a large number of registers and a large number of selectors.

  FIG. 6 is a diagram for explaining the contents of the configuration memory 13C shown in FIG. 5. Configuration data and fixed value data related to the arithmetic unit 22-i corresponding to each state of the arithmetic processing unit 2, Configuration data of the selector / register (bus) 21 is stored. In FIG. 16, CDCVDi is configuration data and fixed value data relating to the arithmetic unit 22-i after bit combination, and CSRDp is configuration data of the selector / register (bus) 21. Note that i and p are subscripts, i = 1 to N (N is an arbitrary number), and p = 1 to Q (Q is an arbitrary number). FUNCk (natural number of k = 1 to 128) indicates a state (circuit surface) for realizing a desired circuit function in the arithmetic processing unit 2.

  In FIG. 6, in order to facilitate the comparison with the third embodiment of the present invention, the configuration data of the selector / register (bus) 21 is divided into Q groups and the configuration corresponding to each group. Data is shown as CSRDp.

  The configuration data of the selector / register (bus) 21 is not limited to the configuration data for reconfiguring the circuit configuration of the arithmetic unit 22-i. The selector / register (bus) 21 includes a large number of selectors and a large number of registers. Therefore, the amount of data is enormous.

  Therefore, the reconfigurable semiconductor device according to the third embodiment of the present invention described below is intended to reduce the storage capacity required to store the configuration data of the selector / register (bus) 21. Specifically, a control data memory for storing configuration data of the selector / register (bus) 21 is provided in the arithmetic processing unit 2, and the selector / register (bus) corresponding to the state is stored in the configuration memory in the sequencer. The configuration designation data for reading the configuration data 21 from the control data memory is stored.

  FIG. 7 is a diagram illustrating a configuration example of a reconfigurable semiconductor device according to the third embodiment. In FIG. 7, components having the same functions as those shown in FIGS. 1, 5, and 10 are denoted by the same reference numerals, and redundant description is omitted.

  The sequencer 1 includes a state control circuit 11, a state register 12, and a configuration memory 13D. The arithmetic processing unit 2 includes a selector / register (bus) 21, an arithmetic unit 22-i, and a data memory 23-j. The selector / register (bus) 21 includes a control data memory 51-p, a setting information register circuit 52 including a large number of registers, and a selector circuit 42 including a large number of selectors. Each arithmetic unit 22-i includes a register 25 composed of a configuration register 25 A and a fixed value register 25 B and an ALU unit 26.

  The configuration memory 13 </ b> D stores configuration data and fixed value data CDCVDi related to the calculation units 22-1 to 22-N in the calculation processing unit 2 and configuration designation data related to the selector / register (bus) 21. The configuration specifying data is information that can uniquely identify the configuration data in the control data memory 51-p corresponding to the state of the selector / register (bus) 21, and is stored in the control data memory 51-p. This is for designating and reading out configuration data corresponding to the state of the selector / register (bus) 21 from the configuration data being stored. In the following, as an example, the configuration designation data is an address in the control data memory 51-p.

  The control data memory 51-p is a memory for storing configuration data related to the selector / register (bus) 21. In this embodiment, the selector / register (bus) 21 is divided into Q groups, and a control data memory 51-p is arranged for each group. The configuration data CSRDp stored in the control data memory 51-p is read out based on the address value CSRADp supplied from the sequencer 1 as configuration designation data and is output to the setting information register circuit 52.

  The setting information register circuit 52 temporarily holds configuration data CSRD1 to CSRDQ supplied from the control data memories 51-1 to 51-Q. The selector circuit 42 reconfigures the circuit configuration based on the configuration data CSRD1 to CSRDQ held in the setting information register circuit 52, controls the data path in the arithmetic processing unit 2, and performs a desired operation.

  Here, configuration data and fixed value data related to the arithmetic units 22-1 to 22-N stored in the configuration memory 13D, configuration designation data related to the selector / register (bus) 21, and control data memory 51- The configuration data of the selector / register (bus) 21 respectively stored in p is written and held in advance from the outside in the configuration memory 13D and the control data memory 51-p before the operation is started. Further, the configuration data and fixed value data related to the arithmetic units 22-1 to 22-N and the configuration designation data related to the selector / register (bus) 21 are held in the configuration memory 13D as one set of data for each state. The

  FIG. 8 is a diagram for explaining the contents of the configuration memory 13D and the control data memory 51-p shown in FIG. In FIG. 8, for comparison purposes, content equivalent to the content of the configuration memory 13C shown in FIG. 6 is shown as an example.

  FIG. 8A shows the contents of the configuration memory 13D. In FIG. 8A, CDCVDi (i = 1 to N is a natural number) is configuration data and fixed value data related to the corresponding arithmetic unit 22-i. For example, the configuration data CDi and fixed value data CVDi are bit-coupled. ("&" In the figure indicates a bit connector). CSRADp (p = 1 to Q is a natural number) is an address value in the control data memory 51-p as configuration designation data related to the selector / register (bus) 21 divided into Q groups. FUNCk (natural number of k = 1 to 128) indicates a state (circuit surface) for realizing a desired circuit function in the arithmetic processing unit 2.

  8B and 8C show the contents of the control data memory 51-p, CSRADp (p = 1 to Q is a natural number) is an address value in the control data memory 51-p, CSRDp is configuration data of the selector / register (bus) 21. 8B and 8C show the contents of the control data memories 51-1 and 51-Q, respectively, as an example. Here, as shown in FIGS. 8B and 8C, the control data memory 51-p does not store the same configuration data CSRDp, but stores only different ones.

  In the reconfigurable semiconductor device according to the third embodiment, the selector / register (bus) 21 in the arithmetic processing unit 2 is divided into Q groups, and the selector / register (bus) 21 includes a control data memory 51-. p (natural number from p = 1 to Q) is provided, and configuration data CSRDp of the selector / register (bus) 21 is stored. In the configuration memory 13D in the sequencer 1, the address value of the control data memory 51-p for reading the configuration data CSRDp corresponding to the state of the selector / register (bus) 21 from the control data memory 51-p is stored. Store as configuration designation data.

  When the state in the arithmetic processing unit 2 is switched, as configuration data and fixed value data CDCVDi relating to each arithmetic unit 22-i corresponding to the state and configuration specifying data relating to the selector / register (bus) 21, Address value CSRADp is read from the configuration memory 13D. The read configuration data and fixed value data CDCVDi related to each calculation unit 22-i are supplied to the corresponding calculation unit 22-i.

  The read address value CSRADp is supplied to the control data memory 51-p, and the configuration data CSRDp is read from the control data memory 51-p based on the address value CSRADp. The configuration data CSRD1 to CSRDQ read from the control data memories 51-1 to 51-Q are held in the setting information register 52. Based on the held configuration data CSRD1 to CSRDQ, the selector circuit 42 Reconfiguration is performed and the desired operation is performed.

  According to the third embodiment, the selector / register (bus) 21 in the arithmetic processing unit 2 is provided with the control data memory 51-p to store the configuration data of the selector / register (bus) 21, and the sequencer 1 In the configuration memory 13D, configuration designation data (address value) for reading configuration data from the control data memory 51-p is stored. In the control data memory 51-p, the configuration data CSRDp having the same value is not stored redundantly but only different ones are stored and selected according to the address value which is the configuration specifying data.

  As a result, the storage capacity required to store the configuration data for reconfiguring the circuit configuration can be reduced. For example, the storage capacity required for the configuration memory 13D can be reduced and the circuit scale can be reduced. . Note that the division number Q when the selector / register (bus) 21 is divided into a plurality of groups may be determined so that the storage capacity required for storing the configuration data of the selector / register (bus) 21 is reduced.

(Fourth embodiment)
Next, a fourth embodiment of the present invention will be described.
FIG. 9 is a diagram illustrating a configuration example of a reconfigurable semiconductor device according to the fourth embodiment. In FIG. 9, components having the same functions as those shown in FIGS. 1 and 7 are given the same reference numerals, and redundant descriptions are omitted.

  As shown in FIG. 9, the reconfigurable semiconductor device in the fourth embodiment includes both the reconfigurable semiconductor device in the first embodiment and the reconfigurable semiconductor device in the third embodiment. It has the characteristic configuration. That is, the reconfigurable semiconductor device according to the fourth embodiment is for control data that stores configuration data and fixed value data related to the calculation unit 22-i in each calculation unit 22-i in the calculation processing unit 2. In addition to the memory 24, the selector / register (bus) 21 includes a control data memory 51-p that stores configuration data related to the selector / register (bus) 21.

  The configuration memory 13E in the sequencer 1 stores configuration designation data (for example, control data) for designating and reading a set of configuration data and fixed value data corresponding to the state of the arithmetic unit 22-i from the control data memory 24. Address designation value CADi) of the memory 24 and configuration designation data for designating and reading configuration data corresponding to the state of the selector / register (bus) 21 from the control data memory 51-p (for example, the control data memory 51- p address value CSRADp) is stored.

  According to the fourth embodiment, the same effect as that of the first embodiment can be obtained, and the same effect as that of the third embodiment can be obtained. For storing configuration data for reconfiguring the circuit configuration. The required storage capacity can be further reduced, and the circuit scale can be reduced.

  The reconfigurable semiconductor device having the characteristic configurations of both the reconfigurable semiconductor device in the second embodiment and the reconfigurable semiconductor device in the third embodiment can be similarly configured. . Even in that case, the same effect as the second embodiment and the same effect as the third embodiment can be obtained, the storage capacity required for storing the configuration data can be reduced, and the circuit scale can be reduced. Can do.

  Further, in each of the above-described embodiments, the control data memory 24 or the first and second control data memories 31 and 32 for storing the configuration data and the fixed value data related to the calculation unit 22-i are stored in each calculation. Although provided in the unit 22-i, a plurality of arithmetic units 22-i form one group, and a control data memory for storing configuration data and fixed value data may be provided for each group. good.

In addition, each of the above-described embodiments is merely an example of implementation in carrying out the present invention, and the technical scope of the present invention should not be construed as being limited thereto. That is, the present invention can be implemented in various forms without departing from the technical idea or the main features thereof.
Various aspects of the present invention will be described below as supplementary notes.

(Supplementary note 1) According to the first configuration information output from the first control data memory, each having a first control data memory for storing the first configuration information and an arithmetic unit. A plurality of arithmetic units capable of reconfiguring the circuit configuration;
First configuration designation information for outputting first configuration information from the first control data memory is stored, and the stored first configuration designation information is stored in the first control data memory. A semiconductor device comprising a configuration memory to be supplied to the semiconductor device.
(Supplementary note 2) The semiconductor device according to Supplementary note 1, wherein the first configuration designation information is address information of the first control data memory indicating an area in which the first configuration information is stored. .
(Supplementary Note 3) The semiconductor device according to Supplementary Note 1, wherein the first configuration information stored in the first control data memory is different from each other.
(Supplementary Note 4) The first control data memory stores, together with the first configuration information, a fixed value that corresponds to the first configuration information and is used for arithmetic processing in the arithmetic unit. The semiconductor device according to appendix 1.
(Additional remark 5) The said calculating part has memory for fixed values which memorize | stores the fixed value used for the arithmetic processing in the said calculator,
The configuration memory outputs a fixed value corresponding to the first configuration information output according to the first configuration designation information from the fixed value memory to the arithmetic unit together with the first configuration designation information. 2. The semiconductor device according to appendix 1, wherein fixed value designation information for storing the information is stored.
(Supplementary note 6) The semiconductor according to supplementary note 5, wherein the fixed value designation information is address information of the fixed value memory indicating an area in which a fixed value corresponding to the first configuration information is stored. apparatus.
(Supplementary note 7) The semiconductor device according to Supplementary note 5, wherein the fixed values stored in the fixed value memory are different from each other.
(Supplementary Note 8) A second control data memory for storing second configuration information is provided, and the circuit configuration is reconfigured according to the second configuration information output from the second control data memory. A selector / register unit that controls data exchange in the arithmetic processing unit including the plurality of arithmetic units,
The configuration memory stores the second configuration designation information for outputting the second configuration information from the second control data memory together with the first configuration designation information, and stores the second configuration designation information. 2. The semiconductor device according to appendix 1, wherein the configuration specifying information 2 is supplied to the second control data memory.
(Supplementary note 9) The selector / register unit is divided into a plurality of groups, and the second control data memory for storing the second configuration information related to the group is provided for each group. The semiconductor device described.
(Supplementary note 10) The semiconductor device according to supplementary note 9, wherein the second configuration designation information is address information of the second control data memory indicating an area in which the second configuration information is stored. .
(Supplementary note 11) The semiconductor device according to supplementary note 9, wherein the second configuration information stored in the second control data memory is different from each other.
(Supplementary Note 12) The selector / register unit includes a setting information register circuit that holds second configuration information output from the second control data memory;
9. The semiconductor device according to claim 8, further comprising: a selector circuit that reconfigures a circuit configuration and controls a data path in the arithmetic processing unit according to the second configuration information held in the setting information register circuit.
(Supplementary note 13) A plurality of arithmetic units each having an arithmetic unit and capable of reconfiguring the circuit configuration according to the supplied control information;
A data memory for storing arithmetic processing data;
A selector / memory having a control data memory for storing configuration information, reconfiguring a circuit configuration in accordance with the configuration information output from the control data memory, and controlling data exchange in the arithmetic unit and the data memory A register section;
A configuration memory for storing configuration designation information for outputting the configuration information from the control data memory, and supplying the stored configuration designation information to the control data memory. Semiconductor device.
(Supplementary note 14) The semiconductor device according to supplementary note 13, wherein the selector / register unit is divided into a plurality of groups, and the control data memory for storing configuration information relating to the group is provided for each group.
(Supplementary note 15) The semiconductor device according to supplementary note 14, wherein the configuration designation information is address information of the control data memory indicating an area where the configuration information is stored. (10)
(Supplementary note 16) The semiconductor device according to supplementary note 14, wherein the configuration information stored in the control data memory is different from each other.
(Supplementary Note 17) The selector / register unit includes a setting information register circuit that holds configuration information output from the control data memory;
14. The semiconductor device according to claim 13, further comprising a selector circuit whose circuit configuration is reconfigured according to the configuration information held in the setting information register circuit.

It is a figure which shows the structural example of the reconfigurable semiconductor device in 1st Embodiment. It is a figure for demonstrating the content of the configuration memory and the memory for control data shown in FIG. It is a figure which shows the structural example of the reconfigurable semiconductor device in 2nd Embodiment. FIG. 4 is a diagram for explaining the contents of a configuration memory and a control data memory shown in FIG. 3. It is a figure which shows the structural example of the semiconductor device which can be reconfigure | reconstructed. It is a figure for demonstrating the content of the configuration memory shown in FIG. It is a figure which shows the structural example of the reconfigurable semiconductor device in 3rd Embodiment. FIG. 8 is a diagram for explaining the contents of a configuration memory and a control data memory shown in FIG. 7. It is a figure which shows the structural example of the reconfigurable semiconductor device in 4th Embodiment. It is a figure which shows the structure of the conventional reconfigurable semiconductor device. It is a figure for demonstrating the content of the configuration memory shown in FIG. It is a figure which shows the other structure of the conventional reconfigurable semiconductor device. It is a figure for demonstrating the content of the configuration memory and the memory for fixed values shown in FIG.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Sequencer 2 Arithmetic processing part 11 Status control circuit 12 Status register 13A-13G Configuration memory 21 Selector / register 22 Arithmetic part 23 Data memory 24 Control data memory 25 Register 26 Calculator unit 31, 32 Control data memory 33, 34 Register 42 Selector circuit 51 Control data memory 52 Setting information register circuit

Claims (5)

Each of the first control data memory for storing the first configuration information and an arithmetic unit is provided, and the circuit configuration is re-established according to the first configuration information output from the first control data memory. A plurality of configurable computing units;
First configuration designation information for outputting first configuration information from the first control data memory is stored, and the stored first configuration designation information is stored in the first control data memory. A semiconductor device comprising a configuration memory to be supplied to the semiconductor device.   2. The semiconductor device according to claim 1, wherein the first configuration designation information is address information of the first control data memory indicating an area in which the first configuration information is stored. A second control data memory for storing second configuration information, and reconfiguring a circuit configuration in accordance with the second configuration information output from the second control data memory to perform the plurality of operations. A selector / register unit for controlling data exchange in the arithmetic processing unit including the unit,
The configuration memory stores the second configuration designation information for outputting the second configuration information from the second control data memory together with the first configuration designation information, and stores the second configuration designation information. 3. The semiconductor device according to claim 1, wherein the configuration designation information is supplied to the second control data memory. A plurality of arithmetic units each having an arithmetic unit and capable of reconfiguring the circuit configuration according to the supplied control information;
A data memory for storing arithmetic processing data;
A selector / memory having a control data memory for storing configuration information, reconfiguring a circuit configuration in accordance with the configuration information output from the control data memory, and controlling data exchange in the arithmetic unit and the data memory A register section;
A configuration memory for storing configuration designation information for outputting the configuration information from the control data memory, and supplying the stored configuration designation information to the control data memory. Semiconductor device.   5. The semiconductor device according to claim 4, wherein the selector / register unit is divided into a plurality of groups, and the control data memory for storing configuration information relating to the group is provided for each group.

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