JP2008085617A - Image processor, image processing method, recording medium, and program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To determine whether to divide and decode a frame on the basis of the difficulty of decoding. <P>SOLUTION: In a step S1, information about the type of a stream to be decoded and a display method of the stream is acquired. In a step S2 to a step S5, it is determined whether the stream to be decoded is a stream comprising only I pictures, whether a scrub bar of an editing screen or a display scale of a time line is equal to or greater than a predetermined value, whether decoding processing for backward reproduction, high speed reproduction or scrub reproduction are performed, and whether it is predetermined reproduction processing with a low load of decoding processing, such as a triple speed for Long GOP. One between normal decoding processing and division decoding processing is performed on the basis of these determinations. The invention is applicable to an editing device. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to an image processing device, an image processing method, a recording medium, and a program, and is particularly suitable for encoding baseband video data or decoding encoded stream data. The present invention relates to an image processing apparatus, an image processing method, a recording medium, and a program.

  MPEG2 (Moving Picture Coding Experts Group / Moving Picture Experts Group 2) video is stipulated in ISO / IEC (International Standards Organization / International Electrotechnical Commission) 13818-2 and ITU-T (International Telecommunication Union-Telecommunication sector) Recommendation H.262 This is a high-efficiency encoding method for video signals.

  In MPEG, encoding efficiency is improved by obtaining a motion compensated difference between adjacent images using temporal redundancy of images. In the MPEG video decoder, for pixels using motion compensation, motion compensation is performed by adding the pixel data of the reference image indicated by the motion vector to the currently decoded pixel, and the image data before encoding is added. Decrypt.

  The MPEG-2 video stream is hierarchically configured for each layer of a sequence, GOP (group_of_picture), picture, slice, macroblock, and block.

  A GOP includes a plurality of pictures. In MPEG-2, an image is composed of three types of pictures: an I picture (intra-frame predictive encoded image), a P picture (forward predictive encoded image), and a B picture (bidirectional predictive encoded image). ing. In the I picture, all macroblocks are intra-coded (intra-frame coding). The P picture includes a macroblock on which intra coding or inter coding (forward interframe predictive coding) is performed. For B pictures, intra coding, forward interframe predictive coding, backward interframe predictive coding, or two predictions in the forward and reverse directions are rounded and averaged between corresponding pixels. Macroblocks for which interpolative interframe predictive coding is performed. Only I pictures can be decoded without other pictures. Therefore, an operation that breaks the context, such as random access, can be easily realized by accessing the I picture.

  The GOP range is from the GOP header to the next sequence header or just before the GOP header. The GOP header is inserted only immediately before the I picture on the bitstream. In general, since a B picture is decoded using bi-directional predictive coding, it is decoded with reference to I and P pictures located before and after the B picture. A GOP including a B picture that needs to refer to an I picture or a P picture included in the immediately preceding or immediately following GOP is called an Open GOP when the referenced picture exists across the GOP. When trying to decode Open GOP alone, there are B pictures that cannot be decoded.

  However, it is not always necessary to use bi-predictive coding for B pictures, and bi-directional prediction, forward prediction only, backward prediction only, and no prediction can be switched for each macroblock. Therefore, a GOP in which a B picture in a GOP can be decoded by referring to only an I picture or a P picture in the GOP is called a closed GOP. The Closed GOP can be decoded independently even if there is no GOP data before and after that.

  In addition, when a video signal compressed and encoded by an encoding method that is completed in a plurality of frames is reproduced at, for example, double speed or triple speed, it is possible to obtain a natural motion reproduction image. (For example, Patent Document 1).

Japanese Patent No. 3564745

  For example, a case where an MPEG Open GOP is to be reproduced at a double speed by applying the technique described in the above-described patent document will be described with reference to FIGS.

  FIG. 1 is a block diagram showing a configuration of a decoding device 1 that decodes an Open GOP stream by performing parallel processing using two decoding chips that can decode at 1 × speed.

  The # 1 decode chip 11-1 and the # 2 decode chip 11-2 receive an input of the encoded stream, perform a decoding process at a single speed in units of one picture, and supply decoded image data to the selector 13. The buffer 12-1 and the buffer 12-2 respectively buffer the encoded streams supplied to the # 1 decode chip 11-1 and the # 2 decode chip 11-2 and decode the P picture or the B picture. This is used to temporarily hold a decoded I picture or P picture used as a reference picture.

  The selector 13 selects and outputs the decoded image data output from the decoded image data supplied from the # 1 decode chip 11-1 or # 2 decode chip 11-2.

  In the playback apparatus 1, the # 1 decode chip 11-1 or the # 2 decode chip 11-2 is configured to successively decode 1 GOP pictures. For example, when high-speed playback is performed, GOP0 is decoded by the # 1 decode chip 11-1, GOP1 is decoded by the # 2 decode chip 11-2, GOP2 is decoded by the # 1 decode chip 11-1, and GOP3 Are decoded by the # 2 decode chip 11-2, and the subsequent GOPs are decoded alternately by any one of the decode chips in the same manner.

  A case where the decoding apparatus 1 attempts to perform a double speed decoding process will be described with reference to FIG.

  For example, when # 1 decode chip 11-1 decodes GOP1, in order to decode the first two B pictures of GOP1, it is necessary to refer to the last P picture of GOP0, and the last P picture of GOP0. In order to decode a picture, it is necessary to refer to the P picture immediately before it. After all, in order to decode the first two B pictures of GOP1, all the I and P pictures in GOP0 are decoded in advance. There is a need to.

  Similarly, when the # 2 decode chip 11-2 decodes GOP2, in order to decode the first two B pictures of GOP2, it is necessary to refer to the last P picture of GOP1, and the last of GOP1 In order to decode the P picture, it is necessary to refer to the immediately preceding P picture. After all, in order to decode the first two B pictures of GOP2, all the I pictures and P pictures of GOP1 must be It needs to be decoded.

  That is, each of the # 1 decode chip 11-1 and # 2 decode chip 11-2 needs to decode the I picture and P picture of the previous GOP prior to decoding of the assigned GOP. Therefore, when the reproduction output is to be performed at the double speed by performing the decoding process alternately by 1 GOP in the # 1 decoding chip 11-1 and the # 2 decoding chip 11-2 of the reproducing apparatus 1, each decoding chip has a decoding output. As a reference image for decoding the allocated GOP, a delay occurs at the playback start time after GOP3 by the amount of time required to decode the I picture and P picture of the previous GOP. The decoding process cannot be realized.

  That is, when trying to realize double speed reproduction using a plurality of decode chips having a single speed decoding capability, in addition to # 1 decode chip 11-1 and # 2 decode chip 11-2, as shown in FIG. Thus, it is necessary to provide a third decoding chip and perform decoding processing in parallel with three chips. With this configuration, it is possible to make up for the time required to decode the I picture and P picture of the previous GOP as a reference picture for decoding the GOP assigned to each decoding chip. Therefore, a double speed decoding process is possible.

  For example, the time required for decoding a certain GOP is T, and as shown in FIG. 4A, the time T1 required for decoding the I picture and the P picture of GOP1 as a reference picture for decoding GOP2 is T / 2. If it is shorter, as described above, double-speed decoding can be performed using three decoding chips. However, when the time T2 required for decoding the I picture and P picture of GOP1 as a reference image for decoding GOP2 is longer than T / 2, for example, when the decoding times of the pictures are not the same Even if three decoding chips are used, the double speed decoding process cannot be performed. Therefore, in order to decode such an Open GOP at double speed, it is necessary to add one more decoding chip.

  When the stream is limited to a closed GOP, as shown in FIG. 5, it is not necessary to decode the I picture and P picture of the previous GOP as a reference image, so double-speed decoding processing is possible even with two chips. Is possible. However, since whether a stream is an Open GOP or a Closed GOP is determined at the time of encoding, it cannot be handled by the playback apparatus 1 that executes the decoding process. Note that the Closed GOP is generally not used except for special cases such as an editing portion because the picture quality is inferior because the referenced picture is closed in the GOP.

  In addition, in order to decode an encoded video stream having a high frame frequency, as described above, it is necessary to use a plurality of decode chips having a 1x speed decoding capability or to increase the clock frequency.

  In video processing devices such as video servers and non-linear editing machines, a plurality of video channels are handled at a time. Such a video processing apparatus may handle a plurality of video formats such as SDTV (standard definition television video) and HDTV (high definition television video). In such a video processing apparatus, a video may be compression-encoded or a compression-encoded stream may be decoded.

  MPEG2 is a representative compression format. Even in MPEG2, the amount of encoding and decoding varies depending on the profile and level. In general, the higher the profile and the level, the larger the processing amount of encoding and decoding.

  A compression format having a LongGOP structure composed of IPB pictures has a larger decoding processing amount than a compression format composed only of I pictures. When the compression format is composed of IPB pictures, the decoding amount of an arbitrary picture is larger than the single-speed decoding processing in the time axis direction.

  As described above, some of the large processing amounts of encoding and decoding exceed the processing capability of the encoder and decoder. Even when the processing capability of the encoder or decoder is exceeded, it is necessary to use a plurality of encoders or decoders or to increase the clock frequency.

  For example, in the conventional video apparatus, the number of encoders and the number of decoders per video channel are determined in accordance with the format that handles the largest amount of processing. In conventional video equipment, multiple encoders and multiple decoders are fixedly assigned to a single video channel, so the processing capacity of encoders and decoders can be effectively utilized even in formats with a small amount of processing. I couldn't increase the video channel.

  The present invention has been made in view of such a situation, and enables encoding and decoding processing to be performed at high speed or with high performance.

  The image processing apparatus according to the first aspect of the present invention includes a second codec processing unit including a plurality of first codec processing units capable of processing one screen by dividing it, and the second codec processing. Based on the degree of difficulty of the codec processing executed by the means, the plurality of first codec processing means included in the second codec processing means respectively process different screens or divide one screen. Control means for determining whether to execute the codec in each.

  The second codec processing means may be caused to execute decoding processing, and the control means may determine whether or not the decoding processing is executed for a stream composed of only I pictures. Based on this, in the plurality of first codec processing means included in the second codec processing means, it is determined whether to process different screens or to divide one screen and execute codecs in each of them. Can be.

  The second codec processing means can be caused to execute a decoding process, and the control means determines whether the decoding process is a predetermined reproduction process with a low load of the decoding process. Further, in the plurality of first codec processing means included in the second codec processing means, it is determined whether to process different screens or to divide one screen and execute codecs in each of them. Can be.

  The second codec processing means may be caused to execute decoding processing, and the control means may be configured to execute the second processing based on whether or not the decoding processing is executed by thinning out every frame. In the plurality of first codec processing means included in the codec processing means, it is possible to determine whether to process different screens or to divide one screen and execute the codec in each of them. .

  The second codec processing means may be caused to execute decoding processing, and the control means may be configured to perform decoding processing for reverse playback, high speed playback, or scrub playback. Based on whether or not there is, the plurality of first codec processing means included in the second codec processing means respectively process different screens or divide one screen and execute codecs in each. It can be made to decide whether to make it.

  The second codec processing means may be caused to execute an encoding process, and the control means includes the second codec processing means included in the second codec processing means based on a profile and a level in the encoding process. In the plurality of first codec processing means, it is possible to determine whether to process different screens or to divide one screen and execute the codec in each of them.

  The first codec processing means of the second codec processing means includes codec execution means for executing codecs in a predetermined area of the screen, and reference pixel data obtained as a result of own processing. The pixel data necessary for the codec processing of the other first codec processing means is supplied to the other first codec processing means and obtained by the codec processing executed in the other first codec processing means. Among the reference pixel data, the pixel data necessary for its own processing can be provided with pixel data exchanging means for acquiring the pixel data from the other first codec processing means. The execution means includes pixel data obtained as a result of its own processing, and the pixel data transfer means. It may be so as to execute the codec processing by referring to the pixel data obtained from the first codec processing means.

  Memory for controlling storage of pixel data obtained as a result of codec processing executed by the codec execution unit or pixel data acquired from the other first codec processing unit by the pixel data transfer unit to the storage unit A control means may be further provided, and the codec execution means may execute codec processing by referring to pixel data whose storage in the storage unit is controlled by the storage control means. be able to.

  The pixel data necessary for the codec processing of the other first codec processing means is relative to a motion compensation reference area included in another predetermined area coded by the other first codec processing means on the screen. The pixel data may be pixel data included in a motion vector search range, and the pixel data necessary for the codec processing of the codec execution unit is included in the predetermined area that the codec execution unit codec on the screen. Pixel data included in a motion vector search range with respect to a motion compensation reference area.

  An image processing method according to an aspect of the present invention is an image processing method for executing codec using a plurality of codec processing units that can divide and process one screen, and the degree of difficulty of codec processing. And a step of determining whether the plurality of codec processing means process different screens or divide one screen and execute the codec in each screen.

  A program according to one aspect of the present invention is a program for causing a computer to execute codec processing using a plurality of codec processing units that can divide and process each screen, and the degree of difficulty of the codec processing Based on the above, the plurality of codec processing means cause the computer to execute a process including a step of determining whether to process different screens or to divide one screen and execute the codec in each of them.

  In the first aspect of the present invention, based on the difficulty level of the codec processing, a plurality of codec processing means that can divide the screen and process each of them, each processing a different screen, or one screen It is determined whether or not the codec is executed in each of them.

  The network is a mechanism in which at least two devices are connected and information can be transmitted from one device to another device. The devices that communicate via the network may be independent devices, or may be internal blocks that constitute one device.

  The communication is not only wireless communication and wired communication, but also communication in which wireless communication and wired communication are mixed, that is, wireless communication is performed in a certain section and wired communication is performed in another section. May be. Further, communication from one device to another device may be performed by wired communication, and communication from another device to one device may be performed by wireless communication.

  The image processing apparatus may be an independent apparatus, or may be a block that performs image processing among other apparatuses.

  The image processing device may be an independent device as a decoding processing device, or may be a block that performs decoding processing among other devices.

  Further, the image processing apparatus may be an independent apparatus as an encoding processing apparatus, or may be a block that performs an encoding process among other apparatuses.

  As described above, according to the first aspect of the present invention, it is possible to execute a codec, and in particular, based on the difficulty level of the codec process, a plurality of codecs that can divide the screen and process each of them. In the processing means, it is possible to determine whether to process different screens or to divide one screen and execute codecs in each, so that encoding and decoding processing can be performed at high speed or high performance. Can be done.

  Embodiments of the present invention will be described below. Correspondences between constituent elements of the present invention and the embodiments described in the specification or the drawings are exemplified as follows. This description is intended to confirm that the embodiments supporting the present invention are described in the specification or the drawings. Therefore, even if there is an embodiment which is described in the specification or the drawings but is not described here as an embodiment corresponding to the constituent elements of the present invention, that is not the case. It does not mean that the form does not correspond to the constituent requirements. Conversely, even if an embodiment is described here as corresponding to a configuration requirement, that means that the embodiment does not correspond to a configuration requirement other than the configuration requirement. It's not something to do.

  The image processing apparatus according to the first aspect of the present invention has a plurality of first codec processing means (for example, # 1 decode chip 73 and # 2 decode shown in FIG. 8) that can divide one screen and process each screen. The second codec processing means (for example, the decoding processing unit 51 in FIG. 8 or the encoding processing unit 52 in FIG. 24) including the chip 76 or the # 1 encoding chip 173 and # 2 encoding chip 176 in FIG. And whether the plurality of first codec processing units included in the second codec processing unit process different screens based on the degree of difficulty of the codec processing executed by the second codec processing unit. Or a control means (for example, CP in FIG. 6) that determines whether to divide one screen and execute codec in each of them. Comprises 40 or control unit 61 in FIG. 7) and.

  The second codec processing means can execute a decoding process, and the control means determines whether or not the decoding process is executed for a stream composed only of I pictures (for example, FIG. 17). Based on the determination in step S2, the plurality of first codec processing units included in the second codec processing unit respectively process different screens, or divide one screen and perform codecs in each. You can decide what to do.

  The second codec processing means can execute a decoding process, and the control means can perform a predetermined playback process with a low load of the decoding process (for example, triple-speed playback for a LongGOP with M = 3). ) (For example, determination in step S5 in FIG. 17), the plurality of first codec processing units included in the second codec processing unit may process different screens, respectively. Alternatively, it is possible to determine whether to divide one screen and execute the codec in each.

  The second codec processing means can execute a decoding process, and the control means determines whether or not the decoding process is executed by thinning out every frame (for example, in step S3 in FIG. 17). Based on whether the scale of the timeline is large), the plurality of first codec processing means included in the second codec processing means each process different screens or divide one screen. Each of them can decide whether to execute the codec.

  The second codec processing means can execute a decoding process, and the control means determines whether the decoding process is a decoding process for backward reproduction, high-speed reproduction, or scrub reproduction ( For example, based on the determination in step S4 of FIG. 17, each of the plurality of first codec processing units included in the second codec processing unit may process different screens or divide one screen. Each of them can decide whether to execute the codec.

  The second codec processing means is capable of executing an encoding process, and the control means is based on the profile and level in the encoding process (for example, the determination in step S102 of FIG. 25), In the plurality of first codec processing means included in the processing means, it is possible to determine whether to process different screens or to divide one screen and execute codecs in each of them.

  The first codec processing means of the second codec processing means is a codec execution means (for example, the decoder 93 or the decoder 113 in FIG. 8 or the encoder 193 in FIG. 24) for executing a codec in a predetermined area of the screen. Alternatively, the encoder 213) and the pixel data necessary for the codec processing of the other first codec processing unit among the reference pixel data obtained as a result of the processing of itself are used as the other first codec processing unit. Among the reference pixel data obtained by the codec processing executed in the other first codec processing means, the pixel data necessary for its own processing is supplied to the other first codec. Pixel data exchange means acquired from the processing means (for example, the inter-chip interface in FIG. 8) 96 or 116, or the inter-chip interface 196 or 216) of FIG. 24, and the codec execution means is provided by the pixel data obtained as a result of its own processing and by the pixel data transfer means. The codec processing can be executed by referring to the pixel data acquired from the first codec processing means.

  Memory for controlling storage of pixel data obtained as a result of codec processing executed by the codec execution unit or pixel data acquired from the other first codec processing unit by the pixel data transfer unit to the storage unit Control means (for example, the 0 buffer 75 or 78 shown in FIG. 8 or the stream / reference image buffer 175 or 178 shown in FIG. 24) can be further provided, and the codec execution means can store the memory by the storage control means. The codec processing can be executed by referring to the pixel data whose storage in the unit is controlled.

  The pixel data necessary for the codec processing of the other first codec processing means is relative to a motion compensation reference area included in another predetermined area coded by the other first codec processing means on the screen. The pixel data may be pixel data included in a motion vector search range, and the pixel data necessary for the codec processing of the codec execution unit is included in the predetermined area that the codec execution unit codec on the screen. Pixel data included in a motion vector search range with respect to a motion compensation reference area.

  An information processing method according to one aspect of the present invention includes a plurality of codec processing units (for example, # 1 decode chip 73 and # 2 decode chip 76 in FIG. 24. An image processing method for executing codec using the # 1 encode chip 173 and the # 2 encode chip 176) of FIG. 24, wherein each of the plurality of codec processing means has different screens based on the difficulty level of the codec process. Or whether to divide one screen and execute codecs in each of them (for example, the processing in steps S2 to S7 in FIG. 17 or the processing in steps S102 to S104 in FIG. 25). Includes steps.

  The program according to one aspect of the present invention includes a plurality of codec processing units (for example, # 1 decode chip 73 and # 2 decode chip 76 in FIG. 8 or FIG. The codec processing using the # 1 encoding chip 173 and the # 2 encoding chip 176) is executed by a computer, and each of the plurality of codec processing means has different screens based on the degree of difficulty of the codec processing. Or whether to divide one screen and execute codecs in each of them (for example, the processing in steps S2 to S7 in FIG. 17 or the processing in steps S102 to S104 in FIG. 25). Cause a computer to execute a process including steps

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 6 is a block diagram showing a hardware configuration of the editing apparatus 21 to which the present invention is applied.

  A CPU (Central Processing Unit) 31 is connected to the north bridge 32 and controls processing such as reading of data stored in an HDD (Hard disk Drive) 36, and controls editing processing executed by the CPU 40, for example. Control signals and commands are generated and output. Further, the CPU 31 can provide a GUI (Graphical User Interface) for prompting the user to input an operation, and can control display of a screen for displaying and outputting the processing result. A user's operation input referring to the displayed image is received, and a command for controlling the encoding or decoding process is generated based on the user's operation input.

  The north bridge 32 is connected to a PCI bus (Peripheral Component Interconnect / Interface) 34. For example, the north bridge 32 receives data stored in the HDD 36 via the south bridge 35 based on the control of the CPU 31, and receives the PCI bus. 34, and supplied to the memory 38 via the PCI bridge 37. The north bridge 32 is also connected to the memory 33, and exchanges data necessary for the processing of the CPU 31.

  The memory 33 stores data necessary for processing executed by the CPU 31. The south bridge 35 controls writing and reading of data in the HDD 36. The HDD 36 stores an uncompressed baseband signal or encoded data.

  The PCI bridge 37 controls the writing and reading of data in the memory 38, the supply of the encoded stream to the decoder unit 42, or the supply of uncompressed data to the selector 43, and the PCI bus 34 and the control. Controls the transmission and reception of data on the bus 39. The memory 38 stores the baseband signal or encoded data read by the HDD 36 and the processed encoded data supplied from the encoder unit 44 based on the control of the PCI bridge 37.

  The CPU 40 includes a PCI bridge 37, a decoder unit 42, a selector 43, and an encoder according to control signals and commands supplied from the CPU 31 via the north bridge 32, the PCI bus 34, the PCI bridge 37, and the control bus 39. The processing executed by the unit 44 is controlled. The memory 41 stores data necessary for the processing of the CPU 40.

  The decoder unit 42 includes m decoding processing units 51-1 to 51-m, decodes the encoded stream supplied from the PCI bridge 37 based on the control of the CPU 40, and selects the selector 43. To supply. Each of the decoding processing units 51-1 to 51-m included in the decoder unit 42 includes two decoders and can be operated in parallel.

  Each of the decoding processing units 51-1 to 51-m can also decode different streams with two decoders under the control of the CPU 40, or divide each frame of one stream into two It is also possible to perform decoding in cooperation with a decoder.

  Hereinafter, the m decoding processing units are respectively referred to as # 0 decoding processing unit 51-1, # 1 decoding processing unit 51-2, # 2 decoding processing unit 51-3,... # M-1 decoding processing unit 51. When it is not necessary to individually distinguish the # 0 decoding processing unit 51-1 to the # m-1 decoding processing unit 51-m, they are simply referred to as the decoding processing unit 51. The detailed configuration of the decoding processing unit 51 will be described later with reference to FIG.

  The selector 43 supplies the uncompressed baseband signal supplied from the PCI bridge 37 or the decoder unit 42 to any one of the encoding processing units 52-1 to 52-n of the encoder unit 44, or the decoder unit The uncompressed baseband signal supplied from 42 is supplied to the PCI bridge 37.

  The encoder unit 44 includes n encoding processing units of the encoding processing units 52-1 to 52-n, and encodes an uncompressed baseband signal supplied from the selector 43 under the control of the CPU 40. And output to the PCI bridge 37. Each of the encoding processing units 52-1 to 52-n included in the encoder unit 44 includes two encoders and can operate in parallel.

  The encoding processing units 52-1 to 52-n can encode different video data with two encoders based on the control of the CPU 40, and divide each image data of one video data. Thus, it is possible to perform the encoding in cooperation with the two encoders.

  In the following, n encoders are converted into # 0 encoding processing unit 52-1, # 1 encoding processing unit 52-2, # 2 encoding processing unit 52-3,... # N-1 encoding processing, respectively. When it is not necessary to individually distinguish the # 0 encoding processing unit 52-1 to # n-1 encoding processing unit 52-n, they are simply referred to as the encoding processing unit 52. A detailed configuration of the encoding processing unit 52 will be described later with reference to FIG.

  Next, the operation of the editing device 21 will be described.

  The HDD 36 stores an encoded stream compressed by the Long GOP Open GOP method or all of which are intra-frame encoded (intra compressed), and an uncompressed baseband signal. The CPU 31 receives a user operation input from an operation input unit (not shown), determines data for executing the decoding process based on the user operation input, determines data for executing the encoding process, and after decoding, Determine the data to be re-encoded.

  The CPU 31 supplies an encoded stream or baseband signal to be processed to the PCI bridge 37 via the north bridge 32 and the PCI bus 34 and generates a command. If there is a parameter necessary for decoding or encoding, the CPU 31 sends the generated command together with the parameter to the CPU 40 via the north bridge 32, the PCI bus 34, the PCI bridge 37, and the control bus 39. Supply.

  The CPU 40 controls the PCI bridge 37 to store the supplied encoded stream or baseband signal in the memory 38, and based on the supplied command, the supplied data is an encoded stream that needs to be decoded. In some cases, the PCI bridge 37 is controlled to supply the encoded stream to the decoder unit 42, and when the supplied data is a baseband signal that is unnecessary for decoding, the PCI bridge 37 is controlled to control the baseband signal. Is supplied to the selector 43.

  All or part of the decoding processing units 51-1 to 51-m included in the decoder unit 42 can operate in parallel. The CPU 40 controls the decoder unit 42 to execute the decoding process, and supplies the uncompressed baseband signal generated by decoding to the selector 43. For example, the CPU 40 determines whether all streams to be decoded are I pictures, Long GOPs including I, B, and P pictures, or whether special reproduction such as fast forward, rewind, and scrub reproduction is executed. Based on the degree of difficulty of the decoding process, such as the above, each of the decoding processing units 51-1 to 51-m decodes different streams with two decoders or divides each frame of one stream to 2 A control signal for controlling whether or not the two decoders perform cooperative decoding is generated and supplied to the corresponding ones of the decoding processing units 51-1 to 51-m included in the decoder unit 42.

  The decoding processing units 51-1 to 51-m constituting the decoder unit 42 decode the supplied data based on the control of the CPU 40 and supply an uncompressed baseband signal to the selector 43. Each of the decoding processing units 51-1 to 51-m can also decode different streams with two decoders under the control of the CPU 40, or divide each frame of one stream into two It is also possible to perform decoding in cooperation with a decoder.

  The CPU 40 controls the selector 43 based on the command supplied from the CPU 31 and supplies the baseband signal supplied to the selector 43 to the memory 38 via the PCI bridge 37 or the encoder unit 44. The data is supplied to the encoding processing unit 52. Based on the control of the CPU 40, the selector 43 supplies the supplied baseband signal to the memory 38 via the PCI bridge 37 or supplies it to the encoding processing unit 52.

  The CPU 40 controls the encoder unit 44 based on the command supplied from the CPU 31 to supply the encoded stream generated by encoding to the PCI bridge 37. All or part of the encoding processing units 52-1 to 52-n included in the encoder unit 44 can operate in parallel. The CPU 40 encodes different video data with two encoders based on the encoding difficulty level such as an encoding profile level, or divides each image data of one video data and cooperates with the two encoders. A control signal for controlling whether to encode is generated and supplied to the corresponding one of the encoding processing units 52-1 to 52-n included in the encoder unit 44.

  Of the encoding processing units 52-1 to 52-n constituting the encoder unit 44, the encoding processing unit 52 that has received the supply of the baseband signal encodes the supplied data under the control of the CPU 40. Based on the control of the CPU 40, the encoding processing unit 52 can encode different streams with two encoders, or divides each frame of one stream and cooperates with the two encoders. It is also possible to encode.

  The CPU 40 controls the PCI bridge 37 based on the command supplied from the CPU 31 and stores the encoded stream supplied from the encoding processing unit 52 in the memory 38.

  The CPU 40 notifies the CPU 31 through the control bus 39, the PCI bridge 37, the PCI bus 34, and the north bridge 32 that the data codec processing based on the supplied command processing has been completed. The CPU 31 reads the data after the codec from the memory 38 via the north bridge 32, the PCI bus 34, and the PCI bridge 37, and stores it in the HDD 36 via the north bridge 32 and the south bridge 35. To output to an external device.

  Next, FIG. 7 is a functional block diagram for explaining a configuration of main functions of the editing device 21 of FIG. In FIG. 7, parts corresponding to those in FIG. 6 are denoted by the same reference numerals, and description thereof is omitted as appropriate.

  The editing device 21 includes a control unit 61, an acquisition unit 62, a decoder unit 42, a selector 43, an encoder unit 44, and a storage / output unit 63.

  The control unit 61 corresponds to the CPU 31 and the CPU 40 and controls each unit of the editing device 21. The acquisition unit 62 acquires data to be processed from the HDD 36 or the memory 38 based on the control of the control unit 61, supplies a portion that requires decoding processing to the decoder unit 42, and stores a portion that requires encoding processing. , Supplied to the selector 43. The acquisition unit 62 may include an HDD 36 or a memory 38 in which a compressed encoded stream or an uncompressed baseband signal is stored, or may be connected to the HDD 36 or the memory 38 or the editing device 21. The acquisition unit 62 may include a PCI bridge 37 that acquires a compression-coded stream or an uncompressed baseband signal from the above device.

  The plurality of decoding processing units 51 included in the decoder unit 42 decode the compressed material video data supplied from the obtaining unit 62, and supply the uncompressed baseband signal obtained as a result to the selector 43. The selector 43 supplies the uncompressed baseband signal supplied from the decoder unit 42 or the acquisition unit 62 to the encoder unit 44 or the storage / output unit 63 based on the control of the control unit 61.

  The plurality of encoding processing units 52 included in the encoder unit 44 encode the uncompressed baseband signal supplied from the selector 43 based on the control of the control unit 61.

  The storage / output unit 63 stores or outputs the ratio-compressed baseband signal decoded and generated in the decoder unit 42 or the encoded stream generated by encoding in the encoder unit 44. The HDD 36 or the memory 38 may be included in the storage / output unit 63, or the PCI bridge 37 that outputs the compression encoded stream to the HDD 36 or the memory 38 or another device connected to the editing device 21. , May be included in the acquisition unit 62.

  FIG. 8 is a block diagram illustrating a configuration of the decoding processing unit 51. Here, description will be made assuming that the decoding processing unit 51 is supplied with an encoded stream encoded by the MPEG2 system, and can decode and output the encoded stream.

  The decoding processing unit 51 includes a controller 71, an input signal selection unit 72, a # 1 decoding chip 73, a stream buffer 74, a video buffer 75, a # 2 decoding chip 76, a stream buffer 77, a video buffer 78, a composition processing unit 79, and The output signal selection unit 80 is configured. The decoding processing unit 51 may be provided with three or more decoding chips, but here, it is assumed that two decoding chips, # 1 decoding chip 73 and # 2 decoding chip 76, are provided. .

  The controller 71 controls the operation of the decoding processing unit 51 on the basis of a user operation input or a control signal supplied from an external device.

  That is, based on the control of the CPU 40, the controller 71 uses the # 1 decode chip 73 and the # 2 decode chip 76 to divide one frame into two parts and perform the decoding process when the decoding process is difficult. If the difficulty level of the decoding process is relatively low, the # 1 decode chip 73 and the # 2 decode chip 76 decode different streams respectively. can do.

  Decoding processing difficulty level is, for example, whether all streams to be decoded are I pictures, Long GOPs consisting of I, B, P pictures, or special playback such as fast forward, rewind, scrub playback, etc. It depends on whether or not it is performed or the condition of special reproduction.

  As described above, the editing apparatus 21 can provide a GUI (Graphical User Interface) for prompting the user to input an operation, and can control display of a screen for displaying and outputting the processing result. For example, the display of the edit screen as shown in FIG. 9 is controlled so that an operation input from the user referring to the edit screen can be received.

  The edit screen 131 shown in FIG. 9 is displayed on a display device or display unit (not shown) based on the control of the CPU 31. For example, a desired edit point is detected by randomly reproducing a plurality of stream data. Then, various GUIs are provided for executing an editing process such as connecting different stream data at a desired editing point.

  For example, the stream data selected by the user is displayed in the playback window 141 after being decoded (decoded) in any of the decoding processing units 51-1 to 51-m of the decoder unit 42.

  The playback position of the stream data is set by moving the position of the pointer 152 of the scrub bar 151 provided at the lower part of the playback window 141 based on the user's operation input. Also, the timeline window 142 is provided with a timeline 153 that can notify the user of the playback position on the time axis in the video stream or audio stream, for example, and allow the user to instruct the playback position. The playback position can be changed (scrubbing playback can be performed) by moving the position of the pointer 152 of the timeline 153 based on the user's operation input.

  The user who has referred to the editing screen 131 described with reference to FIG. 9 inputs selection of a decoding target stream and designation of a reproduction start position, that is, an operation of the pointer 152 of the scrub bar 151 or the pointer 152 of the timeline 153. Is done. Displaying a video at an arbitrary position by such an operation input is called scrub playback. The CPU 31 obtains the stream number of the stream to be reproduced and the frame number of the reproduction start position based on the user's operation input, and along with instructions such as the reproduction speed, the north bridge 32, the PCI bus 34, the PCI bridge 37, Then, the data is supplied to the CPU 20 via the control bus 39.

  In the scrub operation, an immediate response such as within 200 milliseconds is required from the movement of the slider to the display of the video. The video display in a short time determines the operational comfort of the scrub operation, and higher speed decoding processing is required during scrubbing. In the case of a stream composed of IPB pictures, it is necessary to decode all related pictures in order to display a video at an arbitrary position. Accordingly, when scrub playback is performed, since the amount of decoding processing is large, two decoders are allocated to one channel, and the screen is divided and decoded to shorten the time until video display. The

  Also, for example, when the display scale of the scrub bar 151 or the timeline 153 is larger than a certain value, even if the stream decoded for playback is LongGOP, even if scrub playback is executed, for example, There are cases where intermittent display of only I pictures or only I and P pictures is performed.

  In such a case, since the difficulty level of the decoding process is low, it is preferable that the # 1 decode chip 73 and the # 2 decode chip 76 decode different streams.

  In addition, playback modes include, for example, normal playback from a predetermined playback position, fast forward, fast rewind, forward / reverse frame advance, still image display, etc. Each frame interval can be set individually.

  Since the difficulty level of the decoding process is different depending on these playback modes, the decoding processing unit 51 uses the # 1 decoding chip 73 and the # 2 decoding chip 76 when the difficulty level of the decoding process is high. When the frame is divided into two parts to perform decoding processing, and the generated divided images are combined and output. When the difficulty of decoding processing is relatively low, the # 1 decoding chip 73 and # 2 decoding The chip 76 can decode different streams. Using the # 1 decode chip 73 and the # 2 decode chip 76 to divide one frame into two parts and perform the respective decoding processes will be referred to as divided decoding processes.

  For example, non-linear editing machines display icons corresponding to multiple video tracks on the timeline screen so that they can receive editing commands, so they can process a larger number of video tracks. Is required. As described above, the number of chips used for decoding one stream can be changed depending on the difficulty level of the decoding process. For example, even when an inexpensive decoding chip is used, the scrub process is performed. In the case of normal reproduction or the like, the number of video tracks can be increased without causing the processing to be in time.

  Even in normal playback other than scrubbing, if the request for the number of video tracks on the timeline is less than the number of channels when two decoders are assigned to one channel, two decoders are assigned to one channel. It is preferable to leave it as it is. Thereby, it is possible to reduce the overhead time required for switching the decoder.

  Based on the control of the controller 71, the input signal selection unit 72 supplies a stream different from the stream supplied to the # 1 decode chip 73 to the # 2 decode chip 76 when the divided decode process is not executed. Is executed, the same stream as that supplied to the # 1 decode chip 73 is supplied and supplied to the # 2 decode chip 76.

  When executing the divided decoding process, the # 1 decode chip 73 and the # 2 decode chip 76 each recognizes a portion of the supplied picture that is decoded by itself and executes the decode process.

  For example, as shown in FIG. 10A, each picture included in the input stream is divided into the number of decoding chips (two in this case) in units of slices. 10, each picture included in the input stream is vertically divided into the number of decoding chips (two in this case) as shown in B, or included in the input stream as shown in C in FIG. 10. Each picture to be decoded is divided into the number of decoding chips diagonally (in this case, two) (however, when the decoding method is MPEG2 or the like, for example, vertical or diagonal division is divided into slice units). It may be difficult to compare).

  In the MPEG2 video stream, it is specified that each slice is a series of macroblocks located in the same horizontal row, and the vertical position for each slice is indicated in slice_start_code. Therefore, for example, when the # 1 decode chip 73 and the # 2 decode chip 76 divide one picture into the number of decode chips in units of slices, each frame is divided based on the slice start code. , Can recognize the area to be decoded by itself.

  Here, it has been described that the # 1 decode chip 73 and the # 2 decode chip 76 each recognizes a portion of the supplied picture that is decoded by itself and executes the decoding process. Each frame of the stream thus generated may be divided in advance as described with reference to FIG. 10 and supplied to the # 1 decode chip 73 and the # 2 decode chip 76.

  Note that each of the pictures included in the input stream may be divided more than the number of decode chips, and divided into the number of decode chips provided with the plurality of divided pictures. As shown in FIG. 10, dividing each of the pictures included in the input stream into the decoding units in which the number of decoding chips is integrated (not separated) is different from the area decoded in each decoding chip. Since the ratio of the image area to be referred to in the decoding of the decoding chip is reduced, it is preferable that the process of exchanging between the decoding chips of the pixels of the reference portion described later is not complicated.

  Note that the method of dividing the picture may be equal division or unequal division. For example, when the controller 71 is provided with a function for detecting the complexity of the image and the division decoding process is executed, and the complexity of the image varies significantly depending on the picture portion, the complexity of the image (code The division width of the picture (a and b in the drawing in FIG. 10) may be determined based on the conversion difficulty level.

  The # 1 decode chip 73 includes a stream input circuit 91, a buffer control circuit 92, a decoder 93, a motion compensation circuit 94, a buffer control circuit 95, an inter-chip interface (I / F) 96, and an output circuit 97. Based on the control of 71, the entire supplied picture or a predetermined part is decoded. When the division decoding process is executed, the # 1 decode chip 73 supplies pixel data of an area that may be required as a reference image for the decode process of the # 2 decode chip 76 to the # 2 decode chip 76, The decoded pixel data supplied from the # 2 decode chip 76 is supplied to and stored in the video buffer 75, and the decoding process is executed by referring to it as necessary.

  The stream buffer 74 is composed of, for example, a DRAM (Dynamic Random Access Memory) or the like, and temporarily stores the encoded stream supplied to the # 1 decode chip 73. The video buffer 75 is constituted by, for example, a DRAM or the like, and supplies a video signal (pixel data) decoded by the # 1 decode chip 73 and a decoded video signal (pixel data) supplied from the # 2 decode chip 76. And store it temporarily.

  The # 2 decode chip 76 includes a stream input circuit 111, a buffer control circuit 112, a decoder 113, a motion compensation circuit 114, a buffer control circuit 115, an inter-chip interface (I / F) 116, and an output circuit 117. Based on the control of 71, the entire supplied picture or a predetermined part is decoded. When the divided decoding process is executed, the # 2 decode chip 76 supplies pixel data of an area necessary as a reference image for the decode process of the # 1 decode chip 73 to the # 1 decode chip 73 and also the # 1 decode chip The decoded pixel data supplied from 73 is supplied to and stored in the video buffer 78, and the decoding process is executed by referring to it as necessary.

  The stream buffer 77 is constituted by, for example, a DRAM or the like, and temporarily stores the encoded stream supplied to the # 2 decode chip 76. The video buffer 78 is constituted by, for example, a DRAM or the like, and supplies a video signal (pixel data) decoded by the # 2 decode chip 76 and a decoded video signal (pixel data) supplied from the # 1 decode chip 73. And store it temporarily.

  When the division decoding process is executed, the synthesis processing unit 79 receives the decoded pixel data from the # 1 decode chip 73 and the # 2 decode chip 76, synthesizes them, and supplies them to the output signal selection unit 80. The output signal selection unit 80 selects the output of the # 1 decode chip 73 when the division decoding process is not executed. When the division decoding process is executed, the output signal selection unit 80 selects the output of the synthesis processing unit 79 as decoded video data. Output.

  When the division decoding process is not executed, the output from the # 2 decode chip 76 is output as it is. When the division decoding process is executed, the output from the # 2 decode chip 76 is supplied to the synthesis processing unit 79. Is not output.

  Next, the configuration and operation of the # 1 decode chip 73 will be described.

  The stream input circuit 91 supplies the supplied encoded stream to the buffer control circuit 92 when the division decoding process is not executed. The buffer control circuit 92 inputs the input encoded stream to the stream buffer 74 in accordance with a basic clock supplied from a clock generation circuit (not shown). Also, the encoded stream stored in the stream buffer 74 is read and output to the decoder 93.

  The decoder 93 decodes the input stream based on the MPEG syntax and supplies the decoded stream to the motion compensation circuit 94. Specifically, the decoder 93 decodes the macroblock by separating the slice layer into macroblocks, and outputs the prediction vector and the pixels obtained as a result to the motion compensation circuit 94.

  The motion compensation circuit 94 decodes reference pixels decoded from the video buffer 75 via the buffer control circuit 95 as necessary based on whether or not the macroblock output from the decoder 93 uses motion compensation. Data is read to perform motion compensation, and pixel data is supplied to the buffer control circuit 95.

  Specifically, when the macroblock output from the decoder 93 does not use motion compensation, the motion compensation circuit 94 writes the pixel data to the video buffer 75 via the buffer control circuit 95, and displays it. In addition, the pixel data is prepared when it is used as reference data for another image.

  When the macroblock output from the decoder 93 uses motion compensation, the motion compensation circuit 94 receives reference pixel data from the video buffer 75 via the buffer control circuit 95 according to the prediction vector output from the decoder 93. read out. Then, the motion compensation circuit 94 adds the read reference pixel data to the pixel data supplied from the decoder 93 to perform motion compensation. The motion compensation circuit 94 writes the pixel data subjected to motion compensation to the video buffer 75 via the buffer control circuit 95 to prepare for display output, and also prepares when this pixel data is used as reference data.

  The buffer control circuit 95 inputs the pixel data input from the motion compensation circuit 94 to the video buffer 75 in accordance with a basic clock supplied from a clock generation circuit (not shown).

  When the divided decoding process is executed, the stream input circuit 91 recognizes an area for performing the decoding process in the supplied encoded stream, and supplies the area to the buffer control circuit 92. The buffer control circuit 92 inputs a part of the frame of the input encoded stream to the stream buffer 74 in accordance with a basic clock supplied from a clock generation circuit (not shown). In addition, a part of the frame of the encoded stream stored in the stream buffer 74 is read and output to the decoder 93. Note that the buffer control circuit 92 may read the encoded stream in units of slices in order from the data previously written in the stream buffer 74, and output the encoded stream to the decoder 93. In order, the encoded stream may be read out in units of slices and output to the decoder 93.

  The decoder 93 decodes the input stream based on the MPEG syntax and supplies the decoded stream to the motion compensation circuit 94. Specifically, the decoder 93 decodes the macroblock by separating the slice layer into macroblocks, and outputs the prediction vector and the pixels obtained as a result to the motion compensation circuit 94.

  The motion compensation circuit 94 decodes reference pixels decoded from the video buffer 75 via the buffer control circuit 95 as necessary based on whether or not the macroblock output from the decoder 93 uses motion compensation. Data is read, motion compensation is performed in the same manner as described above, and pixel data is supplied to the buffer control circuit 95.

  When the macroblock output from the decoder 93 uses motion compensation, the motion compensation circuit 94 receives reference pixel data from the video buffer 75 via the buffer control circuit 95 according to the prediction vector output from the decoder 93. read out. Then, the motion compensation circuit 94 adds the read reference pixel data to the pixel data supplied from the decoder 93 to perform motion compensation. The motion compensation circuit 94 writes the pixel data subjected to motion compensation to the video buffer 75 via the buffer control circuit 95 to prepare for display output, and also prepares when this pixel data is used as reference data. The buffer control circuit 95 inputs the pixel data input from the motion compensation circuit 94 to the video buffer 75 in accordance with a basic clock supplied from a clock generation circuit (not shown).

  The buffer control circuit 95 also inputs pixel data supplied from the # 2 decode chip 76 to the video buffer 75 via the interchip interface 96. The buffer control circuit 95 also reads the reference pixel data designated from the motion compensation circuit 94 from the pixel data stored in the video buffer 75 and supplies it to the motion compensation circuit 94. The buffer control circuit 95 also reads out pixel data stored in the video buffer 75 and supplies it to the output circuit 97. Also, the buffer control circuit 95 reads out pixel data of an area (motion vector search range) used as a reference pixel for decoding processing of the # 2 decoding chip 76 from the pixel data stored in the video buffer 75, The data is supplied to the # 2 decode chip 76 via the inter-interface 96.

  The output circuit 97 generates a synchronization timing signal for outputting the decoded pixel data, reads out the pixel data from the video buffer 75 via the buffer control circuit 95 based on this timing, and outputs it as decoded video data. .

  The functions of the stream input circuit 111 to the output circuit 117 of the # 2 decode chip 76 are basically the same as those of the stream input circuit 91 to the output circuit 97 of the # 1 decode chip 73. Since it is basically the same as the # 1 decode chip 73, detailed description thereof is omitted.

  Data exchange between the inter-chip interface 96 of the # 1 decode chip 73 and the inter-chip interface 116 of the # 2 decode chip 76 supplies data from the inter-chip interface 96 to the inter-chip interface 116, such as a data bus. And an interface such as a data bus for supplying data from the inter-chip interface 116 to the inter-chip interface 96 are independent interfaces (dedicated lines) so that they are not used for transmission / reception of other data. It is preferable that

  An interface that connects the decoding chips, that is, an interface that supplies data from the interchip interface 96 to the interchip interface 116 and an interface that supplies data from the interchip interface 116 to the interchip interface 96 are independent of each other. In the case where the interface such as the data bus is not shared, the pixel data read from the video buffer 75 by the buffer control circuit 95 is data in the reverse direction (that is, from the inter-chip interface 116 to the inter-chip interface 96). The pixel data that can be transmitted from the inter-chip interface 96 to the inter-chip interface 116 regardless of the supply of the data and read from the video buffer 78 by the buffer control circuit 115 is in the reverse direction. KazuSatoshi, despite the inter-chip interface 96 to the supply of) data to the inter-chip interface 116 can be sent from the inter-chip interface 116 to the inter-chip interface 96. In other words, such a configuration does not require complicated address control accompanying data exchange or timing of data bus occupancy or data exchange timing, and the data transfer speed is also limited to an interface such as a data bus. It is possible to reduce the speed as compared with the case of sharing.

  Specifically, when an interface such as a data bus is shared, not only a waiting time is required when the interface is used to exchange other data, but the data is sent to another decoding chip. Before, send and receive control signals for address control, timing to occupy the data bus, control of data transfer timing, etc. between decode chips, and make various settings for data transfer based on the transferred control signals Since this must be done, time is required for these processes. On the other hand, if the interface such as the data bus is not shared, there is no waiting time for sending / receiving other data, and no processing before sending data is required. Can be transmitted to other decoding chips at the same time, compared to the case where an interface such as a data bus is shared, etc., and the data transfer rate can be reduced.

  The interface connecting the inter-chip interface 96 and the inter-chip interface 116 is, for example, by pattern-connecting the input / output terminals of each chip on the substrate on which the # 1 decode chip 73 and the # 2 decode chip 76 are mounted. Therefore, even if each pattern is prepared independently, the hardware mounting cost required for this is very low.

  Next, transmission / reception of decoded pixel data between the # 1 decode chip 73 and the # 2 decode chip 76 when the division decoding process is executed will be described with reference to FIGS. 11 to 14.

  For example, each frame of the supplied encoded stream is divided into two on the basis of a slice, and is recognized as a decoding processing range in each of the # 1 decode chip 73 and the # 2 decode chip 76. At this time, if the frame is divided into two continuous regions without subdividing the frame, the # 2 decode chip 76 out of the pixel regions required as reference pixels when decoding the P picture or B picture. This is preferable because the area portion of the pixel to be decoded is reduced.

  Of the compressed and encoded stream data (encoded stream) supplied to the decoding processing unit 51, the I picture is intra-frame encoded (without a reference image), and the P picture or B picture is Based on the position of the corresponding macroblock of the reference image (when encoding a P picture, it is the immediately preceding I picture or P picture, and when encoding a B picture, it is the preceding or following I picture or P picture) A reference block that minimizes an error from the macroblock is searched within a predetermined area, a motion vector that is a difference between the position of the original macroblock and the reference macroblock is obtained, and an image is represented by the motion vector and the difference. ing.

  In an encoding process using MPEG, a rectangular block of 16 × 16 pixel units is generally used as a macroblock. Note that the decoding processing unit 51 to which the present invention is applied may be able to perform decoding processing of an encoded stream to which inter-frame prediction other than MPEG is applied, and the size of the motion compensation reference region is limited to this. is not. The reference area for motion compensation can be selected from 16 × 16, 16 × 8, 8 × 16, 8 × 8, 8 × 4, 4 × 8, 4 × 4, for example, H.264 You may make it do. In addition, the motion compensation reference area may be other than the block unit. In addition, since the size of the reference image data (reference image) of the macroblock is a half-pixel level motion vector, for example, 16 × 16, 17 × 16, 16 × 17, 17 × 17, 16 × It takes multiple values such as 8, 16 × 9, 17 × 9, 17 × 8.

  When a predetermined macroblock included in a P picture or B picture is decoded by the # 1 decode chip 73 or the # 2 decode chip 76, information on the search range of the macroblock of the reference image that has been decoded in advance is used. . However, when the macroblock to be decoded is close to the boundary between the image area decoded by the # 1 decode chip 73 and the image area decoded by the # 2 decode chip 76, the motion vector search range required as the reference image Some of them are included in the image area decoded by the other decoding chip. Specifically, as shown in FIG. 11, when a P picture or a B picture is decoded by the # 2 decode chip 76, the image area decoded by the # 2 decode chip 76 (the image range in the vertical direction in the figure is part of the search area corresponding to the macro block in the part close to the image area decoded by the # 1 decode chip 73 in the area indicated by b) is the image area (in the figure) decoded by the # 1 decode chip 73 The vertical image range is included in the area indicated by a).

  Therefore, the # 1 decode chip 73 and the # 2 decode chip 76 have been decoded by the # 1 decode chip 73 and the # 2 decode chip 76 in order to make it possible to search all of the motion vector search ranges required by the # 1 decode chip 73 and the # 2 decode chip 76. Of the I picture and P picture, data of an area that may be a motion vector search range in the other decoding process is supplied in advance to the other decoding chip.

  That is, as shown in FIG. 12, in the I picture and P picture decoded by the # 1 decode chip 73, the image area decoded by the # 1 decode chip 73 whose vertical image range is indicated by a in the figure. Among them, data in an area where the image range in the vertical direction is indicated by α (an image area close to the image area decoded by the # 2 decode chip 76) is supplied to the # 2 decode chip 76, and the image range in the vertical direction is Along with the image area decoded by the # 2 decode chip 76 indicated by b, the video buffer 78 saves it as accumulated video data.

  Also, in the I picture and P picture decoded by the # 2 decode chip 76, the vertical image range of the image areas decoded by the # 2 decode chip 76 indicated by b in the vertical direction in the figure. Is supplied to the # 1 decode chip 73, and the image range in the vertical direction is indicated by a # 1 decode chip. Along with the image area decoded at 73, the video buffer 75 stores it as accumulated video data.

  As described above, the ranges of α and β shown in FIG. 12 are data of a region that may be a motion vector search range in the other decoding process. The motion vector search range in motion compensation is defined by the MPEG standard as ± 1920 pixels (that is, the maximum image frame width) in the horizontal direction and 128 lines in the vertical direction in interlace frame data of 1920 pixels in the horizontal direction and 1080 lines in the vertical direction. Has been. That is, when the encoded stream to be decoded by the decoding processing unit 51 is frame data of interlace format of horizontal 1920 pixels and vertical 1080 lines encoded according to the MPEG standard, the other is shown as α and β in FIG. The line width of the image area supplied (copied) to the decoding chip is 128 lines. This is defined as “parameter restriction on level” by MPEG specification ISO / IEC13818-2 Table 8-8. Further, since each picture is indicated as f_code, α and β may be determined with reference to a line defined by f_code in the vertical direction.

  Specific examples of decoding processing for each picture, decoding processing of the # 1 decoding chip 73 and # 2 decoding chip 76, and exchange of decoded pixel data will be described with reference to FIGS. Here, in each picture, the image area decoded by the # 1 decode chip 73 is called a first area, and the image area decoded by the image area decoded by the # 2 decode chip 76 is called a second area. Shall.

  First, as shown in FIG. 13, the I picture divided into the first area and the second area is supplied to the # 1 decode chip 73 and the # 2 decode chip 76, respectively. The decoder 93 of the # 1 decode chip 73 decodes each slice included in the first area of the I picture supplied via the buffer control circuit 92. The buffer control circuit 95 supplies the decoded pixel data of the first area of the I picture to the video buffer 75 and stores it therein, and among the decoded pixel data of the first area of the I picture, # 2 In the decoding process of the decoding chip 76, pixel data of a region included in the motion vector search range (a region in which the vertical image range is indicated by α in FIG. 12) is supplied to the inter-chip interface 96. The inter-chip interface 96 supplies the supplied pixel data to the inter-chip interface 116 of the # 2 decode chip 76.

  On the other hand, the decoder 113 of the # 2 decode chip 76 decodes each slice included in the second area of the I picture supplied via the buffer control circuit 112. The buffer control circuit 115 supplies the decoded pixel data of the second area of the I picture to the video buffer 78 and stores it, and among the decoded pixel data of the second area, the # 1 decode chip 73. In this decoding process, the pixel data of the region included in the motion vector search range (the region where the vertical image range is indicated by β in FIG. 12) is supplied to the inter-chip interface 116. The inter-chip interface 116 supplies the supplied pixel data to the inter-chip interface 96 of the # 1 decode chip 73.

  The inter-chip interface 116 of the # 2 decode chip 76 includes the pixel data supplied from the inter-chip interface 96 of the # 1 decode chip 73, that is, the pixel data of the first area of the I picture, of the # 2 decode chip 76. In the decoding process, pixel data of a region included in the motion vector search range (a region in which the vertical image range is indicated by α in FIG. 12) is supplied to the buffer control circuit 115. The buffer control circuit 115 supplies the supplied pixel data to the video buffer 78. The inter-chip interface 96 of the # 1 decode chip 73 is the # 1 decode chip of the pixel data supplied from the inter-chip interface 116 of the # 2 decode chip 76, that is, the pixel data of the second area of the I picture. In the decoding process 73, the pixel data of the region included in the motion vector search range (the region in which the vertical image range is indicated by β in FIG. 12) is supplied to the buffer control circuit 95. The buffer control circuit 95 supplies the supplied pixel data to the video buffer 75.

  That is, in the video buffer 75, an area included in the motion vector search range in the decoding process of the # 1 decode chip 73 among the pixel data of the first area of the I picture and the pixel data of the second area (see FIG. 12, the pixel data of the area in which the vertical image range is indicated by β) is stored, and the video buffer 78 stores the pixel data of the second area of the I picture and the pixel data of the first area. In the decoding process of the # 2 decode chip 76, the pixel data of the region included in the motion vector search range (the region in which the vertical image range is indicated by α in FIG. 12) is stored.

  Of the pixel data stored in the video buffer 75, the pixel data of the first area of the I picture is read by the buffer control circuit 95 and supplied to the synthesis processing unit 79 via the output circuit 97. . Of the pixel data stored in the video buffer 78, the pixel data of the second region of the I picture is read by the buffer control circuit 115 and supplied to the synthesis processing unit 79 via the output circuit 117. . Then, the pixel data supplied to the synthesis processing unit 79 is synthesized and output.

  Then, when the P picture is decoded, the motion is performed in the decoding process of the # 1 decoding chip 73 among the pixel data of the first area of the I picture and the pixel data of the second area stored in the video buffer 75. Pixel data in an area included in the vector search range is read out to the buffer control circuit 95 and used for motion compensation processing by the motion compensation circuit 94. In addition, the pixel data of the second area of the I picture stored in the video buffer 78 and the area included in the motion vector search range in the decoding process of the # 2 decode chip 76 among the pixel data of the first area Are read by the buffer control circuit 115 and used for motion compensation processing by the motion compensation circuit 114. That is, as shown in FIG. 14, the motion search range of each macroblock included in the first area of the P picture decoded by the # 1 decode chip 73 includes the first area of the I picture and the second area of the second picture. Each macroblock included in the second area of the P picture corresponding to the area included in the motion vector search range in the decoding process of the # 1 decode chip 73 in the pixel data of the area and decoded by the # 2 decode chip 76 The motion search range corresponds to the second region of the I picture and the region included in the motion vector search range in the decoding process of the # 2 decode chip 76 in the pixel data of the first region.

  The buffer control circuit 95 of the # 1 decode chip 73 supplies the pixel data of the first area of the decoded P picture to the video buffer 75 for storage, and also the pixels of the first area of the decoded P picture. Among the data, pixel data of an area included in the motion vector search range in the decoding process of the # 2 decode chip 76 (area in which the vertical image range is indicated by α in FIG. 12) is supplied to the inter-chip interface 96. . The inter-chip interface 96 supplies the supplied pixel data to the inter-chip interface 116 of the # 2 decode chip 76.

  Further, the buffer control circuit 115 of the # 2 decode chip 76 supplies the decoded pixel data of the second area of the P picture to the video buffer 78 and stores it, and also decodes the decoded pixel data of the second area. Among them, the pixel data of an area included in the motion vector search range in the decoding process of the # 1 decode chip 73 (the area where the vertical image range is indicated by β in FIG. 12) is supplied to the inter-chip interface 116. The inter-chip interface 116 supplies the supplied pixel data to the inter-chip interface 96 of the # 1 decode chip 73.

  The inter-chip interface 116 of the # 2 decode chip 76 includes the pixel data supplied from the inter-chip interface 96 of the # 1 decode chip 73, that is, the pixel data of the first area of the P picture. In the decoding process, pixel data of a region included in the motion vector search range (a region in which the vertical image range is indicated by α in FIG. 12) is supplied to the buffer control circuit 115. The buffer control circuit 115 supplies the supplied pixel data to the video buffer 78. The inter-chip interface 96 of the # 1 decode chip 73 is the # 1 decode chip out of the pixel data supplied from the inter-chip interface 116 of the # 2 decode chip 76, that is, the pixel data of the second area of the P picture. In the decoding process 73, the pixel data of the region included in the motion vector search range (the region in which the vertical image range is indicated by β in FIG. 12) is supplied to the buffer control circuit 95. The buffer control circuit 95 supplies the supplied pixel data to the video buffer 75.

  That is, as shown in FIG. 15, the video buffer 75 stores the motion vector of the pixel data of the first area of the P picture and the pixel data of the second area in the decoding process of the # 1 decode chip 73. Pixel data of a region included in the search range (a region in which the vertical image range is indicated by β in FIG. 12) is stored, and the video buffer 78 stores the pixel data of the second region of the P picture, Among the pixel data of area 1, pixel data of the area included in the motion vector search range (the area where the vertical image range is indicated by α in FIG. 12) in the decoding process of # 2 decode chip 76 is stored. The

  When the B picture is decoded, the pixel data of the first area and the pixel data of the second area in the I or P picture before and after the decoded B picture stored in the video buffer 75 are stored. Among them, pixel data in an area included in the motion vector search range in the decoding process of the # 1 decoding chip 73 is read out to the buffer control circuit 95 and used for the motion compensation process by the motion compensation circuit 94. Also, the pixel data of the second area in the I or P picture before and after the B picture to be decoded, which is stored in the video buffer 78, and the decoding of the # 2 decoding chip 76 among the pixel data of the first area In the processing, pixel data in an area included in the motion vector search range is read out to the buffer control circuit 115 and used for motion compensation processing by the motion compensation circuit 114. That is, as shown in FIG. 16, the motion search range of each macroblock included in the first area of the B picture decoded by the # 1 decode chip 73 is the first area of the I or P picture before and after it. Corresponding to the area included in the motion vector search range in the decoding process of the # 1 decode chip 73 in the pixel data of the second area, and the second area of the B picture decoded by the # 2 decode chip 76 The motion search range of each macroblock included is included in the motion vector search range in the decoding process of the # 2 decode chip 76 in the second area of the I or P picture before and after the macroblock and the pixel data of the first area. Corresponds to the area to be

  The buffer control circuit 95 of the # 1 decode chip 73 supplies the decoded pixel data of the first area of the B picture to the video buffer 75 for storage. Since the B picture is not used as a reference image for other pictures, the B picture decoded by the # 1 decode chip 73 may not be supplied (copied) to the # 2 decode chip 76.

  Further, the buffer control circuit 115 of the # 2 decode chip 76 supplies the pixel data of the second area of the decoded B picture to the video buffer 78 for storage. Since the B picture is not used as a reference image for other pictures, the B picture decoded by the # 2 decoding chip 76 may not be supplied (copied) to any area of the # 1 decoding chip 73.

  In this way, after the I or P picture is decoded, the pixel data of the area used as the reference pixel when decoding the P or B picture of the other decoding chip is supplied to the other decoding chip and copied to the video buffer. Therefore, when one frame is divided into two and decoded by different decoding chips, pixel data of an area used as a reference pixel when decoding a P or B picture is stored in the video buffer in advance. Be available.

  Next, the decoder switching determination process will be described with reference to the flowchart of FIG.

  In step S <b> 1, the CPU 40 acquires information on the type of stream to be decoded and the display method of the stream supplied from the CPU 31 via the north bridge 32, the PCI bus 34, the PCI bridge 37, and the control bus 39. .

  In step S2, the CPU 40 determines whether or not the stream to be decoded is a stream composed only of I pictures. If it is determined in step S2 that the stream is composed of only I pictures, the process proceeds to step S6 described later.

  When it is determined in step S2 that the stream is not composed of only I pictures, in step S3, the CPU 40 displays the display scale of the scrub bar 151 or the timeline 153 on the editing screen 131 described with reference to FIG. It is determined whether or not it is a predetermined value or more. If it is determined in step S3 that the value is equal to or greater than the predetermined value, the process proceeds to step S6 described later.

  If it is determined in step S3 that the value is not equal to or greater than the predetermined value, in step S4, the CPU 40 determines whether or not decoding processing for backward reproduction, high-speed reproduction, or scrub reproduction is executed. If it is determined in step S4 that none of reverse playback, high-speed playback, or scrub playback is performed, the process proceeds to step S6 described later.

  If it is determined in step S4 that the playback is one of reverse playback, high speed playback, and scrub playback, in step S5, the CPU 40 decodes, for example, triple speed for M = 3 LongGOP. It is determined whether or not the predetermined reproduction process has a low processing load.

  If it is determined in step S2 that the stream is composed only of I pictures, or if it is determined in step S3 that it is equal to or greater than a predetermined value, in step S4, reverse playback, high-speed playback, or scrubbing is performed. If it is determined that it is not any of the playback, or if it is determined in step S5 that the playback process is a predetermined playback process with a low load of decoding processing, such as triple speed for M = 3 LongGOP, for example, In S6, the CPU 40 controls the decoder unit 42 to execute normal decoding processing, and the processing ends.

  If it is determined in step S5 that the reproduction process is not a predetermined reproduction process with a low load of decoding processing, such as triple speed for a LongGOP of M = 3, for example, it will be described later with reference to the flowchart of FIG. The division decoding process is executed, and the process ends.

  By such processing, it is determined whether the divided decoding processing or the normal decoding processing is executed based on various conditions of the decoding processing.

  Note that here, the display scale of the timeline is not a predetermined value, not a stream composed only of I pictures, and special playback of reverse playback, high-speed playback, or scrub playback is performed, Furthermore, for example, it has been described that the division decoding process is executed only when it is determined that the reproduction process is not a predetermined reproduction process with a low decoding processing load such as 3 × speed for a LongGOP of M = 3. The condition whether or not to execute is determined by, for example, the decoding processing capability of the decoding processing units 51-1 to 51-m constituting the decoder unit 42, that is, the processing capability of the # 1 decoding chip 73 and # 2 decoding chip 76. Needless to say, it may be different.

  Specifically, for example, when the # 1 decode chip 73 and # 2 decode chip 76 having relatively low processing capability are used, when one or two of the above-described conditions are met, the divided decode processing is performed. It may be executed.

  Next, the division decoding process executed in step S7 of FIG. 17 will be described with reference to the flowchart of FIG.

  In step S31, the decoding processing units 51-1 to 51-m receive supply of stream data.

  In step S32, the supplied frame is supplied to each of the # 1 decode chip 73 and the # 2 decode chip 76.

  In step S33, a divided frame decoding process to be described later with reference to FIG. 19 is executed.

  In step S34, the output circuit 97 of the # 1 decode chip 73 generates a synchronization timing signal for outputting image data constituted by the decoded pixel data, and through the buffer control circuit 95 based on this timing. Of the image data buffered in the video buffer 75, the portion of the image data to be output next decoded by the decoder 93 (that is, the image region indicated by a in the vertical image range in FIG. 12). ) Is output to the synthesis processing unit 79 as decoded video data. The output circuit 117 of the # 2 decode chip 76 generates a synchronization timing signal for outputting image data composed of decoded pixel data. Based on this timing, the output circuit 117 passes through the buffer control circuit 115. Of the image data buffered in the video buffer 78, the portion of the image data to be output next decoded by the decoder 113 (that is, the image region in which the vertical image range is indicated by b in FIG. 12). Image data is read out and output to the synthesis processing unit 79 as decoded video data.

  In step S37, the composition processing unit 79 receives the supply of the divided frame image data decoded from the # 1 decode chip 73 and the # 2 decode chip 76, combines the divided image data into one frame, and outputs it. The signal is output via the signal selector 80, and the process is terminated.

  Through such processing, the decoding processing unit 51 described with reference to FIG. 8 can divide and decode one frame using the # 1 decoding chip 73 and the # 2 decoding chip 76. For example, the decoder 93 of the # 1 decode chip 73 and the decoder 113 of the # 2 decode chip 76 each have a decoding processing speed corresponding to 1 × speed. 8, the decoding processing unit 51 described with reference to FIG. 8 executes the decoding process on either side. Compared to the case, a double speed decoding process is possible.

  Such processing not only enables decoding at double speed, but also reduces the circuit scale (decreases the processing capability of one decoding chip) with equivalent high-speed decoding performance. Even an encoded stream having a high frame frequency that cannot be handled by a single decode chip can be decoded by using a plurality of decode chips. Specifically, for example, by using two decode chips with a processing capacity of 1920 × 1080 / 30P equivalent to one decode chip, it is possible to decode a 1920 × 1080 / 60P encoded stream, and one decode chip By using two decoding chips equivalent to 1920 × 1080 / 60i, it is possible to decode a 1920 × 1080 / 60P encoded stream, and the processing capacity of one decoding chip is 1920 × 1080 / 60i. By using two corresponding decoding chips, it is possible to decode a 1920 × 1080 / 120i encoded stream.

  Furthermore, high-speed decoding processing becomes possible, and when a plurality of decode chips divide and decode one frame to start reproduction from a desired picture, it is necessary to decode the picture at the reproduction start point. Even when there are a plurality of reference images, processing can be performed at high speed, so that high-speed cue playback can be realized.

  Next, the divided frame decoding process executed in step S33 in FIG. 18 will be described with reference to the flowchart in FIG. The divided frame decoding process is executed in parallel in each of the # 1 decode chip 73 and the # 2 decode chip 76.

  In step S61, the stream input circuit 91 of the # 1 decode chip 73 receives the stream data and detects the picture type of the supplied frame. Further, the stream input circuit 111 of the # 1 decode chip 76 receives the stream data and detects the picture type of the supplied frame.

  In step S62, the stream input circuit 91 of the # 1 decode chip 73 and the stream input circuit 111 of the # 1 decode chip 76 are described using, for example, FIG. The range to be decoded is selected and extracted in the same manner as in the above-described frame division.

  In step S63, the stream input circuit 91 of the # 1 decode chip 73 supplies the buffer control circuit 92 with the portion extracted as the decode range in the supplied frame. The buffer control circuit 92 buffers the supplied data in the stream buffer 74. Further, the stream input circuit 111 of the # 1 decode chip 76 supplies the buffer control circuit 112 with the portion extracted as the decode range in the supplied frame. The buffer control circuit 112 buffers the supplied data in the stream buffer 77.

  In step S 64, the buffer control circuit 92 reads the data buffered in the stream buffer 74 and supplies the data to the decoder 93. Also. The buffer control circuit 112 reads the data buffered in the stream buffer 77 and supplies it to the decoder 113. At this time, as described above, it is preferable that the decoder is preferentially supplied to the decoder so that decoding is started from a macroblock in an area that needs to be supplied as a reference pixel to another decode chip.

  In step S65, the decoder 93 and the decoder 113 determine whether or not the supplied picture is an I picture based on the control signal supplied from the controller 71. If it is determined in step S65 that the supplied picture is not an I picture, the process proceeds to step S70 described later.

  If it is determined in step S65 that the supplied picture is an I picture, in step S66, the decoder 93 and the decoder 113 decode the macroblock included in each supplied encoded data.

  In step S67, the buffer control circuit 95 receives the decoded data from the decoder 93, and uses the decoded pixel data (pixel data corresponding to the first area of the I picture in FIG. 13) as the reference image. The image is supplied to the video buffer 75 as an output image. Further, the buffer control circuit 115 receives the decoded data from the decoder 113, and outputs the decoded pixel data (pixel data corresponding to the second region of the I picture in FIG. 13) as a reference image and an output. To the video buffer 78 as an image for use.

  In step S68, the buffer control circuit 95 copies the decoded data supplied from the decoder 93 to the # 2 decode chip 76 for use in the decoding process of the # 2 decode chip 76 (that is, FIG. 12). In the middle, the vertical image range is indicated by α) data is supplied to the inter-chip interface 96. The interchip interface 96 supplies the supplied pixel data of the copy portion to the interchip interface 116 of the # 2 decode chip 76. Also, the buffer control circuit 115 copies the decoded data supplied from the decoder 113 to the # 1 decode chip 73 for use in the decoding process of the # 1 decode chip 73 (ie, in FIG. 12, Data in the vertical image range indicated by β is supplied to the inter-chip interface 116. The inter-chip interface 116 supplies the supplied copy portion pixel data to the inter-chip interface 96 of the # 1 decode chip 73.

  At this time, an interface for connecting the decoding chips, that is, an interface for supplying data from the interchip interface 96 to the interchip interface 116 and an interface for supplying data from the interchip interface 116 to the interchip interface 96 are independent of each other. Data transfer speed without the need for complicated address control associated with data transfer, data bus occupancy timing, or data transfer timing control. However, it is possible to reduce the speed as compared with a case where an interface such as a data bus is shared.

  The interface connecting the inter-chip interface 96 and the inter-chip interface 116 is, for example, by pattern-connecting the input / output terminals of each chip on the substrate on which the # 1 decode chip 73 and the # 2 decode chip 76 are mounted. Therefore, even if each interface is prepared independently, the hardware implementation cost required for that purpose is very low.

  In step S <b> 69, the inter-chip interface 96 of the # 1 decode chip 73 supplies the pixel data supplied from the # 2 decode chip 76 to the buffer control circuit 95. The buffer control circuit 95 supplies the supplied pixel data to the video buffer 75. Also. The inter-chip interface 116 of the # 2 decode chip 76 supplies the pixel data supplied from the # 1 decode chip 73 to the buffer control circuit 115. The buffer control circuit 115 supplies the supplied pixel data to the video buffer 78. That is, as described with reference to FIG. 13, the video buffer 75 moves in the decoding process of the # 1 decoding chip 73 out of the pixel data of the first area of the I picture and the pixel data of the second area. Pixel data of a region included in the vector search range (a region in which the vertical image range is indicated by β in FIG. 12) is stored, and the video buffer 78 stores pixel data of the second region of the I picture and Among the pixel data of the first area, the pixel data of the area (area in which the vertical image range is indicated by α in FIG. 12) included in the motion vector search range in the decoding process of the # 2 decode chip 76 is included. The process is saved, and the process returns to step S33 in FIG. 18 and proceeds to step S34.

  If it is determined in step S65 that the supplied picture is not an I picture, in step S70, the decoder 93 and the decoder 113 are supplied with a P picture based on the control signal supplied from the controller 71. Judge whether there is. If it is determined in step S70 that the supplied picture is not a P picture, the process proceeds to step S75 described later.

  If it is determined in step S70 that the supplied picture is a P picture, in step S71, the decoder 93 and the decoder 113 decode each macroblock using the reference pixel data. Specifically, since the macroblock included in the P picture uses motion compensation, the decoder 93 decodes the macroblock by separating the slice layer into macroblocks, and the resulting prediction vector and pixel Is output to the motion compensation circuit 94. The motion compensation circuit 94 reads the reference pixel data from the video buffer 75 via the buffer control circuit 95 according to the prediction vector output from the decoder 93, and converts the read reference pixel data into the pixel data supplied from the decoder 93. Add and perform motion compensation. In the video buffer 75, all pixels of the reference image necessary for decoding the P picture divided by the process of step S69 or step S74 described later are accumulated. The decoder 113 also separates the slice layer into macroblocks, decodes the macroblocks, and outputs the prediction vectors and pixels obtained as a result to the motion compensation circuit 114. The motion compensation circuit 114 reads the reference pixel data from the video buffer 78 via the buffer control circuit 115 according to the prediction vector output from the decoder 113, and converts the read reference pixel data into the pixel data supplied from the decoder 113. Add and perform motion compensation. In the video buffer 78, all the reference images necessary for decoding the P picture divided by the process of step S69 or step S74 described later are accumulated.

  In step S72, the buffer control circuit 95 receives the decoded data from the decoder 93, and uses the decoded pixel data (pixel data corresponding to the first region of the P picture in FIG. 15) as the reference image. The image is supplied to the video buffer 75 as an output image. Further, the buffer control circuit 115 receives the decoded data from the decoder 113, and outputs the decoded pixel data (the pixel data corresponding to the second region of the P picture in FIG. 15) as a reference image and an output. To the video buffer 78 as an image for use.

  In step S73, the buffer control circuit 95 copies the decoded data supplied from the decoder 93 to the # 2 decode chip 76 for use in the decoding process of the # 2 decode chip 76 (that is, FIG. 12). In the middle, the vertical image range is indicated by α) data is supplied to the inter-chip interface 96. The interchip interface 96 supplies the supplied pixel data of the copy portion to the interchip interface 116 of the # 2 decode chip 76. Also, the buffer control circuit 115 copies the decoded data supplied from the decoder 113 to the # 1 decode chip 73 for use in the decoding process of the # 1 decode chip 73 (ie, in FIG. 12, Data in the vertical image range indicated by β is supplied to the inter-chip interface 116. The inter-chip interface 116 supplies the supplied copy portion pixel data to the inter-chip interface 96 of the # 1 decode chip 73.

  In step S74, the inter-chip interface 96 of the # 1 decode chip 73 supplies the pixel data supplied from the # 2 decode chip 76 to the buffer control circuit 95. The buffer control circuit 95 supplies the supplied pixel data to the video buffer 75. Also. The inter-chip interface 116 of the # 2 decode chip 76 supplies the pixel data supplied from the # 1 decode chip 73 to the buffer control circuit 115. The buffer control circuit 115 supplies the supplied pixel data to the video buffer 78. That is, as described with reference to FIG. 15, the video buffer 75 moves in the decoding process of the # 1 decoding chip 73 out of the pixel data of the first region of the P picture and the pixel data of the second region. Pixel data of a region included in the vector search range (a region in which the vertical image range is indicated by β in FIG. 12) is stored, and the video buffer 78 stores pixel data of the second region of the P picture. Among the pixel data of the first area, the pixel data of the area (area in which the vertical image range is indicated by α in FIG. 12) included in the motion vector search range in the decoding process of the # 2 decode chip 76 is included. The process is saved, and the process returns to step S33 in FIG. 18 and proceeds to step S34.

  When it is determined in step S70 that the supplied picture is not a P picture, in step S75, the decoder 93 and the decoder 113 are supplied with a B picture based on the control signal supplied from the controller 71. Judge whether there is. If it is determined in step S75 that the supplied picture is not a B picture, the process returns to step S65, and the subsequent processes are repeated.

  When it is determined in step S75 that the supplied picture is a B picture, in step S76, the decoder 93 and the decoder 113 decode each macroblock using the reference pixel data. Specifically, since the macroblock included in the B picture uses motion compensation, the decoder 93 decodes the macroblock by separating the slice layer into macroblocks, and the resulting prediction vector and pixel Is output to the motion compensation circuit 94. The motion compensation circuit 94 reads the reference pixel data from the video buffer 75 via the buffer control circuit 95 according to the prediction vector output from the decoder 93, and converts the read reference pixel data into the pixel data supplied from the decoder 93. Add and perform motion compensation. In the video buffer 75, all pixels of the reference image necessary for decoding the B picture divided by the processing of step S69 or step S74 are accumulated. The decoder 113 also separates the slice layer into macroblocks, decodes the macroblocks, and outputs the prediction vectors and pixels obtained as a result to the motion compensation circuit 114. The motion compensation circuit 114 reads reference pixel data from the video buffer 78 via the buffer control circuit 115 according to the prediction vector output from the decoder 113. Then, the read reference pixel data is added to the pixel data supplied from the decoder 113 to perform motion compensation. In the video buffer 78, all the reference images necessary for decoding the B picture divided by the process of step S69 or step S74 are accumulated.

  In step S77, the buffer control circuit 95 receives the decoded data from the decoder 93 and outputs the decoded pixel data (pixel data corresponding to the first area of the B picture in FIG. 16) for output. Is supplied to the video buffer 75 as an image. Further, the buffer control circuit 115 receives the decoded data from the decoder 113 and outputs the decoded pixel data (pixel data corresponding to the second area of the B picture in FIG. 16) as an output image. To the video buffer 78, and the process returns to step S33 in FIG. 18 and proceeds to step S34.

  By such processing, decoding processing based on the picture type detected by the controller 71 is executed in each of the # 1 decoding chip 73 and the # 2 decoding chip 76. At this time, in each of the # 1 decode chip 73 and the # 2 decode chip 76, the pixel data of the portion used as the reference image in the other decode chip is supplied to the other decode chip and the other decode chip. Can be supplied to a video buffer that can be referred to by itself and stored and used as a reference image.

  In the above-described processing, after the decoding of the I picture is completed, the pixel data of the portion referred to in the decoding of the P or B picture is supplied to the other decoding chip, and after the decoding of the P picture is completed, the P or In the above description, it is assumed that the pixel data of the part referred to in the decoding of the B picture is supplied to the other decoding chip. As a result, when the inter-chip copy processing of the decoded pixel data is executed when each picture is decoded, that is, when the P picture is decoded, it is already decoded and buffered. From the pixel data corresponding to the I or P picture, the pixel data of the part to be referred to in the decoding of the P picture is obtained from the other decoding chip, and when decoding the B picture, the already decoded and buffered I or P Compared to the case where the pixel data of the part referred to in the decoding of the B picture is obtained from the other decoding chip from the pixel data corresponding to the picture, each video buffer (video buffer 75 or video buffer 78). Reduce total access time to Theft is possible.

  Specifically, when the inter-chip copy process of the decoded pixel data is executed when each picture is decoded, as shown by A in FIG. The access time to the video buffer (video buffer 75 or video buffer 78) is only the write time T1 of the decoded image corresponding to the I picture, and the access time to the video buffer at the time of decoding the P picture corresponds to the P picture. In addition to the decoded image writing time T1, a forward reference image reading time T2 and a reference image reading time T3 in the range used for the decoding process of the other decoding chip are required. The reference image read time T2 is substantially equal to or longer than the decoded image write time T1. The access time to the video buffer at the time of decoding the B picture includes the read time T2 × 2 of the forward and backward reference pictures in addition to the write time T1 of the decoded picture corresponding to the B picture, and the other decoding A read time T3 × 2 for reference images in the forward and backward directions of the range used for the chip decoding process is required.

  Then, the pixel data of the part referred to in the decoding of the P or B picture after the decoding of the I picture is supplied to the other decoding chip, and the part referred to in the decoding of the P or B picture after the decoding of the P picture is completed 20 is supplied to the other decoding chip, as shown in B in FIG. 20, the access time to the video buffer at the time of decoding the I picture is the time of the decoded image corresponding to the I picture. In addition to the writing time T1, a time T4 for writing a reference image in a range supplied from the other decoding chip and used later when a P or B picture is decoded is required. The access time to the video buffer at the time of decoding the P picture is supplied from the other decoding chip in addition to the decoded image writing time T1 and the forward reference image reading time T2 corresponding to the P picture. A time T4 for writing a reference image in a range used later when a P or B picture is decoded later is required. The access time to the video buffer at the time of decoding the B picture is the total time of the decoded image writing time T1 corresponding to the B picture and the forward and backward reference picture reading time T2 × 2.

  That is, a case in which the inter-chip copy processing of the decoded pixel data is executed when each picture is decoded, and a portion that is referred to in the decoding of the P or B picture after the decoding of the I picture is completed In this case, the first pixel data is supplied in advance to the other decoding chip, and the pixel data of the part referred to in the decoding of the P or B picture is supplied in advance to the other decoding chip after the decoding of the P picture is completed. In FIG. 20, the total access time to the video buffer is maximized when the B picture is decoded, but as shown in FIG. 20B by supplying a reference image of another decoding chip in advance. In addition, the maximum access time to the video buffer for decoding one picture is shortened. Can be shortened by the time indicated by T5 in the drawing, so that the decoding processing time can be shortened. In other words, the decoding processing can be performed at a higher speed or the same decoding processing speed. In this case, the data transfer rate between the decode chip and the video buffer can be lowered.

  At this time, as described above, an interface for connecting the decoding chips, that is, an interface for supplying data from the inter-chip interface 96 to the inter-chip interface 116, and an interface for supplying data from the inter-chip interface 116 to the inter-chip interface 96 Are independent of each other (not sharing an interface such as a data bus), and does not require complicated address control associated with data transfer or control of data bus timing or data transfer timing. The data transfer speed can also be reduced as compared with the case where an interface such as a data bus is shared.

  Further, the decoding processing time can be further shortened depending on which slice the decoding processing executed in each of the # 1 decoding chip 73 and the # 2 decoding chip 76 is performed, in other words, at a higher speed. Decoding processing can be performed.

  The order of decoding processing and the processing speed of decoding processing will be described with reference to FIGS.

  FIG. 21 is a diagram illustrating a plurality of patterns in the processing order of the decoding process executed in each of the # 1 decode chip 73 and the # 2 decode chip 76.

  When an MPEG stream is supplied, a plurality of slices constituting a screen are sequentially supplied as picture_data following picture_header and the like. In this case, the slices are supplied in the order of the slice at the upper left of the screen, and the slice at the lower right of the screen. Therefore, in the normal decoding order, decoding is performed in the order from the top to the bottom of each divided screen as indicated by the arrows 161 and 162 in FIG. 21 in each of the # 1 decode chip 73 and the # 2 decode chip 76. Processing is executed. That is, the reference pixel in the region indicated by α in the figure that is decoded by the # 1 decode chip 73 and needs to be transferred to the # 2 decode chip 76 is finally decoded.

  Therefore, for example, when the B picture is decoded following the decoding of the P picture, even if the decoding of the area decoded by the # 2 decoding chip 76 of the P picture is finished in the # 2 decoding chip 76, the # 1 decoding chip The decoding process of the next B picture cannot be started until the reference pixels in the region indicated by α in the figure decoded in 73 are supplied to the # 2 decoding chip 76 and accumulated in the video decoder 78.

  As described above, in order to reduce the waiting time of the decoding process that occurs due to the time required to copy (transfer) the reference pixel to another decoding chip, the transfer speed of the reference pixel between the decoding chips must be increased. Don't be.

  Therefore, in the decoding processing unit 51 to which the present invention is applied, the decoding processing order in the # 1 decoding chip 73 can be different from the case indicated by the arrow 161.

  That is, in the decoding processing unit 51 shown in FIG. 8, since the divided encoded stream supplied to the # 1 decode chip 73 is accumulated in the stream buffer 74, the buffer control circuit 92 is indicated by α in the figure. The reference pixel in the area to be read is read first and supplied to the decoder 93. Specifically, for example, as indicated by an arrow 163-1 in FIG. 21, in the area indicated by α in the figure, the lower right slice (slice closer to the area decoded by the # 2 decode chip 76) is sequentially ordered. Then, the remaining area of the image of the area decoded by the # 1 decode chip 73 is supplied to the decoder 93 in order from the lower right slice, as indicated by an arrow 163-2. You may do it. Further, as indicated by an arrow 163-3 in FIG. 21, in an area indicated by α in the figure, an image of an area that is supplied to the decoder 93 in order from the upper left slice, and subsequently decoded by the # 1 decode chip 73. Also in the remaining region, as shown by the arrow 163-4, the upper left slice may be supplied to the decoder 93 in order. Further, as indicated by an arrow 163-5 in FIG. 21, in the area indicated by α in the figure, the slice is supplied to the decoder 93 in order from the lower right slice, and subsequently the area decoded by the # 1 decode chip 73 The remaining area of the image may be supplied to the decoder 93 in order from the upper left slice, as indicated by an arrow 163-6.

  If the reference pixel in the area indicated by α in the figure is read out first and supplied to the decoder 93, the decoding process of the area to be decoded by the # 2 decode chip 76 in any of the above-described patterns Before all the processing is completed, the reference pixel in the area indicated by α in the figure is decoded and supplied to the # 2 decode chip 76, so that the decoding process is performed due to the time required for copying (transfer) to another decode chip. Can be prevented from occurring.

  That is, as shown by arrows 161 and 162 in FIG. 21, when decoding processing is executed in the order from the top to the bottom of each divided screen, as shown in FIG. The decoding process of the area indicated by α in the figure is started and the decoding process of the area decoded by the # 2 decoding chip 76 is completed even if the decoded reference pixels are sequentially supplied to the # 2 decoding chip 76. Until then, the data transfer (arrow 164 and arrow 165 in the figure) is not completed. That is, until the reference pixel in the region indicated by α in the figure is supplied to the # 2 decode chip 76 and accumulated in the video decoder 78, the decoding process for the next picture cannot be started (arrow 166 in the figure). .

  On the other hand, as indicated by arrows 163-1 to 163-6 in FIG. 21, the encoded stream in the area indicated by α in the figure is read out first and supplied to the decoder 93. Then, as shown in FIG. 23, in the # 1 decode chip 73, the decoding process of the area indicated by α in the figure is started first, and the supply of the decoded reference pixels to the # 2 decode chip 76 is sequentially performed. Since the decoding process of the other area is executed while the data is being transferred, the data transfer (arrows 167 and 168 in the figure) is not completed until the decoding process of the area decoded by the # 2 decode chip 76 is completed. ) Is terminated. That is, the decoding process for the next picture can be started immediately after the decoding process for the area decoded by the # 2 decoding chip 76 is completed (arrow 169 in the figure).

  In other words, by preferentially executing the decoding of the area supplied to the other decoding chip in each decoding chip, the data transfer process during the decoding process of other parts without significantly increasing the transfer speed Can be terminated.

  Next, FIG. 24 is a block diagram illustrating a configuration of the encoding processing unit 52. Here, description will be made assuming that the encoding processing unit 52 is configured to be able to receive, decode, and output the encoded stream encoded by the MPEG2 system.

  The encoding processing unit 52 includes a controller 171, an input signal selection unit 172, a # 1 encoding chip 173, a video buffer 174, a stream / reference image buffer 175, a # 2 encoding chip 176, a video buffer 177, a stream / reference image buffer 178, A synthesis processing unit 179 and an output signal selection unit 180 are included. The encoding processing unit 52 may be provided with three or more encode chips, but here, it is assumed that two encode chips, # 1 encode chip 173 and # 2 encode chip 176, are provided. To do.

  The controller 171 controls the operation of the encoding processing unit 52 based on a user operation input or a control signal supplied from an external device.

  That is, based on the control of the CPU 40, the controller 171 uses the # 1 encode chip 173 and the # 2 encode chip 176 to divide one screen into two parts and perform the encode process when the difficulty level of the encode process is high. If the difficulty level of the encoding process is relatively low, the # 1 encode chip 173 and the # 2 encode chip 176 encode different video data respectively. Can be.

  The difficulty level of the encoding process varies depending on the profile and level of the video data (baseband image data) to be encoded, for example. The controller 171 determines levels and profiles that can be used to encode different video data with the 1 encode chip 173 and the # 2 encode chip 176 according to the processing capabilities of the # 1 encode chip 173 and the # 2 encode chip 176, respectively. When setting and encoding video data of a level and profile that are more difficult than that, the # 1 encode chip 173 and the # 2 encode chip 176 are used to divide one screen into two and perform encoding processing respectively. And For example, it is assumed that the controller 171 can encode different video data by using the # 1 encoding chip 173 and the # 2 encoding chip 176 for the SP @ ML, MP @ LL, or MP @ ML. For example, in MP @ HL, HP @ HL, etc., the # 1 encode chip 173 and the # 2 encode chip 176 are used to divide one screen of one video stream into two and perform the encoding process respectively. can do.

  Based on the control of the controller 171, the input signal selection unit 172 supplies video data different from the video data supplied to the # 1 encoding chip 173 to the # 2 encoding chip 176 when the division encoding process is not executed. When the encoding process is executed, the same video data as the video data supplied to the # 1 encoding chip 173 is supplied and supplied to the # 2 encoding chip 176.

  When executing the division encoding process, the # 1 encoding chip 173 and the # 2 encoding chip 176 each recognize a portion encoded by itself of the supplied image data and execute the encoding process.

  The method of dividing the screen can be basically the same as in the decoding process described with reference to FIG.

  Here, the # 1 encode chip 173 and the # 2 encode chip 176 have been described as performing the encoding process by recognizing the portion of the supplied image data that is encoded by themselves, for example, The respective image data of the supplied video data may be divided in advance as described with reference to FIG. 10 and supplied to the # 1 encode chip 173 and the # 2 encode chip 176.

  Note that each of the images included in the input video data may be divided more than the number of encode chips, and divided into the number of encode chips provided with the plurality of divided image data. However, as described with reference to FIG. 10, each of the image data included in the input video data is encoded in each encoding chip by dividing the image data into the encoding units in which the number of encoding chips is united (not separated). Since the ratio of the image area to be referred to in the encoding of the other encoding chip in the area to be reduced is reduced, it is preferable because the process of transferring between the encoding chips of the pixels of the reference portion described later does not become complicated.

  The method for dividing the image data may be equal division or unequal division. The controller 171 is provided with a function of detecting the complexity of the image, for example, and the division encoding process is executed. When the complexity of the image is significantly different depending on the portion of the image data, the complexity of the image ( The division width of the picture (a and b in the drawing in FIG. 10) may be determined based on the encoding difficulty level.

  The # 1 encode chip 173 includes a video data input circuit 191, a buffer control circuit 192, an encoder 193, a motion compensation circuit 194, a buffer control circuit 195, an inter-chip interface (I / F) 196, and an output circuit 197. Based on the control of the controller 171, the entire supplied image data or a predetermined portion is encoded. When the division encoding process is executed, the # 1 encode chip 173 refers to the pixel data obtained by local decoding of an area that may be required as a reference image in the motion compensation of the encode process of the # 2 encode chip 176 The pixel data is supplied to the # 2 encoding chip 176, and the reference pixel data supplied from the # 2 encoding chip 176 is supplied to the stream / reference image buffer 175 to be stored and referred to as necessary, thereby performing the encoding process. Execute.

  The video buffer 174 is composed of, for example, a DRAM (Dynamic Random Access Memory) and temporarily stores video data supplied to the # 1 encoding chip 173. The stream / reference image buffer 175 is configured by, for example, a DRAM or the like, and corresponds to a stream composed of encoded frames encoded by the # 1 encode chip 173 and an encoded frame supplied from the # 2 encode chip 176. A part of local decode image (pixel data) is supplied and temporarily stored.

  The # 2 encode chip 176 includes a video data input circuit 211, a buffer control circuit 212, an encoder 213, a motion compensation circuit 214, a buffer control circuit 215, an inter-chip interface (I / F) 116, and an output circuit 217. Based on the control of the controller 171, the entire supplied image data or a predetermined portion is encoded. When the divided encoding process is executed, the # 2 encode chip 176 supplies reference pixel data by local decoding of an area required as a reference image for the encode process of the # 1 encode chip 173 to the # 1 encode chip 173, and The reference pixel data supplied from the # 1 encoding chip 173 is supplied to and stored in the stream / reference image buffer 178, and the encoding process is executed by referring to it as necessary.

  The video buffer 177 is composed of, for example, a DRAM and temporarily stores the video data supplied to the # 2 encoding chip 176. The stream / reference image buffer 178 is constituted by, for example, a DRAM or the like, and corresponds to a stream composed of encoded frames encoded by the # 2 encode chip 176 and an encoded frame supplied from the # 1 encode chip 173. A part of the local decode image (pixel data) is supplied and temporarily stored.

  When the division encoding process is executed, the synthesis processing unit 179 receives a part of the encoded frame data from the # 1 encode chip 173 and the # 2 encode chip 176, synthesizes them, and sends them to the output signal selection unit 180. Supply. When the division encoding process is not executed, the output signal selection unit 180 selects the output of the # 1 encoding chip 173, and when the division encoding process is executed, the output signal selection unit 180 selects the output of the synthesis processing unit 179 and outputs the decoded video data. Output.

  When the division encoding process is not executed, the output from the # 2 encoding chip 176 is output as it is, but when the division encoding process is executed, the output from the # 2 encoding chip 176 is supplied to the synthesis processing unit 179. However, it may not be output.

  Next, the configuration and operation of the # 1 encode chip 173 will be described.

  The video data input circuit 191 supplies the supplied video data to the buffer control circuit 192 when the division encoding process is not executed. The buffer control circuit 192 inputs the input video data to the video buffer 174 in accordance with a basic clock supplied from a clock generation circuit (not shown). Also, the video data stored in the video buffer 174 is read and output to the encoder 193.

  The encoder 193 encodes the input video data based on the MPEG syntax. Specifically, the encoder 193 performs motion compensation as necessary based on the motion compensation information supplied from the motion compensation circuit 194, and then performs discrete cosine transform (DCT) processing on a macroblock basis, The domain data is converted into frequency domain data and quantized with a quantization index Q. Then, the quantized data is subjected to variable length encoding, and the obtained encoded data is buffered in the stream / reference image buffer 175 via the buffer control circuit 195, and the quantized data is inversely quantized to perform inverse DCT. Processing is performed to obtain a local decoded image, which is buffered in the stream / reference image buffer 175 via the buffer control circuit 195.

  The motion compensation circuit 194 includes a motion detection unit and a motion compensation unit, and a difference between a target macroblock of a picture (input picture) to be compressed in the motion detection unit and a referenced picture (reference picture). A macro block that minimizes the sum of absolute values or squares of values is searched for, and a motion vector is obtained. In the motion compensation unit, a local decoded image stored in the stream / reference image buffer 175 is obtained. Motion compensation processing is performed based on the motion vector supplied from the motion detection unit.

  Specifically, when an I picture is encoded by the encoder 193, a motion vector operation is not executed, but a local decoded image is generated and used via the buffer control circuit 195 for use in encoding other pictures. Buffered in the stream / reference image buffer 175. When the P picture is encoded by the encoder 193, the motion vector calculation is performed with reference to the local decoded image buffered in the stream / reference image buffer 175 and used for encoding other pictures. For this purpose, a local decoded image is generated and buffered in the stream / reference image buffer 175 via the buffer control circuit 195. When the B picture is encoded by the encoder 193, the motion vector calculation is executed with reference to the local decoded image buffered in the stream / reference image buffer 175. The local decoded image is generated and buffered. The ring is not executed.

  In addition, when the division encoding process is executed, the video data input circuit 191 recognizes an area in the supplied video data where the encoding process is performed, and supplies the recognized area to the buffer control circuit 192. The buffer control circuit 192 inputs, to the video buffer 174, an area for encoding processing in the input video data in accordance with a basic clock supplied from a clock generation circuit (not shown). Also, the video data stored in the video buffer 174 is read and output to the encoder 193.

  The encoder 193 encodes the input video data based on the MPEG syntax. Specifically, the encoder 193 performs motion compensation as needed based on the motion compensation information supplied from the motion compensation circuit 194, and then performs discrete cosine transform (DCT) processing on a macroblock basis, The domain data is converted into frequency domain data and quantized with a quantization index Q. Then, the quantized data is subjected to variable length encoding, and the obtained encoded data is buffered in the stream / reference image buffer 175 via the buffer control circuit 195, and the quantized data is inversely quantized to perform inverse DCT. Processing is performed to obtain a local decoded image, which is buffered in the stream / reference image buffer 175 via the buffer control circuit 195.

  The motion compensation circuit 194 includes a motion detection unit and a motion compensation unit, and a difference between a target macroblock of a picture (input picture) to be compressed in the motion detection unit and a referenced picture (reference picture). A macro block that minimizes the sum of absolute values or squares of values is searched for, and a motion vector is obtained. In the motion compensation unit, a local decoded image stored in the stream / reference image buffer 175 is obtained. Motion compensation processing is performed based on the motion vector supplied from the motion detection unit.

  Specifically, when an I picture is encoded by the encoder 193, a motion vector operation is not executed, but a local decoded image is generated and used via the buffer control circuit 195 for use in encoding other pictures. Buffered in the stream / reference image buffer 175. When the P picture is encoded by the encoder 193, the motion vector calculation is performed with reference to the local decoded image buffered in the stream / reference image buffer 175 and used for encoding other pictures. For this purpose, a local decoded image is generated and buffered in the stream / reference image buffer 175 via the buffer control circuit 195. When the B picture is encoded by the encoder 193, the motion vector calculation is executed with reference to the local decoded image buffered in the stream / reference image buffer 175. The local decoded image is generated and buffered. The ring is not executed.

  The buffer control circuit 195 also inputs the local decode image supplied from the # 2 encode chip 176 via the inter-chip interface 196 to the stream / reference image buffer 175. The buffer control circuit 195 also reads out the local decoded image, which is the reference pixel data designated from the motion compensation circuit 194, from the local decoded image stored in the stream / reference image buffer 175, and supplies it to the motion compensation circuit 194. . The buffer control circuit 195 also reads the encoded data stored in the stream / reference image buffer 175 and supplies it to the output circuit 197. Also, the buffer control circuit 195 performs local decoding of a region (motion vector search range) used as a reference pixel for encoding processing of the # 2 encoding chip 176 among local decoded images stored in the stream / reference image buffer 175. The image is read out and supplied to the # 2 encode chip 176 via the inter-chip interface 196.

  The output circuit 197 generates a synchronization timing signal for outputting encoded encoded data, and reads encoded data from the stream / reference image buffer 175 via the buffer control circuit 195 based on this timing. Output.

  The functions of the video data input circuit 211 to the output circuit 217 of the # 2 encode chip 176 are basically the same as those of the video data input circuit 191 to the output circuit 197 of the # 1 encode chip 173. The operation of is basically the same as that of the # 1 encode chip 173, and thus detailed description thereof is omitted.

  Data exchange between the inter-chip interface 196 of the # 1 encode chip 173 and the inter-chip interface 216 of the # 2 encode chip 176 supplies data from the inter-chip interface 196 to the inter-chip interface 216, for example, a data bus or the like And the interface for supplying data from the inter-chip interface 216 to the inter-chip interface 196, for example, an interface such as a data bus, is not used as an independent interface (dedicated line) for sending and receiving other data. It is preferable that

  An interface for connecting the encoding chips, that is, an interface for supplying data from the interchip interface 196 to the interchip interface 216 and an interface for supplying data from the interchip interface 216 to the interchip interface 196 are independent of each other. In the case where the interface such as the data bus is not shared, the pixel data read from the stream / reference image buffer 175 by the buffer control circuit 195 is in the reverse direction (ie, from the inter-chip interface 216 to the inter-chip interface 196). The data can be sent from the inter-chip interface 196 to the inter-chip interface 216 regardless of the supply of the data. Pixel data Desa seen, the reverse (i.e., from the inter-chip interface 196 to the inter-chip interface 216) regardless of the supply of data can sent from the inter-chip interface 216 to the inter-chip interface 196. In other words, such a configuration does not require complicated address control accompanying data exchange or timing of data bus occupancy or data exchange timing, and the data transfer speed is also limited to an interface such as a data bus. It is possible to reduce the speed as compared with the case of sharing.

  Specifically, when an interface such as a data bus is shared, not only a waiting time is required when the interface is used to exchange other data, but the data is sent to another encoding chip. Before, send and receive control signals between the encoding chips for address control, timing to occupy the data bus, control of data transfer timing, etc., and make various settings for data transfer based on the transferred control signals Since this must be done, time is required for these processes. On the other hand, if the interface such as the data bus is not shared, there is no waiting time for sending / receiving other data, and no processing before sending data is required. Can be transmitted to other encoding chips at the same time, compared to the case where an interface such as a data bus is shared, etc., and the data transfer rate can be reduced.

  The interface connecting the inter-chip interface 196 and the inter-chip interface 216 is, for example, by pattern-connecting the input / output terminals of each chip on the substrate on which the # 1 encode chip 173 and the # 2 encode chip 176 are mounted. Therefore, even if each pattern is prepared independently, the hardware mounting cost required for this is very low.

  Note that the transfer of reference data for motion compensation when the division encoding process is executed is basically the same as in the case of the division decoding process described with reference to FIGS.

  Next, the encoder switching determination process will be described with reference to the flowchart of FIG.

  In step S <b> 101, the CPU 40 acquires information on the type and encoding method of the video data to be encoded supplied from the CPU 31 via the north bridge 32, the PCI bus 34, the PCI bridge 37, and the control bus 39.

  In step S102, the CPU 40 determines whether or not encoding is possible with one chip.

  Whether or not encoding is possible with one chip can be determined based on, for example, the level of difficulty of encoding determined by the profile and level.

  When it is determined in step S102 that encoding can be performed with one chip, in step S103, the CPU 40 controls the encoder unit 44 to execute normal encoding processing, and the processing is terminated.

  If it is determined in step S102 that encoding cannot be performed by one chip, in step S104, a division encoding process described later with reference to FIG.

  By such processing, it is determined whether the divided encoding processing or the normal encoding processing is executed based on various encoding conditions.

  Next, the division encoding process executed in step S104 of FIG. 25 will be described with reference to the flowchart of FIG.

  In step S141, the encoding processing units 52-1 to 52-n are supplied with image data constituting video data.

  In step S142, the supplied image data is supplied to # 1 encoder chip 173 and # 2 encoder chip 176, respectively.

  In step S143, a divided image encoding process to be described later with reference to FIG. 27 is executed.

  In step S144, the output circuit 197 of the # 1 encoder chip 173 and the output circuit 217 of the # 2 encoder chip 176 are encoded and buffered in the stream / reference image buffer 175 or the stream / reference image buffer 178. Data is read out and output to the synthesis processing unit 179.

  In step S145, the synthesis processing unit 179 receives the encoded divided image frames supplied from the output circuit 197 of the # 1 encoder chip 173 and the output circuit 217 of the # 2 encoder chip 176, and passes through the output signal selection unit 180. Output, and the process is terminated.

  By such processing, the encoding processing unit 52 described with reference to FIG. 24 can divide the image data and decode it using two decoder chips. When the encoding area is assigned so that the encoding difficulty level of one image is divided into two equal parts, the encoding processing unit 52 is twice as fast as the case where the encoding process is executed on either side. It becomes possible to execute the encoding process.

  Next, the divided image encoding process executed in step S143 in FIG. 26 will be described with reference to the flowchart in FIG.

  In step S181, the video data input circuit 191 of the # 1 encode chip 173 and the video data input circuit 211 of the # 2 encoder chip 176 receive the supply of image data constituting the video data, and also encode picture types from the controller 171. Receive the order.

  In step S182, the video data input circuit 191 of the # 1 encode chip 173 and the video data input circuit 211 of the # 2 encoder chip 176, for example, encode the range as in the case of the frame division described with reference to FIG. And the extracted portions are supplied to the buffer control circuit 192 and the buffer control circuit 212, respectively.

  In step S183, the buffer control circuit 192 and the buffer control circuit 212 buffer the supplied data in the video buffer 174 and the video buffer 177, respectively.

  In step S184, the buffer control circuit 192 and the buffer control circuit 212 read the buffered data and supply them to the encoder 193 and the encoder 213, respectively.

  In step S185, the encoder 193 and the encoder 213 determine whether the supplied data is encoded into an I picture. If it is determined in step S185 that the image is not encoded into an I picture, the process proceeds to step S190 described later.

  If it is determined in step S185 that the data is encoded into an I picture, the encoder 193 and the encoder 213 encode the supplied range in step S186.

  In step S187, the encoder 193 and the encoder 213 supply the local decoded image generated in the encoding process to the stream / reference image buffer 175 or 178 via the buffer control circuit 195 or 215 for reference.

  In step S188, the buffer control circuit 195 and the buffer control circuit 215 read the local decoded image of the part to be copied from the stream / reference image buffer 175 or 178, respectively, and transmit it to another encoder via the inter-chip interface 196 or 216. Supply to each chip.

  In step S189, the inter-chip interface 196 and the inter-chip interface 216 supply the supplied local decode images to the buffer control circuit 195 and the buffer control circuit 215, respectively, so that the buffer control circuit 195 and the buffer control circuit 215 The local decode image supplied from the encoder of No. 1 is supplied to the stream / reference image buffer 175 or 178, respectively, and the process returns to step S143 in FIG.

  If it is determined in step S185 that it is not encoded into an I picture, in step S190, the encoder 193 and the encoder 213 determine whether or not the supplied data is encoded into a P picture. If it is determined in step S190 that it is not encoded into a P picture, it is encoded into a B picture, so the process proceeds to step S195 described later.

  If it is determined in step S190 that the P picture is encoded, in step S191, the encoder 193 and the encoder 213 operate using the reference local decoded images stored in the stream / reference image buffer 175 or 178, respectively. Encode the supplied range by performing compensation.

  In step S192, the encoder 193 and the encoder 213 supply the local decoded image generated in the encoding process to the stream / reference image buffer 175 or 178 via the buffer control circuit 195 or 215 for reference.

  In step S193, the buffer control circuit 195 and the buffer control circuit 215 read the local decoded image of the part to be copied from the stream / reference image buffer 175 or 178, respectively, and transmit it to another encoder via the inter-chip interface 196 or 216. Supply to each chip.

  In step S194, the inter-chip interface 196 and the inter-chip interface 216 supply the supplied local decode images to the buffer control circuit 195 and the buffer control circuit 215, respectively, so that the buffer control circuit 195 and the buffer control circuit 215 The local decode image supplied from the encoder of No. 1 is supplied to the stream / reference image buffer 175 or 178, respectively, and the process returns to step S143 in FIG.

  If it is determined in step S190 that it is not encoded into a P picture, it is encoded into a B picture. Therefore, in step S195, the encoder 193 and the encoder 213 store reference streams stored in the stream / reference image buffer 175 or 178, respectively. By performing motion compensation using the local decoded image, the supplied range is encoded, and the process returns to step S143 in FIG. 26 and proceeds to step S144.

  By such processing, encoding processing based on the picture type is executed in each of the # 1 encoding chip 173 and the # 2 encoder chip 176. At that time, the local decoding pixel data used as the reference image in the other encoding chip is supplied to the other encoding chip, and the local decoding reference image supplied from the other encoding chip can be referred to by itself. Can be stored in a video buffer and used as a reference image.

  For example, some encoder chips can only encode low resolution with one encoder. The two encoder chips can perform a split encoding process at high resolution profile levels to prevent the encoding process from being in time or affecting the image, while the low resolution profile level. In this case, the number of input channels can be increased.

  Nonlinear editing machine operations include a digitizing operation with an encoding process and a playout operation with a decoding process. The digitizing operation and the playout operation are often not simultaneous in time. That is, the encoding process and the decoding process are often not simultaneous in time.

  For example, there is a codec chip in which an encoder and a decoder are built in one chip. In such a codec chip, since a part of the configuration of the encoder and the decoder is shared, either the encoder or the decoder can be selected. . When such codec chips are used in a non-linear editing machine, it is redundant to have the sum of the number of codec chips required by the encoder and the number of codec chips required by the decoder.

  Therefore, by making the codec usable for both the encoder and the decoder, for example, the CPU 40 can control the codec chip so that it can be switched between the encoder and the decoder. Depending on the situation, it becomes possible to change the assignment of codecs to encoding and decoding.

  Specifically, for example, at the time of playback, a codec that is not required by the encoder can be operated as a decoder so that a large number of playback tracks can be obtained. At the time of digitization, recording can be performed by operating a codec that is not required by the decoder as an encoder. A large number of channels can be taken.

  As described above, by applying the present invention, it is possible to use a plurality of decoder chips for the decoding process when the processing amount is large. As a result, for example, when a stream of a format composed of IPB pictures with a large amount of decoding processing is decoded and played back by scrubbing, by assigning a plurality of decoders to one stream decoding processing, scrubbing can be performed. The required performance can be ensured, and in the case of a format with a low processing amount, by assigning one decoder to one decoding process, the remaining decoder can be used for another decoding process, and the number of playback tracks Can be increased.

  Further, by applying the present invention, when the processing amount is large in the encoding process, a plurality of encoders can be used for the process. As a result, even when a profile level encoding exceeding the encoding processing capability of the encoder chip is required, a plurality of codecs can be allocated to the encoding processing of one video data. By assigning one encoder to encoding processing of one video data, the remaining encoder can be used for encoding processing of other video data, and the encoder can be used efficiently.

  Furthermore, it goes without saying that the present invention can also be applied to a case where a codec chip in which an encoder and a decoder are incorporated in one chip is used. Such a codec chip can change the allocation of the codec to encoding and decoding, for example, according to the operation situation. As a result, the number of playback tracks can be increased by assigning all the codecs to decoding during playback, and the number of recording channels can be increased by assigning the codecs to encoding during recording.

  Thus, by applying the present invention and using the switching means for the encoder or decoder, the number of channels can be changed according to the processing amount, and the ability of the encoder or decoder can be effectively utilized. It becomes possible. Therefore, the performance of the video apparatus can be improved with a smaller number of encoders and decoders than in the past.

  The series of processes described above can also be executed by software. The software is a computer in which the program constituting the software is incorporated in dedicated hardware, or various functions can be executed by installing various programs, for example, a general-purpose personal computer For example, it is installed from a recording medium. In this case, for example, the editing apparatus 21 described with reference to FIG. 1 includes a personal computer 201 as shown in FIG.

  In FIG. 28, a CPU (Central Processing Unit) 211 performs various processes according to a program stored in a ROM (Read Only Memory) 212 or a program loaded from a storage unit 218 to a RAM (Random Access Memory) 213. Execute. The RAM 213 also appropriately stores data necessary for the CPU 211 to execute various processes.

  The CPU 211, ROM 212, and RAM 213 are connected to each other via a bus 214. An input / output interface 215 is also connected to the bus 214.

  The input / output interface 215 includes an input unit 216 including a keyboard and a mouse, an output unit 217 including a display and a speaker, a storage unit 218 including a hard disk, and a communication unit 219 including a modem and a terminal adapter. It is connected. The communication unit 219 performs communication processing via a network including the Internet.

  A drive 220 is connected to the input / output interface 215 as necessary, and a magnetic disk 231, an optical disk 232, a magneto-optical disk 233, a semiconductor memory 234, or the like is appropriately mounted, and a computer program read from them is loaded. The storage unit 218 is installed as necessary.

  When a series of processing is executed by software, a program constituting the software may execute various functions by installing a computer incorporated in dedicated hardware or various programs. For example, it is installed from a network or a recording medium into a general-purpose personal computer or the like.

  As shown in FIG. 28, this recording medium is distributed to supply a program to the user separately from the main body of the apparatus, and includes a magnetic disk 231 (including a floppy disk) on which the program is stored, an optical disk 232 ( Package media including CD-ROM (compact disk-read only memory), DVD (including digital versatile disk), magneto-optical disk 233 (including MD (mini-disk) (trademark)), or semiconductor memory 234 In addition to being configured, it is configured by a ROM 212 storing a program and a hard disk included in the storage unit 218 supplied to the user in a state of being pre-installed in the apparatus main body.

  Further, in the present specification, the step of describing the program recorded on the recording medium is not limited to the processing performed in chronological order according to the described order, but may be performed in parallel or It also includes processes that are executed individually.

  Furthermore, the series of processes described above can also be realized by executing in parallel using a plurality of sub CPU cores. In this case, for example, the editing device 21 described with reference to FIG. 6 includes an editing system as shown in FIG.

  As shown in FIG. 29, the editing system corresponding to the editing device 21 in FIG. 6 includes an editing device 281, a storage device 283 and a plurality of video tape recorders (VTR) 284 connected to the editing device 281 and the PCI bus 282. -1 to 284-S, and a mouse 285, a keyboard 286, and an operation controller 287 for the user to perform operation input thereto.

  In this editing system, the moving image content captured in the storage device 283 can be connected to a desired state to obtain a desired edited video and audio, and the resulting edited video and edited audio are used as new clips to create a RAID ( It can be stored in a large-capacity storage device 283 made up of Redundant Arrays of Independent Disks, or can be recorded on a video tape via the video tape recorders 284-1 through 284-S. Further, still image content recorded on a video tape mounted on the video tape recorders 284-1 to 284-S can also be taken into the storage device 283.

  The editing device 281 includes a microprocessor 301, a GPU (Graphics Processing Unit) 302, an XDR (Extreme Data Rate) -RAM 303, a south bridge 304, an HDD 305, a USB interface 306, and a sound input / output codec 307.

  In the editing apparatus 281, the GPU 302, the XDR-RAM 303 and the south bridge 304 are connected to the microprocessor 301, and the HDD 305, USB interface 306, and sound input / output codec 307 are connected to the south bridge 304. A speaker 321 is connected to the sound input / output codec 307. A display 322 is connected to the GPU 302.

  In addition, a mouse 285, a keyboard 286, video tape recorders 284-1 to 284-S, a storage device 283, and an operation controller 287 are connected to the south bridge 304 via a PCI bus 282.

  The mouse 285 and the keyboard 286 receive a user operation input, and supply a signal indicating the content of the user operation input to the microprocessor 301 via the PCI bus 282 and the south bridge 304. The storage device 283 and the video tape recorders 284-1 to 284-S can record or reproduce predetermined data.

  The microprocessor 301 includes a general-purpose main CPU core 341 that executes a basic program such as an OS (Operating System), and a plurality (eight in this case) of RISC (Reduced) connected to the main CPU core 341 via an internal bus 345. Instruction Set Computer) type signal processing processors (hereinafter referred to as sub CPU cores) 342-1 to 342-8, and a memory controller 343 that performs memory control on an XDR-RAM 303 having a capacity of, for example, 256 [MByte] A multi-core configuration in which an I / O (In / Out) controller 344 that manages input / output of data to / from the south bridge 304 is integrated on one chip, and realizes, for example, an operating frequency of 4 [GHz]. .

  The microprocessor 301 of the editing device 281 plays a role of a codec such as MPEG, JPEG (Joint Photographic Experts Group) 2000, H.264 / AVC (Advanced Video Coding), and the like. Can be supplied to and stored in the HDD 305 via the south bridge 304, and the playback video of the moving image or still image content obtained as a result of decoding can be transferred to the GPU 302 and displayed on the display 322. In addition, physical operations related to codec processing are performed.

  The microprocessor 301 can also execute processing for extracting various parameters of the baseband signal or encoded stream to be processed.

  In particular, in the microprocessor 301, the eight sub CPU cores 342-1 to 342-8 each play the role of an encoder constituting the encoder unit, and the eight sub CPU cores 342-1 to 342-8 are the bases. It is possible to encode band signals simultaneously and in parallel.

  As described above, the microprocessor 301 can execute the encoding process simultaneously and in parallel by the eight sub CPU cores 342-1 to 342-8.

  Also, the eight sub CPU cores 342-1 to 342-8 of the microprocessor 301 can execute the encoding process in one part and the decoding process in the other part simultaneously and in parallel.

  For example, when an independent encoder or decoder or a codec processing device is connected to the PCI bus 282, the eight sub CPU cores 342-1 to 342-8 of the microprocessor 301 are further connected to the south bridge 304 and The processing executed by these devices can be controlled via the PCI bus 282. When these devices are connected in a plurality, or when these devices include a plurality of decoders or encoders, the eight sub CPU cores 342-1 to 342-8 of the microprocessor 301 are connected to a plurality of decoders. Alternatively, the processing executed by the encoder can be shared and controlled.

  The main CPU core 341 performs processing and management other than those performed by the eight sub CPU cores 342-1 to 342-8, and the mouse 285, the keyboard 286, or the operation via the south bridge 304 is performed. The command supplied from the controller 287 is received, and various processes according to the command are executed.

  That is, at the time of startup, the microprocessor 301 reads out a necessary application program stored in the HDD 305 based on the control program stored in the HDD 305 and develops it in the XDR-RAM 303, and thereafter, based on this application program and operator operation. And execute necessary control processing.

  In addition to final rendering processing related to texture embedding when moving the playback video of the moving image content displayed on the display 322, the GPU 302 displays a plurality of playback videos of the moving image content and still images of the still image content on the display 322 at a time. It controls coordinate transformation calculation processing for display, enlargement / reduction processing for playback images of moving image content and still images of still image content, and the like, and reduces the processing load on the microprocessor 301.

  Under the control of the microprocessor 301, the GPU 302 performs predetermined signal processing on the supplied video data of moving image content and image data of still image content, and displays the resulting video data and image data. The image signal is sent to 322 and the image signal is displayed on the display 322.

  By the way, the playback video in a plurality of video contents decoded in parallel in parallel by the eight sub CPU cores 342-1 to 342-8 in the microprocessor 301 is transferred to the GPU 302 via the bus 311. The transfer speed at this time is, for example, 30 [Gbyte / sec] at the maximum, and even a complex playback video with a special effect can be displayed at high speed and smoothly.

  On the other hand, the microprocessor 301 performs audio mixing processing on audio data among the video data and audio data of the moving image content, and the resulting edited audio data is sent via the south bridge 304 and the sound input / output codec 307. By sending the sound to the speaker 321, the sound based on the sound signal can be output from the speaker 321.

  The series of encoding processes described above can also be realized by executing or controlling in parallel using a plurality of sub CPU cores included in the microprocessor 301 of such an editing system.

  In the above-described embodiment, the editing device 21 has been described as having a decoder and an encoder. However, even when the decoder and the encoder are configured as independent devices, respectively. The present invention is applicable. For example, as shown in FIG. 30, a decoding device 371 that decodes stream data and converts it into a baseband signal, and an encoding device 372 that encodes baseband signals and converts them into stream data are configured as independent devices. May be.

  At this time, the decoding device 371 not only decodes the compressed encoded data that is the video material and supplies it to the encoding device 372, but also is partially encoded by the encoding device 372 by applying the present invention. Thereafter, the compressed encoded data generated by editing can be supplied, decoded, and converted into a baseband signal. The edited stream converted into the baseband signal is supplied to a predetermined display device and displayed, for example, or output to another device and subjected to necessary processing.

  Furthermore, in the above-described embodiment, the decoder unit 22 does not completely decode the supplied compressed encoded data, and the corresponding encoder unit 24 partially converts the corresponding portion of the non-completely decoded data. The present invention can also be applied to the case of encoding to the above.

  For example, when the decoder unit 22 only performs decoding and inverse quantization on the VLC code and has not performed inverse DCT transform, the encoder unit 24 performs quantization and variable length coding processing, but DCT transform processing Do not do. It goes without saying that the present invention can also be applied to an encoder that performs such partial encoding (encoding from an intermediate stage).

  Furthermore, in the above-described embodiment, when the baseband signal completely decoded by the decoder unit 22 is encoded to the middle stage (for example, DCT transform and quantization are performed but variable length encoding processing is performed). The decoder unit 22 is not completely decoded (for example, only decoding and inverse quantization are performed on the VLC code, and no inverse DCT transform is performed), so that the coding is performed halfway. The present invention can also be applied to the case where the encoder unit 24 further encodes the existing data to an intermediate stage (for example, quantization is performed but variable length encoding processing is not performed).

  Further, the decoding device 371 shown in FIG. 30 does not completely decode the supplied stream data, and the corresponding encoding device 372 partially encodes the corresponding part of the incompletely decoded data. Even in this case, the present invention is applicable.

  For example, when the decoding device 371 only performs decoding and inverse quantization on the VLC code and has not performed the inverse DCT transform, the encoding device 372 performs the quantization and variable length coding processing, but the DCT transform No processing is performed. In the decoding process of the decoding device 371 that performs such partial decoding processing (decoding up to the middle stage) and the encoding processing of the encoding device 372 that performs encoding (encoding from the middle stage), the present invention is applied. Needless to say, it can be applied.

  Further, when the encoding device 372 encodes the baseband signal completely decoded by the decoding device 371 to an intermediate stage (for example, DCT transformation and quantization are performed but variable length coding processing is not performed), Since the decoding device 371 has not completely decoded (for example, only decoding and inverse quantization are performed on the VLC code and no inverse DCT conversion is performed), the data encoded to the middle stage is encoded. The present invention can also be applied to a case where the encoding device 372 further encodes to an intermediate stage (for example, quantization is performed but variable length encoding processing is not performed).

  Furthermore, the encoding apparatus 31 that performs such partial decoding (executes some of the decoding process steps) and performs partial encoding (executes some of the encoding process steps). The present invention can also be applied to the transcoder 381 configured by the encoding device 372. As such a transcoder 381, for example, an editing device 382 that performs editing such as splicing, that is, an editing device having a function that can be executed by the stream splicer 25 and the effect / switch 26 of the editing device 21 described above is used. Used in cases.

  Furthermore, in the above-described embodiment, the CPU 11 and the CPU 20 are configured in different forms. However, the present invention is not limited to this, and a form configured as one CPU that controls the entire editing apparatus 21 is also conceivable. Similarly, in the above-described embodiment, the memory 13 and the memory 21 are configured in different forms. However, the present invention is not limited to this, and a form in which the editing apparatus 21 is configured as one memory is also conceivable.

  Further, in the above-described embodiment, the CPU 11 and the CPU 20, and the HDD 16, the decoder unit 22, the selector 23, and the encoder unit 24 are connected via a bridge and a bus, respectively, and integrated as an editing device. However, the present invention is not limited to this, and for example, some of these components may be connected from the outside by wire or wirelessly. In addition, they may be connected to each other in various connection forms.

  Furthermore, in the above-described embodiment, the case where the encoded stream that has been compression-encoded or the non-compressed baseband signal is stored in the HDD has been described. However, the present invention is not limited to this. The present invention can also be applied to processing using encoded streams recorded on various recording media such as an optical disk, a magneto-optical disk, a semiconductor memory, and a magnetic disk, or a baseband signal.

  Furthermore, in the above-described embodiment, the decoder unit 22, the selector 23, and the encoder unit 24 are not limited to the form mounted on the same expansion card (for example, PCI card, PCI-Express card), for example, PCI- If the transfer rate between cards is high due to technologies such as Express, they may be mounted on separate expansion cards.

  The codec executed by the decoder unit 22 and the encoder unit 24 is, for example, MPEG (including HD-LONG GOP or MPEG IMX format), JPEG (Joint Photographic Experts Group) 2000, H.264 / It plays the role of a codec such as AVC (Advanced Video Coding), and performs physical operations related to codec processing.

  In the present specification, the term “system” represents the entire apparatus constituted by a plurality of apparatuses.

  The embodiment of the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the gist of the present invention.

It is a block diagram which shows the structure of the conventional decoding apparatus. It is a figure explaining the case where the decoding apparatus of FIG. 1 tries to perform the decoding process of 2 times speed. It is a figure explaining the process in case three decoding chips are provided. It is a figure explaining the process in case 2 times decoding cannot be implement | achieved even if three decoding chips are provided. It is a figure explaining the process in the case of decoding Closed GOP with the conventional decoding apparatus. It is a block diagram which shows the structural example of the editing apparatus to which this invention is applied. It is a functional block diagram which shows the function structural example of the editing apparatus to which this invention is applied. It is a block diagram which shows the structure of the decoding process part of FIG. It is a figure for demonstrating the display screen for instruct | indicating scrub reproduction | regeneration. It is a figure for demonstrating the division | segmentation of a flame | frame. It is a figure for demonstrating transfer of the reference pixel in two decoding chips. It is a figure for demonstrating transfer of the reference pixel in two decoding chips. It is a figure for demonstrating transfer of the reference pixel in two decoding chips. It is a figure for demonstrating transfer of the reference pixel in two decoding chips. It is a figure for demonstrating transfer of the reference pixel in two decoding chips. It is a figure for demonstrating transfer of the reference pixel in two decoding chips. It is a flowchart for demonstrating a decoder switching determination process. It is a flowchart for demonstrating a division | segmentation decoding process. It is a flowchart for demonstrating a division | segmentation frame decoding process. It is a figure for demonstrating the access time to a video buffer. It is a figure explaining the order of a decoding process, and the processing speed of a decoding process. It is a figure explaining the order of a decoding process, and the processing speed of a decoding process. It is a figure explaining the order of a decoding process, and the processing speed of a decoding process. It is a block diagram which shows the structure of the encoding process part of FIG. It is a flowchart for demonstrating an encoder switching determination process. It is a flowchart for demonstrating a division | segmentation encoding process. It is a flowchart for demonstrating a division | segmentation frame encoding process. And FIG. 11 is a diagram for explaining a configuration of a personal computer. It is a figure for demonstrating the structure of the different apparatus which can apply this invention. It is a figure for demonstrating the structure of the different apparatus which can apply this invention.

Explanation of symbols

  21 Editing Device, 31 CPU, 36 HDD, 40 CPU, 42 Decoder Unit, 44 Encoder Unit, 51 Decoding Processing Unit, 53 Coding Processing Unit, 71 Controller, 72 Input Signal Selection Unit, 73 # 1 Decoding Chip, 75 Video Buffer , 76 # 2 decode chip, 78 video buffer, 79 synthesis processing unit, 96 inter-chip interface, 116 inter-chip interface, 171 controller, 172 input signal selection unit, 173 # 1 encode chip, 175 stream / reference image buffer, 176 # 2 encoding chip, 178 stream / reference image buffer, 179 synthesis processing unit, 196 inter-chip interface, 216 inter-chip interface

Claims (12)

A second codec processing means including a plurality of first codec processing means capable of dividing one screen and processing each;
Based on the difficulty level of the codec processing executed by the second codec processing unit, the plurality of first codec processing units included in the second codec processing unit respectively process different screens, or An image processing apparatus comprising: a control unit that determines whether to divide one screen and execute a codec in each. The second codec processing means executes a decoding process;
The control means includes a plurality of first codec processing means included in the second codec processing means based on whether or not the decoding process is performed on a stream composed of only I pictures. The image processing apparatus according to claim 1, wherein it is determined whether to process different screens or to divide one screen and execute a codec in each screen. The second codec processing means executes a decoding process;
In the plurality of first codec processing units included in the second codec processing unit, the control unit may determine whether the decoding process is a predetermined reproduction process with a low load of the decoding process. The image processing apparatus according to claim 1, wherein it is determined whether to process different screens or to divide one screen and execute codec in each of them. The second codec processing means executes a decoding process;
The control means processes different screens in the plurality of first codec processing means included in the second codec processing means based on whether or not the decoding process is executed by thinning out for each frame. The image processing apparatus according to claim 1, wherein the image processing apparatus determines whether the codec is to be executed by dividing one screen. The second codec processing means executes a decoding process;
The control means includes the plurality of first codec included in the second codec processing means based on whether the decoding process is a decoding process for backward reproduction, high-speed reproduction, or scrub reproduction. The image processing apparatus according to claim 1, wherein the codec processing means determines whether to process different screens or to divide one screen and execute codecs on each screen. The second codec processing means performs an encoding process,
The control unit causes each of the plurality of first codec processing units included in the second codec processing unit to process different screens based on the profile and level in the encoding process, or to process one screen. The image processing apparatus according to claim 1, wherein the image processing apparatus determines whether to divide and execute a codec in each of them. The first codec processing means of the second codec processing means is:
Codec execution means for executing a codec in a predetermined area of the screen;
Among the reference pixel data obtained as a result of its own processing, pixel data necessary for the codec processing of the other first codec processing unit is supplied to the other first codec processing unit, and other Among the reference pixel data obtained by the codec processing executed in the first codec processing means, the pixel for obtaining the pixel data necessary for its own processing from the other first codec processing means Data exchange means, and
The codec execution unit executes the codec process by referring to the pixel data obtained as a result of its own processing and the pixel data acquired from the other first codec processing unit by the pixel data transfer unit. The image processing apparatus according to claim 1. Memory for controlling storage of pixel data obtained as a result of codec processing executed by the codec execution unit or pixel data acquired from the other first codec processing unit by the pixel data transfer unit to the storage unit Further comprising control means,
The image processing apparatus according to claim 7, wherein the codec execution unit executes codec processing by referring to pixel data whose storage in the storage unit is controlled by the storage control unit. The pixel data necessary for the codec processing of the other first codec processing means is relative to a motion compensation reference area included in another predetermined area coded by the other first codec processing means on the screen. Pixel data included in the motion vector search range,
The pixel data necessary for the codec processing of the codec execution unit is pixel data included in a motion vector search range with respect to a motion compensation reference region included in the predetermined region to be codeced by the codec execution unit on the screen. The image processing apparatus according to claim 7. An image processing method for executing a codec using a plurality of codec processing means capable of dividing one screen and processing each screen,
An image processing method including a step of deciding whether to process different screens in each of the plurality of codec processing units or to divide one screen and execute a codec in each of the plurality of codec processing units based on the difficulty level of the codec processing. A program for causing a computer to execute codec processing using a plurality of codec processing means capable of dividing one screen and processing each screen,
Based on the degree of difficulty of the codec processing, the plurality of codec processing means determine whether to process different screens or to divide one screen and execute the codec in each computer. The program to be executed.   A recording medium on which the program according to claim 11 is recorded.

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