JP2008085479A - Solid-state imaging apparatus and digital camera - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a solid-state imaging apparatus capable of suppressing the fluctuations in the gain, while realizing high gain. <P>SOLUTION: The imaging apparatus 100 comprises a pixel array 1, wherein a plurality of unit cells for outputting pixel signals are arrayed; a column amplifier 5 for amplifying and outputting the pixel signals for each column; a noise cancellation part 6 for removing and outputting an offset voltage; a horizontal read part 7 for successively selecting and outputting the pixel signals for each column; and an output amplifier 9 for amplifying and outputting the pixel signals outputted from the horizontal read part. The column amplifier includes a current source transistor to be a current source for each column and a first amplifier transistor for amplifying the pixel signals; the output amplifier includes a load transistor to be a load and a second amplifier transistor for amplifying the pixel signals outputted from the horizontal read part; and all of the current source transistor, the first amplifier transistor, the load transistor and the second amplifier transistor are constituted of MOS transistors formed in the same process. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device in which unit cells for photoelectric conversion upon incidence of light are arranged one-dimensionally or two-dimensionally on a semiconductor substrate, and a digital camera including the solid-state imaging device, in particular, gain variation. It is related with the technique for suppressing.

In recent years, imaging devices such as mobile phones with digital cameras have been widely used.
Since these image pickup devices are required to reduce power consumption in order to reduce weight and extend continuous use time, many of them are equipped with MOS type image pickup devices that consume significantly less power than CCD type image pickup devices. .
Here, the signal readout method of the CMOS image sensor is generally a column parallel output type in which one row in the pixel array is selected and simultaneously read in the column direction.

The column parallel output type signal output circuit includes a method of reading out pixel output by sampling with a switched capacitor, a method of reading by mounting an amplifier for each column, and a method of providing an AD converter for each column. There are things.
For example, a single-ended amplifier is used for reading by mounting an amplifier for each column, and details thereof are disclosed in Patent Document 1 and Patent Document 2.

Patent Document 1 describes a single-ended amplifier including a current source MOS transistor and an amplification MOS transistor. In such a configuration, only the signal component is extracted by removing the offset voltage for each pixel. It is described that the read gain can be arbitrarily set by the ratio of the capacitive elements.
However, the circuit configuration of the common source amplifier as described in Patent Document 1 has a disadvantage that the gain is low.

Patent Document 2 discloses a solid-state amplifier in which a cascode-connected transistor is added to the circuit configuration of a common-source amplifier to overcome the disadvantage of low gain in the circuit configuration of a common-source amplifier as in Patent Document 1. An imaging device is described.
However, the addition of a transistor or a current source for controlling a cascode-connected transistor increases the number of elements constituting the circuit and the number of wirings between the elements.
Japanese Patent Laid-Open No. 5-207220 JP 2005-252529 A

In recent CMOS image sensors, the number of pixels is miniaturized because the number of pixels and the chip size are rapidly decreasing. If the size per pixel is miniaturized, the amount of received light decreases, so that the sensitivity tends to decrease, and it is necessary to further increase the gain of the amplifier in the output stage.
However, the gain variation becomes more significant as the gain of the amplifier is increased.

In addition, when a plurality of amplifiers of the same type are used, gain fluctuations with respect to an increase in input voltage overlap, and the total gain fluctuations increase synergistically, and good sensitivity cannot be obtained over the entire pixel signal.
The first object of the present invention is to provide a solid-state imaging device capable of suppressing gain variation while realizing a high gain, and a second object of bringing the fluctuation of the total gain close to flat. And

  In order to achieve the above object, a solid-state imaging device according to the present invention is connected in common to a pixel array unit in which a plurality of unit cells that output pixel signals corresponding to the amount of received light are arranged, and one column of unit cells. A column amplifier unit that amplifies and outputs a pixel signal output from one of the unit cells in the corresponding column for each column, and is connected to the column amplifier on a one-to-one basis. A noise canceling unit for removing the offset voltage from the pixel signal and outputting the output, a horizontal reading unit connected to the noise canceling unit and sequentially selecting and outputting the pixel signal for each column output from the noise canceling unit; A solid-state imaging device including an output amplifier connected to the horizontal readout unit and configured to amplify and output a pixel signal output from the horizontal readout unit, wherein the column amplifier is a current that is a current source for each column. source A first amplifying transistor for amplifying the pixel signal; and the output amplifier includes a load transistor as a load and a second amplifying transistor for amplifying the pixel signal output from a horizontal readout unit, The current source transistor, the first amplifying transistor, the load transistor, and the second amplifying transistor are all configured by MOS transistors formed in the same process.

With the configuration described in the means for solving the problem, it is possible to suppress gain variation due to manufacturing variation.
Therefore, gain variation can be suppressed while realizing a high gain.
Here, in the solid-state imaging device, all of the current source transistor, the first amplification transistor, the load transistor, and the second amplification transistor may be N-channel MOS.

As a result, the MOS transistors for amplification can be unified to N-channel MOS.
Here, in the solid-state imaging device, all of the current source transistor, the first amplification transistor, the load transistor, and the second amplification transistor may be an enhancement type.

Thereby, the MOS transistors for amplification can be unified into the enhancement type.
Here, in the solid-state imaging device, in the output amplifier, a voltage higher than a power supply voltage applied to a source terminal of the load transistor is applied to a gate terminal of the load transistor. You can also.

This is particularly useful because the voltage drop caused by the load transistor can be suppressed.
Here, in the solid-state imaging device, in the column amplifier, the output potential of the first amplification transistor increases as the pixel signal increases, and in the output amplifier, the output potential of the second amplification transistor increases. The pixel signal may be reduced as it increases.

Thereby, since the polarity of the column amplifier and the polarity of the output amplifier are opposite, the weak point of the gain characteristic between the column amplifier and the output amplifier can be compensated.
Here, in the solid-state imaging device, the output amplifier further includes a level shift transistor connected in front of the second amplification transistor, and the input / output characteristics of the output amplifier are determined by the level shift transistor and the column amplifier. Compared to the input / output characteristics, the shift to the higher input potential side is also possible.

As a result, one amplifier is used in a direction where the gain decreases from a high gain to the pixel signal, and the other amplifier is used in a direction where the gain increases from a low gain to the pixel signal. Therefore, the fluctuation of the total gain can be made close to flat.
Here, in the solid-state imaging device, in the column amplifier, the output potential of the first amplification transistor decreases as the pixel signal increases, and in the output amplifier, the output potential of the second amplification transistor decreases. The pixel signal increases as the pixel signal increases.

Thereby, since the polarity of the column amplifier and the polarity of the output amplifier are opposite, the weak point of the gain characteristic between the column amplifier and the output amplifier can be compensated.
Here, in the solid-state imaging device, the column amplifier further includes a level shift transistor connected in front of the first amplification transistor, and the input / output characteristics of the column amplifier are determined by the level shift transistor and the output amplifier. Compared to the input / output characteristics, the shift to the higher input potential side is also possible.

  As a result, one amplifier is used in a direction where the gain decreases from a high gain to the pixel signal, and the other amplifier is used in a direction where the gain increases from a low gain to the pixel signal. Therefore, the fluctuation of the total gain can be made close to flat.

(Embodiment 1)
<Configuration>
FIG. 1 is a diagram showing an overview of an imaging apparatus 100 according to Embodiment 1 of the present invention.
As shown in FIG. 1, the imaging apparatus 100 according to the first embodiment of the present invention includes a pixel array 1, a timing generator 2, a vertical scanning circuit 3, a load circuit 4, a column amplifier 5, a noise canceling unit 6, and a horizontal reading unit 7. , A horizontal scanning circuit 8 and an output amplifier 9.

The details of the other components except for the timing generator 2, the column amplifier 5, and the noise canceling unit 6 are the same as in Patent Document 2.
In the pixel array 1, unit cells that output a reset voltage, which is a voltage at initialization, and a read voltage, which is a voltage at the time of reading, to the vertical signal lines VLA1 to VLAm for each column are arranged one-dimensionally or two-dimensionally. Although the description is simplified here, the actual number of pixels is several thousand in one dimension and several hundred thousand to several million in two dimensions.

The timing generator 2 is a peripheral circuit that supplies a control signal to the vertical scanning circuit 3, the column amplifier 5, the noise canceling unit 6, the horizontal scanning circuit 8, and the output amplifier 9, and drives and controls it. When an imaging instruction is input, the luminance information is sequentially read from all unit cells after an appropriate exposure time has elapsed.
Here, from the timing generator 2, a reset pulse (initialization signal: RESET) and a read pulse (read pulse: READ) are sent to the vertical scanning circuit 3, and a sampling pulse (SP) and clamp are sent to the noise canceling unit 6. A pulse (CP) is supplied at a determined timing, and the transistors corresponding to these control pulses are opened and closed (OFF / ON).

The vertical scanning circuit 3 includes three control lines (L1 to Ln) of “RESET”, “READ1”, and “READ2” for each horizontal row, and for each pixel of the pixel array 1, Controls reset (initialization) and read (read).
The load circuit 4 is connected to one identical circuit for each vertical column, and applies a load to each pixel of the pixel array 1 in units of columns in order to read out the output potential.

The column amplifier 5 is connected to one identical circuit for each column, amplifies the reset voltage and read voltage for each column from the pixel array 1, and sequentially outputs them to the vertical signal lines VLB1 to VLBm for each column. .
FIG. 2 is a diagram showing a circuit configuration of the column amplifier 5 according to the first embodiment of the present invention.
As shown in FIG. 2, the column amplifier 5 is a negative amplifier in which the output potential increases as the pixel signal increases, and is connected between the power supply voltage VDD and the output terminal and serves as a current source transistor T <b> 1. It includes an amplifying transistor T2 that amplifies the pixel signal, a reset transistor T3 that closes the gate terminal and the output terminal of the amplifying transistor T2 for a certain period of time, and a capacitor C1 that stores luminance information. Here, a voltage Vb1 higher than the power supply voltage is applied to the gate of the current source transistor T1, a reset signal line is connected to the gate of the reset transistor T3, an input signal line is connected to the capacitor C1, and the current source transistor An output signal line is connected between T1 and the amplification transistor T2.

FIG. 3 is a diagram showing input / output characteristics (Vin1-Vout1 characteristics) of the column amplifier 5. In FIG.
As shown in FIG. 3, the input / output characteristics of the column amplifier 5 are not uniform with respect to the input, and when the input potential (Vin1) is in the middle, the output potential (Vout1) is sufficient according to the input potential (Vin). However, when the input potential (Vin1) is low and high, the amount of change in the output potential (Vout1) with respect to the input potential (Vin1) is small.

  In this embodiment, in the state where the input potential (Vin1) is VA1 in FIG. 3, the gate of the reset transistor T3 in FIG. 2 is closed for a predetermined time to be reset, and then the amount of change in the base potential of the amplification transistor T2 (ΔVin1 ) To obtain an amount of fluctuation (ΔVout1) of the output potential, and an operation region is from VA1 to VB1 in FIG. 3 (thick arrow in FIG. 3).

Here, since the column amplifier 5 is a negative amplifier, the input voltage Vin1 goes in the negative direction as time t elapses after reset.
FIG. 4 is a diagram illustrating the gain characteristics (Vin1-G1 characteristics: G1 = ΔVout1 / ΔVin1) of the column amplifier 5.
As shown in FIG. 4, the gain of the column amplifier 5 is not constant with respect to the input, and the gain G1 corresponds to the slope of the Vin1-Vout1 characteristic shown in FIG. 3, so that the input potential (Vin1) is in the middle. When the gain G1 is high and the input potential (Vin1) is low and high, the gain G1 is low.

  In the present embodiment, the highest gain GA1 is obtained in the input voltage Vin1a at the time of VA1 (FIG. 3) having the largest slope of the Vin1-Vout1 characteristic, and the column amplifier 5 is a negative amplifier. The gain G1 decreases as the value goes in the negative direction, and the lowest gain GB1 is obtained in the input voltage Vin1b at the time of VB1 (FIG. 3) (thick line arrow in FIG. 4).

The noise cancellation unit 6 outputs luminance information indicating a difference between the reset voltage and the read voltage output for each column from the column amplifier 5 to the vertical signal lines VLC1 to VLCm for each column.
The horizontal readout unit 7 includes a horizontal signal line HL and switches SW1 to SWm that switch connections between the horizontal signal line HL and the vertical signal lines VLC1 to VLCm based on the control of the horizontal scanning circuit 8, and a noise canceling unit. The luminance information for each column output from 6 is selectively output to the horizontal signal line HL.

The horizontal scanning circuit 8 sequentially switches the switches SW <b> 1 to SWm of the horizontal reading unit 7, connects each vertical signal line to the horizontal signal line HL in order, and controls reading of luminance information for each column.
The output amplifier 9 is connected to the horizontal signal line HL, amplifies the luminance information from the horizontal readout unit 7, and outputs the captured image signal to the outside.
FIG. 5 is a diagram showing a circuit configuration of the output amplifier 9 according to the first embodiment of the present invention.

  As shown in FIG. 5, the output amplifier 9 is a positive amplifier in which the output potential decreases as the pixel signal increases, and the input signal characteristics of the output amplifier 9 are changed by changing the voltage level of the input signal. Level shift transistors T4 and T5 that shift to a higher input potential side, load transistor T6 that is connected between the power supply voltage VDD and the output terminal, and an input signal whose voltage has been changed. It includes an amplifying transistor T7 for amplifying, a reset transistor T8 for closing and resetting the gate terminal and output terminal of the level shift transistor T5 for a certain period of time, and a capacitor C2 for storing luminance information. Here, the gate of the load transistor T6 is connected to the source and the power supply voltage VDD is applied, the reset signal line is connected to the gate of the reset transistor T8, the input signal line is connected to the capacitor C2, and the load transistor T6 An output signal line is connected between the amplification transistors T7.

Further, if the types of transistors used in the column amplifier 5 and the output amplifier 9 are unified to the same type of transistors such as N-channel MOS and enhancement MOS, or are constituted by MOS transistors formed in the same process, it is manufactured. It is desirable in terms of characteristics because variations are uniform.
In particular, for reasons such as the manufacturing process and the superiority of the output potential, the current source transistor and the amplification transistor of the column amplifier, and the amplification transistor of the output amplifier are configured with an enhancement type N-channel MOS and the load of the output amplifier Since transistors are generally composed of depletion MOS, if the gain of the amplifier is increased with the same configuration, manufacturing variations due to different types of transistors affect the disorder and the total gain variation is significant. In this embodiment, at least two of the load transistor T6 and the amplification transistor T7 of the output amplifier 9, or the current source transistor T1 and the amplification transistor T2 of the column amplifier 5, and the output are generated in this embodiment. Load transistor of amplifier 9 6 and the amplifier transistor T7 are unified with the same type of transistors such as N-channel MOS and enhancement MOS, or are formed by MOS transistors formed in the same process, thereby suppressing variations in gain due to manufacturing variations. To do.

FIG. 6 is a diagram showing input / output characteristics (Vin2-Vout2 characteristics) of the output amplifier 9. In FIG.
As shown in FIG. 6, the input / output characteristics of the output amplifier 9 are not uniform with respect to the input, and the output potential (Vout2) is sufficient according to the input potential (Vin2) when the input potential (Vin2) is in the middle. However, when the input potential (Vin2) is low and high, the change amount of the output potential (Vout2) with respect to the input potential (Vin2) is small.

Further, the input / output characteristics of the output amplifier 9 are caused by voltage fluctuation (Vth) due to the level shift transistor T4, compared with the input / output characteristics (Vin1-Vout1 characteristics) of the column amplifier 5 indicated by the dotted line on the left in FIG. The corresponding shift is made to the higher input voltage side.
In the present embodiment, in a state where the input potential (Vin2) is VA2 in FIG. 6, the reset transistor T8 in FIG. 5 is reset by opening the gate of the reset transistor T8 for a certain period of time, and then the amount of change in base potential of the level shift transistor T4 ( The amount of change in output potential (ΔVout2) corresponding to ΔVin2) is obtained, and the region from VA2 to VB2 in FIG. 6 is the operation region (thick arrow in FIG. 6).

Here, since the output amplifier 9 is a positive amplifier, the input voltage Vin2 goes in the positive direction as time t elapses after reset.
FIG. 7 is a diagram illustrating a gain characteristic (Vin2-G2 characteristic: G2 = ΔVout2 / ΔVin2) of the output amplifier 9.
As shown in FIG. 7, the gain of the output amplifier 9 is not constant with respect to the input, and the gain G2 corresponds to the slope of the Vin2-Vout2 characteristic shown in FIG. 6, so the input potential (Vin2) is around the middle. When the gain G2 is high and the input potential (Vin2) is low and high, the gain G2 is low.

  In the present embodiment, the highest gain GA2 is obtained in the input voltage Vin2a when the slope of the Vin2-Vout2 characteristic is small VA2 (FIG. 6), and the output amplifier 9 is a positive amplifier. The gain G2 increases toward the positive direction, and the highest gain GB2 is obtained at the input voltage Vin2b at the time of VB2 (FIG. 6) where the slope of the Vin2-Vout2 characteristic is the largest (thick arrow in FIG. 6).

FIG. 8 is a diagram illustrating the total gain characteristic (Vin1-Gt characteristic: Gt = G1 × G2).
The total gain Gt shown in FIG. 8 is a product of the gain G1 of the column amplifier 5 shown in FIG. 4 and the gain G2 of the output amplifier 9 shown in FIG. 7, and the gain of the column amplifier 5 is the pixel signal gain. Since there is a characteristic that decreases with an increase and the gain of the output amplifier 9 has a characteristic that increases with an increase in pixel signal, the characteristics of each other are canceled, and the total gain Gt can be made almost flat overall.

In the present embodiment, the column amplifier 5 is a negative amplifier and the output amplifier 9 is a positive amplifier, so that the total gain can be made almost flat over the whole, but the characteristics of the column amplifier 5 and the output amplifier 9 The column amplifier 5 may be a positive amplifier and the output amplifier 9 may be a negative amplifier as long as the characteristics are opposite.
<Modification 1>
FIG. 9 is a diagram showing a circuit configuration of the output amplifier 10 in Modification 1 of the present invention.

The output amplifier 10 shown in FIG. 9 is obtained by changing a part of the output amplifier 9 of the first embodiment, except that a voltage Vb2 higher than the power supply voltage VDD is applied to the gate of the load transistor T6. Other parts are the same as those in the first embodiment.
By doing so, the upper limit value of the output signal of the output amplifier 10 can be increased, and the dynamic range can be expanded.

Note that when the load transistor T6 and the amplification transistor T7 are formed of enhancement MOSs, the voltage drop in the load transistor T6 can be suppressed, which is particularly useful.
<Summary>
As described above, according to Embodiment 1 and Modification 1 of the present invention, the types of transistors for amplification in the column amplifier and the output amplifier are unified, or the transistors are formed in the same process. Variation in gain due to the above can be suppressed.

  In addition, since the polarities of the column amplifier and the output amplifier can be reversed to compensate for each other's gain characteristics, the total gain can be made almost flat in general.

  The present invention can be applied to imaging devices such as a video camera and a digital still camera. According to the present invention, in a solid-state imaging device used for the imaging device, it is possible to suppress variations in output for each product while realizing a high gain, and to make the total gain almost flat throughout, thereby improving the image quality of the imaging device. Therefore, its industrial utility value is extremely high.

It is a figure which shows the outline | summary of the imaging device 100 in Embodiment 1 of this invention. It is a figure which shows the circuit structure of the column amplifier 5 in Embodiment 1 of this invention. 6 is a diagram showing input / output characteristics of a column amplifier 5. FIG. 6 is a diagram illustrating gain characteristics of the column amplifier 5. FIG. It is a figure which shows the circuit structure of the output amplifier 9 in Embodiment 1 of this invention. 4 is a diagram showing input / output characteristics of an output amplifier 9. FIG. 6 is a diagram illustrating gain characteristics of an output amplifier 9. FIG. It is a figure which shows a total gain characteristic. It is a figure which shows the circuit structure of the output amplifier 10 in the modification 1 of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Pixel array 2 Timing generator 3 Vertical scanning circuit 4 Load circuit 5 Column amplifier 6 Noise cancellation part 7 Horizontal readout part 8 Horizontal scanning circuit 9 Output amplifier 10 Output amplifier 100 Image pick-up device T1 Current source transistor T2 Amplification transistor T3 Reset transistor T4 Level shift Transistor T5 Level shift transistor T6 Load transistor T7 Amplification transistor T8 Reset transistor C1 Capacitor C2 Capacitor

Claims (8)

A pixel array unit in which a plurality of unit cells that output pixel signals according to the amount of received light are arranged;
A column amplifier unit commonly connected to one column of unit cells and amplifying and outputting a pixel signal output from any of the unit cells in the corresponding column for each column;
A noise canceling unit that is connected to the column amplifier on a one-to-one basis and that outputs an offset voltage from a pixel signal for each column and unit cell;
A horizontal readout unit connected to the noise cancellation unit and sequentially selecting and outputting pixel signals for each column output from the noise cancellation unit;
A solid-state imaging device including an output amplifier connected to the horizontal readout unit and amplifying and outputting a pixel signal output from the horizontal readout unit;
The column amplifier includes, for each column, a current source transistor that becomes a current source and a first amplification transistor that amplifies the pixel signal,
The output amplifier includes a load transistor serving as a load, and a second amplification transistor for amplifying a pixel signal output from the horizontal readout unit,
The solid-state imaging device, wherein all of the current source transistor, the first amplification transistor, the load transistor, and the second amplification transistor are formed by MOS transistors formed in the same process. 2. The solid-state imaging device according to claim 1, wherein all of the current source transistor, the first amplification transistor, the load transistor, and the second amplification transistor are N-channel MOSs. 2. The solid-state imaging device according to claim 1, wherein all of the current source transistor, the first amplification transistor, the load transistor, and the second amplification transistor are of an enhancement type. In the output amplifier,
The solid-state imaging device according to claim 1, wherein a voltage higher than a power supply voltage applied to a source terminal of the load transistor is applied to a gate terminal of the load transistor. In the column amplifier, the output potential of the first amplification transistor increases as the pixel signal increases, and in the output amplifier, the output potential of the second amplification transistor increases as the pixel signal increases. The solid-state imaging device according to claim 1, wherein the solid-state imaging device is reduced. The output amplifier is
And a level shift transistor connected in front of the second amplification transistor,
6. The solid-state imaging device according to claim 5, wherein the input / output characteristics of the output amplifier are shifted to a higher input potential side by the level shift transistor than the input / output characteristics of the column amplifier. . In the column amplifier, the output potential of the first amplification transistor decreases as the pixel signal increases, and in the output amplifier, the output potential of the second amplification transistor increases as the pixel signal increases. The solid-state imaging device according to claim 1, wherein the solid-state imaging device increases. The column amplifier is
And a level shift transistor connected in front of the first amplification transistor,
The solid-state imaging device according to claim 7, wherein the input / output characteristics of the column amplifier are shifted to a higher input potential side by the level shift transistor than the input / output characteristics of the output amplifier. .

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