JP2008084496A - Semiconductor storage device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To easily reserve the operation margin during write operation in a DRAM and the like for which a high-frequency operation is required. <P>SOLUTION: For example, a WENB generation circuit 18-1 provided within a read-write control circuit generates a pulse PULSE having an activation period regulated by an RC delay section 18a comprising a resistance element R and a capacitor element C synchronized with an internal clock CLKIN. The generated pulse PULSE is then inverted by an inverter circuit INVd of an output section and is outputted as a write activation signal WENB to inactivate the pulse PULSE in a write operation period (activation period) of SA. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor memory device, for example, a semiconductor memory device such as a DRAM (Dynamic Random Access Memory) that requires high-frequency operation.

  In recent semiconductor memory devices, particularly semiconductor memory devices that require high-frequency operation, a write period (hereinafter referred to as SA write operation period) to the bit line by the sense amplifier (SA) is incorporated regardless of the operation frequency. This is uniquely defined by the activation period of the write pulse generated based on the output of the RC delay circuit.

  For example, in a data write operation of a semiconductor memory device, when a write pulse WENB defined by an RC delay circuit in the memory and having a certain activation period is activated, a write buffer in the memory is synchronized with the activation. The write buffer activation signal WBUFENB that activates the signal is activated. The write buffer drives the complementary data line DQt / c in the memory during the activation period of the write buffer activation signal WBUFENB, and equalizes the complementary data line DQt / c during the inactivation period of the write buffer activation signal WBUFENB. On the other hand, the CSL control circuit in the memory activates the column select strobe signal CSL in accordance with the address given during the activation period of the write pulse WENB. That is, the SA write operation period is a period in which the activation period of the column select strobe signal CSL and the drive period of the complementary data line DQt / c overlap, and are defined by the write pulse WENB as described above.

  However, as in the prior art, the SA write operation period is defined by the activation period of the write pulse generated based on the output of the RC delay circuit. It will be a disadvantage. For example, the pulse generation circuit requires a certain amount of reset time, but this reset time is included in the cycle time during the write operation. The delay due to the RC delay circuit is less dependent on the power supply voltage than the SA write operation determined by the capability of the transistor.

  As described above, even if the operation frequency is relaxed, no change occurs in the SA write operation period. Therefore, if a sufficient SA write operation period is ensured at the time of a low voltage required for a screening test or the like, a write pulse having an unnecessarily long activation period is generated at a medium voltage, which is used as a product specification voltage. In many cases, high-speed operation at medium voltage is limited. Further, when considering the process variation of the RC delay circuit, it is necessary to define a write operation period with a further margin with respect to the actual capability of the SA, thereby limiting the high-speed operation.

It has already been proposed that a semiconductor memory device can generate a write pulse that compensates for memory cell device characteristics (see, for example, Patent Document 1).
JP 07-153275 A

  An object of the present invention is to provide a semiconductor memory device that can prevent a high-speed operation from being rate-limited and can easily secure an operation margin during a write operation.

  According to one aspect of the present invention, a memory cell for storing data, a sense amplifier for writing the data to the memory cell, and a pulse for generating a pulse that is activated for a certain period in synchronization with an internal clock A generation circuit, and an output circuit that outputs a write activation signal that inverts the pulse generated by the pulse generation circuit and sets a deactivation period of the pulse as a write operation period of the sense amplifier. A featured semiconductor memory device is provided.

  With the above configuration, it is possible to provide a semiconductor memory device that can prevent a high-speed operation from being rate-limited and can easily secure an operation margin during a write operation.

  Embodiments of the present invention will be described below with reference to the drawings. However, it should be noted that the drawings are schematic and dimensional ratios and the like are different from actual ones. Moreover, it is a matter of course that portions having different dimensional relationships and ratios are included between the drawings.

[First Embodiment]
FIG. 1 shows a basic configuration of a semiconductor memory device (semiconductor memory device) according to a first embodiment of the present invention. Here, a DRAM that requires high-frequency operation will be described as an example.

  As shown in FIG. 1, the cell array 11 includes a row decoder unit 12 that selects a word line WL <n> (n =..., I−1, i, i + 1,. A sense amplifier (SA) unit 13 for reading / writing is connected. The SA unit 13 includes a plurality of SAs, and a CSL control circuit 14 adjacent to the SA unit 13 selects a bit line pair BLt / c connected to the SAs and SAs.

  On the other hand, the external clock CLK is taken in by the clock buffer 15 and used to generate the internal clock CLKIN. The address ADD input from the outside is taken into the address buffer 16 in synchronization with the internal clock CLKIN. Of the address ADD, the row address is supplied to the row decoder unit 12 and the column address (signal CADD) is supplied to the CSL control circuit 14.

  A read / write command RD / WT inputted from the outside is taken into the command buffer 17 in synchronization with the internal clock CLKIN. The read / write command RD / WT (or internal write command signal WC) is supplied to the read / write control circuit 18, the CSL control circuit 14, the write buffer control circuit 19 and the like together with the internal clock CLKIN to control these circuits. To do.

  On the other hand, the write data on the external input write data DIN is supplied to the I / O (input / output) buffer 20 and then sent to the write buffer unit 21 through the write data line WDATA. Further, the write data is transmitted to the SA unit 13 through the complementary data line DQt / c.

  FIG. 2 shows an example of connection between the SA and the memory cell in the semiconductor memory device having the configuration shown in FIG. 1, focusing on one write buffer. In other words, the cell array 11 includes a plurality of word lines WL <n> and a plurality of bit line pairs BLt / c, and an intersection of the word line WL <n> and one of the bit line pairs BLt / c ( In this example, memory cells CL are arranged at the intersections of the word lines WL <i> and the bit lines BLt and the intersections of the word lines WL <i + 1> and the bit lines BLc. Of the memory cells CL on the row address selected by the arbitrary word line WL <n>, the memory cells CL belonging to the bit line pair BLt / c connected to the SA 13a selected by the column address strobe signal CSL. The data is read / written by SA13a.

  Usually, a plurality of cell arrays 11 exist in the memory according to the memory capacity of data to be stored.

  Each SA 13a constituting the SA unit 13 reads data on the bit line pair BLt / c onto the complementary data line DQt / c, or writes write data on the complementary data line DQt / c to the bit line pair BLt / c. (The bit line pair BLt / c is driven according to the write data). Normally, the SA 13a is connected to each pair of complementary data lines DQt / c, and the CSL gate pair 14a corresponding to the SA 13a selected by the column address strobe signal CSL is turned on, whereby the selected SA 13a and the complementary data line are connected. Data is read / written from / to DQt / c.

  For example, when the internal write command signal WC is activated by the command buffer 17, the CSL control circuit 14 activates the column address strobe signal CSL selected by the column address signal CADD for controlling the CSL gate pair 14 a. . The activation period of the column address strobe signal CSL is an activation period in which the write activation signal WENB supplied from the read / write control circuit 18 is at a high (H) level.

  When the internal write command signal WC is activated, the write buffer control circuit 19 activates a write buffer activation signal WBUFENB for controlling the write buffer 21a. In the present embodiment, the activation period of the write buffer activation signal WBUFENB is an activation period in which the write activation signal WENB is at the H level.

  The write buffer unit 21 is composed of a plurality of write buffers 21a. Each write buffer 21a latches write data on the write data line WDATA in synchronization with the write buffer activation signal WBUFENB, and at the same time, complementary data lines DQt / Write data to c. Further, when the write buffer activation signal WBUFENB becomes inactive, the complementary data line DQt / c is equalized.

  Normally, there are as many write buffers 21a in the memory as there are bits corresponding to the required data transfer rate.

  The write activation signal WENB is generated by the WENB generation circuit 18-1 in the read / write control circuit 18.

  FIG. 3 shows a configuration example of the WENB generation circuit 18-1. The WENB generation circuit 18-1 is provided in the read / write control circuit 18, and generates a write activation signal WENB synchronized with the internal clock CLKIN. In the case of the present embodiment, the WENB generation circuit 18-1 has an RC delay unit (pulse generation circuit) 18a composed of a resistance element R and a capacitance element C, and an activation period defined by the RC delay unit 18a ( A pulse PULSE having an H level is generated. The generated pulse PULSE is inverted by an inverter circuit (output circuit) INVd arranged in the output unit and output as a write activation signal WENB. That is, the inactivation period (L level) of the generated pulse PULSE becomes the activation period of the write activation signal WENB.

  In addition to the RC delay unit 18a and the inverter circuit INVd, the WENB generation circuit 18-1 includes, for example, a P-channel Metal Oxide Semiconductor (PMOS) transistor MP10, an N-channel MOS (NMOS) transistor MN10, and inverter circuits INVa and INVb. , INVc, and a flip-flop unit F / F composed of a NANDa circuit and a NANDb circuit.

  FIG. 4 is a timing chart shown for explaining the operation of the WENB generation circuit 18-1 shown in FIG. First, when the internal clock CLKIN is activated and becomes H level, the L level of the inverted clock CLKINn inverted by the inverter circuit INVb is supplied to the flip-flop unit F / F including the NANDa circuit and the NANDb circuit.

  In the reset state, the level of the node RESET is H level. Therefore, at this time, the level of the node PULSEn is latched at the L level, whereby the node (pulse) PULSE is activated and becomes the H level. As a result, the output node (write activation signal) WENB is deactivated and becomes L level. When the level of the node PULSEn becomes L level, the PMOS transistor MP10 becomes conductive, and the node RCdelay is charged via the RC delay unit 18a composed of the resistance element R and the capacitance element C.

  When the node RCdelay is charged to a certain level and exceeds the circuit threshold value of the inverter circuit INVc composed of the PMOS transistor MP20 and the NMOS transistor MN20, the NMOS transistor MN20 becomes conductive and the level of the node RESET becomes L level. As a result, the level of the node PULSEn becomes H level, the node PULSE is deactivated, and becomes L level. As a result, output node WENB is activated and becomes H level.

  This is the process for generating the activation period in the pulse. That is, the speed at which the node RCdelay is charged after the node PULSE is activated by the resistance element R and the capacitance element C depends on the resistance value of the resistance element R and the capacitance of the capacitance element C. The activation time of the node PULSE is defined.

  Thereafter, in response to the H level of the node PULSEn, the NMOS transistor MN10 becomes conductive and the node RCdelay is discharged. Further, the PMOS transistor MP20 becomes conductive, and the level of the node RESET becomes the H level in the reset state. Thus, the flip-flop unit F / F composed of the NANDa circuit and the NANDb circuit is in a state where it can accept the L level of the node CLKINn when the internal clock CLKIN is activated in the next cycle.

  Even if the internal clock CLKIN of the next cycle is activated before the level of the node RESET is reset, the pulse PULSE is not activated, and therefore the write activation signal WENB is activated. There is no. That is, the operation cycle time of the WENB generation circuit 18-1 is determined by the sum of the activation period of the node PULSE and the subsequent reset operation period (reset time).

  FIG. 5 is a timing chart for explaining the operation in the configuration (memory macro) shown in FIG. First, when the internal write command WC is activated, the write buffer activation signal WBUFENB is activated in synchronization with the write activation signal WENB. As a result, the write buffer 21a writes the write data onto the complementary data line DQt / c.

  Next, the write activation signal WENB is deactivated, whereby the write buffer activation signal WBUFENB is deactivated. Then, the write buffer 21a equalizes the complementary data line DQt / c.

  On the other hand, the CSL control circuit 14 sequentially activates the column address strobe signal CSL selected by the column address signal CADD in synchronization with the write activation signal WENB. Thus, the write data is written to the bit line pair BLt / c by the SA 13a selected by the column address strobe signal CSL.

  At this time, the reset operation of the WENB generation circuit 18-1 is performed during the write operation period, so that the reset time does not affect the cycle time.

  Further, for example, as shown in FIG. 6, the SA write operation period can be extended by relaxing the operation frequency. Therefore, unlike the conventional case, data can be written by SA even at a considerably low voltage.

  In addition, since the pulse activation period does not include the operation compensation period at the time of low voltage, high-speed operation near the specification voltage is possible.

  In addition, since the pulse activation period defined by the RC delay unit 18a in the WENB generation circuit 18-1 is significantly smaller than the conventional one, the process variation of the RC delay unit 18a is also relatively small, and the operation The effect on frequency is reduced.

  As described above, in a semiconductor memory device including a pulse generation circuit that defines an activation period of a certain pulse by an RC delay unit, an inactive period of a generated pulse is set as an SA write operation period. That is, by inverting the pulse generated by the RC delay unit, the write activation signal WENB whose inactivation period (L level) is the pulse activation period (H level) is generated. Thus, the cycle time can be defined by the sum of the pulse activation period and the reset operation period. Therefore, it is possible to prevent the high-speed operation from being limited, and to easily secure an operation margin during the write operation.

[Second Embodiment]
FIG. 7 shows a basic configuration of a semiconductor memory device (semiconductor memory device) according to the second embodiment of the present invention. Here, a case where a large-capacity memory (DRAM) having a plurality of memory sub macros is configured will be described as an example. In addition, the same code | symbol is attached | subjected to FIG. 1 and an identical part, and detailed description is omitted.

  As shown in FIG. 7, the semiconductor memory device is provided with a plurality of memory sub macros SMa, SMb, SMc, SMd,. Each of the memory sub macros SMa, SMb, SMc, SMd,... Includes a cell array 11, a row decoder unit 12, a sense amplifier (SA) unit 13, a write buffer unit 21, a CSL control circuit 14, a write buffer control circuit 19, and A read / write control circuit 18 is provided. In each of the sub macros SMa, SMb, SMc, SMd,..., Only the WENB generation circuit 18-1 among the circuits constituting the read / write control circuit 18 is shown for convenience.

  Each of the memory sub macros SMa, SMb, SMc, SMd,... Is sequentially arranged in a direction along the global write data line GWDATA <k> (k = 0, 1, 2, 3,...) Connected to the I / O buffer 20. It is installed. That is, the I / O buffer 20 and the write buffer unit 21 of each of the sub macros SMa, SMb, SMc, SMd,... Have global write data lines GWDATA <0>, <1>,. Are connected to each other.

  On the other hand, the external clock CLK is taken in by the clock buffer 15 and used to generate the internal clock CLKIN. Further, the internal clock CLKIN is re-driven by the buffer 31 in the vicinity of the central portion in the direction along the global write data line GWDATA <k>, and then treeed to become the control clock TCLKIN. Supplied to SMd,. This is for making the various operation timings among the sub-macros SMa, SMb, SMc, SMd,... With respect to the external clock CLK the same, and the internal clock CLKIN is often made into a tree in a large-capacity memory. . Further, since the H level period of the external clock CLK input from the outside may be reduced depending on the memory user, the internal clock CLKIN is designed to reduce the RC delay.

  Other descriptions such as an address buffer and a command buffer are omitted.

  In the present embodiment, since the global write data line GWDATA <k> is multi-bit, it is impossible to form a tree, and its wiring length increases compared to the wiring length of the internal clock CLKIN. It is also difficult to ensure a sufficient wiring width. Therefore, the difference in RC wiring delay between the internal clock CLKIN wiring and the global write data line GWDATA <k> increases as shown in FIG. 8, for example. Since this difference is not reduced even when the voltage becomes high, it should be compensated by the delay by the RC delay unit 18a. This is because, if an attempt is made to compensate this by an inverter delay, the inverter delay greatly deteriorates the cycle time at a low voltage.

  That is, in the configuration of the present embodiment, for example, as shown in FIG. 8, the function of compensating for the RC wiring delay between the wiring of the internal clock CLKIN and the global write data line GWDATA <k> has the function of the WENB generation circuit 18-1. The cycle time can be shortened by merging with the RC delay unit 18a.

  Even when such a configuration having a plurality of memory sub-macros SMa, SMb, SMc, SMd,... Is used, as in the case of the first embodiment described above, each memory sub-macro SMa, SMb, SMc,. In SMd,..., Generation of a write activation signal WENB synchronized with the control clock TCLKIN and having a pulse inactive period as the SA write operation period can prevent the high-speed operation from being rate-limited and the write operation. It is possible to easily secure an operation margin at the time.

  In the above-described embodiments, description has been made by taking a DRAM requiring high-frequency operation as an example. However, the present invention is not limited to this. For example, a semiconductor including a pulse generation circuit that defines an activation period of a certain pulse by an RC delay unit The same applies to any memory device.

  Further, the present invention is not limited to a single semiconductor memory device, and can be applied to, for example, a semiconductor memory device embedded in a semiconductor integrated circuit or the like.

  In addition, the present invention is not limited to the above (each) embodiment, and various modifications can be made without departing from the scope of the invention in the implementation stage. Further, the above (each) embodiment includes various stages of the invention, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. For example, even if several constituent requirements are deleted from all the constituent requirements shown in the (each) embodiment, the problem (at least one) described in the column of the problem to be solved by the invention can be solved. When the effect (at least one of the effects) described in the “Effect” column is obtained, a configuration from which the constituent requirements are deleted can be extracted as an invention.

1 is a block diagram showing a configuration example of a semiconductor memory device according to a first embodiment of the present invention. FIG. 2 is a configuration diagram showing an example (memory macro) of connection between an SA and a memory cell in the semiconductor memory device shown in FIG. 1. The circuit diagram which shows the structural example of the WENB production | generation circuit provided in the read-write control circuit. 4 is a timing chart for explaining the operation of the WENB generation circuit shown in FIG. 3 is a timing chart for explaining the operation of the memory macro shown in FIG. 2. FIG. 3 is a view for explaining control characteristics of the semiconductor memory device having the configuration shown in FIG. 1. The block diagram which shows the structural example of the semiconductor memory device according to 2nd Embodiment of this invention. 8 is a timing chart shown for explaining basic operations of the semiconductor memory device shown in FIG.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 11 ... Cell array, 12 ... Row decoder part, 13 ... Sense amplifier (SA) part, 13a ... SA, 14 ... CSL control circuit, 15 ... Clock buffer, 16 ... Address buffer, 17 ... Command buffer, 18 ... Read-write control circuit 18-1 ... WENB generation circuit, 18a ... RC delay unit, 19 ... write buffer control circuit, 20 ... I / O buffer, 21 ... write buffer unit, 21a ... write buffer, WL <n> ... word line, BLt / c: Bit line pair, INVd: Inverter circuit.

Claims (5)

A memory cell for storing data;
A sense amplifier for writing the data to the memory cell;
A pulse generation circuit that generates a pulse that is activated for a certain period in synchronization with an internal clock; and
An output circuit that outputs a write activation signal that inverts the pulse generated by the pulse generation circuit and sets a deactivation period of the pulse as a write operation period of the sense amplifier. Storage device.   The pulse generation circuit includes an RC delay circuit including a resistance element (R) and a capacitance element (C), and generates a pulse having an activation period defined by the RC delay circuit. The semiconductor memory device according to claim 1.   The sense amplifier is provided for each memory cell, and drives the bit line connected to the memory cell connected to the selected word line according to the write data on the data line, whereby the data for the memory cell is transferred. 2. The semiconductor memory device according to claim 1, wherein writing is performed. A plurality of cell arrays having a predetermined number of the memory cells;
A semiconductor memory device in which a plurality of memory sub-macros each including the plurality of cell arrays are arranged along a global data line connected to an input / output buffer,
2. The semiconductor memory device according to claim 1, wherein the pulse generation circuit has a function of compensating for a difference in wiring delay between the internal clock wiring and the global data line. Each of the plurality of memory sub macros includes a row decoder, a sense amplifier, a write buffer, a CSL control circuit, a write buffer control circuit, and a read / write control circuit,
5. The semiconductor memory device according to claim 4, wherein the pulse generation circuit and the output circuit are provided in the read / write control circuit.

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