JP2008083144A - Manufacturing method of liquid crystal panel - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To enhance reliability and manufacturing efficiency of a device by performing plate thinning treatment of at least a first substrate with respect to the first substrate and a second substrate which are stuck to each other. <P>SOLUTION: In a liquid crystal panel 1 wherein an array substrate 11 and a counter substrate 21 are stuck to each other, plate thinning treatment is applied so that its thickness is reduced. An extended region ER extended from a facing region OR where the array substrate 11 faces the counter substrate 21 so as to be exposed to surroundings is included, and after a supporting member 112s supporting the extended region ER is formed on the side of a surface where the array substrate 11 and the counter substrate 21 are opposite to each other in the extended region ER, the plate thinning treatment is applied. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a liquid crystal panel. In particular, it includes a first substrate, a second substrate bonded to the first substrate so as to face the first substrate, and a liquid crystal layer sealed between the first substrate and the second substrate. The first liquid crystal panel including the extended region extending from the facing region where the first substrate faces the second substrate to the periphery is bonded to the liquid crystal panel so as to reduce the thickness of the liquid crystal panel. The present invention relates to a method for manufacturing a liquid crystal panel in which a thinning process is performed on at least a surface of a first substrate in a substrate and a second substrate.

  Since the liquid crystal panel has advantages such as thinness, light weight, and low power consumption, in mobile electronic devices such as mobile phones, digital still cameras, digital video cameras, personal digital assistants (PDAs), etc. Many are used.

  In the liquid crystal panel, the array substrate includes an extension region extending so as to be exposed from the facing region facing the counter substrate to the periphery. In the extended region, a wiring pad is provided. For example, the flexible printed board is installed so as to be connected to the wiring pad. In addition, a semiconductor chip is mounted on the extended region by COG (Chip on glass).

  In order to reduce the thickness and weight of this liquid crystal panel, a thinning process is performed on a glass substrate constituting the liquid crystal panel. Here, the thinning process is performed by a process such as chemical etching or mechanical polishing. For example, the thinning process is performed so that the thickness of the glass substrate is 0.5 mm or less. In such a case, it is difficult to thin the large substrate itself, and it is also difficult to cut out and inject liquid crystal when the substrate is thin, so the liquid crystal is injected while maintaining a certain thickness. After sealing, the thinning process is performed by polishing the liquid crystal panel (see, for example, Patent Document 1, Patent Document 2, and Patent Document 3).

JP 2003-84265 A JP 11-142826 A JP 2003-322841 A

  FIG. 8 is a cross-sectional view showing a state in which a thinning process is performed on the liquid crystal panel 1.

  First, as shown in FIG. 8A, in the liquid crystal panel 1 in which the array substrate 11 and the counter substrate 21 face each other and are bonded together with the sealing material S, wiring formed in the extending region ER of the array substrate 11 In order to protect the pad (not shown), the pad protection material 112 is formed.

  Here, the pad protection material 112 is formed in the extending region ER so as to cover the wiring pad, and foreign substances such as an abrasive used in polishing are prevented from entering the wiring pad. For example, the pad protection material 112 is formed of a resin film.

  Next, as shown in FIG. 8B, the liquid crystal panel 1 is subjected to a thinning process.

  Here, for example, the surfaces of the array substrate 11 and the counter substrate 21 are polished by sequentially performing roughing (lapping) and finish polishing (polishing). That is, in the liquid crystal panel 1, the surface opposite to the surface where the array substrate 11 and the counter substrate 21 face each other is polished. Thereby, since the initial thickness D0 of the liquid crystal panel 1 becomes the thin thickness D1, the liquid crystal panel 1 can be thinned.

  Specifically, after the liquid crystal panel is set on the polishing carrier, the upper and lower plates are simultaneously rotated to scrape both surfaces of the array substrate 11 and the counter substrate 21 simultaneously.

  However, as shown in FIG. 8B, with respect to the array substrate 11, since stress is applied to the extension region ER in the above-described thinning process, the extension region ER has a bow shape toward the counter substrate 21 side. On the other hand, the thickness DTe of the extension region ER may be formed thicker than the thickness DTt of the facing region OR.

  FIG. 9 shows an optical micrograph taken of the side surface of the array substrate 11 after performing the thinning process on the liquid crystal panel 1. 9A is an optical micrograph of the facing region OR of the array substrate 11, and FIG. 9B is an optical micrograph of the extended region ER of the array substrate 11.

  As shown in FIG. 9A, the thickness DTt of the facing region OR of the array substrate 11 is formed to 110 μm, whereas the thickness of the extended region ER of the array substrate 11 is shown in FIG. 9B. DTe was formed to 125 μm.

  As described above, since the extension region ER warps toward the counter substrate 21 and the extension region ER has a thick thickness DTe, the thinning process may be performed so as to have a predetermined shape. It can be difficult. For this reason, for example, when a semiconductor chip is mounted in the extension region ER, it may be difficult to properly connect the semiconductor chip to a wiring pad formed in the extension region ER. Therefore, the reliability and manufacturing efficiency of the apparatus may be reduced, such as inability to perform image display.

  Further, when the final polishing is performed on the liquid crystal panel 1 including the array substrate 11 in which the extension region ER is warped as described above, the entire surface cannot be uniformly polished, and a polishing residue is generated. There may be a problem that the part becomes cloudy. And when it is in a white state, the strength of the glass substrate becomes very weak, and it becomes difficult to recognize the alignment mark when mounting a semiconductor chip or a flexible printed board on the pad. Problems may occur. Therefore, the reliability and manufacturing efficiency of the apparatus may be reduced.

  Accordingly, an object of the present invention is to provide a liquid crystal panel manufacturing method capable of improving the reliability and manufacturing efficiency of the apparatus.

  In order to achieve the above object, a method of manufacturing a liquid crystal panel according to the present invention includes a first substrate, a second substrate bonded to the first substrate so as to face the first substrate, and the first substrate. And a liquid crystal layer sealed between the first substrate and the second substrate, and the first substrate includes an extended region extending from a facing region facing the second substrate to the periphery And a thinning process step of performing a thinning process on at least the first substrate in the bonded first substrate and the second substrate so as to reduce the thickness of the liquid crystal panel. In the thinning process step, after the supporting member that supports the extension region is formed on the side of the surface where the first substrate and the second substrate face in the extension region, the thin plate Execute the conversion process.

  In the present invention, the thinning process is performed on at least the first substrate in the bonded first substrate and second substrate. Here, after the support member that supports the extension region is formed on the side of the extension region facing the first substrate and the second substrate, the thinning process is performed.

  ADVANTAGE OF THE INVENTION According to this invention, the manufacturing method of the liquid crystal panel which can improve the reliability and manufacturing efficiency of an apparatus can be provided.

An example of an embodiment according to the present invention will be described.
(Constitution)
1, 2 and 3 are views showing a liquid crystal panel 1 manufactured in an embodiment according to the present invention.

  Here, FIG. 1 is a cross-sectional view showing the overall configuration of the liquid crystal panel 1 manufactured in the embodiment according to the present invention. FIG. 2 is a circuit diagram showing a circuit configuration of the liquid crystal panel 1 manufactured in the embodiment according to the present invention. Moreover, FIG. 3 is sectional drawing which shows a part of liquid crystal panel 1 manufactured in embodiment concerning this invention.

  The liquid crystal panel 1 is an active matrix system, and includes an array substrate 11, a counter substrate 21, and a liquid crystal layer 31, as shown in FIG.

  Each part of the liquid crystal panel 1 will be described sequentially.

  As shown in FIG. 1, the array substrate 11 is a substrate, and is formed of an insulator that transmits light, such as glass. For example, the array substrate 11 is made of alkali-free glass. Although details will be described later, in the present embodiment, the array substrate 11 is subjected to a thinning process and has a thickness of 0.3 mm or less, for example. As shown in FIG. 1, the array substrate 11 has one surface facing the counter substrate 21 with a space therebetween, and the counter substrate is surrounded by a sealing material S around a facing region OR facing the counter substrate 21. 21 is attached. In the facing region OR of the array substrate 11, the pixel electrode 101, the pixel switching element 102, the storage capacitor element 103, the scanning wiring 201, the signal wiring 202, the storage capacitor wiring 203, and the gate driver in the member shown in FIG. 301 and a source driver 302 are formed. Here, as shown in FIG. 2, the pixel electrode 101, the pixel switching element 102, the storage capacitor element 103, the scanning wiring 201, the signal wiring 202, and the storage capacitor wiring 203 are pixel regions in which image display is performed in the liquid crystal panel 1. It is formed in PR. A gate driver 301 and a source driver 302 are formed in the peripheral region of the pixel region PR. In addition, as shown in FIG. 1, the array substrate 11 includes an extension region ER extending so as to be exposed to the periphery from the facing region OR facing the counter substrate 21, and the extension region In the ER, wiring pads (not shown) connected to the gate driver 301 and the source driver 302 are formed.

  As shown in FIG. 1, the counter substrate 21 is a substrate, and is formed of an insulator that transmits light, such as glass, like the array substrate 11. For example, the counter substrate 21 is made of alkali-free glass. Moreover, although mentioned later for details, in this embodiment, the opposing board | substrate 21 is thinned, and thickness is 0.3 mm or less, for example. Further, as shown in FIG. 1, the counter substrate 21 faces one side of the array substrate 11 with a space therebetween, and is attached by a sealing material S around the facing region OR. As shown in FIG. 3, a counter electrode 23 is formed as a transparent electrode such as ITO on the surface facing the array substrate 11. Here, the common electrode corresponding to the plurality of pixel electrodes 101 is formed in a solid shape so as to cover the entire surface of the pixel region PR. A color filter layer (not shown) is formed so as to correspond to each pixel electrode 101.

  As shown in FIG. 1, for example, twisted nematic liquid crystal is injected between the array substrate 11 and the counter substrate 21 in the liquid crystal layer 31. Here, the liquid crystal layer 31 is aligned by alignment films (not shown) provided on each of the array substrate 11 and the counter substrate 21. Then, as shown in FIG. 2, the liquid crystal layer 31 is connected to the pixel electrode 101 and the counter electrode 23, and based on the voltage applied between the pixel electrode 101 and the counter electrode 23, The orientation state changes. As a result, the liquid crystal layer 31 changes its light transmittance for transmitting light, and an image is displayed.

  Each part formed on the array substrate 11 will be described.

  The pixel electrode 101 is a transparent electrode formed using a light-transmitting conductive material such as ITO (Indium Tin Oxide). As illustrated in FIG. 2, in the pixel region PR, a plurality of pixels are arranged in the x direction and the y direction. Are arranged in a matrix so as to be aligned with each other and connected to the liquid crystal layer 31.

  As shown in FIG. 2, a plurality of pixel switching elements 102 are arranged in a matrix in the x direction and the y direction so as to correspond to each of the plurality of pixel electrodes 101 in the pixel region PR. It is connected to each pixel electrode 101. As shown in FIG. 3, the pixel switching element 102 is formed on the surface of the array substrate 11 facing the counter substrate 21 with the light shielding film 12 and the interlayer insulating film 13 interposed therebetween. In the present embodiment, the pixel switching element 102 is a thin film transistor (TFT) as shown in FIG. 3, and includes a semiconductor layer 14, a gate insulating film 102x, and a gate electrode 102g. The pixel switching element 102 is, for example, a TFT using polysilicon. As shown in FIG. 3, the semiconductor layer 14, the gate insulating film 102x, and the gate electrode 102g are sequentially formed from the array substrate 11 side. The top gate type has an LDD structure.

  Specifically, in the pixel switching element 102, the semiconductor layer 14 is polysilicon, and a pair of first and second source / drain regions 102a and 102b are formed so as to sandwich the channel formation region 102c. . Here, in the first and second source / drain regions 102a and 102b formed so as to sandwich the channel region 102c, one first source / drain region 102a is connected to the signal wiring 202 and the other first The second source / drain region 102 b is connected to the pixel electrode 101 and the storage capacitor element 103.

  Further, in the pixel switching element 102, each of the first and second source / drain regions includes the first and second impurity diffusion regions 102Fa and 102Fb and the first and second low diffusion regions as shown in FIG. Concentration impurity regions 102La and 102Lb are provided. Here, the first and second impurity diffusion regions 102Fa and 102Fb are formed by diffusing impurities in a region of the semiconductor layer 14 sandwiching the channel formation region 102c. Each of the first and second low-concentration impurity regions 102La and 102Lb includes the first and second impurities between the first and second impurity diffusion regions 102Fa and 102Fb and the channel formation region 102c. It is formed by diffusing impurities in the semiconductor layer 14 so as to have an impurity concentration lower than that of the diffusion regions 102Fa and 102Fb.

  In the pixel switching element 102, the gate insulating film 102x is formed to face the channel formation region 102c as shown in FIG.

  Further, as shown in FIG. 3, the gate electrode 102g is formed so as to correspond to the channel formation region 102c through the gate insulating film 102x, and is connected to the scanning wiring 201 as shown in FIG. .

  The pixel switching element 102 is driven and controlled by a scanning signal input from the gate driver 301 to the gate electrode 102g via the scanning wiring 201. The pixel switching element 102 is supplied with a data signal from the source driver 302 to the pixel switching element 102 via the signal wiring 202. The pixel switching element 102 supplies a data signal to each of the pixel electrode 101 and the storage capacitor element 103 in the on state.

  As shown in FIG. 2, a plurality of storage capacitor elements 103 are arranged in a matrix in each of the x direction and the y direction so as to correspond to each of the plurality of pixel electrodes 101 in the pixel region PR. The storage capacitor element 103 is formed so as to be in parallel with the electrostatic capacitance of the liquid crystal layer 31, and holds a charge due to a data signal applied to the liquid crystal layer 31. As shown in FIG. 3, the storage capacitor element 103 is formed so as to correspond to a region where the signal wiring 202 is formed on the surface of the array substrate 11, similarly to the pixel switching element 102. That is, the storage capacitor element 103 is formed so as to overlap the signal wiring 202 via the interlayer insulating film 16 in the direction perpendicular to the surface of the array substrate 11. In addition, as shown in FIG. 3, the storage capacitor element 103 is formed on the surface of the array substrate 11 facing the counter substrate 21 so that the light shielding film 12 and the interlayer insulating film 13 are interposed therebetween. As shown in FIG. 3, the storage capacitor 103 has an upper electrode 103a, a lower electrode 103b, and a dielectric film 103c, and the lower electrode 103b, the dielectric film 103c, and the upper electrode 103a are array substrates. 11 are sequentially formed.

  Specifically, in the storage capacitor 103, the upper electrode 103a is formed of a conductive material in the same manner as the gate electrode 102g, and is connected to the storage capacitor wiring 203. As shown in FIG. 2, the lower electrode 103b is a second source / drain region on the side where the signal wiring 202 is not connected in the first and second source / drain regions 102a, 102b of the pixel switching element 102. 102b. The dielectric film 103c is formed so as to be sandwiched between the upper electrode 103a and the lower electrode 103b facing each other.

  As shown in FIG. 2, the scanning wiring 201 is formed to extend in the x direction in the pixel region PR, and is connected to the plurality of pixel switching elements 102 arranged in the x direction. A plurality of scanning wirings 201 are formed side by side in the y direction so as to correspond to the plurality of pixel switching elements 102 arranged in the y direction. The scanning wiring 201 is connected to the gate driver 301, and supplies the scanning signal from the gate driver 301 to the pixel switching element 102 so as to sequentially select the rows of the pixel electrodes 101.

  As shown in FIG. 2, the signal wiring 202 is formed to extend in the y direction in the pixel region PR, and is connected to a plurality of pixel switching elements 102 arranged in the y direction. A plurality of signal wirings 202 are formed side by side in the x direction so as to correspond to the plurality of pixel switching elements 102 arranged in the x direction. The signal wiring 202 supplies a data signal to the pixel electrode 101 through the pixel switching element 102 to which the scanning signal is supplied. In the present embodiment, as shown in FIG. 3, the signal wiring 202 is formed so as to include a region facing the pixel switching element 102 in the pixel region PR, and the first source / drain of the pixel switching element 102 is formed. It is connected to the area 102a.

  As shown in FIG. 2, the storage capacitor line 203 is formed to extend in the x direction in the pixel region PR, and is connected to a plurality of storage capacitor elements 103 arranged in the x direction. In addition, a plurality of storage capacitor lines 203 are formed side by side in the y direction so as to correspond to the plurality of storage capacitor elements 103 arranged in the y direction. The storage capacitor wiring 203 is connected to the counter electrode 23 on the opposite side of the storage capacitor 103.

(Production method)
Below, the manufacturing method of said liquid crystal panel 1 is demonstrated.

  FIG. 4 is a flowchart when the thinning process is performed on the liquid crystal panel 1 in the embodiment according to the present invention.

  First, as shown in FIG. 4, the support member 112s is formed (S11).

  FIG. 5 is a diagram showing how the support member is formed in the embodiment according to the present invention. 5, FIG. 5 (a) is a front view of the liquid crystal panel 1, and FIG. 5 (b) is a side view.

  Here, after forming each part on the array substrate 11 and the counter substrate 21, as shown in FIGS. 5A and 5B, the array substrate 11 and the counter substrate 21 face each other and are bonded together. Thereafter, in the liquid crystal panel 1 in which the array substrate 11 and the counter substrate 21 face each other and are bonded to each other, a support member 112 s that supports the extension region ER is attached to the array substrate 11 in the extension region ER of the array substrate 11. It is formed on the side facing the counter substrate 21.

  Specifically, the array substrate 11 and the counter substrate 21 in which the respective parts are formed as described above are bonded to each other with the sealing material S facing each other.

  Thereafter, as shown in FIGS. 5A and 5B, the support member 112 s is bonded to the extended region ER where the wiring pads are formed on the array substrate 11 using the double-sided adhesive tape 113. In the present embodiment, a support member 112s formed using glass is used. For example, non-alkali glass having a hardness of 0.5 to 2 times the hardness of the array substrate 11 is used. When the hardness of the support member 112s is less than 0.5 times the hardness of the array substrate 11, the back surface of the pad portion (extended region ER) is not sufficiently polished as if polished without a support agent. In some cases, the edge of the pad portion (extension region ER) becomes particularly thick, and when the hardness of the array substrate 11 exceeds twice, the pad portion (extension) This is because there may be a problem such that the area (ER) is excessively cut and the pad portion (extended area ER) becomes thin.

  Further, as the support member 112s, the entire thickness when the double-sided adhesive tape 113 is bonded in the extending region ER is the entire thickness when the array substrate 11 and the counter substrate 21 are bonded in the facing region OR. Use a shape that is the same as the thickness. That is, in the direction in which the array substrate 11 and the counter substrate 21 face each other, the support member 112s and the double-sided adhesive tape 113 having such a thickness that the thickness in the extending region ER and the thickness in the facing region OR are the same. Select and use.

  Next, as shown in FIG. 4, a first polishing process is performed (S21).

  Here, “lap”, that is, “roughing” is performed. In the present embodiment, the surfaces of the array substrate 11 and the counter substrate 21 are polished simultaneously. That is, both surfaces of the opposite surface of the bonded array substrate 11 and counter substrate 21 with respect to the surfaces facing each other are simultaneously polished.

  Specifically, the slurry is supplied to the surface opposite to the surface where the array substrate 11 and the counter substrate 21 face each other, and the polishing pad is pressurized and brought into contact with the surface supplied with the slurry. Then, the polishing process is performed by rotationally driving the polishing pad along the surface to which the slurry is supplied.

  FIG. 6 is a side view schematically showing how the first polishing process is performed in the embodiment according to the present invention.

  As shown in FIG. 6, after setting the liquid crystal panel on the polishing carrier, the upper surface plate 201 and the lower surface plate 202 are rotated simultaneously to scrape both surfaces of the array substrate 11 and the counter substrate 21 simultaneously.

  Here, as shown in FIG. 6, the array substrate 11 and the counter substrate 21 sandwiched between the upper surface plate 201 and the lower surface plate 202 have a thickness in the extending region ER in the direction in which they face each other, Since the thickness in the facing region OR is the same, the extension region ER and the facing region OR are in a state of being crimped with substantially the same pressure. Therefore, the extended region ER and the facing region OR are uniformly polished.

  Next, as shown in FIG. 4, the support member 112s is removed (S31).

  Here, as described above, the support member 112s bonded to the extending region ER of the array substrate 11 with the double-sided adhesive tape 113 is peeled off. At the same time, the double-sided adhesive tape 113 is also peeled off from the extended region ER and removed.

  Next, as shown in FIG. 4, a second polishing process is performed (S41).

  Here, “polish”, that is, “finish polishing” is performed. Specifically, similarly to the first polishing process, the surfaces of the array substrate 11 and the counter substrate 21 are polished. For example, 20 μm on one side is polished so as to be a mirror surface. The final glass thickness is, for example, 0.1 mm on one side and 0.2 mm on both sides. For this reason, the rough cutting is made 20 μm + 20 μm thick compared to the final glass.

  Thereafter, after the scribing process, the liquid crystal layer 31 is injected into the gap between the array substrate 11 and the counter substrate 21. Then, a liquid crystal display device is completed by mounting a driving circuit for driving the liquid crystal panel and peripheral devices such as a polarizing plate and a backlight.

  As described above, in the present embodiment, the thinning process is performed so that the thickness of the liquid crystal panel 1 in which the array substrate 11 and the counter substrate 21 are bonded is reduced. Here, the array substrate 11 includes an extension region ER extending so as to be exposed to the periphery from the facing region OR facing the counter substrate 21, and a support member 112 s that supports the extension region ER. Is formed on the side of the surface where the array substrate 11 and the counter substrate 21 face each other in the extended region ER, and this thinning process is performed. That is, the supporting member 112s is attached to the portion that is a single glass and polished. For this reason, in the present embodiment, as described above, when the thinning process is performed, the extending region ER and the facing region OR are polished by substantially the same pressure by the support member 112s. Therefore, the thinning process is performed uniformly in the extension region ER and the facing region OR.

  FIG. 7 is an optical micrograph showing how the surfaces of both the array substrate 11 and the counter substrate 21 are polished in the embodiment according to the present invention.

  As shown in FIG. 7, the array substrate 11 is polished so that both the facing region OR and the extending region ER are uniform.

  As described above, in the present embodiment, the extension region ER is formed on the support member 112s so that the polishing is performed with substantially the same pressure between the extension region ER and the facing region OR when the thinning process is performed. Since it supports, it can prevent that the extension area | region ER warps to the opposing board | substrate 21 side, and the malfunction that the thickness DTe of the extension area | region ER is formed thickly occurs, and it becomes a predetermined shape. It is easy to perform the thinning process. For this reason, when a semiconductor chip is mounted in the extension region ER, it is possible to easily connect the semiconductor chip to the wiring pads formed in the extension region ER. Therefore, according to the present embodiment, it is possible to prevent the reliability and manufacturing efficiency of the apparatus from being lowered such that image display cannot be performed, and it is possible to improve the reliability and manufacturing efficiency of the apparatus.

  In the present embodiment, non-alkali glass is used for the support member 112s as in the case of the array substrate 11 and the counter substrate 21. Thus, in this embodiment, since the support member 112s is provided with the same material as the array substrate 11 and the counter substrate 21, the polishing rate is substantially equal, and the thinning process can be performed uniformly. It is possible to prevent a decrease in device reliability and manufacturing efficiency, and to improve device reliability and manufacturing efficiency.

  In the above embodiment, the liquid crystal panel 1 corresponds to the liquid crystal panel of the present invention. In the above embodiment, the array substrate 11 of the present invention corresponds to the first substrate of the present invention. In the above embodiment, the counter substrate 21 of the present invention corresponds to the second substrate of the present invention. In the above embodiment, the liquid crystal layer 31 of the present invention corresponds to the liquid crystal layer of the present invention. In the above embodiment, the support member 112s of the present invention corresponds to the support member of the present invention. Moreover, in said embodiment, the double-sided adhesive tape 113 of this invention is corresponded to the double-sided adhesive tape of this invention. In the above embodiment, the facing area OR of the present invention corresponds to the facing area of the present invention. Moreover, in said embodiment, the extension area | region ER of this invention is corresponded to the extension area | region of this invention.

  Moreover, when implementing this invention, it is not limited to above-described embodiment, A various deformation | transformation form is employable.

  For example, as the support member, alkali glass may be used in addition to alkali-free glass. When alkali glass is used, it is particularly suitable from the viewpoint of cost and ease of use. In addition to inorganic materials such as alkali-free glass and alkali glass, organic materials such as resins may be used. In this case, it is preferable to function as a support member by coining the resin itself after adhering it to the extension region ER.

  Further, for example, the present invention is not limited to the case of manufacturing a liquid crystal panel in the process order shown in the above embodiment. For example, before the above process is performed, the above process may be performed for each panel after the entire substrate is thinned by polishing or etching. Specifically, the thickness is 1.4 mm when the glass substrates are bonded to each other, but first, etching is performed up to a half thickness of 0.7 mm (0.35 mm × 2). Thereafter, the glass is cut out and liquid crystal is injected. And you may grind | polish to 0.2 mm thickness (0.1 mm x 2) in said process.

  Further, for example, in the above embodiment, the thinning process is performed by simultaneously polishing both surfaces of the array substrate 11 and the counter substrate 21, but the present invention is not limited to this. For example, each side may be polished. Moreover, even when only the array substrate 11 is subjected to the thinning process, a suitable effect can be obtained.

FIG. 1 is a cross-sectional view showing a configuration of a liquid crystal panel manufactured in an embodiment according to the present invention. FIG. 2 is a circuit diagram showing a circuit configuration of the liquid crystal panel manufactured in the embodiment according to the present invention. FIG. 3 is a cross-sectional view showing a part of the liquid crystal panel manufactured in the embodiment according to the present invention. FIG. 4 is a flow chart when the thinning process is performed on the liquid crystal panel in the embodiment according to the present invention. FIG. 5 is a diagram showing how the support member is formed in the embodiment according to the present invention. FIG. 6 is a side view showing a state in which the first polishing process is performed in the embodiment according to the present invention. FIG. 7 is an optical micrograph showing how the surfaces of both the array substrate and the counter substrate are polished in the embodiment according to the present invention. FIG. 8 is a cross-sectional view showing a state in which a thinning process is performed on the liquid crystal panel. FIG. 9 shows an optical micrograph taken of the side surface of the array substrate after performing the thinning process on the liquid crystal panel.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Liquid crystal panel (liquid crystal panel), 11 ... Array board | substrate (1st board | substrate), 14 ... Semiconductor layer, 16 ... Interlayer insulation film, 21 ... Opposite board | substrate (2nd board | substrate), 31 ... Liquid crystal layer (liquid crystal layer), 23 Reference electrode, 101 ... Pixel electrode, 102 ... Pixel switching element, 102x ... Gate insulating film, 102g ... Gate electrode, 102c ... Channel formation region, 102a ... First source / drain region, 102b ... Second source / drain 102Fa, first impurity diffusion region, 102Fb, second impurity diffusion region, 102La, first low concentration impurity region, 102Lb, second low concentration impurity region, 103, storage capacitor element, 103a, upper electrode , 103b ... lower electrode, 103c ... dielectric film, 112s ... support member (support member), 113 ... double-sided adhesive tape (double-sided adhesive tape), 201 ... run Wiring, 202 ... signal wire, 203 ... storage capacitor wiring, 301 ... gate driver, 302 ... source driver, PR ... pixel region, OR ... facing region (facing region), ER ... extending region (extension region)

Claims (6)

A first substrate; a second substrate bonded to the first substrate so as to face the first substrate; and a liquid crystal layer sealed between the first substrate and the second substrate A method of manufacturing a liquid crystal panel including an extended region in which the first substrate extends from a facing region facing the second substrate to the periphery,
A thinning process step of performing a thinning process on at least the first substrate in the bonded first substrate and second substrate so as to reduce the thickness of the liquid crystal panel;
In the thinning process step, the supporting member that supports the extension region is formed on the side of the surface where the first substrate and the second substrate are facing in the extension region, and then the thinning is performed. The manufacturing method of a liquid crystal panel which performs a process. Each of the first substrate and the second substrate is formed using glass,
The support member is formed using glass,
The manufacturing method of the liquid crystal panel of Claim 1. The support member has a hardness of 0.5 to 2 times the hardness of the first substrate and the second substrate.
The manufacturing method of the liquid crystal panel of Claim 2. The support member is made of alkali-free glass,
The manufacturing method of the liquid crystal panel of Claim 2. The support member is formed of alkali glass.
The manufacturing method of the liquid crystal panel of Claim 2. The method for manufacturing a liquid crystal panel according to claim 1, wherein when the support member is formed in the extension region, the support member is bonded to the extension region using a double-sided adhesive tape.