JP2008080428A - Double-sided polishing device and double-sided polishing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a double-sided polishing device, and a double-sided polishing method capable of evenly polishing top and bottom faces of a wafer edge parts without reversing the top and bottom faces of a semiconductor wafer in the middle of polishing both faces of the semiconductor wafer, and manufacturing the semiconductor wafer with high quality and low manufacturing cost. <P>SOLUTION: This both-sided polishing device polishes both of top and back faces of a semiconductor wafer 10 by rotation of bottom and top surface plates provided with polishing clothes 22a, 24a for polishing top and rear faces on opposed faces. A semiconductor wafer holding hole 30 is provided on a carrier 14 arranged between a bottom surface plate and a top surface plate, and an abrasive material 12 for polishing an annular semiconductor wafer edge is provided on an inner periphery of the semiconductor wafer holding hole 30. The abrasive material 12 has a vertical cross sectional shape symmetrical upward and downward, and the top and the bottom of the abrasive material 12 extends in a central direction of the semiconductor wafer holding hole 30. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a double-side polishing apparatus and a double-side polishing method capable of simultaneously polishing both front and back surfaces of a semiconductor wafer and polishing an edge portion of a semiconductor wafer.

A silicon wafer sliced from an ingot (hereinafter, also simply referred to as a wafer) is processed into a mirror wafer in which the front and back surfaces of the wafer or one surface thereof is mirror-finished through lapping, etching, and polishing (polishing) processes. The wafer flowing in each of these steps is processed while maintaining a disk shape. In addition, procedures such as cleaning, drying, and conveyance are included between the processes.
At this time, the surface of the wafer edge portion of the silicon wafer is a rough surface having large shape irregularities when no special treatment is performed. When the surface of the edge part is in such a state, the edge part comes into contact with an apparatus or the like during conveyance of each process, so that fine particles due to microfracture are generated or contaminated particles are entrained in the rough surface. In the subsequent process, particles are dissipated in the subsequent process to contaminate the precision processed wafer surface, greatly affecting the product quality and yield. In order to prevent these phenomena, it is common to chamfer the wafer edge portion at the initial stage of wafer processing, and then mirror-finish the wafer edge portion by polishing before or after double-side polishing (polishing). Done.
However, mirror processing by polishing the wafer edge is difficult, which increases the manufacturing cost of the wafer. Further, since the processing is performed while attracting the wafer surface during mirror processing of the wafer edge portion, there is also a problem that a suction mark or the like is generated on the wafer surface. Naturally, the manufacturing cost increases by adding a polishing process of the wafer edge portion.
In order to avoid the above problems, Patent Document 1 discloses a double-side polishing apparatus and method for polishing a wafer edge portion simultaneously with double-side polishing of a wafer.
JP-A-9-150366

  However, in the conventional double-side polishing apparatus disclosed in Patent Document 1, the shape of the abrasive for polishing the wafer edge provided in the inner peripheral portion of the holding hole for holding the wafer is vertically asymmetric in the cross section. It has become. For this reason, it is difficult to uniformly polish the upper surface and the lower surface of the wafer edge portion, and in order to perform uniform polishing, the upper surface and the lower surface of the semiconductor wafer must be reversed during the polishing, and the double-side polishing step However, there is a problem that the manufacturing cost increases. In addition, there is a risk of quality deterioration due to complicated manufacturing processes.

  The present invention has been made in consideration of the above circumstances, and the object of the present invention is to change the upper and lower surfaces of the wafer edge portion without inverting the upper and lower surfaces of the semiconductor wafer during double-side polishing of the semiconductor wafer. An object of the present invention is to provide a double-side polishing apparatus and a double-side polishing method capable of manufacturing a semiconductor wafer that is uniformly polished, high quality, and low in manufacturing cost.

The double-side polishing apparatus of one embodiment of the present invention includes:
By rotating the lower surface plate provided with the polishing cloth for polishing the back surface of the semiconductor wafer and rotating the upper surface plate provided with the polishing cloth for polishing the surface of the semiconductor wafer facing the lower surface plate, A double-side polishing apparatus for polishing,
A semiconductor wafer holding hole is provided in a carrier disposed between the lower surface plate and the upper surface plate,
An annular semiconductor wafer edge polishing material is provided on the inner periphery of the semiconductor wafer holding hole,
The abrasive has a vertically symmetric vertical cross-sectional shape;
The upper and lower portions of the abrasive extend in the center direction of the semiconductor wafer holding hole.

  Here, it is desirable that the abrasive can be divided vertically.

  Further, it is desirable that the material of the abrasive is a synthetic resin foam, a non-woven fabric, a non-woven resin processed product, a synthetic leather, or a composite thereof.

The double-side polishing method of one embodiment of the present invention is a double-side polishing method using the above polishing apparatus,
Inserting the semiconductor wafer into the wafer holding hole provided with the abrasive so that the upper and lower surfaces of the wafer edge of the semiconductor wafer are sandwiched between the abrasive; and
The method includes the step of simultaneously polishing the upper and lower surfaces of the wafer edge and both the front and back surfaces of the semiconductor wafer.

  Here, in the step of polishing, it is desirable that a vertically symmetrical surface of the abrasive coincides with a horizontal center surface of the semiconductor wafer.

  According to the present invention, the upper surface and the lower surface of the wafer edge portion are evenly polished without reversing the upper surface and the lower surface of the semiconductor wafer during the double-side polishing of the semiconductor wafer, and the semiconductor has high quality and low manufacturing cost. It becomes possible to provide a double-side polishing apparatus and a double-side polishing method that enable the production of a wafer.

  Hereinafter, embodiments of a double-side polishing apparatus and a double-side polishing method according to the present invention will be described with reference to the accompanying drawings. Here, a case where a silicon wafer is manufactured as a semiconductor wafer will be described as an example. In the drawings, the same or similar members are denoted by the same reference numerals.

(First embodiment)
FIG. 2 is an explanatory view showing an example of a double-side polishing apparatus 20 that can be used in the present embodiment. 2A is a top view, and FIG. 2B is a cross-sectional view taken along the line BB in FIG. 2A. However, in FIG. 2A, an upper surface plate described later is omitted from the drawing. As shown in FIG. 2B, the double-side polishing apparatus 20 has a lower surface plate 22 and an upper surface plate 24 provided to face each other. A lower polishing cloth 22a for polishing the wafer back surface is attached to the upper surface of the lower surface plate 22, and an upper polishing cloth 24a for polishing the wafer surface is attached to the lower surface of the upper surface plate 24. These upper and lower surface plates can be rotated in opposite directions by driving means (not shown).

  As shown in FIG. 2A, a sun gear 26 is provided at the center of the double-side polishing apparatus 20, and an annular internal gear 28 is provided at the outermost periphery of the double-side polishing apparatus 20. A plurality of disk-shaped carriers 14 are arranged so as to be sandwiched between the sun gear 26 and the internal gear 28.

  As shown in FIG. 2B, the sun gear 26 is provided on the upper surface of the center portion of the lower surface plate 22. The disk-shaped carrier 14 is disposed between the lower surface plate 22 and the upper surface plate 24. More specifically, the carrier 14 is sandwiched between the upper surface of the lower polishing cloth 22 a of the lower surface plate 22 and the lower surface of the upper polishing cloth 24 a of the upper surface plate 24. The carrier 14 is slidable between the lower polishing cloth 22a and the upper polishing cloth 24a while rotating and revolving, as will be described in detail later, by the action of the sun gear 26 and the internal gear 28. Yes.

FIG. 3 is an explanatory diagram of the structure of the carrier according to the present embodiment. FIG. 3A is a plan view of the carrier, and FIG. 3B is a cross-sectional view taken along line AA showing the main part of the carrier of FIG.
As shown in FIG. 3A, the carrier 14 is provided with a wafer holding hole 30, and the wafer 10 to be polished is disposed in the wafer holding hole 30.
Here, the case where one wafer holding hole 30 is provided in one carrier 14 is shown, but as shown in FIG. 4, a configuration in which a plurality of wafer holding holes 30 are provided in one carrier 14 is shown. It is also possible to take.

In the present embodiment, as shown in FIG. 3, an annular abrasive 12 for polishing a wafer edge is provided on the inner peripheral surface of the wafer holding hole 30. In the present embodiment, as shown in FIG. 3 (b), the abrasive 12 has a vertically symmetric vertical cross-sectional shape, and the upper and lower portions of the abrasive 12 are in the center direction of the semiconductor wafer holding hole 30. It is characterized by extending to. That is, the upper and lower portions of the abrasive 12 are gradually thinned inward symmetrically.
As a material of the abrasive 12, for example, a synthetic resin foam, a nonwoven fabric, a processed resin product of a nonwoven fabric, a synthetic leather, or a composite of any of these can be used.

Next, a double-side polishing method using the above-described double-side polishing apparatus and its operation and effect will be described with reference to FIGS. 1, 3, 5, 6, 7 and 12.
First, FIG. 1 is a cross-sectional view of a main part of the carrier according to the present embodiment. FIG. 1A shows a state before the wafer is inserted into the carrier, FIG. 1B shows a state where the wafer is inserted into the carrier, and FIG. 1C shows a state where the wafer is polished on both sides. As shown in FIG. 1B, the wafer 10 has an upper surface and a lower surface of the wafer 10 with the wafer edge polishing abrasive 12 shown in FIG. Is inserted into the wafer holding hole 30 of the carrier 14 so as to be sandwiched between. Here, the minimum inner diameter of the polishing material 12 for polishing the wafer edge is smaller than the outer diameter of the wafer 10, and the insertion is performed, for example, by utilizing the restoring property of the polishing material 12 itself. From this point of view, it is more desirable to use a material that is easy to restore as a polishing material for polishing the wafer edge.

  Next, as shown in FIG. 1C, the carrier 14 in which the wafer 10 is inserted is sandwiched between the upper surface of the lower polishing cloth 22a of the lower surface plate and the lower surface of the upper polishing cloth 24a of the upper surface plate. Polish. At this time, the double-side polishing is performed in such a manner that the upper and lower surfaces of the wafer edge are polished simultaneously with the front and back surfaces of the wafer so that the upper and lower surfaces are in contact with the abrasive for polishing the wafer edge.

In the present embodiment, as shown in FIG. 1C, during polishing of the wafer 10, the vertically symmetrical symmetry plane EE of the wafer edge polishing abrasive 12 and the horizontal direction of the wafer 10. Center planes WW coincide with each other. As described above, in order to make the vertically symmetrical symmetry plane EE of the abrasive 12 for polishing the wafer edge coincide with the horizontal center plane WW of the wafer 10, the thickness of the wafer 10 and the thickness of the carrier 14 are set. It is necessary to comprehensively optimize the double-side polishing conditions such as the elasticity of the lower polishing cloth 22a and the upper polishing cloth 24a and the load applied to the wafer 10.
Here, the term “match” is not necessarily limited to the case of matching without any error. That is, it is a concept that includes a deviation that can achieve the same action and effect as practically identical to the perfect match, specifically, a deviation of about ± 5% with respect to the thickness of the wafer 10.

    FIG. 12 is an explanatory diagram of a conventional carrier structure. 12A is a plan view of the carrier, and FIG. 12B is a cross-sectional view taken along the line CC of FIG. 12A showing the main part of the carrier. As described above, in the carrier of the prior art, the abrasive 12 for polishing the wafer edge has a vertically asymmetric structure as shown in FIG. For this reason, mainly the lower half of the wafer edge of the wafer 10 is polished during double-side polishing. Therefore, in order to polish both the upper and lower sides of the wafer edge, it is necessary to perform the double-side polishing while the upper and lower surfaces of the wafer 10 are reversed during the double-side polishing, and the double-side polishing process becomes complicated.

  In the present embodiment, as shown in FIG. 3, the abrasive 12 for polishing the wafer edge is vertically symmetrical. Therefore, unlike the prior art, it is possible to polish the top and bottom of the wafer edge simultaneously, and it becomes unnecessary to perform double-side polishing with the top and bottom surfaces reversed, and the double-side polishing process can be simplified.

Further, in the present embodiment, the upper and lower surfaces of the wafer edge are more evenly polished by matching the vertically symmetrical symmetry plane of the wafer edge polishing abrasive and the horizontal center plane of the wafer. It is possible. FIG. 5 is an explanatory diagram showing a state in which the symmetrical surface of the wafer edge polishing abrasive material does not coincide with the horizontal center surface of the wafer during double-side polishing. As shown in FIG. 5, since the carrier 14 sticks to the lower polishing cloth 22a due to gravity, the horizontal center plane W-W of the wafer 10 is symmetrical with the vertical symmetry plane E- of the polishing material 12 for wafer edge polishing. It is shifted upward relative to E. For this reason, the abrasive 12 contacts the upper and lower surfaces of the wafer edge unevenly, and it becomes difficult to completely and evenly polish the upper and lower surfaces of the wafer edge. In the present embodiment, the polishing material 12 contacts the upper and lower surfaces of the wafer edge evenly by matching the vertically symmetrical symmetry surface of the polishing material for polishing the wafer edge with the center surface in the horizontal direction of the wafer. In addition, the upper and lower surfaces of the wafer edge can be completely and evenly polished.
Then, as in this embodiment, the wafer thickness, carrier thickness, lower polishing cloth are used in order to make the symmetrical surface of the wafer edge polishing abrasive and the center plane in the horizontal direction of the wafer coincide with each other. It is necessary to optimize the double-sided polishing conditions such as the elasticity of the upper polishing cloth and the load applied to the wafer, not only for mirror polishing the front and back surfaces of the wafer, but also for polishing the wafer edge. It becomes.

As an example of optimizing the double-side polishing conditions, a case where the carrier thickness is adjusted will be described with reference to FIGS. 3, 6, and 7. 6 is a cross-sectional view of the main part of the carrier when the carrier is thicker than in FIG. 3, and FIG. 7 is a cross-sectional view of the main part of the carrier when the carrier is thin as compared to FIG.
Here, let us consider a case where conditions other than the thickness of the carrier and the load applied to the wafer are the same. Then, in the case of FIG. 6 (c) where the carrier is the thickest, it is applied to the wafer that is required to make the vertical symmetry plane of the polishing material for wafer edge polishing coincide with the horizontal center plane of the wafer. The load is the smallest among the three carrier thickness conditions. This is because the difference between the thickness of the wafer 10 and the thickness of the carrier 12 is the smallest. On the contrary, in the case of FIG. 7C in which the carrier is the thinnest, the wafer that is required to match the vertically symmetrical symmetry surface of the wafer edge polishing material with the horizontal center surface of the wafer. The applied load is the largest among the three carrier thickness conditions. This is because the difference between the thickness of the wafer 10 and the thickness of the carrier 12 is the largest, and it is necessary to greatly push the wafer into the lower polishing cloth 22a to compensate for this difference. And since the magnitude of the load is generally proportional to the polishing amount on the front and back surfaces of the wafer, the carrier thickness must be reduced in order to increase the polishing amount on the front and back surfaces of the wafer and make the polishing of the wafer edge even in the vertical direction. You can do it. On the other hand, in order to make the wafer edge polishing even in the vertical direction while reducing the polishing amount on the front and back surfaces of the wafer, it is necessary to increase the thickness of the carrier.

Next, the general principle of wafer edge polishing will be briefly described below.
FIG. 8 shows the positional relationship of the carrier 14 and the movement of the carrier 14 during double-side polishing. First, the carrier 14 has a gear (not shown) on its outer periphery. Then, the carrier 14 performs revolution (arrow R3) and rotation (arrow R2) from the rotation of the lower surface plate (not shown) and the upper surface plate (not shown) and the rotation of the sun gear 26 and the internal gear 28. Yes. The wafer 10 held in the wafer holding hole 30 of the carrier 14 that performs such revolution and rotation is rotated (arrow R1). Then, due to the rotation of the wafer 10, an abrasive (not shown) provided on the inner periphery of the wafer holding hole 30 for polishing the wafer 10 and the wafer edge relatively moves, and as a result, the wafer edge of the wafer 10 is moved. Mirror polishing is performed simultaneously with the polishing of the front and back surfaces of the wafer.
The rotation number ωw of this wafer is derived from the following (formula 1).

ωw = (Up + Lp) / 2− (ωc + Ωc) (Formula 1)

Here, Up is the rotation speed of the upper surface plate, Lp is the rotation speed of the lower surface plate, ωc is the rotation number of the carrier, and Ωc is the revolution number of the carrier.
As can be seen from this equation, if the number of rotations of the carrier is constant, the number of rotations of the wafer increases as the number of rotations of the upper and lower surface plates increases. Therefore, the improvement in the specularity of the wafer edge (increase in the polishing amount) can be realized by increasing the number of rotations of the upper and lower surface plates.
The carrier rotation number ωc and the carrier revolution number Ωc are expressed by the following (Equation 2) and (Equation 3), respectively.

ωc = Gi × Gs (is) / {Gc × (Gi + Gs)} (Expression 2)

Ωc = (Gi × i + Gs × s) / (Gi + Gs) (Formula 3)

Here, Gi is the number of teeth of the internal gear, Gs is the number of teeth of the sun gear, Gc is the number of teeth of the carrier, i is the number of rotations of the internal gear, and s is the number of rotations of the sun gear.
The specularity (polishing amount) of the wafer edge is determined by the magnitude of the carrier rotation number ωc derived from the above formula.

  As described above, according to the present embodiment, the upper surface and the lower surface of the wafer edge portion are evenly polished without reversing the upper surface and the lower surface of the wafer during the double-side polishing of the wafer, the quality is high, and Thus, it is possible to provide a double-side polishing apparatus and a double-side polishing method that enable manufacturing of a wafer with low manufacturing cost.

(Second Embodiment)
This embodiment is the same as the first embodiment except that the wafer edge polishing abrasive provided on the inner surface of the carrier is wider than the thickness of the carrier toward the center of the wafer holding hole. The description is omitted.

  FIG. 9 is a cross-sectional view of the main part of the carrier according to the present embodiment. FIG. 9A shows a state in which the wafer is inserted into the carrier, and FIG. 9B shows a state in which the wafer is polished on both sides. As shown in FIG. 9, in the present embodiment, the wafer edge polishing abrasive provided on the inner surface of the carrier extends in the vertical direction from the thickness of the carrier toward the center of the wafer holding hole. Features.

  As described above with reference to FIG. 7, it is conceivable that the thickness of the carrier 14 is reduced with respect to the wafer 10 in order to optimize the double-side polishing conditions in consideration of the polishing of the wafer edge. In this case, as in the first embodiment shown in FIG. 7, when the thickness of the carrier 14 and the vertical width of the polishing material 12 for polishing the wafer edge are equal, the wafer edge surface of the polishing material 12 is contacted. The area to be processed becomes small, and sufficient wafer edge polishing may not be realized at the uppermost and lowermost portions of the wafer edge.

On the other hand, as shown in FIG. 9B, in this embodiment, the polishing material 12 for polishing the wafer edge extends in the vertical direction from the thickness of the carrier toward the center of the wafer holding hole. Therefore, even when the carrier 14 is thin, the abrasive 12 sufficiently contacts the uppermost part and the lowermost part of the wafer edge.
Therefore, in addition to the effects of the first embodiment, it is possible to realize sufficiently uniform polishing of the wafer edge even when the carrier 14 is relatively thin with respect to the wafer 10.

(Third embodiment)
Since this embodiment is the same as the first embodiment except that the polishing material for wafer edge polishing can be divided into upper and lower parts, the description is omitted.

  FIG. 10 is a cross-sectional view of the main part of the carrier according to the present embodiment. 10A shows a state before the wafer is inserted into the carrier, FIG. 10B shows a state where the wafer is inserted into the carrier, and FIG. 10C shows a state where the wafer is polished on both sides. As shown in FIG. 10 (a), in the present embodiment, the upper half of the wafer edge polishing abrasive 12 fixed to a part of the inner periphery of the carrier 14 can be removed from the carrier body, The abrasive 12 can be divided into upper and lower parts.

As described above, by allowing the abrasive 12 to be divided vertically, it is possible to facilitate insertion of the wafer 10 into the carrier in addition to the effects of the first embodiment. That is, as shown in FIG. 10B, first, the wafer 10 is placed on the carrier 14 with the upper half of the abrasive 12 for polishing the wafer edge removed. Thereafter, the upper half of the polishing material 12 for polishing the wafer edge is placed and fixed so that the polishing material 12 covers the upper edge of the wafer 10. Then, as shown in FIG. 10C, the carrier 14 is sandwiched between the lower polishing cloth 22a and the upper polishing cloth 24a to perform double-side polishing of the wafer 10.
In this manner, making the abrasive 12 vertically split is particularly effective when a material that is not easily restored due to its properties is applied as the material of the abrasive 12.

Here, the upper half of the polishing material for wafer edge polishing is fixed to a part of the inner periphery of the carrier, but only the upper half of the polishing material for wafer edge polishing is removable. Alternatively, the entire upper half of the carrier may be divided along with the upper half of the polishing material for wafer edge polishing.
(Fourth embodiment)
This embodiment is the first embodiment except that the thickness of the carrier outer periphery is thinner than a part of the carrier, that is, the vicinity of the region where the abrasive for polishing the wafer edge is fixed. Since it is the same as that of form, description is abbreviate | omitted.

  FIG. 11 is a cross-sectional view of the main part of the carrier according to the present embodiment. 11A shows a state before the wafer is inserted into the carrier, FIG. 11B shows a state where the wafer is inserted into the carrier, and FIG. 11C shows a state where the wafer is polished on both sides. As shown in FIG. 11A, in the present embodiment, the thickness of the outer periphery of the carrier 14 is relatively smaller than the carrier thickness in the vicinity of the region where the abrasive 12 for polishing the wafer edge is fixed. It is characterized by being.

  By adopting such a structure, as shown in FIG. 11C, the area where the upper surface of the carrier 14 contacts the upper polishing cloth 24a during double-side polishing of the wafer 10 can be significantly reduced. Therefore, in addition to the effect of the first embodiment, the frictional resistance between the upper surface of the carrier 14 and the upper polishing pad 24a is reduced, and as a result, the power consumption necessary for maintaining the same number of revolutions of the upper board 24 is reduced. There is an effect that. Furthermore, the amount of wear of the upper polishing pad 24a is reduced, and the effect that the life of the upper polishing pad 24a is extended can be expected.

The embodiments of the present invention have been described above with reference to specific examples. In the description of the embodiment, the description of the double-side polishing apparatus, the double-side polishing method, etc., which is not directly necessary for the description of the present invention is omitted, but the required double-side polishing apparatus, double-side polishing method, etc. The elements involved can be appropriately selected and used.
In addition, all the double-side polishing apparatuses and double-side polishing methods that include the elements of the present invention and can be appropriately modified by those skilled in the art are included in the scope of the present invention.

Sectional drawing of the principal part of the carrier of 1st Embodiment. Explanatory drawing of the double-side polish apparatus which can be used in 1st Embodiment. Explanatory drawing of the structure of the carrier of 1st Embodiment. Explanatory drawing of the carrier which has several wafer holding holes of 1st Embodiment. Explanatory drawing of the state in which the symmetrical surface of the abrasive for polishing the wafer edge does not coincide with the horizontal center plane of the wafer Explanatory drawing about optimization of double-sided polishing conditions. Explanatory drawing about optimization of double-sided polishing conditions. Explanatory drawing which shows the positional relationship and movement of a carrier at the time of double-sided grinding | polishing. It is principal part sectional drawing of the carrier of 2nd Embodiment. It is principal part sectional drawing of the carrier of 3rd Embodiment. It is principal part sectional drawing of the carrier of 4th Embodiment. It is explanatory drawing of the structure of the carrier of a prior art.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Wafer 12 Polishing material 14 for wafer edge polishing Carrier 20 Double-side polishing apparatus 22 Lower surface plate 22a Lower polishing cloth 24 Upper surface plate 24a Upper polishing cloth 26 Sun gear 28 Internal gear 30 Wafer holding hole

Claims (5)

By rotating the lower surface plate provided with the polishing cloth for polishing the back surface of the semiconductor wafer and rotating the upper surface plate provided with the polishing cloth for polishing the surface of the semiconductor wafer facing the lower surface plate, A double-side polishing apparatus for polishing,
A semiconductor wafer holding hole is provided in a carrier disposed between the lower surface plate and the upper surface plate,
An annular semiconductor wafer edge polishing material is provided on the inner periphery of the semiconductor wafer holding hole,
The abrasive has a vertically symmetric vertical cross-sectional shape;
The double-side polishing apparatus, wherein an upper portion and a lower portion of the abrasive extend in the center direction of the semiconductor wafer holding hole.   The double-side polishing apparatus according to claim 1, wherein the abrasive can be divided into upper and lower parts.   2. The double-side polishing apparatus according to claim 1, wherein the material of the abrasive is a synthetic resin foam, a nonwoven fabric, a resin processed product of a nonwoven fabric, a synthetic leather, or a composite thereof. A double-side polishing method using the double-side polishing apparatus according to claim 1,
Inserting the semiconductor wafer into the wafer holding hole provided with the abrasive so that the upper and lower surfaces of the wafer edge of the semiconductor wafer are sandwiched between the abrasive; and
A double-side polishing method comprising the step of simultaneously polishing the upper and lower surfaces of the wafer edge and both the front and back surfaces of the semiconductor wafer. 5. The double-side polishing method according to claim 4, wherein, in the polishing step, a vertically symmetrical symmetry plane of the abrasive coincides with a horizontal center plane of the semiconductor wafer.

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