JP2008078674A - Semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor memory device capable of reducing the capacity between a resistive element and a substrate in a peripheral circuit of a semiconductor device, especially a non-volatile semiconductor memory, such as a flash memory. <P>SOLUTION: A flash memory is formed in a semiconductor substrate 1, and an element isolation insulating film 2 dividing an element region, a gate oxide film 4 in an element region 3 isolated from the element isolating region 2, a first gate electrode 5 functioning as a floating gate (FG), a second gate electrode material 7 functioning as a control gate (CG: word line) of a central transistor are formed on a first insulating film 6. In the peripheral circuit section, a resistive element 7a is provided comprising the second gate electrode material via the first insulating film 6 on the element isolation insulating film 2. The impurity concentration of the semiconductor substrate 1 below the resistive element 7a is equal to or lower than that of bulk. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to the structure of a peripheral circuit portion of, for example, a semiconductor device, particularly a nonvolatile semiconductor memory.

  In general, a flash memory has various delay circuits necessary for operation, a high voltage stabilizing circuit for writing / erasing, and a reference voltage generating circuit in addition to memory cells in a chip. For this reason, the resistance element which comprises these circuits is needed. As these resistive elements, generally resistive elements having ohmic characteristics are used. In order to increase the efficiency of the manufacturing process, this resistance element is formed in substantially the same process as the formation of the memory cell when the chip is formed.

  As an example of a circuit using the above-described resistance element, the operation of a high voltage stabilizing circuit for writing / erasing will be described with reference to FIG. FIG. 7A schematically shows a high voltage stabilizing circuit for writing / erasing, and FIG. 7B shows each voltage during the above-described operation. As shown in FIG. 7A, this circuit is feedback for controlling the output voltage of the booster circuit. That is, for example, the resistance elements R1 and R2 are connected to the output terminal of the booster circuit composed of a charge pump circuit. These resistors R1 and R2 divide the output voltage of the booster circuit to generate a voltage Va. This voltage Va is compared with the reference voltage Vref in the operational amplifier OP1, and a control signal Φ1 is generated. The booster circuit operates in response to the control signal Φ1, and the output voltage is controlled.

  As shown in FIG. 7B, when the voltage Va becomes smaller than the reference voltage Vref, the booster circuit shown in FIG. 7A operates. When the voltage Va becomes larger than the reference voltage Vref, the boosting is stopped and the potential rises. So that the feedback works. As a result, the output voltage is maintained at the required voltage Vpp.

  However, if the capacitance between the resistance elements R1 and R2 and other nodes in the semiconductor substrate is large, the delay due to the CR time constant increases. Then, the feedback is delayed, and the output voltage greatly deviates from the required voltage Vpp. This hinders stable operation and high-speed operation of the flash memory. Therefore, the smaller the capacitance between the resistance element and the node of another element, the more accurate voltage stabilization circuit can be realized.

  FIG. 8 schematically shows a cross-sectional view of a conventional flash memory. In this flash memory, as shown in FIG. 8, an element isolation region 22 is formed in a silicon substrate 21, and then a gate oxide film 24 and a first gate electrode 25 are sequentially deposited in the element region 23 of the cell portion. Yes. The first gate electrode 25 is used as a floating gate in the cell portion and used as a resistance element 25a in the peripheral circuit portion. In FIG. 8, 26 is a first insulating film, 27 is a second gate electrode, 28 is an insulating film between layers, and 30 is a wiring.

  There is also a method in which the first gate electrode as a floating gate in the cell portion has a two-layer structure, and in the peripheral circuit portion, the resistance element 25a is formed with an upper layer gate material.

  In the case of the above example, the resistive element 25a is formed on the thick element isolation region 22 in the peripheral circuit portion. For this reason, the capacity | capacitance of the resistive element 25a and the other node in a semiconductor substrate can be made small.

  However, in the flash memory configured as described above, the first gate electrode 25 is formed after the element isolation region 22 is formed. Therefore, as shown in FIG. 8, the first gate electrode 25 protrudes on the element isolation region 22. Therefore, the element isolation region 22 cannot be reduced in size and it is difficult to further miniaturize the element.

  FIG. 9 shows another conventional example and shows a cross-sectional view of a flash memory. In FIG. 9, the same parts as those in FIG. In this flash memory, as shown in FIG. 9, a gate oxide film 24 of about several tens to 500 Å is formed on the entire surface of the substrate 21, and then a first gate electrode material 25 is deposited on the gate oxide film 24. The first gate electrode material 25, the gate oxide film 24, and the substrate 21 are etched to form a trench 21a. The trench is filled with an insulating film to form an element isolation region 22. Therefore, the element isolation region 22 and the first gate electrode G are isolated in a self-aligning manner. In the peripheral circuit portion, the first gate electrode material 25 on the gate oxide film 24 is used as the resistance element 25a. In such a configuration, since the element isolation region 22 can be reduced in size, the memory cell can be further miniaturized.

  However, in the peripheral circuit portion, the resistance element 25a is formed on the gate oxide film 24 of about several tens to about 500 mm. For this reason, the capacity | capacitance between the resistive element 25a and the board | substrate 21 will increase.

  As described above, when the capacitance between the resistance element and the substrate increases, the feedback operation of the high voltage stabilization circuit is delayed, making it difficult to generate a stable voltage.

  The present invention provides a semiconductor memory device capable of reducing the capacitance between a resistance element and a substrate in a peripheral circuit portion even when the first gate electrode is element-isolated in a self-aligning manner.

  A semiconductor memory device according to an example of the present invention includes an element isolation insulating film that is formed in a semiconductor substrate and partitions an element region, and a resistance element including a conductive film formed on the element isolation insulating film, The impurity concentration of the semiconductor substrate under the element is equal to or less than the bulk impurity concentration.

  A semiconductor memory device according to an example of the present invention includes an element isolation insulating film that is formed in a first conductivity type semiconductor substrate and partitions an element region, and a resistance element including a conductive film formed on the element isolation insulating film. A semiconductor substrate formed in an element region adjacent to the element isolation insulating film in which the resistance element is formed, and an impurity region of the second conductivity type of the reverse conductivity type, and the resistance element and the second conductivity type at the time of reading, writing or erasing A voltage having the same polarity is applied to the impurity region of two conductivity types.

  According to the present invention, it is possible to provide a semiconductor memory device capable of reducing the capacitance between the resistance element and the substrate in the peripheral circuit portion even when the first gate electrode is element-isolated in a self-aligning manner.

  Embodiments of the present invention will be described below with reference to the drawings.

  A first embodiment of a flash memory according to the present invention will be described with reference to FIG. FIG. 1 is a cross-sectional view schematically showing a flash memory. As shown in FIG. 1, in the cell portion, a gate oxide film 4 and a first gate electrode 5 are formed in an element region 3 isolated by an element isolation region 2 in a semiconductor substrate 1. Therefore, the first gate electrode 5 does not exist on the element isolation region 2. The first gate electrode 5 functions as a floating gate (FG).

  Further, a second gate electrode material 7 is formed on the first insulating film 6. The second gate electrode material 7 functions as a control gate (CG: word line) of the cell transistor.

  In the peripheral circuit portion, a resistance element 7 a made of a second gate electrode material 7 is provided on the element isolation region 2 with a first insulating film 6 interposed therebetween.

  In addition, 8 is a 2nd insulating film, 9 is a contact, 10 is wiring.

  According to the above configuration, the resistance element 7 a is formed on the element isolation region 2 via the first insulating film 6 in the peripheral circuit portion. Therefore, the capacitance between the resistance element 7a and the substrate 1 can be reduced. Therefore, the CR delay can be reduced, and the high voltage stabilization circuit using the resistance element 7a can be operated stably and with high accuracy.

  A method for manufacturing the flash memory having the above configuration will be described below with reference to FIG.

  In FIG. 2A, 1 is a semiconductor substrate. Reference numeral 4 denotes a gate oxide film, for example, silicon oxide or silicon nitride. Reference numeral 5 denotes a first gate electrode material, for example, polysilicon or amorphous silicon. A gate oxide film 4 and a first gate electrode material 5 are sequentially formed on the entire surface of the semiconductor substrate 1. A mask material 11 made of an insulator is formed on the first gate electrode material 5. Using this mask material 11 as a mask, the first gate electrode 5, the gate oxide film 4 and the substrate 1 are etched in a self-aligned manner to form trenches 12 as shown in FIG.

  Next, as shown in FIG. 2B, an insulating film 2a is deposited on the entire surface and polished by a CMP (Chemical Mechanical Polishing) method using the mask material 11 as a stopper. By doing so, the insulating film 2a is removed up to the surface of the mask material 11, and the trench 12 is filled with the insulating film 2a. Thereafter, the mask material 11 is removed, and the element isolation region 2 is formed as shown in FIG. Thus, a floating gate (FG) made of the first gate electrode material 5 is formed in a self-aligned manner with respect to the element isolation region 2.

  Subsequently, a second insulating film 6 and a second gate electrode material 7 are sequentially deposited on the entire surface. Next, as shown in FIG. 2D, the second gate electrode material 7 and part of the gate oxide film 6 are etched. In this manner, the word line as the control gate (CG) is formed by the second gate electrode material 7 in the cell portion, and the resistance element 7a is formed by the second gate electrode material 7 in the peripheral circuit portion. . Thereafter, as shown in FIG. 1, a second insulating film 8 is deposited on the entire surface, and a contact hole 9 is formed in the second insulating film 8. At this time, in the peripheral circuit portion, the contact hole 9 is formed in a predetermined portion of the resistance element 7a so as to obtain a required resistance value. Subsequently, a metal film is formed on the entire surface of the second insulating film 8 to fill the contact hole 9. Thereafter, the metal film is etched and the wiring 10 is formed.

  According to the first embodiment, since the floating gate FG is formed in a self-aligned manner with the element isolation region 2 in the cell portion, the size of the cell can be reduced. Moreover, in the peripheral circuit portion, the resistance element 7 a is formed on the element isolation region 2 by the second gate electrode material 7 via the insulating film 6. For this reason, since the element isolation region 2 and the insulating film 6 are interposed between the resistance element 7a and the substrate 1, the capacitance of the resistance element 7a and the substrate 1 can be reduced. Therefore, a stable and highly accurate boosted voltage can be generated by applying the resistance element 7a to, for example, a high voltage stabilizing circuit.

  In the first embodiment, the resistance element 7 a in the peripheral circuit portion is formed of the second gate electrode material 7. However, it is not limited to this. For example, it is possible to form a resistance element by wiring other than the word line formed above the second gate electrode material 7. This wiring is formed of polysilicon having a sheet resistance of, for example, 100Ω or more. With such a configuration, the capacitance between the resistance element 7a and the substrate 1 can be further reduced.

  FIG. 3 shows a second embodiment of the present invention. FIG. 3A schematically shows a cross-sectional view of a peripheral circuit portion of the flash memory. This configuration is almost the same as in the first embodiment.

  In the second embodiment, in addition to the above-described configuration, P-type or N-type impurities are not implanted into the surface of the semiconductor substrate 1 located below the resistance element 7a, and the impurity concentration is the same as that of the bulk. Alternatively, when the conductivity type of the semiconductor substrate 1 is, for example, P type, an impurity having a conductivity type opposite to this, for example, N type, is implanted into the substrate surface.

  Usually, a P-type or N-type well is formed in a semiconductor substrate, and a cell portion and a peripheral circuit are formed in this well. For this reason, the impurity concentration in the semiconductor substrate 1 increases as it approaches the surface, that is, as the depth X becomes shallower, as indicated by a broken line in FIG. On the other hand, in the second embodiment, by setting the semiconductor substrate 1 to the same impurity concentration as that of the bulk, the impurity concentration can be kept constant as shown by a solid line in FIG. Further, by implanting an impurity having a conductivity type opposite to that of the semiconductor substrate 1, the impurity concentration on the surface of the substrate 1 can be lowered as shown by a one-dot chain line in FIG. When the impurity concentration in the substrate 1 is high, the capacitance with the resistance element 7a increases. However, by setting the impurity concentration in the substrate 1 low as in the second embodiment, the capacitance between the resistance element 7a and the substrate is increased. The capacity can be reduced. Therefore, a highly accurate and stable boosted voltage can be generated by a high voltage stabilization circuit using a resistance element.

  FIG. 4 shows a third embodiment of the present invention, and the same parts as those in the first and second embodiments are denoted by the same reference numerals.

  In the second embodiment, when the semiconductor substrate 1 is, for example, P-type and the insulating film 8 thereon is positively charged, if the impurity concentration of the semiconductor substrate 1 is low, electrons are collected on the surface of the semiconductor substrate 1 and inverted. Sometimes. In this state, when a high voltage is applied to the resistance element 7a, the inverted electrons in the surface of the substrate 1 are collected in the substrate 1 immediately below the resistance element 7a, and the time variation of the voltage of the resistance element 7a causes the time in the inversion layer. The movement of the voltage follows. Therefore, the capacitance between the resistance element 7a and the semiconductor substrate 1 is increased.

  Therefore, in the third embodiment, as shown in FIG. 4, for example, a high-concentration P-type impurity is implanted in the P-type semiconductor substrate 1 so as to correspond to the periphery of the resistance element 7a. In this way, the high concentration region 13 is formed in the substrate 1.

  According to the third embodiment, the high concentration region 13 is formed around the resistance element 7 a on the surface of the semiconductor substrate 1. Thus, even when a high voltage is applied to the resistance element 7a and electrons are generated on the surface of the semiconductor substrate 1, it is possible to prevent the electrons from collecting on the surface of the substrate 1 below the resistance element 7a. Therefore, it is possible to prevent the surface of the semiconductor substrate 1 under the resistance element 7a from being inverted. Therefore, an increase in capacitance between the resistance element 7a and the semiconductor substrate 1 can be suppressed, and a boosted voltage can be stably generated with high accuracy by the high voltage stabilization circuit using the resistance element 7a.

  5 (a) and 5 (b) schematically show a fourth embodiment of the present invention. In FIG. 5A, the same parts as those in FIG.

  In the fourth embodiment, as shown in FIG. 5A, in order to reduce the capacitance between the resistance element 7a and the substrate 1, an element region adjacent to the resistance element 7a is formed in a reverse conductivity type opposite to the substrate 1. Region 14 is assumed. Further, a contact is formed in the reverse conductivity type region 14 so that a potential can be applied independently of the resistance elements 7a to the substrate 1.

  Hereinafter, a case where the semiconductor substrate 1 is P-type and the reverse conductivity type region 14 is N-type will be described as an example. However, in the case of an N-type semiconductor substrate, the same operation is performed by inverting the conductivity type and the potential. it can.

  The resistance element 7a included in the voltage stabilization circuit operates to stably supply a specific potential when reading, writing, or erasing data according to the operation of the flash memory. At this time, as shown in FIG. 5B, a positive potential is applied to the resistance element 7a, and the semiconductor substrate 1 is set to the ground potential Vss. At the same time, a positive potential is applied to the reverse conductivity type region 14. During the time other than those described above, the resistance element 7a and the reverse conductivity type region 13 are set to the ground potential Vss.

  When a positive potential is applied to the resistance element 7a, an inversion layer is formed in the semiconductor substrate 1 within the time during which the resistance element 7a is operated. Then, the capacity between the resistance element 7a and the semiconductor substrate 1 increases. Therefore, the positive potential applied to the reverse conductivity type region 14 is optimally controlled so that the depletion layer 15 below the resistance element 7a and the depletion layer formed around the reverse conductivity type region 14 are connected. Thereby, the minority carrier electrons generated in the substrate 1 under the resistance element 7 a can be absorbed by the reverse conductivity type region 14. Therefore, generation of an inversion layer in the semiconductor substrate 1 under the resistance element 7a can be suppressed. That is, the depletion layer 15 that reacts to the oscillation of the potential of the resistance element 7a is driven deeper into the semiconductor substrate 1 (Deep-Depletion). Then, the change of the depletion layer on the surface of the semiconductor substrate 1 is reduced. Therefore, the capacitance between the semiconductor substrate 1 and the resistance element 7a can be reduced.

  According to the fourth embodiment, the same effects as those of the first to third embodiments can be obtained.

  FIG. 6 shows a fifth embodiment of the present invention. The fifth embodiment is a modification of the first embodiment. In FIG. 6, the same parts as those in FIG. 1 are denoted by the same reference numerals.

  In order to increase the capacitance between the floating gate 5 and the control gate 7 in the cell portion, a method is considered in which the element isolation region of the cell portion is etched so that the height of the element isolation region is lower than the height of the floating gate 5. Yes.

  However, according to the above method, when the element isolation region is etched, if the height of the element isolation region in the peripheral circuit portion is also reduced, the capacitance between the resistance element 7a and the substrate increases.

  Therefore, in the fifth embodiment, as shown in FIG. 6, when the element isolation region 2 'of the cell portion is etched, the region where the resistance element 7a of the element isolation region 2 is formed is covered. By doing so, as shown in FIG. 6, the height of the element isolation region 2 of the peripheral circuit can be maintained.

  According to the fifth embodiment, the same effect as that of the first embodiment can be obtained. Further, the height of the element isolation region 2 'in the cell portion is set lower than that of the floating gate. By doing so, the capacity of the memory cell can be increased.

  The case where the floating gate has a single layer structure has been described in the first to fifth embodiments. However, the present invention is not limited to this, and the floating gate may have a two-layer structure, and the resistance element may be formed of an upper gate material.

  Of course, various modifications can be made without departing from the scope of the present invention.

  As described above, according to the present invention, the semiconductor memory device can reduce the capacitance between the resistance element and the substrate in the peripheral circuit section even when the first gate electrode is isolated in a self-aligning manner. Can provide.

The figure which shows the 1st Example of the flash memory which concerns on this invention. The figure which shows the manufacture process in 1st Example of the flash memory based on this invention. The figure which shows the 2nd Example of the flash memory which concerns on this invention. The figure which shows the 3rd Example of the flash memory based on this invention. The figure which shows the 4th Example of the flash memory which concerns on this invention. The figure which shows the 5th Example of the flash memory based on this invention. The figure which shows the step-up potential stabilization circuit using a resistance element, and a waveform. The figure which shows the 1st prior art example of flash memory. The figure which shows the other conventional example of flash memory.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 2 ... Element isolation region, 3 ... Element region, 4 ... Gate oxide film, 5 ... 1st gate electrode material, 6 ... 1st insulating film, 7 ... 2nd gate electrode material, 7a ... Resistance element, 8 ... second insulating film, 9 ... contact hole, 10 ... wiring.

Claims (4)

An element isolation insulating film formed in the semiconductor substrate and partitioning the element region;
Comprising a resistive element made of a conductive film formed on the element isolation insulating film,
2. A semiconductor memory device according to claim 1, wherein an impurity concentration of the semiconductor substrate under the resistance element is equal to or less than a bulk impurity concentration.   2. The semiconductor memory according to claim 1, wherein the semiconductor substrate has an impurity region having the same conductivity type as the semiconductor substrate and having a higher concentration than the semiconductor substrate on a surface of a region surrounding a lower periphery of the resistance element. apparatus. An element isolation insulating film that is formed in a semiconductor substrate of the first conductivity type and partitions an element region;
A resistance element made of a conductive film formed on the element isolation insulating film;
The semiconductor substrate formed in the element region adjacent to the element isolation insulating film in which the resistance element is formed, and an impurity region of a second conductivity type of a reverse conductivity type,
A semiconductor memory device, wherein a voltage having the same polarity is applied to the resistance element and the impurity region of the second conductivity type at the time of reading, writing, or erasing.   When the semiconductor substrate is p-type, a positive voltage is applied to the resistance element and the second conductivity type impurity region, and when the semiconductor substrate is n-type, the resistance element and the second conductivity type impurity are applied. 4. The semiconductor memory device according to claim 3, wherein a negative voltage is applied to the region.

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