JP2008078344A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To widen a margin to an electrical short circuit caused by a contact between a wiring layer and a through hole which occurs for a misalignment in forming the through hole through between wiring layers formed on a semiconductor substrate. <P>SOLUTION: A method for manufacturing a semiconductor device comprises the steps of depositing an insulating film 101 on the semiconductor substrate 100, depositing a conductive film 102 on the insulating film, forming an interconnection pattern 105 by conducting a dry etching process to the conductive film, depositing a protective insulating film 110 so as to cover the interconnection pattern, forming a through hole 111 so as to penetrate through the interconnection pattern in the protective insulating film, and forming a plug 112 in the through-hole. Making the size of the upper part of the interconnection pattern smaller than that of the lower part of the interconnection pattern makes the space width between the upper parts of the interconnection pattern larger than that between the lower parts of the interconnection pattern. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  According to the present invention, when a through hole is formed through a wiring layer formed on a semiconductor substrate, a margin for an electrical short caused by contact between the wiring layer and the through hole caused by misalignment can be increased. The present invention relates to a semiconductor device and a manufacturing method thereof.

  In recent years, there has been a growing demand for higher speed and lower power consumption in semiconductor devices. For this reason, miniaturization of element sizes such as the dimensions of the wiring patterns constituting the semiconductor device, the space width between the wiring patterns, and the contact diameter for electrically connecting the semiconductor substrate and the upper wiring layer is accelerating. In particular, in a semiconductor device having a thickness of 0.09 μm or less, the space width between the wiring layers has become as small as 200 nm or less, and an unavoidable alignment misalignment that occurs in the lithography process when forming a contact plug through the wiring layer ( As a result, the electrical short margin between the contact and the adjacent wiring layer has become increasingly severe.

Hereinafter, an example of a manufacturing process of a conventional semiconductor device will be described with reference to FIGS. First, as shown in FIG. 8A, a known photolithography technique and a dry etching technique are used to form a gate electrode 3 made of, for example, a 150 nm polysilicon film on a semiconductor substrate 1 with a 2 nm gate oxide film 2 interposed therebetween. It forms using. At this time, the space width 3a between the gate electrodes 3 is 140 nm. Next, the N-type diffusion layer 4 having a low impurity concentration, which becomes a part of the source / drain diffusion layer, is self-aligned by ion implantation using the gate electrode 3 as a mask (for example, P ⁺ is 5 × 10 ¹³ / cm ² ). To form.

  Next, as shown in FIG. 8B, a silicon oxide film (not shown) is deposited by, for example, 10 nm by the CVD method so as to cover the surface of the substrate to be processed, and then a silicon nitride film (not shown) is formed. For example, 30 nm is deposited by the CVD method. Next, anisotropic etching is performed on the laminated film of the silicon oxide film and the silicon nitride film to remove the silicon oxide film and the silicon nitride film so that only the side surface of the gate electrode 3 is left, and a sidewall having a width of 30 nm. The spacer 5 is formed.

Next, as shown in FIG. 8C, the gate electrode 3 and the side wall spacer 5 are used as a mask, and the source / drain diffusion layers are formed by ion implantation (for example, As ⁺ 5 × 10 ¹⁵ / cm ² ). A high-concentration diffusion layer 6 which is another part is formed in a self-aligning manner.

  Next, as shown in FIG. 9A, a silicide layer 7 made of, for example, a compound of Si and Co is formed on the upper portion of the gate electrode 3 and the upper portion of the source / drain diffusion layer 4 using a known salicide technique. To do. Then, after depositing a silicon oxide film (not shown) by, for example, 700 nm by a CVD method, the silicon oxide film is polished by 300 nm using a known CMP method, and a flattened silicon oxide film having a thickness of 400 nm is obtained. 8 is formed.

  Next, as shown in FIG. 9B, a through hole 9 for connecting to the semiconductor substrate 1 through the gate electrode 3 is formed on the silicon oxide film 8 by using a lithography technique and a dry etching technique. The through hole 9 has a hole diameter 9a of 80 nm. At this time, in the lithography process when forming the through-hole 9, an alignment deviation 9b of about 35 nm that cannot be avoided occurs.

  Next, as shown in FIG. 9C, a Ti / TiN film (not shown) is deposited by CVD, for example, 10 nm / 30 nm, and then a W film (not shown) is deposited by CVD, for example, 100 nm. To do. Next, the plug 10 for electrically connecting the semiconductor substrate and the upper layer wiring is formed by removing an unnecessary portion of the Ti / TiN film and the W film by using a CMP method.

  Here, in the manufacturing process of the semiconductor device shown in FIGS. 8 to 9, the gate electrode 3 and the plug 10 are in contact with each other by about 5 nm due to the alignment shift 9 b when the through hole 9 is formed (reference numeral 11). As a result, there arises a problem that an electrical short circuit failure occurs.

However, Patent Document 1 discloses one method for preventing the contact between the gate electrode and the plug caused by the alignment shift. In this Patent Document 1, as shown in FIG. 10, silicon nitride films 24 and 25 are formed on the gate electrode 22 and on the side wall 23 formed on the semiconductor substrate 21, thereby passing through the silicon oxide film 26. It has been proposed that when the hole 27 and the wiring 28 are formed, the contact between the gate electrode 22 and the wiring 28 can be prevented.
JP-A-6-177265

  However, when the through hole is formed between the gate electrodes using the above-described conventional technique such as Patent Document 1, the following problems occur. Since an extra step of forming a silicon nitride film on the gate electrode or on the side wall of the side wall is necessary, the number of steps increases and the manufacturing cost of the semiconductor device increases. In addition, when the semiconductor device is further miniaturized and the space width between the gate electrodes becomes smaller, when forming the silicon nitride film on the side wall of the sidewall, the space between the gate electrodes is filled with the silicon nitride film, There arises a problem that through holes cannot be formed.

  Accordingly, an object of the present invention is to solve the conventional drawbacks as described above, and in the process of forming a through hole between gate electrodes, even when the miniaturization of a semiconductor device element is advanced, the alignment displacement is reduced. It is an object of the present invention to provide a semiconductor device capable of expanding an electrical short margin caused by contact between a gate electrode and a through hole due to the above and a manufacturing method thereof.

  In order to achieve the above object, a semiconductor device according to claim 1 of the present invention includes a plurality of wiring patterns formed on a semiconductor substrate, an insulating film deposited so as to cover the wiring patterns, and a wiring in the insulating film. A through hole formed so as to pass between the patterns and a plug made of a conductive film embedded in the through hole is provided, and the upper width dimension of the wiring pattern is smaller than the lower width dimension. .

  3. The method of manufacturing a semiconductor device according to claim 2, wherein a step of depositing an insulating film on the semiconductor substrate, a step of depositing a conductive film on the insulating film, and a plurality of wiring patterns by performing a dry etching process on the conductive film. In the step of forming the wiring pattern, the width of the upper portion of the wiring pattern is made smaller than the width of the lower portion.

  A method for manufacturing a semiconductor device according to claim 3 is the method for manufacturing a semiconductor device according to claim 2, wherein a step of depositing a protective insulating film so as to cover the wiring pattern and a space between the wiring patterns in the protective insulating film are provided. In this way, a step of forming a through hole and a step of forming a plug in the through hole are included.

  A method for manufacturing a semiconductor device according to claim 4 is the method for manufacturing a semiconductor device according to claim 2 or 3, wherein the step of depositing the conductive film includes the step of depositing a polysilicon film on the insulating film, and a polysilicon film. A step of implanting a group V impurity by ion implantation to form a region having a high group V impurity concentration on the polysilicon film, and the step of forming a wiring pattern includes the step of implanting the group V impurity. The polysilicon film is dry-etched so that the width dimension of the portion where the V group impurity concentration is high located at the upper part of the wiring pattern is changed to the width dimension of the portion where the V group impurity concentration is located below the wiring pattern. Make it smaller than the width dimension.

  The method of manufacturing a semiconductor device according to claim 5 is the method of manufacturing a semiconductor device according to claim 4, wherein the dry etching process of the polysilicon film into which the Group V impurity is implanted is performed using polysilicon having a high Group V impurity concentration. The etching is performed under the condition that the etching rate of the film is higher than that of the polysilicon film having a low Group V impurity concentration.

  A method for manufacturing a semiconductor device according to claim 6 is the method for manufacturing a semiconductor device according to claim 4 or 5, wherein the polysilicon film into which the Group V impurities are implanted is subjected to a dry etching process using fluorine (F), chlorine ( A gas containing a halogen element such as Cl), bromine (Br), or iodine (I) is used.

  A method of manufacturing a semiconductor device according to claim 7 is the method of manufacturing a semiconductor device according to claim 2 or 3, wherein the step of depositing the conductive film includes a step of depositing a polysilicon film on the insulating film, and a polysilicon film. A step of depositing a doped polysilicon film containing a Group V impurity, and a step of forming a wiring pattern is a dry etching process on a laminated film in which a polysilicon film and a doped polysilicon film are sequentially deposited. Then, the width dimension of the doped polysilicon film portion located above the wiring pattern is made smaller than the width dimension of the polysilicon film portion located below the wiring pattern.

  The method of manufacturing a semiconductor device according to claim 8 is the method of manufacturing a semiconductor device according to claim 7, wherein the dry etching process of the laminated film in which the polysilicon film and the doped polysilicon film are sequentially deposited is performed as a group V impurity. The etching is performed under the condition that the etching rate of the polysilicon film having a high concentration is higher than the etching rate of the polysilicon film having a low V group impurity concentration.

  A method for manufacturing a semiconductor device according to claim 9 is the method for manufacturing a semiconductor device according to claim 7 or 8, wherein the dry etching process of the laminated film in which the polysilicon film and the doped polysilicon film are sequentially deposited is performed by fluorine ( A gas containing a halogen element such as F), chlorine (Cl), bromine (Br), or iodine (I) is used.

The method of manufacturing a semiconductor device according to claim 10 is the method of manufacturing a semiconductor device according to claim 2 or 3, wherein the step of forming the wiring pattern is performed by forming an organic film, SiC _w H _x O _y N _z ( sequentially depositing an organic-inorganic hybrid film represented by w> 0, x ≧ 0, y> 0, z ≧ 0), forming a resist pattern on the organic-inorganic hybrid film by lithography, and resist pattern And a step of dry-etching the laminated film of the organic film and the organic-inorganic hybrid film to form a laminated film pattern of the organic film and the organic-inorganic hybrid film. Etching is performed to reduce the upper width dimension of the wiring pattern compared to the lower width dimension.

  The method for manufacturing a semiconductor device according to claim 11 is the method for manufacturing a semiconductor device according to claim 10, wherein the dry etching process of the organic film includes an element of oxygen (O), nitrogen (N), or hydrogen (H). A gas is used and a fluorocarbon gas is used for the dry etching treatment of the organic-inorganic hybrid film.

  The method for manufacturing a semiconductor device according to claim 12 is the method for manufacturing a semiconductor device according to claim 10, wherein the dry etching process of the conductive film is performed by etching the organic-inorganic hybrid film functioning as a mask material during the dry etching process. The condition is set so as to disappear.

  A method for manufacturing a semiconductor device according to claim 13 is the method for manufacturing a semiconductor device according to claim 10 or 12, wherein the conductive film is subjected to a dry etching process of fluorine (F), chlorine (Cl), bromine (Br) or iodine. A gas containing a halogen element (I) is used.

  According to the semiconductor device of the first aspect of the present invention, since the width of the upper part of the wiring pattern is smaller than the width of the lower part, the space width between the upper parts of the wiring pattern is lower than the lower part of the wiring pattern. It becomes larger than the space width. For this reason, when the through hole is formed between the wirings, the space width between the upper parts of the wirings is wide even if an alignment misalignment occurs of about 35 nm, so that contact between the wirings and the through holes can be avoided. That is, the electrical short margin between the plug and the adjacent wiring layer can be increased. Furthermore, as semiconductor device elements become finer, the space width between wirings becomes smaller and the embedding property of the insulating film between the wirings becomes more severe, but the space width between the upper parts of the wiring becomes the space width between the lower parts of the wiring. Since it is larger than the above, it becomes an advantageous structure for the embedding property of the insulating film.

  According to the semiconductor device manufacturing method of the present invention, the upper width of the wiring pattern is smaller than the lower width, so that the space width between the upper portions of the wiring pattern is reduced. It becomes larger than the space width between the lower parts of the pattern.

  In the present invention, the method for manufacturing a semiconductor device according to claim 3 can provide the same effects as those of the semiconductor device according to claim 1.

  According to the present invention, in the method of manufacturing a semiconductor device according to claim 4, in the step of depositing the conductive film, a polysilicon film is deposited on the insulating film, and a group V impurity is implanted into the polysilicon film. Thus, a region having a high Group V impurity concentration can be formed on the upper portion of the polysilicon film. When forming a wiring pattern by performing dry etching on the polysilicon film, the size of the portion of the V group having a high impurity concentration located on the polysilicon film can be selectively reduced. Thereby, the space width between the upper parts of the wiring pattern can be made larger than the space width between the lower parts of the wiring pattern.

  According to the present invention, in the method of manufacturing a semiconductor device according to claim 5, the etching rate of the polysilicon film having a high V group impurity concentration is higher than the etching rate of the polysilicon film having a low V group impurity concentration. The dry etching process is performed under the faster conditions. For this reason, when forming a wiring pattern by dry-etching a polysilicon film into which a group V impurity is implanted, an upper portion of the polysilicon film having a high group V impurity concentration is laterally extended. Since the etching easily proceeds, the size of the upper portion of the polysilicon film can be selectively reduced.

  In the present invention, according to the method of manufacturing a semiconductor device according to claim 6, fluorine (F), chlorine (Cl), bromine (Br) is used for the dry etching process of the polysilicon film into which the Group V impurity is implanted. ) Or iodine (I) containing a halogen element is preferably used. Since the halogen element generally has a high electron affinity, the reactivity with a material containing excessive electrons tends to increase, and the etching rate tends to increase. Therefore, the etching rate of the polysilicon film having a high group V impurity concentration is higher than the etching rate of the polysilicon film having a low group V impurity concentration.

  According to the present invention, in the method of manufacturing a semiconductor device according to claim 7, in the step of depositing the conductive film, a polysilicon film is deposited on the insulating film, and a group V impurity is deposited on the polysilicon film. Since the doped polysilicon film is deposited, when the wiring pattern is formed by dry etching the stacked film of the polysilicon film and the doped polysilicon film containing the Group V impurity, the doped polysilicon film It is possible to selectively reduce the size of the upper portion of the wiring. Thereby, the space width between the upper parts of the wiring pattern can be made larger than the space width between the lower parts of the wiring pattern.

  According to the semiconductor device manufacturing method of the present invention, the etching rate of the polysilicon film having a high V group impurity concentration is higher than the etching rate of the polysilicon film having a low V group impurity concentration. The dry etching process is performed under the faster conditions. For this reason, when a wiring pattern is formed by dry etching the laminated film of the polysilicon film and the doped polysilicon film, the lateral direction is not applied to the doped polysilicon film located on the upper part of the wiring. Since the etching easily proceeds, the dimension of the upper part of the wiring pattern can be selectively reduced.

  Further, in the present invention, according to the method for manufacturing a semiconductor device according to claim 9, as in the method for manufacturing a semiconductor device according to claim 6, the polysilicon film and the doped polysilicon film containing a group V impurity It is preferable to use a gas containing a halogen element such as fluorine (F), chlorine (Cl), bromine (Br), or iodine (I) in the dry etching process.

Further, in the present invention, according to the method for manufacturing a semiconductor device according to claim 10, the organic film and SiC _w H _x O _y N _{z are} used as a mask material when the conductive film is dry-etched to form a wiring pattern. A laminated film pattern of an organic-inorganic hybrid film represented by (w> 0, x ≧ 0, y> 0, z ≧ 0) is used. In this case, the organic / inorganic hybrid film functions as an etching mask material in the initial stage of dry etching the conductive film. In a dry etching process of a conductive film, a product such as an organic substance generated from a mask material is generally used as a protective film against side etching on the side wall of an etchant pattern. However, when the organic / inorganic hybrid film is an etching mask, the content of the organic element is small, so that the amount of products generated from the mask material that serves to protect the pattern sidewall is small. For this reason, while the organic-inorganic hybrid film functions as a mask material, side etching with respect to the conductive film easily proceeds and the pattern dimension becomes small. If the organic-inorganic hybrid film is etched away during the dry etching of the conductive film, the lower organic film functions as an etching mask material. In this case, as in the case of normal dry etching, the amount of products generated from the mask material increases, so that side etching on the conductive film is suppressed. For this reason, the pattern dimension of the conductive film after the mask material is switched to the organic film is increased. In this way, by using a laminated film of an organic film and an organic / inorganic hybrid film as a mask material, when forming a wiring pattern by dry-etching the conductive film, the size of the upper part of the wiring can be selectively reduced. Can do. Thereby, the space width between the upper parts of the wiring pattern can be made larger than the space width between the lower parts of the wiring pattern.

According to the semiconductor device manufacturing method of the invention, in the present invention, a gas containing an element of oxygen (O), nitrogen (N) or hydrogen (H) is used for the dry etching process of the organic film. It is preferable to use a fluorocarbon gas for the dry etching treatment of the organic-inorganic hybrid film represented by SiC _w H _x O _y N _z (w> 0, x ≧ 0, y> 0, z ≧ 0). Here, in the dry etching process of the organic-inorganic hybrid film, the upper resist pattern functions as a mask material. In the organic film dry etching process, the organic-inorganic hybrid film functions as a mask material. Since the etching gas at this time is a gas containing oxygen, nitrogen and hydrogen elements, the organic-inorganic hybrid film of the mask material is hardly etched.

According to the semiconductor device manufacturing method of the twelfth aspect of the present invention, as described in the effect of the semiconductor device manufacturing method of the tenth aspect of the present invention, as a mask material during the dry etching process, It is preferable that conditions be set so that the organic / inorganic hybrid film represented by the functioning SiC _w H _x O _y N _z (w> 0, x ≧ 0, y> 0, z ≧ 0) is etched away. .

  According to the method of manufacturing a semiconductor device according to the thirteenth aspect of the present invention, the dry etching treatment of the conductive film includes fluorine (F), chlorine (Cl), bromine (Br), or iodine (I) halogen. It is preferable to use a gas containing an element.

  A first embodiment of the present invention will be described with reference to FIGS. 1 to 2 are process cross-sectional views illustrating the manufacturing process of the semiconductor device according to the first embodiment of the present invention.

  The main points of the manufacturing method according to the first embodiment of the present invention are that after the step of forming an insulating film on a semiconductor substrate and the step of depositing a polysilicon film on the insulating film, a group V is formed on the upper portion of the polysilicon film. When the polysilicon film is dry-etched to form a wiring pattern, the width dimension of the upper portion of the polysilicon film in which the V group impurity concentration is high is selectively reduced. It is. The space width between the upper parts of the wiring pattern is made larger than the space width between the lower parts of the wiring pattern.

First, as shown in FIG. 1A, a polysilicon film 102 of, eg, 150 nm is deposited on a semiconductor substrate 100 through a gate oxide film 101 of, eg, 2 nm by a CVD method. Next, P (not shown) is implanted by 8E15 / cm ² at an acceleration energy of 15 keV, for example, by ion implantation to form a polysilicon film 103 having a high P concentration. The thickness of the polysilicon film 103 having a high P concentration is about 50 nm. Next, using a known photolithography method, a polysilicon film 103 having a high P concentration and a resist pattern 104 serving as a mask when the polysilicon film 102 is dry-etched are formed.

Next, as shown in FIG. 1B, using the resist pattern 104 as a mask, the polysilicon film 103 and the polysilicon film 102 having a high P concentration are dry-etched to form a gate electrode 105 as a wiring pattern. . At this time, the space width 105a between the lower portions of the gate electrode 105 is 140 nm. The dimension of the upper part of the gate electrode 105 is 20 nm smaller than the dimension of the lower part of the gate electrode 105, and the space width 105b between the upper parts of the gate electrode 105 is 160 nm. Next, the N-type diffusion layer 106 having a low impurity concentration, which becomes a part of the source / drain diffusion layer, is self-aligned by ion implantation (for example, P ⁺ is 5 × 10 ¹³ / cm ² ) using the gate electrode 105 as a mask. To form.

  Next, as shown in FIG. 1C, a silicon oxide film (not shown) is deposited by, for example, 10 nm by the CVD method so as to cover the surface of the substrate to be processed, and then a silicon nitride film (not shown) is formed. For example, 30 nm is deposited by the CVD method. Next, anisotropic etching is performed on the laminated film of the silicon oxide film and the silicon nitride film to remove the silicon oxide film and the silicon nitride film so that only the side surface of the gate electrode 105 is left, and a sidewall having a width of 30 nm. A spacer 107 is formed. The sidewall spacer 107 also functions as a protective film for preventing the contact between the side surface of the gate electrode 105 and the through hole 111 when forming the subsequent through hole 111.

Next, as shown in FIG. 1D, the gate electrode 105 and the side wall spacer 107 are used as a mask, and the source / drain diffusion layers of the source / drain diffusion layer are formed by ion implantation (for example, As ⁺ is 5 × 10 ¹⁵ / cm ² ). A high-concentration diffusion layer 108 to be another part is formed in a self-aligning manner.

  Next, as shown in FIG. 2A, a silicide layer 109 made of, for example, a compound of Si and Co is formed on the upper portion of the gate electrode 105 and the upper portion of the source / drain diffusion layer 106 using a known salicide technique. To do. Then, after depositing a silicon oxide film (not shown) by, for example, 700 nm by a CVD method, the silicon oxide film is polished by 300 nm using a known CMP method, and a flattened silicon oxide film having a thickness of 400 nm is obtained. 110 is formed.

  Next, as shown in FIG. 2B, a through hole 111 for connecting to the semiconductor substrate 100 through the gate electrode 105 is formed on the silicon oxide film 110 using a lithography technique and a dry etching technique. The through hole 111 has a hole diameter 111a of 80 nm. At this time, in the lithography process when forming the through-hole 111, an alignment deviation 111b of 35 nm that cannot be avoided occurs.

  Next, as shown in FIG. 2C, a Ti / TiN film (not shown) is deposited by CVD, for example, 10 nm / 30 nm, and then a W film (not shown) is deposited by CVD, for example, 100 nm. To do. Next, unnecessary portions of the Ti / TiN film and the W film are removed by CMP to form a plug 112 for electrically connecting the semiconductor substrate and the upper layer wiring.

  In this embodiment, an inevitable alignment shift 111b of 35 nm occurs in the lithography process when forming the through hole 111, but the dimension of the upper part of the gate electrode 105 is larger than the dimension of the lower part of the gate electrode 105. Since it is 20 nm smaller, no contact between the gate electrode 105 and the plug 112 occurs. That is, the contact between the gate electrode 105 and the plug 112, that is, the electrical short margin can be expanded by 5 nm, compared with the case where the upper and lower portions of the gate electrode 105 have the same dimensions.

Here, an example of conditions for dry-etching the polysilicon film 103 and the polysilicon film 102 having a high P concentration is shown. In dry etching, an inductively coupled plasma etching apparatus provided with two or more high-frequency power sources capable of independently controlling plasma generation and ion energy control was used. As the dry etching conditions, the first step of etching partway between the polysilicon film 103 and the polysilicon film 102 with high P concentration, the second step of etching the remaining polysilicon film 102, and the residue of the polysilicon film 102 are removed. It consists of a three-step configuration of the third step.
<First step>
Processing pressure: 1.0 (Pa)
Upper applied power (for plasma generation) ... 600 (W)
Lower applied power (for ion energy control) ... 60 (W)
Gas: Cl ₂ / O ₂ = 100/20 (ml / min)
Wafer temperature: 20 ° C
<Second step>
Processing pressure: 1.0 (Pa)
Upper applied power (for plasma generation) ... 600 (W)
Lower applied power (for ion energy control) ... 20 (W)
Gas: HBr / O ₂ = 100/4 (ml / min)
Wafer temperature: 20 ° C
<Third step>
Processing pressure: 5.0 (Pa)
Upper applied power (for plasma generation) ... 600 (W)
Lower applied power (for ion energy control) ... 40 (W)
Gas: HBr / O ₂ / He = 100/4/100 (ml / min)
Wafer temperature: 20 ° C
Here, since the halogen element generally has a high electron affinity, the reactivity with a material containing excessive electrons tends to increase and the etching rate tends to increase. FIG. 3 shows the results of comparing the etching rates of the polysilicon film in which P is implanted at 8E15 / cm ² with the acceleration energy of 15 keV and the polysilicon film into which no impurity is implanted with respect to the conditions in step 1. In FIG. 3, the horizontal axis indicates the film type, and the vertical axis indicates the ratio of the polysilicon film not doped with impurities to the etching rate. FIG. 3 shows that the etching rate of the polysilicon film implanted with P is about 20% faster than the etching rate of the polysilicon film. Therefore, in the present embodiment, when etching is performed under the condition of Step 1, the lateral etching with respect to the polysilicon film 103 having a higher P concentration is larger than the polysilicon film 102. Therefore, the dimension of the upper part of the gate electrode 105 is 20 nm smaller than the dimension of the lower part of the gate electrode 105.

  As described above, in the manufacturing method according to the present embodiment, when the gate electrode is formed by implanting P into the upper portion of the polysilicon film and dry-etching the polysilicon film, the P concentration increases. The size of the upper portion of the polysilicon film can be selectively reduced. Since the space width between the upper portions of the gate electrodes can be made larger than the space width between the lower portions of the gate electrodes, a margin for contact between the gate electrodes and the through holes can be increased when forming the through holes between the gate electrodes. Can be enlarged.

  Further, in the step of forming the polysilicon film 103 having a high P concentration, the film thickness of the polysilicon film 103 having a high P concentration can be changed by the implantation energy when P is implanted, and the P concentration is varied depending on the P implantation amount. Can be changed. That is, by controlling the implantation energy and concentration at the time of implanting P, the size reduction amount in the upper portion of the polysilicon film can be controlled in the horizontal and vertical directions.

  Note that a gas containing a halogen element such as fluorine (F), chlorine (Cl), bromine (Br), or iodine (I) is used for the dry etching process of the polysilicon film into which the Group V impurity is implanted. it can.

  A second embodiment of the present invention will be described with reference to FIGS. 4 to 5 are process cross-sectional views illustrating the manufacturing process of the semiconductor device according to the second embodiment of the present invention.

  The main points of the manufacturing method according to the second embodiment of the present invention are a step of forming an insulating film on a semiconductor substrate, a step of depositing a polysilicon film on the insulating film, and a group V impurity on the polysilicon film. After the step of depositing the doped polysilicon film, the doped polysilicon film and the doped polysilicon film containing Group V impurities are dry-etched to form a wiring pattern. This is to selectively reduce the width dimension of the silicon film portion. The space width between the upper parts of the wiring pattern is made larger than the space width between the lower parts of the wiring pattern.

First, as shown in FIG. 4A, a polysilicon film 202 of, for example, 100 nm is deposited on the semiconductor substrate 200 through a gate oxide film 201 of, for example, 2 nm by a CVD method. Next, a doped polysilicon film 203 containing 5E20 / cm ^{3 of} P is deposited by, for example, 50 nm by the CVD method. Next, using a known photolithography method, a resist pattern 204 is formed that serves as a mask when the doped polysilicon film 203 and the polysilicon film 202 are dry-etched.

Next, as shown in FIG. 4B, using the resist pattern 204 as a mask, the doped polysilicon film 203 and the polysilicon film 202 are dry-etched to form a gate electrode 205 as a wiring pattern. At this time, the space width 205a between the lower portions of the gate electrode 205 is 140 nm. The dimension of the upper part of the gate electrode 205 is 20 nm smaller than the dimension of the lower part of the gate electrode 205, and the space width 205b between the upper parts of the gate electrode 205 is 160 nm. Next, the N-type diffusion layer 206 having a low impurity concentration, which becomes a part of the source / drain diffusion layer, is self-aligned by ion implantation (for example, P ⁺ is 5 × 10 ¹³ / cm ² ) using the gate electrode 205 as a mask. To form.

  Next, as shown in FIG. 4C, a silicon oxide film (not shown) is deposited by, for example, 10 nm by the CVD method so as to cover the surface of the substrate to be processed, and then a silicon nitride film (not shown) is formed. For example, 30 nm is deposited by the CVD method. Next, anisotropic etching is performed on the laminated film of the silicon oxide film and the silicon nitride film to remove the silicon oxide film and the silicon nitride film so as to leave only the side surface of the gate electrode 205, and a sidewall having a width of 30 nm. A spacer 207 is formed. The sidewall spacer 207 also functions as a protective film that prevents the side surface of the gate electrode 205 from contacting the through hole 211 when the subsequent through hole 211 is formed.

Next, as shown in FIG. 4D, the gate electrode 205 and the side wall spacer 207 are used as a mask, and the source / drain diffusion layers of the source / drain diffusion layer are formed by ion implantation (for example, As ⁺ is 5 × 10 ¹⁵ / cm ² ). A high-concentration diffusion layer 208 to be another part is formed in a self-aligning manner.

  Next, as shown in FIG. 5A, a silicide layer 209 made of, for example, a compound of Si and Co is formed on the upper portion of the gate electrode 205 and the upper portion of the source / drain diffusion layer 206 by using a known salicide technique. To do. Then, after depositing a silicon oxide film (not shown) by, for example, 700 nm by a CVD method, the silicon oxide film is polished by 300 nm using a known CMP method, and a flattened silicon oxide film having a thickness of 400 nm is obtained. 210 is formed.

  Next, as shown in FIG. 5B, through holes 211 for connecting to the semiconductor substrate 200 through the gaps between the gate electrodes 205 are formed on the silicon oxide film 210 by using a lithography technique and a dry etching technique. The through hole 211 has a hole diameter 211a of 80 nm. Further, at this time, in the lithography process when forming the through hole 211, an alignment deviation 211b of 35 nm that cannot be avoided occurs.

  Next, as shown in FIG. 5C, a Ti / TiN film (not shown) is deposited by CVD, for example, 10 nm / 30 nm, and then a W film (not shown) is deposited by CVD, for example, 100 nm. To do. Next, unnecessary portions of the Ti / TiN film and the W film are removed by CMP to form a plug 212 for electrically connecting the semiconductor substrate and the upper layer wiring.

  In this embodiment, an inevitable alignment shift 211b of 35 nm occurs in the lithography process when forming the through hole 211, but the dimension of the upper part of the gate electrode 205 is larger than the dimension of the lower part of the gate electrode 205. Since it is 20 nm smaller, no contact between the gate electrode 205 and the plug 212 occurs. That is, the contact between the gate electrode 205 and the plug 212, that is, the electrical short margin can be expanded by 5 nm, compared with the case where the upper and lower portions of the gate electrode 205 have the same dimensions.

  Here, in the dry etching process of the doped polysilicon film 203 and the polysilicon film 202, the dimensions of the upper part of the gate electrode 205 are reduced by using the same conditions as those in the first embodiment. It was possible to make it 20 nm smaller than the dimension.

  As described above, in the manufacturing method according to the present embodiment, when the gate electrode is formed by dry etching the stacked film of the polysilicon film and the doped polysilicon film containing P, the doped polysilicon film The size of the part can be selectively reduced. Since the space width between the upper portions of the gate electrodes can be made larger than the space width between the lower portions of the gate electrodes, a margin for contact between the gate electrodes and the through holes can be increased when forming the through holes between the gate electrodes. Can be enlarged.

  Further, in the step of forming the doped polysilicon film 203, by controlling the P concentration and the film thickness contained in the doped polysilicon film, the dimensional thinning amount in the doped polysilicon film 203 is vertically increased. Each can be controlled laterally.

  A third embodiment of the present invention will be described with reference to FIGS. 6 to 7 are process cross-sectional views illustrating the manufacturing process of the semiconductor device according to the third embodiment of the present invention.

The main point of the manufacturing method according to the third embodiment of the present invention is that a wiring pattern is formed by performing a dry etching process on a conductive film after a step of depositing an insulating film on a semiconductor substrate and a step of depositing a conductive film on the insulating film. As a mask material for dry etching, an organic film and an organic-inorganic hybrid film represented by SiC _w H _x O _y N _z (w> 0, x ≧ 0, y> 0, z ≧ 0) are used. By using the laminated film pattern to control the amount of product generated from the mask material during dry etching, the width dimension of the upper part of the wiring layer is made smaller than the width dimension of the lower part of the wiring layer. is there. The space width between the upper parts of the wiring pattern is made larger than the space width between the lower parts of the wiring pattern.

  First, as shown in FIG. 6A, a polysilicon film 302 of, eg, 150 nm is deposited on a semiconductor substrate 300 by a CVD method through a gate oxide film of, eg, 2 nm. Next, an organic resist film 303 containing 85% or more of carbon is deposited to a thickness of 200 nm by a coating method. Next, an SiOC film 304 having a Si content of about 25% is deposited by a coating method to a thickness of 70 nm. Next, a resist pattern 305 having a film thickness of, for example, 250 nm is formed using a known lithography method.

Next, as shown in FIG. 6B, the SiOC film 304 and the organic film 303 are dry-etched using the resist pattern 305 as a mask to form a laminated film pattern 306 of the SiOC film 304 and the organic film 303. . Here, in this dry etching process, a parallel plate type plasma etching apparatus provided with two or more high-frequency power sources capable of independently controlling plasma generation and ion energy control was used. The dry etching conditions include a two-step configuration of a first step for etching the SiOC film 304 and a second step for etching the organic film 303.
<First step>
Processing pressure: 6.7 (Pa)
Upper applied power (for plasma generation) ... 1000 (W)
Lower applied power (for ion energy control) 50 (W)
Gas: CF ₄ = 100 (ml / min)
Wafer temperature: 0 ° C
<Second step>
Processing pressure: 1.3 (Pa)
Upper applied power (for plasma generation) ... 600 (W)
Lower applied power (for ion energy control) ... 100 (W)
Gas: O ₂ / N ₂ = 100/200 (ml / min)
Wafer temperature: 0 ° C
In the first step of the dry etching process, the resist pattern 305 functions as an etching mask material. In the second step, since the O ₂ / N ₂ gas is used as the etching gas, the resist pattern 305 is lost at the initial stage of the etching in the second step. Accordingly, during the second step etching, the SiOC film 304 functions as a mask material. However, since the etching gas in the second step is O ₂ / N ₂ gas, the etching selectivity of the organic film 303 to the SiOC film 304 is high. Even after the etching of the organic film 303 is finished, the SiOC film 304 remains almost unetched.

Next, using the laminated film pattern 306 of the SiOC film 304 and the organic film 303 as a mask, the polysilicon film 302 is dry-etched to form a gate electrode 307 as a wiring pattern. Here, in this dry etching process, an inductively coupled plasma etching apparatus provided with two or more high-frequency power sources capable of independently controlling plasma generation and ion energy control was used. The dry etching conditions include a first step of etching the polysilicon film 302 by 100 nm, a second step of etching the remaining 50 nm of the polysilicon film 302 while ensuring an etching selection ratio with the base insulating film, The third etching step is a third step of removing the residue of the polysilicon film 302 while securing the etching selectivity.
<First step>
Processing pressure: 1.0 (Pa)
Upper applied power (for plasma generation) ... 600 (W)
Lower applied power (for ion energy control) 50 (W)
Gas: CF ₄ / Cl ₂ / HBr = 20/100/20 (ml / min)
Wafer temperature: 20 ° C
<Second step>
Processing pressure: 1.0 (Pa)
Upper applied power (for plasma generation) ... 600 (W)
Lower applied power (for ion energy control) ... 20 (W)
Gas: HBr / O ₂ = 100/4 (ml / min)
Wafer temperature: 20 ° C
<Third step>
Processing pressure: 5.0 (Pa)
Upper applied power (for plasma generation) ... 600 (W)
Lower applied power (for ion energy control) ... 40 (W)
Gas: HBr / O ₂ / He = 100/4/100 (ml / min)
Wafer temperature: 20 ° C
In the first step of the dry etching process, a CF ₄ gas having a low etching selection ratio of the polysilicon film 302 to the SiOC film 304 is used as an etching gas, and when the polysilicon film 302 has been etched by 50 nm, the SiOC gas is removed. The setting is such that the film 304 is eliminated. Therefore, the SiOC film 304 functions as an etching mask material when the polysilicon film 302 is etched by 50 nm, and the organic film 303 functions as an etching mask material when the remaining 100 nm of the polysilicon film 302 is etched. Become.

  FIG. 6C shows a process cross-sectional view at the time when the first step in the dry etching process of the polysilicon film 302 is completed. In this first step, the polysilicon film 302 is etched by 100 nm. In the first step, the SiOC film 304 serves as a mask material while the polysilicon film 302 is etched by 50 nm, so that the supply of products from the mask material is small during this time. For this reason, the adhesion amount of the sidewall protective film to the polysilicon film 302 is reduced, and the etching in the lateral direction is likely to proceed. In contrast, while the remaining 100 nm of the polysilicon film 302 is being etched, the organic film 303 serves as a mask material, so that the supply of products from the mask material increases. For this reason, the adhesion amount of the side wall protective film with respect to the polysilicon film 302 increases, and the etching in the lateral direction is suppressed. Accordingly, in the first step, since the etching mask material changes during the dry etching of the polysilicon film 302, the dimension of the upper part of the polysilicon film 302 is larger than the dimension of the lower part of the polysilicon film 302. Get smaller.

  FIG. 6D is a process cross-sectional view at the time when the second step and the third step in the dry etching process of the polysilicon film 302 are completed. In the second and third steps, since the organic film 303 functions as an etching mask material, etching in the lateral direction does not proceed. In this way, the gate electrode 307 is formed in which the size of the upper portion is smaller than the size of the lower portion.

  At this time, the space width 307a between the lower portions of the gate electrode 307 is 140 nm. The dimension of the upper part of the gate electrode 307 is 20 nm smaller than the dimension of the lower part of the gate electrode 307, and the space width 307b between the upper parts of the gate electrode 307 is 160 nm.

Next, as shown in FIG. 7A, an N-type diffusion layer 308 with a low impurity concentration, which becomes a part of the source / drain diffusion layer, is used as a mask with the gate electrode 307 as a mask (for example, P ⁺ is 5 × 10 5). ¹³ / cm ² ). Next, a silicon oxide film (not shown) is deposited by, for example, 10 nm so as to cover the surface of the substrate to be processed, and then a silicon nitride film (not shown) is deposited by, for example, 30 nm by the CVD method. Next, anisotropic etching is performed on the laminated film of the silicon oxide film and the silicon nitride film to remove the silicon oxide film and the silicon nitride film so that only the side surface of the gate electrode 307 is left, and a sidewall having a width of 30 nm. A spacer 309 is formed. The side wall spacer 309 also functions as a protective film that prevents the side surface of the gate electrode 307 and the through hole 313 from coming into contact when the subsequent through hole 313 is formed. Next, using the gate electrode 307 and the sidewall spacer 309 as a mask, a high-concentration diffusion layer that becomes the other part of the source / drain diffusion layer by ion implantation (for example, As ⁺ 5 × 10 ¹⁵ / cm ² ). 310 is formed in a self-aligning manner.

  Next, as shown in FIG. 7B, a silicide layer 311 made of, for example, a compound of Si and Co is formed on the upper portion of the gate electrode 307 and the upper portion of the source / drain diffusion layer 308 using a known salicide technique. To do. Then, after depositing a silicon oxide film (not shown) by, for example, 700 nm by a CVD method, the silicon oxide film is polished by 300 nm using a known CMP method, and a flattened silicon oxide film having a thickness of 400 nm is obtained. 312 is formed. Next, a through hole 313 for connecting to the semiconductor substrate 300 through between the gate electrodes 307 is formed on the silicon oxide film 312 using a lithography technique and a dry etching technique. The through hole 313 has a hole diameter 313a of 80 nm. At this time, in the lithography process when forming the through hole 313, an alignment deviation 313b of 35 nm that cannot be avoided is generated.

  Next, as shown in FIG. 7C, a Ti / TiN film (not shown) is deposited by CVD, for example, 10 nm / 30 nm, and then a W film (not shown) is deposited by CVD, for example, 100 nm. To do. Next, unnecessary portions of the Ti / TiN film and the W film are removed by CMP to form a plug 314 for electrically connecting the semiconductor substrate and the upper layer wiring.

  In this embodiment, an inevitable alignment shift 313b of 35 nm occurs in the lithography process when forming the through hole 313, but the dimension of the upper part of the gate electrode 307 is larger than the dimension of the lower part of the gate electrode 307. Since it is 20 nm smaller, no contact between the gate electrode 307 and the plug 314 occurs. That is, the contact between the gate electrode 307 and the plug 314, that is, the electrical short margin can be expanded by 5 nm, compared with the case where the upper and lower portions of the gate electrode 307 have the same dimensions.

As described above, in the manufacturing method according to the present embodiment, when the gate electrode is formed by dry etching the polysilicon film, the organic film and SiC _w H _x O _y N _z ( By controlling the amount of product generated from the mask material during dry etching using a laminated film pattern of an organic-inorganic hybrid film represented by w> 0, x ≧ 0, y> 0, z ≧ 0) The dimension of the upper part of the wiring layer can be made smaller than the dimension of the lower part of the wiring layer. Since the space width between the upper portions of the gate electrodes can be made larger than the space width between the lower portions of the gate electrodes, a margin for contact between the gate electrodes and the through holes can be increased when forming the through holes between the gate electrodes. Can be enlarged.

  Here, in the step of dry-etching the polysilicon film 302 using the laminated film pattern 306 of the organic film and the SiOC film as a mask material, the SiOC film 304 is changed by changing the film thickness of the SiOC film 304 and the dry etching conditions. It is possible to control the amount of shaving of the polysilicon film 302 at the time when it disappears. That is, by changing the film thickness of the SiOC film 304 and the dry etching conditions, the amount of dimension reduction in the upper part of the polysilicon film 302 can be controlled in the vertical and horizontal directions, respectively.

  In the embodiment of the present invention, the case where a polysilicon film is used as the conductive film has been described. However, the same effect can be obtained for metal compounds such as W, Ti, Co, and Pt.

Note that a gas containing an element such as oxygen (O), nitrogen (N), or hydrogen (H) is used for the dry etching process of the organic film, and a fluorocarbon such as CF ₄ is used for the dry etching process of the organic-inorganic hybrid film. Gas (C _x F _y ) or hydrofluorocarbon gas (CH _x F _y ) can be used. For the dry etching treatment of the conductive film, a gas containing a halogen element such as fluorine (F), chlorine (Cl), bromine (Br), or iodine (I) can be used.

  In Embodiments 1, 2, and 3 of the present invention, inductively coupled plasma and two-frequency parallel plate plasma are used for ion generation. However, ECR (Electron Cytron Resonance) type plasma and capacitively coupled plasma are used. Even if microwave excitation type plasma is used, the same effect can be obtained.

  In the embodiment of the present invention, the effect of the invention has been described by taking a polysilicon gate electrode as an example. However, the wiring pattern formation of other conductive films, for example, the formation of a metal gate electrode using a W film, a TiN film, etc. It can also be applied to bit line wiring formation, upper layer wiring pattern formation using an aluminum film, and the like.

  The method for manufacturing a semiconductor device according to the present invention is useful as a method for manufacturing a semiconductor device having a step of forming a through hole through a wiring layer formed on a semiconductor substrate.

FIG. 5D is a process cross-sectional view illustrating the manufacturing method of the semiconductor device according to the first embodiment of the invention. FIG. 2 is a process cross-sectional view subsequent to FIG. 1. It is a figure showing the etch rate ratio of the P containing polysilicon film and polysilicon film in the 1st Embodiment of this invention. It is process sectional drawing explaining the manufacturing method of the semiconductor device by the 2nd Embodiment of this invention. FIG. 5 is a process sectional view subsequent to FIG. 4. It is process sectional drawing explaining the manufacturing method of the semiconductor device by the 3rd Embodiment of this invention. FIG. 7 is a process sectional view subsequent to FIG. 6; It is process sectional drawing for demonstrating the manufacturing method of the conventional semiconductor device. FIG. 9 is a process sectional view subsequent to FIG. 8. It is process sectional drawing for demonstrating the manufacturing method of the conventional semiconductor device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Gate oxide film 3 Polysilicon film 3a Space between gate electrodes 4 Source / drain diffusion layer 5 Side wall spacer 6 Source / drain diffusion layer 7 Silicide layer 8 Planarized silicon oxide film 9 Through hole 9a Through hole 9b Alignment deviation 10 Plug 21 Semiconductor substrate 22 Gate electrode 23 Side wall 24, 25 Silicon nitride film 26 Silicon oxide film 27 Through hole 28 Wiring 100 Semiconductor substrate 101 Gate oxide film 102 Polysilicon film 103 Poly in which P is implanted Silicon film 104 Resist pattern 105 Gate electrode 105a Space width between lower portions of gate electrode 105b Space width between upper portions of gate electrode 106 Source / drain diffusion layer 107 Side wall spacer 10 Source / drain diffusion layer 109 Silicide layer 110 Flattened silicon oxide film 111 Through hole 111a Hole diameter of through hole 111b Alignment shift 112 Plug 200 Semiconductor substrate 201 Gate oxide film 202 Polysilicon film 203 Polysilicon film implanted with P 204 Resist pattern 205 Gate electrode 205a Space width between lower portions of gate electrode 205b Space width between upper portions of gate electrode 206 Source / drain diffusion layer 207 Side wall spacer 208 Source / drain diffusion layer 209 Silicide layer 210 Flattened silicon oxide Film 211 Through hole 211a Hole diameter 211b Alignment shift 212 Plug 300 Semiconductor substrate 301 Gate oxide film 302 Polysilicon film 303 Organic film 304 SiC _w H _x O _y N _z (w> 0, x ≧ 0, y> 0, z ≧ 0) Organic-inorganic hybrid film 305 Resist pattern 306 Organic film and SiC _w H _x O _y Stack pattern of organic-inorganic hybrid film represented by N _z (w> 0, x ≧ 0, y> 0, z ≧ 0) 307 Gate electrode 307a Space width between lower portions of gate electrode 307b Space between upper portions of gate electrodes Width 308 Source / drain diffusion layer 309 Side wall spacer 310 Source / drain diffusion layer 311 Silicide layer 312 Planarized silicon oxide film 313 Through hole 313a Hole diameter 313b Alignment displacement 314 Plug

Claims (13)

  A plurality of wiring patterns formed on a semiconductor substrate; an insulating film deposited so as to cover the wiring patterns; a through hole formed in the insulating film so as to pass between the wiring patterns; and the through hole A semiconductor device comprising: a plug made of a conductive film embedded therein, wherein an upper width dimension of the wiring pattern is smaller than a lower width dimension.   Depositing an insulating film on a semiconductor substrate; depositing a conductive film on the insulating film; and performing a dry etching process on the conductive film to form a plurality of wiring patterns. The step of forming a pattern is characterized in that the upper width dimension of the wiring pattern is made smaller than the lower width dimension.   Depositing a protective insulating film to cover the wiring pattern; forming a through hole in the protective insulating film so as to pass between the wiring patterns; and forming a plug in the through hole; A method for manufacturing a semiconductor device according to claim 2, comprising:   The step of depositing the conductive film includes a step of depositing a polysilicon film on the insulating film, a group V impurity is implanted into the polysilicon film by an ion implantation method, and a group V group is formed on the polysilicon film. A step of forming a region having a high impurity concentration, wherein the step of forming the wiring pattern is performed by performing a dry etching process on the polysilicon film into which the Group V impurities are implanted, and is positioned above the wiring pattern. 4. The semiconductor device according to claim 2, wherein a width dimension of a portion where the Group V impurity concentration is high is made smaller than a width dimension of a portion where the V group impurity concentration is low and located below the wiring pattern. Production method.   The dry etching process of the polysilicon film into which the group V impurity is implanted is performed under the condition that the etching rate of the polysilicon film having a high group V impurity concentration is higher than the etching rate of the polysilicon film having a low group V impurity concentration. The method of manufacturing a semiconductor device according to claim 4, wherein   The gas containing a halogen element of fluorine (F), chlorine (Cl), bromine (Br), or iodine (I) is used for dry etching treatment of the polysilicon film into which the group V impurity is implanted. The manufacturing method of the semiconductor device of description.   The step of depositing the conductive film includes the step of depositing a polysilicon film on the insulating film, and the step of depositing a doped polysilicon film containing a Group V impurity on the polysilicon film, The step of forming a wiring pattern is performed by performing a dry etching process on the laminated film in which the polysilicon film and the doped polysilicon film are sequentially deposited, and the width of the doped polysilicon film portion located above the wiring pattern. 4. The method of manufacturing a semiconductor device according to claim 2, wherein the size of the semiconductor device is made smaller than a width of a polysilicon film portion located below the wiring pattern.   The dry etching process of the laminated film in which the polysilicon film and the doped polysilicon film are sequentially deposited is performed by etching the polysilicon film having a high group V impurity concentration and the etching speed of the polysilicon film having a low group V impurity concentration. The method of manufacturing a semiconductor device according to claim 7, wherein the method is performed under a faster condition.   A gas containing a halogen element such as fluorine (F), chlorine (Cl), bromine (Br), or iodine (I) is used for the dry etching process of the laminated film in which the polysilicon film and the doped polysilicon film are sequentially deposited. A method for manufacturing a semiconductor device according to claim 7 or 8. The step of forming the wiring pattern includes an organic film on the conductive film, an organic / inorganic hybrid film represented by SiC _w H _x O _y N _z (w> 0, x ≧ 0, y> 0, z ≧ 0). A step of sequentially depositing a layer, a step of forming a resist pattern on the organic-inorganic hybrid film by a lithography method, and a dry etching treatment of the laminated film of the organic film and the organic-inorganic hybrid film using the resist pattern as a mask, Forming a laminated film pattern of the organic film and the organic-inorganic hybrid film, and performing a dry etching process on the conductive film using the laminated pattern as a mask to reduce the width of the upper part of the wiring pattern to the lower part 4. The method of manufacturing a semiconductor device according to claim 2, wherein the width is made smaller than the width of the semiconductor device.   The gas containing an oxygen (O), nitrogen (N), or hydrogen (H) element is used for the dry etching process of the organic film, and a fluorocarbon gas is used for the dry etching process of the organic-inorganic hybrid film. Semiconductor device manufacturing method.   The method for manufacturing a semiconductor device according to claim 10, wherein the dry etching process of the conductive film is set so that the organic-inorganic hybrid film functioning as a mask material is etched away during the dry etching process.   13. The method for manufacturing a semiconductor device according to claim 10, wherein a gas containing a halogen element such as fluorine (F), chlorine (Cl), bromine (Br), or iodine (I) is used for the dry etching treatment of the conductive film.

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