JP2008077125A - Interface circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To allow output of data in processing units for lowering a load of post processing. <P>SOLUTION: Reference data corresponding to known data such as a preamble and a header included in transmission data are stored in an FIFO register 12, and by using a comparison circuit 13, the reference data are sequentially compared with data of a shift register 11. When agreement is detected, data of the shift register 11 are written into the data register 13, and the transmission data are allowed to be read in processing units by the CPU 3. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to an interface circuit, and more particularly to an interface circuit that transfers data serially communicated from a communication LSI (Large Scale Integration) composed of a radio circuit or the like to a CPU (Central Processing Unit) in a predetermined number of bits.

  Currently, as in the technique disclosed in Patent Document 1, synchronous serial communication is used as a communication format between the communication LSI and the CPU. In the synchronous serial communication, for example, as shown in FIG. 8, the communication LSI 81 and the CPU 82 are connected by two or more signal lines including the clock signal line 81a and the data signal line 81b, and the clock signal of the clock signal line 81a is connected. The data signal is transmitted on a bit-by-bit basis by changing the state of the data signal on the data signal line 81b. This is a conventional technique as disclosed in Patent Document 2. The serial interface circuit for serial communication disclosed in Patent Document 1 is realized by a CPU as disclosed in Patent Document 2.

  Data communication operation by the combination of the communication LSI 81 and the CPU 82 is as follows. Transmission data synchronized with the clock signal is output from the communication LSI 81, and the state of the data signal on the data signal line 81b is stored bit by bit in a register inside the CPU 82 in synchronization with the rising edge (or one of the falling edges) of the clock signal. take in. The CPU 82 processes the transmission data when a predetermined number of bits, for example, 8 bits are prepared. In this type of synchronous serial communication, synchronization is established by data of a known bit pattern added to the head of transmission data, and then transmission data is sequentially extracted, for example, every 8 bits, and processed efficiently.

In particular, there is a communication LSI 81 that includes a wireless circuit 83. In wireless communication using the wireless circuit 83 or the like, there is a high risk that bits of transmission data may be lost due to influence of interference or noise, compared to wired communication. For example, as disclosed in Patent Document 3, communication is performed by adding predetermined (known) data for each application consisting of a plurality of byte sequences to the head of transmission data. These data are referred to as a preamble, a header, and the like, and can be communicated by determining individual communication as different data for each application. In the case of wireless communication, if transmission data is transmitted from multiple wireless transmitters at the same time, bits of the transmission data are likely to be lost due to interference, noise, etc., and multiple types of wireless transmitters can be identified. In order to do this, a preamble, a header, etc. composed of a plurality of byte sequences are used.
JP-A-5-336121 Japanese Patent Laid-Open No. 62-103745 Japanese Patent Laid-Open No. 11-220469

  Whether the preamble, header, or the like composed of a plurality of byte strings is taken into a work area such as a RAM (Random Access Memory) via a synchronous communication circuit built in the CPU 82, and whether or not it matches a predetermined preamble by the processing of the CPU 82 Or, the preamble, header, etc. are detected by comparing bit by bit. The preamble, header, and the like are configured by a predetermined processing unit, for example, 8 bits (1 byte). This is a high-load process for the CPU 82.

  The synchronous communication circuit temporarily stores transmission data in a shift register having a register for 8 bits in a predetermined processing unit, and outputs it to the work area in units of 8 bits. It will read to the area. In the coincidence process of whether or not it is a preamble, the shift register data is read into the work area and compared with the preamble bit by bit to detect a coincidence with the preamble.

  After specifying the head position, interrupt processing is performed every time 8 bits of transmission data is received, and the transmission data is stored in the work area for post-processing in units of 8 bits.

  Here, the end of the preamble (LSB: Less Significant Bit) may be detected due to a part of the preamble missing, in other words, the position of the head of the subsequent data (MSB: Most Significant Bit) is specified. When this is done, the beginning of the data may already be input to the shift register, and the beginning of the data is stored with a bit shift with respect to the shift register.

  Since this bit shift extends to all subsequent transmission data, interrupt processing is performed every time 8 bits of transmission data are input to the shift register, and the transmission data is stored in units of 8 bits after being similarly bit-shifted. . In the bit shift process, a shift operation is performed on transmission data over a plurality of bit units, so the process becomes complicated.

  As an example, in FIG. 9, transmission data 91, 92, 93 are followed by “10101011 (ABH (H at the end indicates that this is a hexadecimal notation, the same applies hereinafter)”) as the end preamble. “10110001 (B1H)” and “10110010 (B2H)” are sent, and the above-described bit shift is 2 bits. FIG. 9A shows a preamble. FIG. 9B shows a state in which transmission data 91, 92, and 93 are transmitted and input to the shift register, and each bit is transmitted in order from the left (upper side) in FIG. (C) of FIG. 9 shows the data state of the shift register for each interrupt process. The timing at which the position of the head of the data is specified is set to the previous state, and transmission data is input every 8 bits from there. The state is shown.

  In the case of the figure, in the process of storing the transmission data 92 in the work area for post-processing, for example, as shown in (d) of FIG. 9, two bits of the bit string “10” following the preamble and the subsequent bits “10110001” is obtained by combining the shift operation based on the upper 6 bits “110001” of the bit string and the logical sum. As described above, in the interrupt process every time 8 bits are input, if data including the end of data is obtained in the shift register in the current interrupt process, the shift in the previous interrupt process held in the work area is obtained. By shifting the contents of the register to the left (upper side) by 6 bits, shifting the contents of the shift register at the time of this interrupt processing by 2 bits to the right (lower side), and taking these logical sums The target transmission data is obtained. As described above, the interrupt processing by the CPU is complicated, and this is also a high-load processing for the CPU 82.

  Accordingly, an object of the present invention is to reduce the load on the CPU.

In order to achieve the above object, the interface circuit of the present invention comprises:
An interface circuit that relays transmission data input from a first circuit through serial communication to a second circuit,
A shift register having a register for a predetermined number of bits as a processing unit of the transmission data, and capturing the transmission data bit by bit;
Each stage has a register for a predetermined number of bits as a processing unit of the transmission data, and sequentially stores reference data corresponding to known data such as a preamble and a header included in the transmission data in the predetermined processing unit. A FIFO register to
A comparison circuit that compares the transmission data stored in the shift register with the reference data stored in the output stage of the FIFO register, and detects a match between the transmission data and the reference data;
A data register that is read by the second circuit and to which the transmission data stored in the shift register is written when coincidence is detected by the comparison circuit;
It is provided with.

  Here, it is preferable that the second circuit includes a control circuit, and the control circuit updates the reference data stored in the FIFO register when coincidence is detected by the comparison circuit.

  The data register outputs to the second circuit a data input signal indicating that the data is written when the transmission data stored in the shift register is written, and the control circuit It is also preferable to instruct the change of the reference data stored in the FIFO register when the data input signal is received from the data register.

  In addition, when the control circuit controls each time the update is performed, the reference data stored in the register of each stage of the FIFO register is sent to the register of the next stage, and the input stage of the FIFO register becomes empty It is also preferable to input new reference data.

  The first circuit preferably includes a radio circuit.

  According to the interface circuit of the present invention, since known data such as a preamble and a header are detected and data can be output in a predetermined processing unit, the processing by the CPU can be simplified.

  The interface circuit according to the embodiment of the present invention will be described below.

  As shown in FIG. 1, the interface circuit 1 according to the embodiment of the present invention is provided between the communication LSI 2 and the CPU 3, receives data sent by synchronous serial communication output from the communication LSI 2, This data is stored in an internal data register in a predetermined processing unit, and the content is read by the CPU 3, whereby the CPU 3 is configured to receive data in a predetermined processing unit, in this example, 8 bits at a time.

  The interface circuit 1 includes a shift register 11 connected to the clock signal line 2a and the data signal line 2b from the communication LSI 2. The shift register 11 is a shift register including an 8-stage register (not shown) corresponding to 8 bits of a predetermined processing unit, and the data signal “2” of the data signal line 2 b is synchronized with the rising edge of the clock signal of the clock signal line 2 a. The transmission data indicated by the “H” level and the “L” level is fetched bit by bit from the input stage register, and the data fetched from the previous stage register to the subsequent stage register is shifted. Further, the data stored in each register is output in parallel to the later-described comparison circuit and data register via the data signal lines 11a and 11b, respectively.

  The first-in first-out (FIFO) register 12 includes an input register 12a as an input stage register and a compare register 12b as an output stage register. The input register 12a and the compare register 12b are registers for a predetermined number of bits, which is a processing unit of transmission data, in this example, 8 bits. In the input register 12a and the compare register 12b, known data to be detected such as a preamble and a header are sequentially stored. The data sent in parallel from the CPU 3 is written in the input register 12a, and the data previously stored in the input register 12a is sent in parallel via the data line 12c and written in the compare register 12b. The data written in the compare register 12b is output in parallel to the comparison circuit via the data line 12d.

  The comparison circuit 13 receives data stored in each register of the shift register 11 via the data signal line 11a in parallel, and receives data stored in the compare register 12b via the data signal line 12d in parallel. The comparison circuit 13 receives a clock signal via the clock signal line 2a, compares these data in synchronization with the clock signal, and sends a coincidence signal to the CPU 3 via the signal line 13a when both data coincide. When the two data do not match, a mismatch signal is sent to the CPU 3 via the signal line 13b. When both data match, a data output signal is sent to the shift register 11 via the signal line 13c. When receiving the data output signal, the shift register 11 sends the data stored in each register to the data register via the signal line 11b.

  The data register 14 is a register in which the values stored in the respective registers of the shift register 11 are written in parallel via the data signal line 11b when a data output signal is sent, and stores 8-bit data of a processing unit. The When data is stored, the data register 14 outputs a data input signal to the CPU 3 via the signal line 14a. Thus, the CPU 3 can read in parallel each bit of the data stored in the data register 14 via the data signal line 14b in response to the data input signal.

  The reset circuit 15 resets the interface circuit 1 under the control of the CPU 3 via the signal line 3b, whereby the data in the shift register 11 and the data in the data register 14 are all reset to “0”.

  The communication LSI 2 includes a radio circuit 21 including an RF receiver, an RF transmitter, a demodulator, a modulator, a synchronous serial communication unit, etc. (not shown), and synchronizes data demodulated from the radio signal with the clock signal of the clock signal line 2a. And output as a data signal of the data signal line 2b.

  The CPU 3 reads data input to the shift register 11 via the data register 13. Further, the CPU 3 controls the interface circuit 1 based on each signal sent from the FIFO register 12, the comparison circuit 13, and the data register 14.

  Next, the operation of the interface circuit 1 according to the embodiment will be described. 2, 3, and 4 are flowcharts for explaining the operation of the CPU 3, the FIFO register 11, and the comparison circuit 13 a, respectively, and FIG. 5 shows a part of the flowchart of FIG. 4. This will be described with reference to these.

  In this example, data to be detected among transmission data transmitted from the communication LSI 2 to the CPU 3 via the interface circuit 1 is a “00000101 (09H)” preamble, followed by a “01011010 (5AH)” header. Will be described.

  In order to start communication between the communication LSI 2 and the CPU 3, as shown in FIG. 2, the CPU 3 first sends a reset signal to the interface circuit 1 to reset it (step 21).

  The interface circuit 1 receives the reset signal via the reset circuit 15 and clears the value stored in each register to “0”. When the FIFO register 12 receives a reset signal as shown in FIG. 3 (step 31), the value stored in each register is cleared to "0", the register empty signal is set to "1", and the signal line 12e (Step 32). It should be noted that when each loop process as in the case of “No” in step 31 exceeds an appropriate period, the operation is terminated as an error.

  The CPU 3 determines the presence or absence of reference data corresponding to the preamble, header, etc. to be written to the FIFO register 12 (step 22). If there is reference data to be written here, the CPU 3 determines whether or not writing to the FIFO register 12 is possible by a register empty signal (step 23). If the register empty signal is set to “1”, the CPU 3 writes the reference data to the FIFO register 12 (step 24). First, the CPU 3 sends “09H” corresponding to the preamble as the first reference data to the FIFO register 12 via the data line 3a.

  Next, the CPU 3 determines whether or not there is a coincidence signal from the comparison circuit 13 (step 25), but here, the processing of the comparison circuit 13 has not yet been performed and has not been received. In this case, the CPU 3 determines whether or not there is a mismatch signal from the comparison circuit 13 (step 26), and returns to the processing of step 22.

  The FIFO register 12 determines whether or not reference data is written after the register empty signal is set (step 33). When the reference data is received, it is written to the input register 12a (step 34). Following this write, the FIFO register 12 clears the register empty signal to “0” and clears the comparison end signal to “0” to indicate the detection operation state.

  Next, the FIFO register 12 writes the reference data written in the input register 12a into the compare register 12b (step 35). Following this writing, the input register 12a is cleared and the register empty signal is set to "1".

  When the register empty signal is set to “1” (step 23), the CPU 3 sends “5AH” corresponding to the header which is the reference data next to the previously written reference data to the FIFO via the data line 3a. The data is sent to the register 12 (step 24).

  The FIFO register 12 determines whether or not reference data is written after writing to the compare register (step 36). When the reference data is received via the data line 3a, it is written to the input register 12a (step 37). . Following this write, the FIFO register 12 clears the register empty signal to “0”.

  Through the processing up to this point, the reference register “0000101” corresponding to the preamble and the reference data “01011010” corresponding to the subsequent header are stored in the compare register 12b and the input register 12a, respectively. Further, the period required for the processing so far is sufficiently shorter than the rising cycle of the clock signal of the clock signal line 2a, and the processing so far is performed by the comparison circuit 13 between the data of the shift register 11 and the data of the compare register 12b. End before starting the comparison.

  As shown in FIG. 4, the comparison circuit 13 determines that the comparison end signal is cleared to “0” (step 41), starts processing, and waits for the rising edge of the clock signal (step 42).

  As shown in FIGS. 6A to 6D, in synchronization with the rising edge of the clock signal on the clock signal line 2a, the shift register 11 sets each bit of the existing data to 1 bit on the upper side (MSB side). And the transmission data sent in correspondence with the “H” level of the data signal on the data signal line 2 b corresponding to “1” and the “L” level of the data signal corresponding to “0” is input stage (LSB) Is fetched bit by bit from the register.

  The comparison circuit 13 compares the data stored in the shift register 11 with the head reference data stored in the compare register 12b in synchronization with the rising edge of the clock signal (step 43). The comparison circuit 13 determines whether or not a data match is detected (step 44). If no data match is detected, the comparison circuit 13 returns to step 42. Each time the clock signal rises, the comparison circuit 13 repeats the comparison operation until it detects a match between the data stored in the shift register 11 and the head reference data stored in the compare register 12b.

  As shown in FIG. 6D, when the data stored in the shift register 11 and the head reference data stored in the compare register 12b match, the comparison circuit 13 sets the match signal to “1”. Then, the data is sent to the CPU 3 and the FIFO register 12 through the signal line 13a (step 45). At the same time, the comparison circuit 13 sets the data output signal to “1” and sends it to the shift register 11 via the signal line 13c, and counts up a bit counter (not shown) that counts up in synchronization with the rising edge of the clock signal. Is cleared to “0”.

  When receiving the data output signal, the shift register 11 sends the stored data to the data register 14 via the data signal line 11b. When the data register 14 stores the data from the shift register 11, it outputs a data input signal to the CPU 3 via the signal line 14a.

  When receiving the coincidence signal (step 25), the CPU 3 determines whether or not there is a data input signal from the data register 14 (step 27). The CPU 3 receives the data input signal immediately after the coincidence signal, and in response to this, reads data from the data register 14 via the data signal line 14b (step 28). Next, the CPU 3 determines whether or not there is a comparison end signal sent from the FIFO register 12 via the signal line 12f, that is, whether the comparison end signal is set to “1” or cleared to “0”. If it is determined (step 29) and the comparison end signal is cleared to "0", in other words, if there is still reference data to be compared in the FIFO register 12, the process returns to step 22. In the process of step 22 here, since the reference data is described as two in this example, there is no reference data to be sent to the FIFO register 12, and the process proceeds to step 25.

  When receiving the coincidence signal (step 38), the FIFO register 12 clears the data in the compare register 12b to “0” (step 39). At this time, the data stored in each register is as shown in FIG. Next, the FIFO register 12 determines whether or not the register empty signal is set to “1” (step 3A). The FIFO register 12 writes the reference data to the compare register 12b if the register empty signal is not set to "1", that is, if the reference data to be compared next is the input register 12a (step 3B). Following this, the FIFO register 12 clears the data in the input register 12a to “0” and sets the register empty signal to “1”. At this time, the data stored in each register is as shown in FIG.

  After writing to the compare register 12b, the FIFO register 12 returns to the process of determining the presence / absence of writing in step 36. At this time, assuming that the reference data to be written to the FIFO register 12 has been sent to the CPU 3, the FIFO register 12 proceeds to a process of determining the presence or absence of a coincidence signal in step 38.

  The comparison circuit 13 sets the coincidence signal, sets the data output signal, and clears the bit counter in the process of step 45, and then determines whether or not there is a comparison end signal in the same manner as the CPU 3 (step 46). In other words, if the comparison end signal is cleared to “0”, it waits for the rising edge of the clock signal (step 47).

  The processing up to this point after the coincidence of the first reference data is detected in the processing of step 44 in response to the rise of the clock signal ends before the rise of the next clock signal.

  Next, when the clock signal rises, the comparison circuit 13 increases the count value of an internal bit counter (not shown) by one (step 48). Next, the comparison circuit 13 determines whether or not the count value is a predetermined value “8 (1000B)” (step 49). If the count value is not the predetermined value “8”, the process returns to step 47, where Wait for the rising edge of the clock signal. In this way, the comparison circuit 13 counts up in synchronization with the rising edge of the clock signal, and when the count value reaches the predetermined value “8”, in other words, the data for 8 bits is shifted after the previous coincidence signal is generated. When input to the register 11, the data stored in the shift register 11 is compared with the reference data stored in the compare register 12b (step 4A). The comparison circuit 13 determines whether or not coincidence of these data is detected (step 44). If the data coincides, the process returns to step 45 to generate a coincidence signal and a data output signal. Clear the bit counter. As a result, the data in the shift register 11 is sent to the data register 14 and can be read therefrom by the CPU 3 that has received the data input signal.

  When receiving the coincidence signal (step 38), the FIFO register 12 clears the data in the compare register 12b in the process of step 39, and then determines whether or not the register empty signal is set in the process of step 3A. Here, as shown in FIG. 6 (f), the data in the input register 12a is cleared and the register empty signal is set to “1”, so that the FIFO register 12 has the register empty signal set. judge. In this case, the FIFO register 12 sets the comparison end signal to “1” and sends it to the CPU 3 and the comparison circuit 13 via the signal line 12f (step 3C). As a result, the FIFO register 12 sends to the circuits that the reference data to be compared is exhausted by the set of the comparison end signal and the comparison processing is completed, and ends its operation.

  On the other hand, the CPU 3 receives the coincidence signal (step 25), receives the data input signal (step 27), reads the transmission data (step 28), and determines whether there is a comparison end signal (step 29). When the CPU 3 determines that there is a comparison end signal, in other words, “1” is set, it determines whether or not to end communication (step 2A), and if communication is continued, the data input signal. (Step 2B), each time it is received, the transmission data is read from the data register 14 (step 2C). If it is determined in step 2A that communication is terminated, a signal indicating that is sent to the comparison circuit 13 via a signal line (not shown), and the communication process is terminated.

  After setting the coincidence signal, the comparison circuit 13 determines the presence / absence of a comparison end signal in the same manner as the CPU 3 (step 45). When the comparison circuit 13 determines that there is a comparison end signal, it determines whether or not it has received a signal indicating the end of communication from the CPU 3 (step 4D). If the communication continues, it is compared with the reference data. The transmission data subsequent to the header is processed (step 4E). This subsequent transmission data processing is shown in the flowchart of FIG.

  In the subsequent transmission data processing, the comparison circuit 13 operates as a bit counter, waits for the rising edge of the clock signal (step 51), counts up at each rising edge (step 52), and the count value is a predetermined value “8”. Every time "" (step 53), the data output signal is set and the count value is cleared to "0". Thus, even after the coincidence signal with respect to the last reference data is generated, the data output signal is sent to the shift register 11 every time 8-bit data is input to the shift register 11, and the data in the shift register 11 is stored in the data register. The CPU 3 that has received the data input signal can read out the data.

  If the comparison circuit 13 determines that the data stored in the shift register 11 and the reference data stored in the compare register 12b do not match in the process of step 4B, the comparison signal is set to “1”. It is set and sent to the CPU 3 via the signal line 13b.

  If the CPU 3 determines in step 26 that there is a mismatch signal, it returns to step 21 and sends a reset signal 21 to the interface circuit 1 to reset it. That is, when there is a mismatch signal, communication is restarted from the beginning.

  As described above, in the communication using the configuration in which the interface circuit 1 and the CPU 3 are combined, the head reference data corresponding to the preamble and the reference data corresponding to the header following the preamble are sequentially stored in the FIFO register 12 in a predetermined processing unit. The data stored in the compare register 12b, which is the output stage register, is compared with the data stored in the shift register 11 that receives the transmission data, and when they match, the data in the shift register 11 is transferred to a predetermined processing unit. Are stored in the data register 14 and read from the CPU 3. For this reason, with the above configuration, it is possible to suppress a load for detecting the preamble, header, and the like of the CPU 3. In addition, it is not necessary for the CPU 3 to perform a shift process for arranging transmission data into a predetermined processing unit, and the load on the CPU 3 is also reduced accordingly.

  The first reference data is compared with the data in the shift register 11 every time one bit of data is input to the shift register 11, and the reference data after this is processed in a predetermined process in the shift register 11. Every time 8 bits as a unit is input, it is compared with the data of the shift register 11. According to this, it is possible to reliably supplement the transmission data corresponding to the head reference data, and thereafter to reduce the processing load.

  In the above description, the reference data is described as two for convenience, but the present invention is not limited to this. For example, as shown in FIG. 7, a table defining reference data for each target communication pattern may be prepared in a nonvolatile memory (not shown) of the CPU 3 and three or more reference data may be used.

  In the above description, a configuration is employed in which the coincidence signal and the disagreement signal are sent to the CPU 3 via different signal lines, but the present invention is not limited to this. For example, assuming that only the coincidence signal is used and the state where there is no coincidence signal is the state where there is a disagreement signal, the process of step 26 of the CPU 3 in the above-described process is a process for determining whether or not a coincidence signal has been received. What is necessary is just to change so that the process of step 4C of the comparison circuit 13 may be omitted.

  In the above description, the FIFO register 12 is configured with two stages of registers. However, the present invention is not limited to this and may be configured with registers of three or more stages. In that case, in the above processing, the register empty signal handled in steps 35, 36, and 37 of the FIFO register 12 indicates whether or not the register of the input stage corresponding to the input register 12a is cleared, and is handled in step 3A. The register empty signal may indicate whether or not one input stage side register is cleared from the output stage corresponding to the compare register 12b.

  The present invention is not limited to the above-described embodiment, and the function of the interface circuit 1 may be provided to the communication LSI or the CPU 3.

It is a block diagram which shows the structure of the interface circuit concerning embodiment of this invention. 5 is a flowchart for explaining the operation of the interface circuit according to the embodiment of the present invention, particularly for explaining the operation of the CPU. 5 is a flowchart for explaining the operation of the interface circuit according to the embodiment of the present invention, particularly for explaining the operation of the FIFO register. 6 is a flowchart for explaining the operation of the interface circuit according to the embodiment of the present invention, particularly for explaining the operation of the comparison circuit. 6 is a flowchart for explaining the operation of the interface circuit according to the embodiment of the present invention, particularly for explaining the operation of the comparison circuit. It is a block diagram explaining the data stored in each register. It is explanatory drawing explaining the example of reference data. It is a block diagram explaining the conventional interface circuit. It is explanatory drawing explaining operation | movement of the conventional interface circuit.

Explanation of symbols

1 Interface Circuit 2 Communication LSI (First Circuit)
3 CPU (second circuit, control circuit)
11 Shift register 12 FIFO register 13 Comparison circuit 14 Data register

Claims (5)

An interface circuit that relays transmission data input from a first circuit through serial communication to a second circuit,
A shift register having a register for a predetermined number of bits as a processing unit of the transmission data, and capturing the transmission data bit by bit;
Each stage has a register for a predetermined number of bits as a processing unit of the transmission data, and sequentially stores reference data corresponding to known data such as a preamble and a header included in the transmission data in the predetermined processing unit. A FIFO register to
A comparison circuit that compares the transmission data stored in the shift register with the reference data stored in the output stage of the FIFO register, and detects a match between the transmission data and the reference data;
A data register that is read by the second circuit and to which the transmission data stored in the shift register is written when coincidence is detected by the comparison circuit;
An interface circuit characterized by comprising: The second circuit includes a control circuit;
The interface circuit according to claim 1, wherein the control circuit updates the reference data stored in the FIFO register when coincidence is detected by the comparison circuit. The data register outputs a data input signal indicating that the data has been written to the second circuit when the transmission data stored in the shift register is written,
The interface circuit according to claim 1, wherein the control circuit instructs to change the reference data stored in the FIFO register when receiving the data input signal from the data register. Under the control of the control circuit, each time the update is performed, the reference data stored in the register at each stage of the FIFO register is sent to the register at the next stage, and when the input stage of the FIFO register becomes empty, a new one is sent. The interface circuit according to claim 2 or 3, wherein the reference data is input. The interface circuit according to claim 1, wherein the first circuit includes a radio circuit.