JP2008076596A - Data line selecting circuit, data line driving circuit, electrooptical device, and electronic apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce variation in data potential during switching of a data line to be driven. <P>SOLUTION: When a temperature signal Tc is supplied from a temperature sensor 500, a data line controller 110 generates control signals (CN1, XCN1, CN2, XCN2, CN3, and XCN3) according to settings and supplies them to transmission gates of respective selection units Ur, Ug, and Ub to control operations of P-channel transistors (TP1, TP2, and TP3) for charge injection and N-channel transistors (TN1, TN2, and TN3) for charge extraction. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a technique for selecting a plurality of data lines.

As a color display device, a liquid crystal display device using a color filter is known. The liquid crystal display device displays gradation by adjusting the transmittance of the liquid crystal by controlling the voltage applied to the liquid crystal. In such a liquid crystal display device, pixel electrodes are arranged in a matrix corresponding to a plurality of scanning lines, a plurality of data lines, and intersections of the scanning lines and the data lines, and a liquid crystal is provided between the pixel electrode and the counter electrode. Is pinched. Then, a voltage signal corresponding to the gradation to be displayed on the data line is supplied, and the voltage is written in the liquid crystal capacitor.

In such a display device, in order to suppress the number of signal lines connected to the outside of the liquid crystal panel, data lines are shared between pixels of each color by time division, and a signal for each color is separated by a demultiplexer. (For example, Patent Document 1 and Patent Document 2).

A single-gate demultiplexer using N-channel transistors is configured as shown in FIG. 12, and a signal Di inputted from a data input terminal is selected as a selection signal (SEL_R, SEL_
G, SEL_B) is supplied to each color pixel circuit. When the gate-source capacitance of the transistor is Cgs and the capacitance of the data line is Cdata, the variation ΔV in the potential of the data line when each transistor is turned off by setting each selection signal to the low level indicates the amplitude of each selection signal. Assuming Vh, the following equation (1) is given.

特開２００６−６５３２８号公報（図２および図３） 特開２００６−１１３５４８号公報（図２および図３） 特開２００４−１７０７６６号公報（図３） In the demultiplexer shown in FIG. 13, the potential of the data line fluctuates due to switching of the gate transistor, so that there is a problem in that gradation control cannot be performed correctly. Therefore,
In order to suppress fluctuations in the potential of the data line, a demultiplexer using a transmission gate as shown in FIG. 12 is also known (Patent Document 3). In such a demultiplexer using a transmission gate, the gate-source capacitance of the N-channel transistor is Cgsn, the gate-source capacitance of the P-channel transistor is Cgsp, and the data line capacitance is Cdata. The potential fluctuation ΔV is given by the following equation (2).

Japanese Patent Laying-Open No. 2006-65328 (FIGS. 2 and 3) JP 2006-113548 A (FIGS. 2 and 3) Japanese Patent Laying-Open No. 2004-170766 (FIG. 3)

However, even in the configuration using the transmission gate disclosed in Patent Document 3, the gate-source capacitance Cgsn,
When Cgsp is different, the potential of the data line varies. For this reason, there has been a problem that the gradation of the pixels in the vertical direction fluctuates and vertical stripes occur.
The present invention has been made in view of such circumstances, and an object of the present invention is to solve the problem of reducing the fluctuation of the data potential when switching the data line to be driven and suppressing the occurrence of vertical stripes.

In order to solve this problem, a data line selection circuit according to the present invention (for example, the DM shown in FIG.
P1) is used in an electro-optical device having a plurality of data lines, a plurality of scanning lines, and a plurality of pixel circuits provided corresponding to intersections of the data lines and the scanning lines. Is provided for each of K (K is a natural number of 2 or more) data lines, and one of the K data lines is selected, and each is connected to a different data line. K processing units (for example, Ur, Ug, Ub shown in FIG. 3) and input terminals (for example, IN shown in FIG. 3) common to the K processing units, Is connected to the data line with a transmission gate for selecting a data line (for example, 10 shown in FIG. 5) in which the input terminal and one terminal are connected and the other terminal is connected to the data line, To select the data line In synchronization with the on and off of Nsu transmission gate, a plurality of charge adjusting means for performing injection and drawing of electric charge on the data lines (e.g., 30 shown in FIG. 5,
40, 50), and the transmission gate for selecting the data line includes an N-channel transistor (for example, 11 shown in FIG. 5) and a P-channel transistor (
For example, each of the plurality of charge adjusting means includes a P-channel transistor for charge injection in which the drain electrode and the source electrode are short-circuited (for example, TP shown in FIG. 5).
1 to TP3) and N channel transistors for charge supply (for example, TN1 to TN3 shown in FIG. 5) in which the drain electrode and the source electrode are short-circuited, the P channel transistor for charge injection and the charge supply The N-channel transistor is connected in parallel.

The transmission gate for selecting the data line is composed of an N channel transistor and a P channel transistor. If the gate-source capacitances of these transistors are equal, there is no charge transfer from the data line when the transmission gate is switched from the on state to the off state. However, due to manufacturing variations and temperature changes, the gate-source capacitances of both often do not match. According to the present invention, a plurality of charge adjusting means are provided, and each charge adjusting means includes a P-channel transistor and an N-channel transistor for charge injection. Therefore, it is possible to accurately compensate for variations in the gate-source capacitance of the N-channel transistor and the P-channel transistor that constitute the transmission gate for selecting the data line.

As a specific mode of the data selection circuit, a selection signal (for example, FIG. 5) is connected to the gate electrode of the N-channel transistor in the transmission gate for selecting the data line.
SELr) shown in FIG. 5 is connected to a first control line (for example, L1 shown in FIG. 5) and a gate electrode of a P-channel transistor in the transmission gate for selecting the data line, and an inverted selection signal obtained by inverting the selection signal (For example, XSELr shown in FIG. 5) for supplying a second control line (for example, L2 shown in FIG. 5), and each of the plurality of charge adjusting means includes a gate electrode of the P-channel transistor for charge injection And a first switching means (for example, GP1 shown in FIG. 5) that is provided between the first control line and the first control line and can control a connected state and an open state.
GP3) and first potential supply means (for example, Ru shown in FIG. 5) for supplying a potential at which the P-channel transistor is turned off to the gate electrode of the P-channel transistor when the first switching means is in an open state. ) And a second switching means (for example, GN1 to GN1 shown in FIG. 5), which is provided between the gate electrode of the N channel transistor for charge extraction and the second control line, and can control the connection state and the open state. GN3) and second potential supply means (for example, Rd shown in FIG. 5) for supplying a potential at which the N-channel transistor is turned off to the gate electrode of the N-channel transistor when the second switching means is open. It is preferable to comprise.

According to the present invention, when the data line selection P channel transistor and the N channel transistor change from the on state to the off state, the charge injection P channel transistor and the charge extraction N channel transistor are turned on from the off state. It is possible to cancel the movement of charges with respect to the data line by changing the state. Further, when the charge injection P-channel transistor and the charge extraction N-channel transistor are not used for compensation, the potential to be turned off is supplied to the gate electrode, so that the charge injection P-channel transistor and the charge extraction It is possible to accurately perform the compensation operation while avoiding that the N-channel transistor is in a floating state.

Here, the first potential supply means is a pull-up resistor provided between a high potential power supply and the gate electrode of the P channel transistor, and the second potential supply means is a low potential power supply and the N channel. A pull-down resistor provided between the gate electrode of the transistor is preferable. In this case, the first and second potential supply means can be simply configured.

The first potential supply means is provided between a high potential power supply and the gate electrode of the P-channel transistor, and is connected when the first switching means is open, and the first switching means is connected. And the second potential supply means is provided between the low potential power source and the gate electrode of the N-channel transistor, and is connected when the second switching means is in the open state. It is preferable that the fourth switching means be in an open state when the second switching means is in a connected state. In this case, the influence of the parasitic capacitance of each transistor can be reduced and the capacitance can be adjusted more reliably.

Next, a data line driving circuit according to the present invention includes a plurality of the data line selection circuits described above, and supplies a data signal for driving the pixel circuit to each of the input terminals of the plurality of data line selection circuits. The selection signal and the inverted selection signal are supplied to each of the data signal distribution circuit and the plurality of data line selection circuits, and the charge injection P-channel transistor and the charge extraction circuit in each of the plurality of charge adjustment means. Control means (for example, 210 shown in FIG. 2) for supplying a control signal for independently controlling the N-channel transistor for use to the plurality of charge adjusting means. According to the present invention, when the data signal is selected and the data signal is supplied, the gates of the P-channel transistor and the N-channel transistor for selecting the data line are selected.
Since charge transfer to the data line due to the source-to-source capacitance can be compensated, so-called streak unevenness can be suppressed.

Here, the control means includes N in the transmission gate for selecting the data line.
The control signal is preferably generated based on an index indicating a change in gate-source capacitance of the channel transistor and the P-channel transistor. In this case, it is possible to compensate for the charge transfer with respect to the data line following the fluctuation factors such as temperature and change with time.
Further, the control means is a temperature detecting means for detecting temperature (for example, 500 shown in FIG. 1).
And the temperature detected by the temperature detecting means may be used as the index. Alternatively, the control means may be configured to electrically connect a test P-channel transistor and a test N-channel transistor, and the test P-channel transistor and the test N-channel transistor (for example, Tp and Tn shown in FIG. 8). Measuring means for measuring various characteristics (for example, FIG.
And the measurement result measured by the measuring means is preferably used as the index.

Next, an electro-optical device according to the present invention includes a plurality of data lines, a plurality of scanning lines, a plurality of pixel circuits provided corresponding to intersections of the data lines and the scanning lines, and the above-described data. A line drive circuit. According to the present invention, it is possible to greatly improve display quality by suppressing streak unevenness.
Next, an electronic apparatus according to the invention includes the above-described electro-optical device. Such electronic devices include mobile phones, personal computers, digital cameras, and the like.

<A: First Embodiment>
FIG. 1 is a block diagram illustrating a schematic configuration of the electro-optical device according to the first embodiment of the invention. The electro-optical device 1 includes an electro-optical panel AA and an external circuit. In the electro-optical panel AA, a pixel region A, a scanning line driving circuit 100, a data line driving circuit 200, and a temperature sensor 500 are formed. Among these, m scanning lines 101 are formed in the pixel region A in parallel with the X direction. In addition, 3n data lines 103 are formed in parallel with the Y direction orthogonal to the X direction. A pixel circuit 400 is provided corresponding to each intersection of the scanning line 101 and the data line 103. The pixel circuit 400 includes an OLED element. The symbols “R”, “G”, and “B” shown in the figure indicate the emission color of the OLED element. In this example, data line 10
3, pixel circuits 400 of the respective colors are arranged.

Among the pixel circuits 400, the pixel circuit 400 corresponding to the R color is connected to the power supply line LR, and the pixel circuit 400 corresponding to the G color is connected to the power supply line LG, and corresponds to the B color. The pixel circuit 400 is connected to the power supply line LB. The power supply circuit 600 has a power supply voltage Vddr.
, Vddg, and Vddb. Power supply voltages Vddr, Vddg, and Vddb
Is supplied to the pixel circuit 400 corresponding to each color of RGB via the power supply lines LR, LG, and LB. The temperature sensor 500 measures the temperature and outputs a temperature signal Tc indicating the measured temperature.

The scanning line driving circuit 100 scans signals Y1 and Y for sequentially selecting a plurality of scanning lines 101.
2, Y3,..., Ym are generated and supplied to the pixel circuits 400, respectively. The scanning signal Y1 is 1
A pulse having a width corresponding to one horizontal scanning period (1H) from the first timing of the vertical scanning period (1F) is supplied to the scanning line 101 in the first row. Thereafter, the pulses are sequentially shifted and supplied as scanning signals Y2, Y3,..., Ym to the scanning lines 101 in the 2, 3,. Generally, when the scanning signal Yi supplied to the scanning line 101 in the i-th row (i is an integer satisfying 1 ≦ i ≦ m) is at the H level, the scanning line 101 is selected.

The data line driving circuit 200 applies gradation signals Xr1, Xg1, Xb1, Xr2, Xg2, Xb2,..., Xrn, Xgn to each of the pixel circuits 400 positioned on the selected scanning line 101.
, Xbn is supplied. In this example, the gradation signals Xr1 to Xbn are given as voltage signals indicating gradation luminance. In the following description, the subscript “r” is R color, “g”
Indicates G color, and “b” indicates B color. Further, the data line driving circuit 200
Performs a compensation operation according to the temperature signal Tc of the temperature sensor 500.

The control circuit 300 generates various control signals and supplies them to the scanning line driving circuit 100 and the data line driving circuit 200. Further, the control circuit 300 outputs, for example, 10-bit gradation data Dout to the data line driving circuit 200. In this example, the control circuit 300
Although the power supply circuit 600 is provided outside the electro-optical panel AA, some or all of these components may be taken into the electro-optical panel AA. Furthermore, some of the components provided in the electro-optical panel AA may be provided as an external circuit.

FIG. 2 is a block diagram showing a configuration of the data line driving circuit 200. Data line drive circuit 2
In 00, every three data lines 103, demultiplexers DMP1, DMP,.
n is provided. In addition, the data line driving circuit 200 includes a data line controller 210 that selects the data line 103 to be driven, and gradation data Dout from the data line driving circuit 200.
Is distributed to each demultiplexer DMPi (i = 1, 2,..., N).
20 is provided. Each demultiplexer DMP1, DMP2,..., DMPn includes a control signal and a selection signal from the data line controller 210, and a data signal distribution circuit 220.
A drive signal Di and the like are supplied.

The data line controller 210 generates a selection signal based on the X start pulse DX and the X clock signal XCLK from the control circuit 300. The selection signal sequentially selects the data line 103 to be driven, and the corresponding demultiplexer DMPi and the demultiplexer DMPi.
Which of the data lines 103 connected to is selected. Data signal distribution circuit 22
0 includes a serial-parallel conversion circuit, a shift register, a latch circuit, an AD conversion circuit, and the like. The shift register sequentially transfers the X transfer start pulse DX in synchronization with the X clock signal XCLK to generate a dot sequential latch signal. The latch circuit latches the gradation data Dout using the latch signal. The AD conversion circuit generates a drive signal Di (gradation signals Xri (i = 1, 2,..., N), Xgi, Xbi) corresponding to the latched gradation data Dout and supplies it to the corresponding demultiplexer DMPi. To do.

FIG. 3 is a block diagram showing a configuration of each demultiplexer DMPi (i = 1, 2,..., N). Each demultiplexer DMPi includes selection units Ur, Ug, Ub corresponding to R, G, B colors. In each of the selection units Ur, Ug, Ub, control signals CN1, XCN1 (representing an inverted signal of CN1; the same applies hereinafter) from the data line controller 210, CN2, XCN2, CN3, XCN3, CP1, XCP1, CP2 , XCP2,
CP3 and XCP3 are supplied. Further, selection signals SELr and XSELr from the data line controller 210 are supplied to the selection unit Ur. Selection signals SELg and XSELg from the data line controller 210 are supplied to the selection unit Ug.
The selection unit Ub includes selection signals SELb and XSEL from the data line controller 210.
b is supplied. Further, each of the selection units Ur, Ug, Ub is supplied with a drive signal Di (i = 1, 2,..., N) from the data signal distribution circuit 220 via a common input terminal IN.

FIG. 4 is a timing chart showing the operation of the data line driving circuit 200. As shown in the figure, the drive signal Di from the data signal distribution circuit 220 is sent to each selection unit Ur, Ug.
, Ub, the gray scale signals Xri, Xbi, Xgi are time-division multiplexed to select units Ur, U
Commonly supplied to g and Ub. Each of the selection units Ur, Ug, Ub receives selection signals (SELr, XSELr, SELg, XSELg, SEL) from the data line controller 210.
b, XSELb), the gradation signals Xri, Xbi, and Xgi are extracted from the drive signal Di and output to the corresponding data lines 103, respectively.

FIG. 5 is a circuit diagram showing a configuration of each selection unit Ur (Ug, Ub). The selection unit Ur of this embodiment includes a transmission gate 10 for selecting a data line, and charge adjusting units 30, 40, and 50 for compensating the charge of the data line. The data line selection transmission gate 10 is configured by connecting an N-channel transistor 11 and a P-channel transistor 12 in parallel. The gate electrode of the N-channel transistor 11 is connected to the first control line L1, and the selection signal SELr is supplied through the first control line L1. On the other hand, the gate electrode of the P-channel transistor is connected to the second control line L2, and the selection signal XSELr is supplied through the second control line L2. The selection signal XSELr is obtained by inverting the selection signal SELr.

The charge adjusting units 30 to 50 are provided with a plurality of P-channel transistors for injecting charges into the data lines and a plurality of N-channel transistors for extracting charges from the data lines. Each P
The gates of the channel transistors (TP1, TP2, TP3) are connected to transmission gates GP1, GP2, GP3 that are opened and closed by control signals (CP1, XCP1, CP2, XCP2, CP3, XCP3) supplied as differential voltages, respectively. Thus, the selection signal SEL can be supplied. Also, each N-channel transistor (TN1, TN2
, TN3) are supplied to the gates of control signals (CN1, XCN1,
CN2, XCN2, CN3, XCN3) transmission gate G opened and closed
The selection signal XSEL can be supplied via N1, GN2, and GN3. The charge injection P-channel transistors (TP1, TP2, TP3) are connected to the high potential Vh via the pull-up resistor Ru, and the charge extraction N-channel transistors (
TN1, TN2, and TN3) are grounded to a low potential via a pull-down resistor Rd.

<B: Operation of the electro-optical device>
The data line controller 210 has control signals CN1, XC corresponding to the temperature signal Tc in advance.
The values of N1, CN2, XCN2, CN3, XCN3 are set, and the control signals CN1, XCN1, CN2 are set according to the temperature signal Tc supplied from the temperature signal Tc of the temperature sensor 500.
, XCN2, CN3, XCN3 are supplied to the selection units Ur, Ug, Ub.

Here, as shown in FIG. 6, when there is one P-channel transistor TP1 for charge injection and one N-channel transistor TN1 for charge extraction, the variation in potential of the data line Δ
V is given by the following formula (3).

Where Cgsp is the gate-source capacitance of the P-channel transistor TP1 for charge injection,
Cgsn is the capacitance between the gate and source of the N channel transistor TN1 for extracting charge, Cp is the sum of the parasitic capacitance between the gate and source and between the gate and drain of the transistor TP1 for charging, and Cn is the capacitance of the transistor TN1 for extracting charge. It is the sum of the parasitic capacitance between the gate and source and between the gate and drain. P-channel transistor TP1 and N-channel transistor TN
If 1 is symmetrical, the capacitance Cgsp and the capacitance Cgsn become the same, and ΔV is close to 0. However, these capacitances vary depending on variations in manufacturing and temperature in Cgsp and Cgsn.

For this reason, in this embodiment, as shown in FIG. 5, a plurality of P-channel transistors for charge injection and N-channel transistors for charge extraction are provided.
Controls the operation of each transistor in accordance with the temperature signal Tc of the temperature sensor 500. In the selection unit Ur, each transistor TP1, TP2, TP3 corresponds to the above Cgsp.
The gate-source capacitances Cgsp1, Cgsp2, and Cgsp3 are connected in parallel. Since the gate-source capacitance of the transistor to which the selection signal SELr is not supplied is not connected by the transmission gate GP1, GP2, GP3, for example, when the selection signal SELr is supplied only to the transistors TP1 and TP2. Is a value in which the gate-source capacitances Cgsp1 and Cgsp2 of these transistors are connected in parallel.

Similarly, the above-mentioned Cgsn corresponds to the value obtained by connecting the gate-source capacitances Cgsn1, Cgsn2, and Cgsn3 of the transistors TN1, TN2, and TN3 in parallel, but is selected by the transmission gates GN1, GN2, and GN3. Since the gate-source capacitances of the transistors not supplied with the signal XSELr are not connected, for example, when the selection signal XSELr is supplied only to the transistors TN1 and TN2, the gates and sources of these transistors are supplied. The inter-capacitances Cgsn1 and Cgsn2 are values connected in parallel.

In the present embodiment, since ON / OFF of the transmission gates GN1 to GN3 and GP1 to GP3 is controlled independently, the amount of charge injected into the data line 103 and the amount of charge extracted from the data line can be balanced.

As described above, the gate-source capacitance Cgs depends on the temperature. For this reason, the gate-source capacitance C of the P-channel transistors (TP1, TP2, TP3) for injecting charges with respect to temperature and the N-channel transistors (TN1, TN2, TN3) for extracting charges in advance.
Each control signal CN1, XCN1 is measured so that the change in gs can be measured and canceled.
, CN2, XCN2, CN3, XCN3 are set. Specifically, a table in which the temperature and the state of the control signal are stored in association with each other is stored in the data line controller 210, and each control signal CN1, XCN1, CN2, XCN2, CN3, XCN3 is referred to by referring to this table. Generate. As a result, it is possible to suppress fluctuations in the potential of the data line due to changes in the gate-source capacitance Cgs of each transistor in accordance with temperature changes. As a result, the occurrence of vertical stripes on the display surface due to fluctuations in the potential of the data lines can be suppressed.

The size of each transistor (TP1, TP2, TP3) may be set to, for example, 1: 2: 4, and the size of each transistor (TN1, TN2, TN3) may be set to, for example, 1: 2: 4. Since the gate-source capacitance of each transistor has a correlation with the size of the transistor, the capacitance can be adjusted stepwise by varying the size of each transistor in this way.

<C: Second Embodiment>
FIG. 7 shows a selection unit Ur (Ug) constituting the electro-optical device according to the second embodiment of the invention.
, Ub). The electro-optical device according to the second embodiment is configured in the same manner as in the first embodiment described above except that the circuit configuration of the selection unit Ur (Ug, Ub) is different. In the first embodiment described above, the charge injection P-channel transistors (TP1, T
P2, TP3) are connected to the high potential Vh via the pull-up resistor Ru, and the N-channel transistors (TN1, TN2, TN3) for extracting charges are grounded to a low potential via the pull-down resistor Rd. . On the other hand, in this embodiment, it is pulled up via the transmission gate W and pulled down via the transmission gate Z.

With such a configuration, it is possible to reduce the influence of the parasitic capacitance of each transistor and more reliably adjust the capacitance as compared with the case where pull-up or pull-down is performed via a resistor.

<D: Modification>
In each of the above embodiments, each transistor (in accordance with the temperature signal Tc of the temperature sensor 500).
The operation of TP1, TP2, TP3, TN1, TN2, and TN3) is controlled. For example, as shown in FIG. 8, a monitor transistor (P-channel transistor Tp, N-channel transistor Tn) is disposed on the electro-optical panel AA. The capacitance of these transistors (
Cgs) is measured by the sensor 510, and each transistor (TP1, TP1) is changed according to the change in capacitance.
The operations of TP2, TP3, TN1, TN2, and TN3) may be controlled. As a result, more accurate control can be performed in accordance with the change in the capacitance of the transistors formed on the same panel.

<E: Application example>
Next, an electronic apparatus using the electro-optical device 1 according to the present invention will be described. FIG. 9 is a perspective view showing a configuration of a mobile personal computer that employs the electro-optical device 1 according to any one of the embodiments described above as a display device. The personal computer 2000 includes the electro-optical device 1 as a display device and a main body 2010. In the main body 2010,
A power switch 2001 and a keyboard 2002 are provided. This electro-optical device 1
Since an OLED element is used for the electro-optic element 11, a screen with a wide viewing angle and easy to see can be displayed.

FIG. 10 shows a configuration of a mobile phone to which the electro-optical device 1 according to the embodiment is applied. A cellular phone 3000 includes a plurality of operation buttons 3001, scroll buttons 3002, and the electro-optical device 1 as a display device. By operating the scroll button 3002, the screen displayed on the electro-optical device 1 is scrolled.

FIG. 11 shows a personal digital assistant (PDA: Personal) to which the electro-optical device 1 according to the embodiment is applied.
Digital Assistants). The information portable terminal 4000 includes a plurality of operation buttons 40.
01, a power switch 4002, and the electro-optical device 1 as a display device.
When the power switch 4002 is operated, various types of information such as an address book and a schedule book are displayed on the electro-optical device 1.

The electronic apparatus to which the electro-optical device according to the present invention is applied includes, in addition to those shown in FIGS. 9 to 11, a digital still camera, a television, a video camera, a car navigation device, a pager, an electronic notebook, electronic paper, Examples include calculators, word processors, workstations, videophones, POS terminals, printers, scanners, copiers, video players, devices equipped with touch panels, and the like. The use of the electro-optical device according to the invention is not limited to image display. For example, in an image forming apparatus such as an optical writing type printer or an electronic copying machine, a writing head that exposes a photosensitive member according to an image to be formed on a recording material such as paper is used. However, the electro-optical device of the present invention is used.
The electronic circuit referred to in the present invention is a concept including not only a pixel circuit constituting a pixel of a display device as in each embodiment but also a circuit that is a unit of exposure in the image forming apparatus.

1 is a block diagram illustrating a configuration of an electro-optical device according to a first embodiment of the invention. FIG. It is a block diagram showing a configuration of a data line driving circuit constituting the electro-optical device. It is a block diagram which shows the structure of the demultiplexer which comprises a data line drive circuit. It is a timing chart which shows the waveform of each signal. It is a circuit diagram which shows the structure of the selection unit which comprises an electro-optical apparatus. It is a circuit diagram which shows the example of a structure of a part of selection unit. FIG. 6 is a circuit diagram illustrating a configuration of a selection unit configuring an electro-optical device according to a second embodiment of the invention. FIG. 10 is a circuit diagram illustrating a configuration of an electro-optical device according to a modification. It is a perspective view which shows the specific form of the electronic device which concerns on this invention. It is a perspective view which shows the specific form of the electronic device which concerns on this invention. It is a perspective view which shows the specific form of the electronic device which concerns on this invention. It is a circuit diagram which shows the structure of the conventional demultiplexer. It is a circuit diagram which shows the structure of the conventional demultiplexer.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Electro-optical apparatus, 100 ... Scan line drive circuit, 101 ... Scan line, 103 ... Data line, 200 ... Data line drive circuit, 210 ... Data line controller, 220 ... Data signal distribution circuit, 400 ... Pixel circuit, 500 ... Temperature sensor, 510 ... Sensor, A ...
... Pixel area, AA ... Electro-optical panel, GP1, GP2, GP3, GN1, GN2, GN
3 ... Transmission gate, DMPi ... Demultiplexer, TP1, TP2, T
P3, TN1, TN2, TN3 ... Transistor, Ur, Ug, Ub ... Selection unit.

Claims (10)

K used for an electro-optical device having a plurality of data lines, a plurality of scanning lines, and a plurality of pixel circuits provided corresponding to intersections of the data lines and the scanning lines. (K is a natural number of 2 or more) A data line selection circuit that is provided for each of the data lines and selects one of the K data lines,
K processing units each connected to a different data line;
A common input terminal for the K processing units;
Each of the processing units is
A transmission gate for selecting a data line in which the input terminal is connected to one terminal and the other terminal is connected to the data line;
A plurality of charge adjusting means connected to the data line and injecting and extracting charges to and from the data line in synchronization with on / off of the transmission gate for selecting the data line;
The transmission gate for selecting the data line includes an N channel transistor and a P channel transistor connected in parallel,
Each of the plurality of charge adjusting means includes
A charge injection P-channel transistor in which the drain electrode and the source electrode are short-circuited; and a charge supply N-channel transistor in which the drain electrode and the source electrode are short-circuited, and the charge injection P-channel transistor and the charge A supply N-channel transistor is connected in parallel;
A data line selection circuit. A first control line connected to a gate electrode of an N channel transistor in the transmission gate for selecting the data line and supplying a selection signal;
A second control line connected to a gate electrode of a P-channel transistor in the transmission gate for selecting the data line and supplying an inverted selection signal obtained by inverting the selection signal;
Each of the plurality of charge adjusting means includes
First switching means provided between a gate electrode of the P-channel transistor for charge injection and the first control line and capable of controlling a connected state and an open state;
First potential supply means for supplying a potential at which the P-channel transistor is turned off to the gate electrode of the P-channel transistor when the first switching means is in an open state;
Second switching means provided between the gate electrode of the N channel transistor for extracting charge and the second control line, and capable of controlling a connected state and an open state;
Second potential supply means for supplying a potential at which the N-channel transistor is turned off to the gate electrode of the N-channel transistor when the second switching means is in an open state;
The data line selection circuit according to claim 1, further comprising: The first potential supply means is a pull-up resistor provided between a high potential power supply and the gate electrode of the P-channel transistor,
The second potential supply means is a pull-down resistor provided between a low potential power supply and the gate electrode of the N-channel transistor.
The data line selection circuit according to claim 2, wherein: The first potential supply means is provided between a high potential power supply and the gate electrode of the P-channel transistor, and is connected when the first switching means is open, and when the first switching means is connected. A third switching means to be opened;
The second potential supply means is provided between a low potential power supply and the gate electrode of the N-channel transistor, and is connected when the second switching means is open, and when the second switching means is connected. A fourth switching means that is in an open state;
The data line selection circuit according to claim 2, wherein: A plurality of data line selection circuits according to any one of claims 1 to 4,
A data signal distribution circuit for supplying a data signal for driving the pixel circuit to each of input terminals of the plurality of data line selection circuits;
The selection signal and the inverted selection signal are supplied to each of the plurality of data line selection circuits, and the charge injection P channel transistor and the charge extraction N channel transistor in each of the plurality of charge adjustment means, Control means for supplying a control signal for independently controlling the plurality of charge adjusting means,
A data line driving circuit comprising: 6. The control means generates the control signal based on an index indicating a change in gate-source capacitance of an N-channel transistor and a P-channel transistor in the transmission gate for selecting the data line. A data line driving circuit according to 1. The data line driving circuit according to claim 6, wherein the control unit includes a temperature detection unit that detects a temperature, and uses the temperature detected by the temperature detection unit as the index. The control means includes a test P-channel transistor and a test N-channel transistor, and a measurement means for measuring electrical characteristics of the test P-channel transistor and the test N-channel transistor. 7. The data line driving circuit according to claim 6, wherein a measurement result measured by the means is used as the index. Multiple data lines,
A plurality of scan lines;
A plurality of pixel circuits provided corresponding to the intersections of the data lines and the scanning lines;
A data line driving circuit according to any one of claims 5 to 8,
An electro-optical device comprising:   An electronic apparatus comprising the electro-optical device according to claim 9.

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