JP2008072742A - Ad converter, electronic equipment, and receiver - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technology for reducing the power consumption of a circuit having an amplifier. <P>SOLUTION: A current supply circuit 80 supplies bias currents to arithmetic amplifiers 30a and 30b configuring a pipelined AD converter circuit 10. A current switching circuit 70 switches output currents according to a current control signal from a current control means 100, thereby switching currents supplied from a bias circuit 50 to the arithmetic amplifiers 30 via transistors 40. When a high frequency operation is performed, currents large enough for the operation are supplied, and when a low frequency operation is performed, a current value of the current to be supplied is switched to be lower. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to an electric circuit, and more particularly to a semiconductor circuit having an amplifier, an AD converter, an electronic device, a receiving device, a current supply circuit for supplying current to the amplifier, and a method for controlling the current supplied to the amplifier.

  As an example of a circuit for converting an input analog signal into a digital signal, there is a pipeline type AD converter. The pipeline type AD converter is formed by connecting a plurality of low bit sub AD converters in stages, and performs AD conversion step by step by each sub AD converter. An operational amplifier is inserted between the stages of the sub A / D converter, and amplifies an analog signal input to the next stage A / D converter.

When operating a pipelined AD converter at multiple operating frequencies in a device equipped with a pipelined AD converter, the most severe of the operating modes, that is, the operation at the highest frequency, is selected. It is necessary to design the circuit. In general, the higher the operating frequency of the pipeline type AD converter, the more current consumption is required in the operational amplifier constituting the pipeline AD converter. Therefore, all the currents sufficient for the operation at the highest frequency among the plurality of operation modes must be obtained. The circuit was designed to supply the operational amplifier in this mode of operation.
JP 2001-28519 A

  However, in the circuit design as described above, when operating in an operation mode with a low operating frequency, more current than necessary is supplied, and unnecessary power is consumed.

  The present invention has been made in view of such problems, and an object thereof is to provide a technique for reducing power consumption of a circuit having an amplifier.

  One embodiment of the present invention relates to a control method. In this method, when a current necessary for the operation of the amplifier is supplied, the value of the current is changed according to the operating frequency of the amplifier. When the operating frequency of the amplifier is high, sufficient current is supplied for the operation. On the other hand, when the operating frequency of the amplifier is low, power consumption can be reduced by switching the supplied current to a current having a low current value. it can.

  Another aspect of the present invention relates to a current supply circuit. This current supply circuit is a circuit for supplying a current necessary for the operation of the amplifier, and receives a current control signal generated in response to switching of the operating frequency of the amplifier, and switches the current supplied to the amplifier. Is provided.

  Yet another embodiment of the present invention relates to a semiconductor circuit. The semiconductor circuit includes a plurality of amplifiers and a current switching unit that receives a current control signal generated in response to switching of the operating frequency of the amplifiers and switches a current supplied to the plurality of amplifiers.

  The semiconductor circuit further includes a bias circuit that is connected to each of the plurality of amplifiers and supplies a bias current to the amplifier, and the current switching unit switches the current to be output to the bias circuit, thereby switching the plurality of amplifiers. You may switch the electric current supplied to.

  The current switching means may collectively switch currents supplied to the plurality of amplifiers. For example, all the amplifiers constituting the circuit may be switched at once by one current switching means. The current switching unit may be provided corresponding to each of the plurality of amplifiers, and may switch a current supplied to an amplifier to which the current switching unit is connected.

  The current switching means is a circuit configured by a plurality of current paths provided in parallel, and each current path may include a transistor circuit in which a gate terminal and a drain terminal are short-circuited, and a switch circuit. . A current path is selected by turning on and off the switch circuit, and a current determined by the characteristics of the transistor circuit is output. The switch circuit may be configured by a MOSFET or the like.

  Yet another embodiment of the present invention relates to an AD conversion apparatus. This AD conversion apparatus includes a plurality of sub AD conversion circuits connected in series, an amplifier inserted between the sub AD conversion circuits and amplifying an input signal to the sub AD conversion circuit in the next stage, and the operation of the amplifier Current switching means for switching a current supplied to the amplifier in response to a current control signal generated in response to frequency switching.

  Still another embodiment of the present invention relates to an electronic device. The electronic device receives a plurality of amplifiers, current control means for controlling a current to be supplied to the amplifier in response to switching of an operating frequency of the amplifier, and a current control signal generated by the current control means. Current switching means for switching currents supplied to the plurality of amplifiers.

  Still another embodiment of the present invention also relates to an electronic apparatus. The electronic apparatus includes a plurality of sub A / D conversion circuits connected in series, an amplifier that is inserted between the sub A / D conversion circuits, amplifies an input signal to the sub A / D conversion circuit in the next stage, and supplies the amplifier to the amplifier An AD converter including current switching means for switching current, frequency control means for switching the operating frequency of the amplifier, and current control for controlling current to be supplied to the amplifier in accordance with switching of the operating frequency of the amplifier Current control means for issuing a signal to the current switching means, and the frequency control means, when the AD converter converts a plurality of series of input signals in a time division manner, The operating frequency is switched accordingly.

  The frequency control means may increase the operating frequency as the number of the input signal series increases, and the current control means may increase the current supplied to the amplifier as the operating frequency increases. Thereby, the current required for the operation of the amplifier can be appropriately supplied. Conversely, the current control means may decrease the current supplied to the amplifier as the operating frequency is lower. Thereby, power consumption can be reduced. Note that such frequency / current control is digital switch switching and can be dynamically changed. That is, these switching operations correspond to the operation mode switching of the electronic device system, and can be freely changed during the operation in accordance with, for example, the low power consumption mode.

  A plurality of antennas, a plurality of sub A / D conversion circuits connected in series, an amplifier inserted between the sub A / D conversion circuits and amplifying an input signal to the sub A / D conversion circuit in the next stage, and supplied to the amplifier An AD converter including current switching means for switching current, frequency control means for switching the operating frequency of the amplifier, and current control for controlling current to be supplied to the amplifier in accordance with switching of the operating frequency of the amplifier Current control means for emitting a signal to the current switching means, and the frequency control means causes the AD converter to convert a plurality of series of input signals received by the plurality of antennas in a time division manner, The operating frequency is switched according to the number of input signal sequences.

  The frequency control means may increase the operating frequency in a mode in which the receiving apparatus receives an analog signal in a diversity manner with a plurality of antennas, rather than a mode in which the receiving apparatus receives an analog signal with a single antenna. The current control means may increase the current supplied to the amplifier as the operating frequency is higher.

  It should be noted that any combination of the above-described constituent elements and a representation of the present invention converted between a method, an apparatus, a system, etc. are also effective as an aspect of the present invention.

  ADVANTAGE OF THE INVENTION According to this invention, the technique which reduces the power consumption of the circuit which has an amplifier can be provided.

(First embodiment)
FIG. 1 shows an overall configuration of a pipelined AD converter circuit 10 according to a first embodiment of the present invention. The analog signal Vin input to the input terminal is input to the first-stage sub AD converter 20a and converted into a digital signal having a predetermined number of bits. This digital signal is output to the encoder 12 and the sub DA converter 22a. The sub DA converter 22a converts the digital signal output from the sub AD converter 20a into an analog signal. Then, a signal obtained by subtracting the output signal of the sub DA converter 22a from the input signal to the sub AD converter 20a is amplified by the operational amplifier 30a and used as an input signal to the sub AD converter 20b in the next stage. By repeating the above signal processing for a predetermined number of stages, AD conversion is performed in stages, and finally a digital signal is output from the encoder 12.

  The pipeline type AD converter circuit 10 includes a current supply circuit 80 that supplies a bias current to the operational amplifiers 30 a and 30 b constituting the pipeline type AD converter circuit 10. The current supply circuit 80 is configured to be able to switch bias currents supplied to the respective operational amplifiers 30, and each of the bias circuits 50a and 50b and the bias circuits 50a and 50b connected to the operational amplifiers 30a and 30b, respectively. Transistors 40a and 40b connected between operational amplifiers 30a and 30b, constant current source 60, and current switching circuit 70 are included.

  The current switching circuit 70 switches the current supplied from the constant current source 60 to a plurality of different current values according to the current control signal from the current control means 100, and outputs it to the bias circuits 50a and 50b. The currents adjusted by the bias circuits 50a and 50b are input to the gate electrodes of the transistors 40a and 40b, respectively. Since the current flowing between the source and the drain changes according to the change in the current to the gate electrodes of the transistors 40a and 40b, the current consumption of the operational amplifiers 30a and 30b is switched. In the present embodiment, the current switching circuit 70 comprehensively switches the current supplied to the plurality of operational amplifiers 30a and 30b. That is, the bias currents of all the operational amplifiers 30 constituting the pipeline type AD converter circuit 10 are collectively switched by one current switching circuit 70.

The current control means 100 sends a current control signal to the current switching circuit 70 in accordance with the operating frequency required for the pipelined AD converter circuit 10. In general, the higher the bias current supplied to the operational amplifier 30 constituting the pipeline AD converter circuit 10, the higher the slew rate of the operational amplifier 30 and the higher frequency AD conversion can be realized. That is, when the pipeline type AD converter circuit 10 is operated at a high frequency, it is necessary to supply a bias current sufficient for the operation. On the other hand, when the pipeline type AD converter circuit 10 is operated at a low frequency, less current is supplied than at a high frequency. It is enough. Therefore, in the current supply circuit 80 of the present embodiment, when high frequency AD conversion is required in the pipelined AD converter circuit 10, a sufficient bias current is supplied to the operation, while low frequency AD conversion is performed. When performing the above, the power consumption is reduced by switching the bias current value to a low value. As a result, an appropriate bias current can be supplied according to the operating frequency, reducing unnecessary current consumption and reducing power consumption compared to conventional circuits that supply a constant bias current regardless of the operating frequency. can do.

  For example, when the operating frequency of the pipeline AD converter circuit 10 is switched in accordance with the operation mode of the electronic device incorporating the pipeline AD converter circuit 10, the current control unit 100 is a program for controlling the operation mode of the electronic device. It may be. At this time, the current control means 100 can be realized by a hardware configuration such as a CPU or a memory. In the operation mode that requires high-frequency AD conversion, the current control means 100 sends a current control signal to the current switching circuit 70 to output a current necessary for realizing a high slew rate. In the operation mode in which low-frequency AD conversion is performed, a current control signal for outputting a current having a value lower than the current required for high-frequency operation is sent to the current switching circuit 70. According to such a configuration, it is possible to dynamically control the bias current in accordance with a change in the operating frequency required for the pipelined AD converter circuit 10 and reduce the average power consumption. The current control unit 100 may be realized by hardware such as a system register.

  The current control unit 100 may statically switch the bias current value. For example, when a design change occurs in the operating frequency of the pipelined AD converter circuit 10, in order to be able to set a bias current suitable for operation at the changed operating frequency, a bias current having a plurality of current values is set in advance. Is provided. Then, after the operating frequency is finally determined, a current control signal is given to the current switching circuit 70 so as to supply an appropriate bias current. In this case, the current control means 100 may be a changeover switch such as a DIP switch, or may be a program such as firmware or a driver. The switch element of the current switching circuit 70 may be constituted by a dip switch so that it can be switched from the outside. Programs such as firmware can be updated from the outside after manufacturing the device. Thereby, even after the device is manufactured, it is possible to set an appropriate bias current in accordance with the change in the operating frequency of the pipelined AD converter circuit 10 and suppress unnecessary power consumption.

  FIG. 2 shows an example of the circuit configuration of the current switching circuit 70. The current switching circuit 70 inputs the current supplied from the constant current source 60 from the input terminal 71 and outputs the current from the output terminal 77 to the bias circuit 50. Two current paths connected in parallel are provided between the input terminal 71 and the output terminal 77. From the input terminal 71 side, the switch element 72a, the transistor 76a, and the switch element are provided in the first path. 74a are connected in this order. Similarly, the switch element 72b, the transistor 76a, and the switch element 74b are connected in this order to the second path. Each of the transistors 76a and 76b has a source electrode grounded and a gate electrode and a drain electrode short-circuited, and functions as a load resistor having a rectifying action. That is, by using the transistors 76a and 76b having different characteristics, different currents can be output in the first path and the second path.

  The on / off state of the switch elements 72a, 72b, 74a, and 74b selects a current path and switches the output current. In addition to the path selection, all the switch elements 72a, 72b, 74a, and 74b may be turned on to change the characteristics of the transistors 76a and 76b. The switch elements 72a, 72b, 74a, and 74b may actually be realized by MOSFETs or the like. A current control signal from the current control means 100 is input to these MOSFETs to control on / off of the switches. Also good. Although FIG. 2 shows an example that can be switched to two kinds of current values, of course, three or more kinds of paths may be provided. Further, the current value may be continuously controlled using a variable resistor or the like.

  FIG. 3 shows an example of the circuit configuration of the bias circuit 50. The bias circuit 50 includes four transistors 52, 54, 56, and 58, adjusts the current input from the current switching circuit 70 to the input terminal 51, and outputs the current from the output terminal 59 to the transistor 40. The bias circuit 50 shown in FIG. 3 is an example, and any bias circuit can be applied.

  FIG. 4 shows an example of the circuit configuration of the operational amplifier 30. The operational amplifier 30 operates by the bias current input from the bias circuit 50 to the bias current input terminal 31 via the transistor 40, and amplifies the difference between the input voltage Vin and the auto-zero voltage Vaz to obtain the output voltage Vout. Although FIG. 4 shows an example in which the operational amplifier 30 is configured by an active load circuit, other arbitrary operational amplifiers 30 can be applied. The bias current is preferably variably controlled within a range in which the operational amplifier 30 maintains ideal characteristics.

  Note that any combination of the circuits shown in FIG. 1 may be configured as an LSI. When the current control means 100 is realized by a register or the like, it may be implemented as an LSI including the register.

(Second Embodiment)
FIG. 5 shows the overall configuration of a pipelined AD converter circuit 10 according to the second embodiment of the present invention. In the first embodiment, the bias current value input to all the operational amplifiers 30 is switched by one current switching circuit 70, but in this embodiment, the bias current value is set for each of the operational amplifiers 30. Switchable current switching circuits 70a and 70b are provided. The same components as those in the pipeline type AD converter circuit 10 according to the first embodiment shown in FIG. In the following, the description will be centered on differences from the first embodiment.

  The current switching circuits 70a and 70b receive the current control signal from the current control means 100, switch the value of the current to be output, and supply it to the bias circuits 50a and 50b, respectively. The circuit configuration of the current switching circuits 70a and 70b is the same as the circuit configuration of the current switching circuit 70 of the first embodiment shown in FIG. The current control means 100 may send the same current control signal to all the current switching circuits 70 or may send different current control signals to the individual current switching circuits 70. Thus, by finely controlling the bias current supplied to each operational amplifier 30, finer current control is possible.

(Third embodiment)
FIG. 6 shows an overall configuration of a receiving apparatus 200 according to the third embodiment of the present invention. The receiving device 200 is a portable television receiving device that decodes and reproduces MPEG stream data from a received broadcast wave. The receiving apparatus 200 includes two antennas 102a and 102b, and is configured to be able to receive a diversity scheme. Even when the reception signal of one antenna 102a is disturbed due to multipath interference caused by reflected waves, etc., by receiving a broadcast wave by the diversity method, the reception signal from the other antenna 102b is used appropriately. MPEG stream data can be decoded.

The broadcast signal received by the antenna 102a is band-limited by a band pass filter (BPF) 104a, amplified by a low noise amplifier (LNA) 106a, and input to the frequency conversion IC 110. In the frequency conversion IC 110, the orthogonal local oscillation signal generated by the frequency generation circuit 122 and the phase shifter 116a is multiplied by the broadcast signal by the mixers 112a and 114a, and the I baseband signal and the Q orthogonal to each other by the direct conversion method. Converted to baseband signal. The I baseband signal and the Q baseband signal are low pass filters 118a and 1 respectively.
Harmonic components are removed by 20a and input to sample hold circuits 132a and 134a of an Orthogonal Frequency Division Multiplexing (OFDM) demodulation LSI 130.

  Similarly, the broadcast signal received by the antenna 102b is band-limited by the band-pass filter 104b, amplified by the low noise amplifier 106b, and input to the frequency conversion IC 110. In the frequency conversion IC 110, the orthogonal local oscillation signal generated by the frequency generation circuit 122 and the phase shifter 116b is multiplied by the broadcast signal by the mixers 112b and 114b, and the I baseband signal and the Q orthogonal to each other by the direct conversion method. Converted to baseband signal. The I baseband signal and the Q baseband signal have their harmonic components removed by the low-pass filters 118b and 120b, respectively, and are input to the sample hold circuits 132b and 134b of the OFDM demodulation LSI 130.

  In the OFDM demodulation LSI 130, a total of four series of I baseband signals and Q baseband signals respectively obtained from broadcast signals received by the two antennas 102a and 102b are converted into digital signals by the pipelined AD converter circuit 10. And demodulated by the OFDM demodulation circuit 140. Further, the subcarriers rearranged in the frequency direction or the time direction by the deinterleave circuit 142 are deinterleaved in the original order, subjected to error correction processing by the error correction circuit 144, and output MPEG data.

  Here, in the present embodiment, instead of providing four AD converter circuits for AD conversion of four series of signals, the pipeline AD converter circuit 10 of the first or second embodiment is used. Thus, AD conversion is performed on the four series of signals in a time division manner. Therefore, the analog signals held in the four sample hold circuits 132a, 134a, 132b, and 134b are selected one by one by the analog selector (parallel-serial conversion) 136 and input to the pipelined AD converter circuit 10. The digital signal output from the pipelined AD converter circuit 10 in a time division manner is divided into four original signals by a digital selector (serial-parallel conversion) 138, and each signal is input to the OFDM demodulation circuit 140. Is done. With such a configuration, the circuit scale can be reduced, and the apparatus can be reduced in size, weight, and cost.

  The diversity method enables transmission of high-quality signals, but requires a plurality of signal processing systems as described above, and thus generally increases the circuit scale and power consumption. In the present embodiment, the reception mode can be switched between a normal mode in which broadcast waves are received by only one antenna 102a and a diversity mode in which broadcast waves are received by the diversity method by two antennas 102a and 102b. This suppresses an increase in power consumption.

  In the normal mode, it is only necessary to AD-convert two series of signals, but in the diversity mode, it is necessary to AD-convert four series of signals within the same time. Therefore, in the diversity mode, the pipeline AD converter circuit 10 is operated at a frequency twice that of the normal mode. For example, in the normal mode, a 4 MHz clock is supplied from the clock generation circuit 146 to the pipelined AD converter circuit 10, and in the diversity mode, an 8 MHz clock is supplied from the clock generation circuit 146 to the pipelined AD converter circuit 10. This is equivalent to AD conversion of each signal at a frequency of 2 MHz in any case.

The control unit 150 controls switching of the reception mode between the normal mode and the diversity mode. In the diversity mode, the control unit 150 turns on the sample hold circuits 132b and 134b and causes the clock generation circuit 146 to generate a clock signal of 8 MHz, for example. In the normal mode, the control unit 150 turns off the sample hold circuit 132b and the sample hold circuit 134b, and causes the clock generation circuit 146 to generate a clock signal of 4 MHz, for example. That is, the control unit 150 functions as a frequency control unit.

  The current control means 100 of the pipeline type AD converter circuit 10 receives an instruction of the operating frequency required for the pipeline type AD converter circuit 10 from the control unit 150 and sends a current control signal to the current switching circuit 70. Specifically, when the pipeline AD converter circuit 10 is operated at a high frequency, for example, 8 MHz, in the diversity mode, a bias current sufficient for the operation is supplied to the operational amplifier 30, and in the normal mode, the pipeline AD converter circuit 10 is operated. When the converter circuit 10 is operated at a low frequency, for example, 4 MHz, a bias current smaller than that in the diversity mode is supplied to the operational amplifier 30. Thereby, power consumption can be reduced.

  The present invention has been described based on the embodiments. This embodiment is an exemplification, and it is understood by those skilled in the art that various modifications can be made to the combination of each component and each processing process, and such modifications are within the scope of the present invention. . Such an example is described below.

  In the embodiment, a pipelined AD converter has been described as an example of a semiconductor circuit having an amplifier. However, the technology of the present invention can be applied to any semiconductor circuit having an amplifier, such as a front-end circuit for storage use. For example, in the case of a front-end circuit for storage use, power consumption can be reduced by controlling the amount of current supplied to the operational amplifier in accordance with the reading or writing speed.

  In the embodiment, the pipeline AD converter having a plurality of amplifiers has been described as an example. However, the technique of the present invention can also be applied to a semiconductor circuit having one amplifier. In the embodiment, the operational amplifier has been described as an example. However, the technique of the present invention can be applied to an arbitrary amplifier such as an RF amplifier.

It is a figure which shows the circuit structure of the pipeline type AD converter which concerns on 1st Embodiment. It is a figure which shows the example of a circuit structure of a current switching circuit. It is a figure which shows the example of a circuit structure of a bias circuit. It is a figure which shows the example of the circuit structure of an operational amplifier. It is a figure which shows the circuit structure of the pipeline type AD converter which concerns on 2nd Embodiment. It is a figure which shows the whole structure of the receiver which concerns on 3rd Embodiment.

Explanation of symbols

  10 pipeline AD converter circuit, 20 sub AD converter, 22 sub DA converter, 30 operational amplifier, 40 transistor, 50 bias circuit, 60 constant current source, 70 current switching circuit, 72 switch element, 74 switch element, 76 transistor, 80 current supply circuit, 100 current control means, 102a, 102b antenna, 122 frequency generation circuit, 136 analog selector, 138 digital selector, 140 OFDM demodulation circuit, 142 deinterleave circuit, 144 error correction circuit, 146 clock generation circuit, 150 control Part, 200 receiver.

Claims (7)

A plurality of sub A / D conversion circuits connected in series;
An amplifier inserted between the sub A / D conversion circuits and amplifying an input signal to the sub A / D conversion circuit in the next stage;
A current switching means for switching a current supplied to the amplifier in response to a current control signal generated in response to switching of an operating frequency of the amplifier;
An AD conversion device comprising: A plurality of amplifiers;
Current control means for controlling the current to be supplied to the amplifier in response to switching of the operating frequency of the amplifier;
A current switching means for switching a current supplied to the plurality of amplifiers in response to a current control signal generated by the current control means;
An electronic device comprising: A plurality of sub A / D conversion circuits connected in series, an amplifier inserted between the sub A / D conversion circuits and amplifying an input signal to the sub A / D conversion circuit in the next stage, and a current switching for switching a current supplied to the amplifier And an AD conversion device including:
Frequency control means for switching the operating frequency of the amplifier;
Current control means for issuing a current control signal for controlling the current to be supplied to the amplifier to the current switching means in response to switching of the operating frequency of the amplifier, and
The electronic apparatus according to claim 1, wherein the frequency control means switches the operating frequency in accordance with the number of the input signal sequences when the AD converter converts the input signals of a plurality of sequences in a time division manner. The frequency control means increases the operating frequency as the number of the input signal series increases.
The electronic device according to claim 3, wherein the current control unit increases the current supplied to the amplifier as the operating frequency is higher. Multiple antennas,
A plurality of sub A / D conversion circuits connected in series, an amplifier inserted between the sub A / D conversion circuits and amplifying an input signal to the sub A / D conversion circuit in the next stage, and a current switching for switching a current supplied to the amplifier And an AD conversion device including:
Frequency control means for switching the operating frequency of the amplifier;
Current control means for issuing a current control signal for controlling the current to be supplied to the amplifier to the current switching means in response to switching of the operating frequency of the amplifier, and
The frequency control means is configured to switch the operating frequency in accordance with the number of the input signal sequences when the AD converter device converts the input signals of the plurality of sequences received by the plurality of antennas in a time division manner. A receiving device.   The frequency control means increases the operating frequency in a mode in which the receiving apparatus receives an analog signal in a diversity manner using a plurality of antennas, compared to a mode in which the analog signal is received by a single antenna. The receiving device according to claim 5.   The receiving apparatus according to claim 6, wherein the current control unit increases the current supplied to the amplifier as the operating frequency is higher.

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