JP2008071454A - Semiconductor storage device and writing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To inexpensively prepare a logic circuit and a semiconductor nonvolatile memory on one and the same semiconductor substrate. <P>SOLUTION: A second boosting circuit 26 is arranged between a memory cell selection circuit 21 and a memory cell array 22. By this arrangement, after a power source voltage Vdd is elevated by a first boosting circuit 25 to the order of 5V which is a writing voltage, a voltage lowered by its passing through the memory selection circuit 21 can be elevated to 5V again by the second boosting circuit 26 right before the memory cell array 22. Consequently, a maximum voltage applied to each transistor constituting the memory cell selection circuit 21, the first boosting circuit 25 and the second boosting circuit 26, becomes to the order of 5V. As a result, by setting an withstanding voltage of the normal transistor to the extent of a little exceeding 5V, the preparation of the transistor having high withstanding voltage separately with the normal transistor, which involves in the increase of a manufacturing process, becomes unnecessary, then the manufacturing process of the semiconductor storage device can be simplified and also the low cost preparation of the device is attained. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor memory device and a writing method thereof.

  In recent years, a so-called nonvolatile memory mixed process has been performed in which a logic circuit that performs arithmetic processing and the like and an electrically rewritable semiconductor nonvolatile memory are formed on the same semiconductor substrate.

  By the way, rewriting of the electrically rewritable semiconductor nonvolatile memory usually requires a voltage higher than the voltage necessary for the operation of the logic circuit. The high voltage for rewriting the semiconductor nonvolatile memory is generated in the chip by the booster circuit.

  FIG. 8 shows a charge pump type booster circuit. FIG. 9 shows voltage waveforms applied to the capacitance of the booster circuit shown in FIG.

  In FIG. 8, T0 to T4 are N-type MOS transistors, C1 to C4 are capacitances, and N1 to N4 are node names. N-type MOS transistors (hereinafter also simply referred to as transistors) T0 to T4 are connected in series, and the gates of the respective N-type MOS transistors are the respective N-type MOS transistors (that is, their own). Connected to the source. Capacitances C1 to C4 are connected to the nodes N1 to N4, and either the pulse voltage PA or the pulse voltage PB shown in FIG. 9 is connected to the nodes N1 to N4 through the capacitances C1 to C4. Is applied. The N-type MOS transistor T0 is a backflow prevention transistor. Here, the combination of the capacitance C and the N-type MOS transistor T is a basic structural unit of the booster circuit, and the booster circuit shown in FIG. 8 has a four-stage configuration.

  The operation of the charge pump type booster circuit shown in FIG. 8 will be described below. Here, the threshold value of the transistors T0 to T4 is assumed to be Vth.

  First, when the pulse voltage PA is set to Gnd and the pulse voltage PB is set to Vdd, carriers flow from the power supply through the transistor T0 that is turned on, and the voltage at the node N1 subtracts the threshold value of the transistor T0 from the power supply voltage Vdd ( Vdd-Vth). Next, when the pulse voltage PA is set to Vdd and the pulse voltage PB is set to Gnd, the transistor T0 is turned off, and the carrier at the node N1 moves to the node N2 through the transistor T1 that is turned on. By repeating the above, when the pulse voltage PA is the power supply voltage Vdd, the potential of the node N1 finally rises to (2 * Vdd−Vth) and the potential of the node N2 becomes (2 * Vdd− 2 * Vth). That is, (Vdd−Vth) can be boosted per stage in the booster circuit, and the maximum output voltage Vout of the booster circuit shown in FIG. 8 is 5 * (Vdd−Vth).

  By the way, in order to actually apply the high voltage generated by the booster circuit to the memory cell, it is usually necessary to pass through several transistors such as a memory cell selection circuit for selecting a desired memory cell in the memory cell array. There is. In that case, the high voltage generated in the booster circuit decreases by the threshold value of the transistor every time it passes through the several transistors, and further, the resistance of the transistor and the resistance of the wiring until reaching the memory cell. There is also a problem that the voltage decreases due to the like. The booster circuit is arranged not at a location between the memory cell selection circuit and the memory cell array, but at a location other than that.

  Therefore, in the booster circuit, since the generated high voltage decreases until it reaches the memory cell, a high voltage obtained by adding the predicted value corresponding to the voltage drop to the write voltage necessary for writing to the memory cell is set. There is a problem that needs to be generated.

  On the other hand, a normal transistor used in a normal logic circuit is required to operate at high speed, and is not designed to withstand the high voltage as described above. Therefore, it is used in a transistor used in a booster circuit for generating a voltage higher than a write voltage necessary for writing in a memory cell, or in a memory selection circuit for supplying the generated high voltage to a desired memory cell. As the transistor, a high breakdown voltage transistor having a breakdown voltage higher than that of the normal transistor is separately required.

  In the following, for example, a conventional method for forming a high voltage transistor and a normal transistor on the same chip as in the method of manufacturing a high voltage transistor disclosed in Japanese Patent Laid-Open No. 7-94734 (Patent Document 1) will be described. 10 to FIG. 10 to 12, the right side portion shows a high voltage transistor portion, and the left side portion shows a normal transistor portion.

  First, as shown in FIG. 10, the element isolation region 2 is formed on the semiconductor substrate 1. Thereafter, after patterning the high breakdown voltage transistor portion with a resist (not shown), ion implantation is performed to form a well 3b for the high breakdown voltage transistor. Next, after removing the resist, the normal transistor portion is patterned with a new resist (not shown), and then ion implantation is performed to form the normal transistor well 3a.

  Thereafter, a gate insulating film 4 and a polysilicon film are sequentially formed on the surface of the semiconductor substrate 1. Then, after patterning using a resist (not shown), etching is performed to form the gate insulating film 4 and the gate electrode 5 for the normal transistor and the high voltage transistor.

  Thereafter, using the resist 6, patterning is performed to expose only the source and drain regions for the normal transistor and the source region for the high breakdown voltage transistor. Thereafter, ion implantation is performed to form a low concentration impurity diffusion region 7 for an LDD (Lightly Doped Drain) structure.

  After that, an insulating film is deposited on the entire surface of the semiconductor substrate 1 and etched back by RIE (reactive ion etching), so that as shown in FIG. Sidewalls 8 are formed as spacers when forming the high concentration impurity diffusion region. Thereafter, by patterning using a resist 9, only the drain side of the high breakdown voltage transistor is exposed, and ion implantation is performed to form a low concentration impurity diffusion region 10 as an offset portion for the high breakdown voltage transistor.

  Next, as shown in FIG. 12, after patterning the resist 11, ion implantation is performed to form the high concentration impurity diffusion regions 12 of the normal transistor and the high breakdown voltage transistor. Thereafter, by performing a known process, a semiconductor device in which a high voltage transistor and a normal transistor are formed on the same chip is completed.

  However, there are the following problems in a semiconductor memory device in which a logic circuit that performs the above-described conventional arithmetic processing and an electrically rewritable semiconductor nonvolatile memory are formed on the same semiconductor substrate.

  That is, as described above, in order to form a logic circuit for performing arithmetic processing and the like and an electrically rewritable semiconductor nonvolatile memory on the same semiconductor substrate, in addition to the normal transistor, a high breakdown voltage transistor having a high breakdown voltage. Is required. This is because the high voltage generated in the booster circuit is lowered by passing through a memory selection circuit or the like before reaching the memory cell, so that the booster circuit expects the voltage drop and writes to the memory cell. This is because it is necessary to generate a high voltage that is higher than the write voltage required for.

However, the manufacturing of the high breakdown voltage transistor disclosed in Patent Document 1 is applied to a semiconductor memory device in which a logic circuit for performing the arithmetic processing and the like and an electrically rewritable semiconductor nonvolatile memory are formed on the same semiconductor substrate. When the normal transistor and the high breakdown voltage transistor are formed on the same chip by applying the method, the well 3b for the high breakdown voltage transistor and the low concentration impurity diffusion region 10 for the high breakdown voltage transistor are separately required. There are problems that the number of manufacturing steps is increased and the manufacturing cost is increased as compared with the case of manufacturing only a transistor.
JP-A-7-94734

  Therefore, an object of the present invention is to create a logic circuit that performs arithmetic processing and the like and an electrically rewritable semiconductor nonvolatile memory on the same semiconductor substrate, as compared with the case where only the logic circuit is created. It is an object of the present invention to provide a semiconductor memory device that can be manufactured at low cost without increasing the number of manufacturing steps, and a writing method for the semiconductor memory device.

In order to solve the above problems, a semiconductor memory device according to the present invention provides:
A memory cell array in which electrically rewritable memory cells are arranged in a matrix;
A first booster circuit that boosts a power supply voltage to at least a predetermined voltage that is a write voltage to the memory cell;
A memory cell selection circuit that receives an output from the first booster circuit and selects a desired memory cell that is a target of data writing, data reading, and data erasing from the memory cell array;
The memory cell selection circuit is arranged between the memory cell selection circuit and the memory cell selection circuit, and the output voltage from the memory cell selection circuit is boosted to the predetermined voltage to obtain a desired memory cell selected by the memory cell selection circuit. And a second booster circuit to be supplied.

  According to the above configuration, the second booster circuit that boosts the output voltage from the memory cell selection circuit to a predetermined voltage that is a write voltage to the memory cell is disposed between the memory cell selection circuit and the memory cell array. Yes. For this purpose, in the first booster circuit which is arranged before the memory cell selection circuit and boosts the power supply voltage and supplies the boosted power supply voltage to the memory cell selection circuit, at least up to the predetermined voltage which is a write voltage to the memory cell. The voltage may be boosted, and it is not necessary to boost the voltage to a high voltage that is equal to or higher than the predetermined voltage. Therefore, as the transistors constituting the first booster circuit, the memory cell selection circuit, and the second booster circuit, normal transistors having a withstand voltage set slightly higher than the predetermined voltage can be used. There is no need to separately create a high voltage transistor that leads to an increase.

  That is, according to the present invention, the manufacturing process of the semiconductor memory device can be simplified and can be produced at low cost.

In the semiconductor memory device of one embodiment,
The second booster circuit is composed of an inverter and a capacitance.

  According to this embodiment, since the second booster circuit is composed of an inverter and a capacitance, it can be easily manufactured.

In the semiconductor memory device of one embodiment,
The semiconductor memory device is mounted on the same chip with a logic circuit having a function other than the function of performing each of a selection operation, a write operation, a read operation, and an erase operation for the memory cell array.

  According to this embodiment, a logic circuit that is normally formed of transistors and has functions other than the function of performing the selection operation, the write operation, the read operation, and the erase operation for the memory cell array on the same chip. Can use a normal transistor set to a withstand voltage that slightly exceeds the predetermined voltage, which is a write voltage to the memory cell. Therefore, when the logic memory is produced by embedding the semiconductor memory device and the logic circuit on the same chip, it is not necessary to separately create a high breakdown voltage transistor and the number of processes does not increase. it can.

In the semiconductor memory device of one embodiment,
Each of the memory cells constituting the memory cell array is
A semiconductor substrate;
A gate insulating film formed on the semiconductor substrate;
A gate electrode formed on the gate insulating film;
A charge storage region formed on the sidewall of the gate electrode;
A channel region formed immediately below the gate insulating film in the semiconductor substrate;
And a diffusion region formed adjacent to both ends of the channel region in the semiconductor substrate.

  According to this embodiment, a memory cell of a type that accumulates charges in the charge accumulation region formed on the side wall of the gate electrode has substantially the same structure as the normal transistor. Therefore, the logic circuit and the semiconductor memory device can be mixedly mounted on the same chip without increasing the number of processes compared to the case where only the logic circuit is created.

In the semiconductor memory device of one embodiment,
Of the two diffusion regions formed adjacent to both ends of the channel region in the memory cell, one is formed so as to overlap the gate electrode, and the other is formed without overlapping the gate electrode. Has been.

  According to this embodiment, one of the two diffusion regions formed adjacent to both ends of the channel region in the memory cell overlaps with the gate electrode, and the other is the gate. Since it is formed without overlapping with the electrode, the two diffusion regions formed adjacent to both ends of the channel region have a lower voltage than the memory cell that does not overlap with the gate electrode. It becomes possible to perform writing. Therefore, the area of the capacitance component in the second booster circuit can be reduced, and a more highly integrated semiconductor memory device can be realized.

Further, a writing method of the semiconductor memory device of the present invention is as follows:
In writing to the memory cell in the semiconductor memory device, a pulse voltage is output as the output voltage from the memory cell selection circuit to the second booster circuit.

  According to the above configuration, by setting the output voltage from the memory cell selection circuit to the second booster circuit in the semiconductor memory device as a pulse voltage, a desired data write, data read, and data erase target are obtained. Even if the voltage boosted by the second booster circuit drops due to current consumption in the memory cell, the voltage is boosted to the predetermined voltage before dropping to the input voltage from the memory cell selection circuit. It becomes possible to do.

  Therefore, even when the voltage boosted by the second booster circuit drops because current is consumed in the memory cell, the predetermined voltage can be stably supplied to the memory cell.

  As apparent from the above, the semiconductor memory device of the present invention boosts the output voltage from the memory cell selection circuit to a predetermined voltage which is a write voltage to the memory cell, between the memory cell selection circuit and the memory cell array. Since the second booster circuit is arranged, the first booster circuit that boosts the power supply voltage and supplies it to the memory cell selection circuit only needs to boost the voltage to at least the predetermined voltage, and needs to boost the voltage to a voltage higher than the predetermined voltage. There is no. Therefore, as the transistors constituting the first booster circuit, the memory cell selection circuit, and the second booster circuit, normal transistors having a withstand voltage set slightly higher than the predetermined voltage can be used. There is no need to separately create a high voltage transistor that leads to an increase.

  That is, according to the present invention, the manufacturing process of the semiconductor memory device can be simplified and the manufacturing cost can be reduced.

  Furthermore, when a logic embedded memory is created on the same chip as a logic circuit that performs arithmetic processing or the like, there is no need to separately create a high voltage transistor, and the process is compared to the case where only the above logic circuit is created. Does not increase. Therefore, the logic embedded memory can be created at a low cost.

  Hereinafter, the present invention will be described in detail with reference to the illustrated embodiments.

First Embodiment FIG. 1 is a diagram showing a schematic configuration of a semiconductor memory device according to the present embodiment. In FIG. 1, T0 to T3 are N-type MOS transistors, C1 to C3 are capacitances, 21 is a memory cell selection circuit, 22 is a memory cell array, and 23 and 24 are inverters. The N-type MOS transistors T0 to T2 and the capacitances C1 and C2 constitute a first booster circuit 25, and the inverters 23 and 24, the capacitance C3 and the N-type MOS transistor T3 constitute a second booster circuit 26. .

  In the first booster circuit 25, the N-type MOS transistors T0 to T2 are connected in series, and the gates of the respective N-type MOS transistors T0 to T2 are connected to the respective N-type MOS transistors T0 to T2 (that is, themselves). Connected to the source). Capacitances C1 and C2 are connected to the nodes N1 and N2, and the pulse voltage PA and the pulse voltage PB shown in FIG. 9 are applied to the nodes N1 and N2 through the capacitances C1 and C2. ing. The N-type MOS transistor T0 is a backflow prevention transistor. Here, the combination of the capacitance C and the N-type MOS transistor T is a basic structural unit of the first booster circuit 25, and the first booster circuit 25 shown in FIG. 1 has a two-stage configuration.

  The output from the first booster circuit 25 is input to a memory cell selection circuit 21 that selects a desired memory cell from the memory cell array 22. The output of the memory cell selection circuit 21 is applied to the selected memory cell in the memory cell array 22 via the second booster circuit 26. Here, as described above, the second booster circuit 26 includes the two inverters 23 and 24, the capacitance C3, and the N-type MOS transistor T3. By adopting the above-described configuration, the second booster circuit 26 can boost the voltage immediately before the memory cell to be applied in the memory cell array 22.

  The operation of the semiconductor memory device in the present embodiment shown in FIG. 1 will be described below. Here, the threshold value of the N-type MOS transistors T0 to T2 is Vth.

  First, when the pulse voltage PA is set to Gnd and the pulse voltage PB is set to Vdd, carriers flow from the power supply through the transistor T0 that is turned on, and the voltage at the node N1 is changed from the power supply voltage Vdd to the threshold of the N-type MOS transistor T0. Subtracted (Vdd-Vth). Next, when the pulse voltage PA is set to Vdd while the pulse voltage PB is set to Gnd, the N-type MOS transistor T0 is turned off, and the carrier at the node N1 moves to the node N2 through the turned-on N-type MOS transistor T1. By repeating the above, when the pulse voltage PA is the power supply voltage Vdd, the potential of the node N1 finally rises to (2 * Vdd-Vth), and the potential of the node N2 is (2 * Vdd). -2 * Vth). That is, the boosting circuit can boost (Vdd−Vth) per stage, and the maximum output voltage Vout of the first boosting circuit 25 shown in FIG. 1 is 3 * (Vdd−Vth).

  Next, after the memory cell selection circuit 21 receives the output from the first booster circuit 25 and selects a desired memory cell from the memory cell array 22, the output voltage from the memory cell selection circuit 21 is N The voltage is applied to the node N4 through the type MOS transistor T3. The voltage applied to the node N4 is further boosted through the inverters 23 and 24 and the capacitance C3, and is raised to a voltage necessary for rewriting the memory cell.

  Here, in the case of a conventional semiconductor memory device that does not have the second booster circuit 26 between the memory cell selection circuit 21 and the selected desired memory cell, the desired memory cell is reached. Since the voltage drops by the time, if it is necessary to rewrite the memory cell, for example, 5V, the booster circuit needs to generate a high voltage of about 7V. Therefore, a high voltage transistor that can withstand a voltage of 7 V or more is required in addition to the normal transistor.

  On the other hand, in the semiconductor memory device of the present embodiment, since the second booster circuit 26 exists between the memory cell selection circuit 21 and the memory cell array 22, the first booster circuit 25 provides about 5V. Even if the voltage drops by passing through the memory cell selection circuit 21 after being boosted from the power supply voltage Vdd, the voltage can be boosted to 5 V again immediately before the memory cell array 22 by the second booster circuit 26. Therefore, the maximum voltage applied to each N-type MOS transistor is about 5V.

  As a result, if the breakdown voltage of the normal transistor is set slightly higher than 5V, it is not necessary to create a high breakdown voltage transistor separately from the normal transistor, which leads to an increase in the manufacturing process, and the manufacturing process can be simplified and the cost can be reduced. Thus, the semiconductor memory device can be created.

  Here, the memory cells in the memory cell array 22 in the semiconductor memory device may be a so-called floating gate structure nonvolatile memory that holds charges in a conductive charge storage region, and may be an insulating material such as a silicon nitride film. It may be a non-volatile memory having a so-called MONOS (Metal Nitride Oxide Semiconductor) structure for accumulating charges in the charge storage region.

Second Embodiment In this embodiment, a writing method of the semiconductor memory device shown in FIG. 1 in the first embodiment will be described.

  FIG. 2 shows voltage waveforms at nodes N3 and N4 in the semiconductor memory device shown in FIG. In FIG. 2, VN3 indicates a voltage at the node N3, and VN4a and VN4b indicate voltages at the node N4.

  In the memory cell of the memory cell array 22 in the semiconductor memory device shown in FIG. 1, when the boosted voltage does not consume current during rewriting, for example, when the boosted voltage is applied to the gate of the memory cell, Unlike the VN 4a in FIG. 2, the boosted voltage does not decrease. However, when the boosted voltage is applied to the drain of the memory cell, current is consumed, and the boosted voltage is reduced to VN3 as VN4b in FIG.

  Therefore, in the writing method in the semiconductor memory device of the present embodiment, when the generated high voltage consumes current, the memory cell selection circuit 21 is controlled, and as shown in FIG. The applied voltage waveform is pulsed. By controlling the memory cell selection circuit 21 in this way, the voltage at the node N4 is re-boosted to a desired voltage (for example, 5V) immediately before decreasing to VN3, as indicated by VN4 in FIG. become. Therefore, even when the boosted high voltage consumes current, a voltage necessary for rewriting the memory cell can be secured.

Third Embodiment FIG. 4 shows a normal transistor used for the first booster circuit, the memory cell selection circuit, and the second booster circuit in the semiconductor memory device of the present embodiment, and a memory cell of the memory cell array. It is sectional drawing of the state which formed the transistor provided with the charge storage area | region in the side wall of the gate electrode on the same semiconductor substrate. The first booster circuit, the memory cell selector circuit, and the second booster circuit are the same as the first booster circuit 25, the memory cell selector circuit 21, and the second booster circuit 26 in the first embodiment, and are described in detail. Description is omitted.

  In FIG. 4, the normal transistor 31 is shown on the left side, and the memory cell 32 is shown on the right side.

  The normal transistor 31 has a sidewall 41a comprising a gate insulating film 36, a gate electrode 37, an oxide film 38 / a charge storage film 39a / an oxide film 40 on a semiconductor substrate 33 on which an element isolation region 34 and a well 35 are formed. A side wall 41b comprising the oxide film 38 / charge storage film 39b / oxide film 40, a low concentration impurity diffusion region 42a, a low concentration impurity diffusion region 42b, a high concentration impurity diffusion region 43a, and a high concentration impurity diffusion region 43b are formed. Has been configured.

  The memory cell 32 includes a gate insulating film 36, a gate electrode 37, an oxide film 38 / a charge storage film 39a / an oxide film 40 on a semiconductor substrate 33 on which an element isolation region 34 and a well 35 are formed. A wall 41a, a sidewall 41b composed of an oxide film 38 / charge storage film 39b / oxide film 40, a high concentration impurity diffusion region 43a, and a high concentration impurity diffusion region 43b are formed.

  The gate insulating film 36 is not particularly limited as long as it is used in a normal semiconductor device. For example, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, an aluminum oxide film, a hafnium oxide film, or the like is used. Can be used. Among these, the silicon oxide film is preferable. The thickness of the gate insulating film 36 is preferably about 1 nm to 10 nm. Here, in the present embodiment, the film thicknesses of the gate insulating film 36 of the transistor 31 and the memory cell 32 are usually the same, but they may be different.

  The gate electrode 37 is not particularly limited as long as it is used in a normal semiconductor device. For example, a polysilicon film, a cobalt silicide film, a titanium silicide film, a nickel silicide film, or a composite film thereof is used. be able to. The charge storage film 39a and the charge storage film 39b are not particularly limited as long as they have a function of storing charges therein. For example, a dot-shaped charge storage region is formed in the silicon nitride film and the insulating film. The film | membrane etc. which have can be used.

  Here, the low concentration impurity diffusion region 42a and the low concentration impurity diffusion region 42b exist in the semiconductor substrate 33 under the sidewall 41a and the sidewall 41b of the normal transistor 31. Therefore, even if electrons enter the charge storage film 39a or the charge storage film 39b in the side wall 41a and the side wall 41b of the normal transistor 31, the threshold value of the normal transistor 31 does not change.

  On the other hand, the low concentration impurity diffusion region does not exist in the semiconductor substrate 33 under the sidewall 41a and the sidewall 41b of the memory cell 32. Therefore, when electrons enter the charge storage film 39a or the charge storage film 39b in the side wall 41a and the side wall 41b of the memory cell 32, the threshold value of the memory cell 32 changes. As a result, the memory cell 32 can function as a nonvolatile memory.

  The operation of the memory cell 32 configured as described above is as follows. Here, it is assumed that the data writing state is a state where electrons are held in the charge storage film 39a or the charge storage film 39b, that is, a state where the threshold value of the memory transistor constituting the memory cell 32 is high. On the other hand, it is assumed that the data erasing state is a state in which there are no electrons in the charge storage film 39a and the charge storage film 39b, that is, a state in which the threshold value of the memory transistor constituting the memory cell 32 is low.

  The memory cell 32 has a charge storage layer 39a and a charge storage film 39b, which are insulating films including trap levels, as charge holding layers. Data can be stored independently in each of the two sidewalls 41a and 41b. That is, the memory cell 32 (one memory transistor) can store 2 bits.

  First, data is written to the charge storage film 39a of the memory transistor that constitutes the memory cell 32 with 5 [V] in the high concentration impurity diffusion region 43a, 0 [V] in the high concentration impurity diffusion region 43b, By applying 5 [V] to the electrode 37 and 0 [V] to the semiconductor substrate 33, hot electrons generated in the channel region near the high concentration impurity diffusion region 43a are trapped in the charge storage film 39a. .

  On the other hand, reading of data written in the charge storage film 39a is performed by so-called reverse reading. That is, by applying about 3 [V] to the gate electrode 37, 1.5 [V] to the high concentration impurity diffusion region 43b, and 0 [V] to the high concentration impurity diffusion region 43a and the semiconductor substrate 33, Data is determined based on the amount of current flowing between the source and drain. In other words, if a certain amount or more of electrons are present in the charge storage film 39a, the threshold value of the channel region under the charge storage film 39a increases, and the amount of current flowing between the source and drain decreases, so that it can be determined that the writing state is established. it can. In that case, the channel region under the charge storage film 39b is pinched off according to the voltage at the time of reading, whether or not electrons are present in the charge storage film 39b opposite to the written charge storage film 39a. Therefore, the amount of current between the source and drain is not affected by the charge storage film 39b. That is, two bits can be read independently from one memory cell 32 (one memory transistor).

  The data writing and reading to the charge storage film 39b are performed by reversing the voltage applied to the high-concentration impurity diffusion region 43a and the high-concentration impurity diffusion region 43b in the case of writing to and reading from the charge storage film 39a. By this, it can be realized by the same method as described above.

  Next, the data written in the charge storage film 39a or the charge storage film 39b is erased by injecting hot holes by band-to-band tunneling into the charge storage film 39a and the charge storage film 39b. Specifically, −5 [V] is applied to the gate electrode 37, 5 [V] is applied to the high concentration impurity diffusion region 43 a and the high concentration impurity diffusion region 43 b, and 0 [V] is applied to the semiconductor substrate 33. The hot holes generated in the vicinity of the high concentration impurity diffusion region 43a and the high concentration impurity diffusion region 43b are injected into the charge storage film 39a and the charge storage film 39b to neutralize the trapped electrons.

  The structure and operation of the memory cell 32 having the charge storage region on the side wall of the gate electrode 37 have been described above. As can be seen from FIG. 4, the difference between the normal transistor 31 and the memory cell 32 is that The only difference is that there is no low-concentration impurity diffusion region 42a and low-concentration impurity diffusion region 42b. Therefore, when the impurity for forming the low-concentration impurity diffusion region is implanted into the normal transistor 31, the memory cell 32 can be formed by the same process as the normal transistor 31 only by masking the memory cell 32 portion with a resist mask. It becomes possible.

  Therefore, if the breakdown voltage of the normal transistor 31 is set to a value slightly exceeding 5V, a high breakdown voltage transistor necessary for memory rewriting becomes unnecessary. However, the memory cell 32 can be formed without increasing the number of processes as compared with the case where only the normal transistor 31 is formed. Therefore, the semiconductor memory device can be formed by the normal transistor 31 and the memory cell 32, and when the logic circuit including the normal transistor 31 is mounted on the same chip as the logic circuit, the logic embedded nonvolatile memory is formed. As compared with the case where only the logic circuit composed of the normal transistor 31 is formed, the number of steps is not increased and the circuit can be formed at a low cost.

Fourth Embodiment FIG. 7 shows a normal transistor used in the first booster circuit, the memory cell selection circuit, and the second booster circuit in the semiconductor memory device of the present embodiment, and a memory cell of the memory cell array. It is sectional drawing of the state which formed the transistor provided with the charge storage area | region in the side wall of the gate electrode on the same semiconductor substrate. The first booster circuit, the memory cell selector circuit, and the second booster circuit are the same as the first booster circuit 25, the memory cell selector circuit 21, and the second booster circuit 26 in the first embodiment, and are described in detail. Description is omitted.

  Here, the difference from the case of the third embodiment is that, in the memory cell 32 in the third embodiment, the low concentration impurity diffusion region is not formed adjacent to both ends of the channel. In the memory cell in the present embodiment, the low concentration impurity diffusion region 42a is formed adjacent to only one side of the channel. The configuration other than the low-concentration impurity diffusion region 42a in the memory cell of the present embodiment is the same as that of the third embodiment, and is given the same number.

  In FIG. 7, a normal transistor 31 is shown on the left side, and a memory cell 32 is shown on the right side.

  The normal transistor 31 has a sidewall 41a comprising a gate insulating film 36, a gate electrode 37, an oxide film 38 / a charge storage film 39a / an oxide film 40 on a semiconductor substrate 33 on which an element isolation region 34 and a well 35 are formed. A side wall 41b comprising the oxide film 38 / charge storage film 39b / oxide film 40, a low concentration impurity diffusion region 42a, a low concentration impurity diffusion region 42b, a high concentration impurity diffusion region 43a, and a high concentration impurity diffusion region 43b are formed. Has been configured.

  The memory cell 32 includes a gate insulating film 36, a gate electrode 37, an oxide film 38 / a charge storage film 39a / an oxide film 40 on a semiconductor substrate 33 on which an element isolation region 34 and a well 35 are formed. A wall 41a, a side wall 41b comprising an oxide film 38 / charge storage film 39b / oxide film 40, a low concentration impurity diffusion region 42a, a high concentration impurity diffusion region 43a, and a high concentration impurity diffusion region 43b are formed. Yes.

  The gate insulating film 36 is not particularly limited as long as it is used in a normal semiconductor device. For example, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, an aluminum oxide film, a hafnium oxide film, or the like is used. Can be used. Among these, the silicon oxide film is preferable. The thickness of the gate insulating film 36 is preferably about 1 nm to 10 nm. Here, in the present embodiment, the gate insulating films of the transistor 31 and the memory cell 32 are usually the same in thickness, but may be different.

  The gate electrode 37 is not particularly limited as long as it is used in a normal semiconductor device. For example, a polysilicon film, a cobalt silicide film, a titanium silicide film, a nickel silicide film, or a composite film thereof is used. be able to. The charge storage film 39a and the charge storage film 39b are not particularly limited as long as they have a function of storing charges therein. For example, a dot-shaped charge storage region is formed in the silicon nitride film and the insulating film. The film | membrane etc. which have can be used.

  As in the present embodiment, the presence of the low concentration impurity diffusion region 42a adjacent to one side of the channel in the memory cell 32 allows the low concentration impurity on both sides of the memory cell 32 as in the third embodiment. Compared to the case where there is no diffusion region, a write operation at a low voltage is possible. This is because when the low-concentration impurity diffusion region 42 a is present adjacent to one side of the channel in the memory cell 32, the memory cell 32 has a structure in which the low-concentration impurity diffusion region is not present on both sides of the channel. This is because the voltage drop in the memory cell 32 at the time of writing can be kept low.

  Therefore, the amount of boosted voltage can be reduced, and the capacitance of the capacitance in the second booster circuit existing between the memory cell selection circuit and the memory cell array can be kept small.

  Hereinafter, a method for manufacturing the semiconductor memory device of the present embodiment will be described in detail with reference to FIGS.

  First, as shown in FIG. 5, the element isolation region 34 is formed on the semiconductor substrate 33. The element isolation region 34 is formed of, for example, a silicon oxide film, and is formed by a LOCOS (Local Oxidization of Silicon) method, an STI (Shallow Trranch Isoration) method, or the like. Thereafter, P-type wells 35 for N-type normal transistors and memory cells are formed. The P-type well 35 is formed by injecting a P-type impurity such as boron into the semiconductor substrate 33 by photolithography or ion implantation.

  Thereafter, as shown in FIG. 6, the gate insulating film 36 is formed. The gate insulating film 36 is composed of, for example, a silicon oxide film having a thickness of about 1 nm to 10 nm formed by a thermal oxidation method.

  Next, a gate electrode 37 is formed on the gate insulating film 36. The gate electrode 37 is made of, for example, a polysilicon film formed by a CVD (Chemical Vapor Deposition) method or the like. Thereafter, the resist is patterned by a photolithography method, and then etched by, for example, a RIE (Reactive Ion Etching) method or the like to form the gate electrode 37.

Next, as shown in FIG. 6, the resist 44 is patterned by photolithography, and one side is covered with the resist 44 with the gate electrode 37 of the memory cell 32 as a boundary. Thereafter, an N-type impurity such as arsenic is implanted into the semiconductor substrate 33 by ion implantation at an implantation energy of 5 keV to 30 keV and an implantation amount of 1E13 [l / cm ² ] to 1E15 [l / cm ² ]. Low concentration impurity diffusion regions 42a and 42b are formed.

  Next, as shown in FIG. 7, after removing the resist 44, an oxide film 38 is formed by, eg, thermal oxidation. Thereafter, the charge storage film 39 is formed of, eg, a silicon nitride film by, eg, CVD. Thereafter, the oxide film 40 is formed by, eg, CVD. After that, the side wall 41a and the side wall 41b are formed by etching back the laminated film composed of the oxide film 38, the charge storage film 39 and the oxide film 40 by an etch back method.

Thereafter, an N-type impurity such as arsenic is implanted into the semiconductor substrate 33 with an implantation energy of 10 keV to 50 keV and an implantation amount of about 1E14 [l / cm ² ] to 1E16 [l / cm ² ] by ion implantation or the like. Thus, the high concentration impurity diffusion region 43a and the high concentration impurity diffusion region 43b are formed. Thereafter, the transistor 31 and the memory cell 32 are normally formed through a known process such as an activation annealing process.

  Here, one of the diffusion regions formed adjacent to both ends of the channel region in the memory cell 32 overlaps the gate electrode 32, and the other does not overlap the gate electrode 32. Therefore, as in the third embodiment, writing is performed at a low voltage to the memory cell 32 in which the diffusion region formed adjacent to both ends of the channel region does not overlap the gate electrode 32. Is possible.

  Therefore, the area of the capacitance in the second booster circuit (corresponding to the capacitance C3 in the second booster circuit 26 in FIG. 1) can be reduced, and a more highly integrated semiconductor memory device can be realized. It can be done.

  As described above, according to each of the above embodiments, the high-breakdown-voltage transistor normally required for writing and erasing the nonvolatile memory becomes unnecessary, and the manufacturing process is greatly reduced. Therefore, it is possible to manufacture a logic mixed nonvolatile memory device at low cost.

  Further, as described above, by using the memory cell having the charge storage films 39a and 39b on the side walls 41a and 41b of the gate electrode 37 as the memory cell 32, the process is compared with the case where only the normal transistor 31 is manufactured. Thus, the semiconductor memory device including the first booster circuit 25 and the second booster circuit 26 can be mounted on the same chip as the logic circuit that performs arithmetic processing or the like.

  The above embodiment is merely an example, and the specific configuration and operation of the semiconductor memory device are also examples in all respects and should be considered as not restrictive. The scope of the present invention is shown not by the above-described embodiments but by the scope of claims, and includes all modifications and variations within the scope and meaning equivalent to the scope of claims.

It is a figure which shows schematic structure in the semiconductor memory device of this invention. It is a figure which shows the voltage waveform in node N3, N4 in FIG. FIG. 2 is a diagram showing a voltage waveform applied to a node N3 under the control of the memory cell selection circuit in FIG. FIG. 2 is a cross-sectional view of a state in which normal transistors and memory cell transistors used in a semiconductor memory device different from FIG. 1 are formed on the same semiconductor substrate. FIG. 5 is a cross-sectional view showing a method of forming the normal transistor and the memory cell transistor shown in FIG. 4 on the same chip. It is sectional drawing which shows the formation method following FIG. FIG. 5 is a cross-sectional view of a state in which a normal transistor and a memory cell transistor different from FIG. 4 are formed on the same semiconductor substrate. It is a figure showing a charge pump type booster circuit. It is a figure which shows the voltage waveform given to the capacitance in FIG. It is sectional drawing which shows the conventional method of forming a high voltage transistor and a normal transistor on the same chip. It is sectional drawing which shows the formation method following FIG. It is sectional drawing which shows the formation method following FIG.

Explanation of symbols

T0 to T3 ... N-type MOS transistor,
C1 to C3 ... capacitance,
21 ... Memory cell selection circuit,
22: Memory cell array,
23, 24 ... Inverter,
25. First booster circuit,
26: second booster circuit,
31 ... Normal transistor,
32 ... memory cells,
33 ... Semiconductor substrate,
34 ... element isolation region,
35 ... Well,
36. Gate insulating film,
37 ... Gate electrode,
38 ... Oxide film,
39a, 39b ... charge storage film,
40 ... oxide film,
41a, 41b ... sidewalls,
42a, 42b ... low concentration impurity diffusion regions,
43a, 43b ... high concentration impurity diffusion regions,
44. Resist.

Claims (6)

A memory cell array in which electrically rewritable memory cells are arranged in a matrix;
A first booster circuit that boosts a power supply voltage to at least a predetermined voltage that is a write voltage to the memory cell;
A memory cell selection circuit that receives an output from the first booster circuit and selects a desired memory cell that is a target of data writing, data reading, and data erasing from the memory cell array;
The memory cell selection circuit is arranged between the memory cell selection circuit and the memory cell selection circuit, and the output voltage from the memory cell selection circuit is boosted to the predetermined voltage to obtain a desired memory cell selected by the memory cell selection circuit. A semiconductor memory device comprising: a second booster circuit for supplying the semiconductor memory device. The semiconductor memory device according to claim 1,
The semiconductor memory device, wherein the second booster circuit includes an inverter and a capacitance. The semiconductor memory device according to claim 1,
The semiconductor memory device is characterized in that it is mounted on the same chip with a logic circuit having a function other than the function of performing each of a selection operation, a write operation, a read operation and an erase operation for the memory cell array. Storage device. The semiconductor memory device according to claim 1,
Each of the memory cells constituting the memory cell array is
A semiconductor substrate;
A gate insulating film formed on the semiconductor substrate;
A gate electrode formed on the gate insulating film;
A charge storage region formed on the sidewall of the gate electrode;
A channel region formed immediately below the gate insulating film in the semiconductor substrate;
A semiconductor memory device comprising: a diffusion region formed adjacent to both ends of the channel region in the semiconductor substrate. The semiconductor memory device according to claim 4.
Of the two diffusion regions formed adjacent to both ends of the channel region in the memory cell, one is formed so as to overlap the gate electrode, and the other is formed without overlapping the gate electrode. A semiconductor memory device. 2. The semiconductor memory device according to claim 1, wherein when writing into the memory cell, a pulse voltage is output as the output voltage from the memory cell selection circuit to the second booster circuit. Writing method.

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