JP2008067252A - Optical receiver, pon optical communication system, and frame synchronizing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To surely establish frame synchronization and to reduce the circuit scale of a synchronization circuit. <P>SOLUTION: In an optical receiver, the synchronization part of a burst optical signal to be transmitted through an optical transmission line is configured using an FEC frame including parity data for error correction, respectively. Capacitance for a predetermined length is stored from among data of burst optical signals received from the optical transmission line is stored by a plurality of detection buffers, respectively. Error correction decoding processing is performed on the basis of the stored data (S1), the boundary of frames of data on which error correction decoding has been successfully performed, is detected and on the basis of the boundary, frame synchronization is established (S2). Error correction decoding of data is performed using the FEC frame whose synchronization has been established (S3). Therefore, a burst optical signal including an FEC frame is received, error correction decoding processing is performed using the plurality of detection buffers, and frame synchronization is established on the basis of the data on which error correction decoding has been successfully performed, so that probability of erroneous synchronization of the FEC frame can be decreased and the circuit scale of the synchronization circuit can be reduced. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to an optical receiver, a PON optical communication system, and a frame synchronization method capable of achieving frame synchronization of burst optical signals in a PON optical communication system.

  Using the optical data communication network between the station side equipment OLT (Optical Line Terminal: optical subscriber line terminal equipment) and a plurality of home side equipment ONU (Optical Network Unit: optical subscriber line termination equipment) In particular, there is a practical single-star network configuration in which a single optical fiber is used between the station-side device OLT and each home-side device ONU. This network configuration simplifies the system and equipment configuration, but if one home-side device ONU occupies one optical fiber and there are N home-side device ONUs, it is directly connected from the station-side device OLT. N optical fibers are required, and it is difficult to reduce the cost of the system.

Therefore, a PON (Passive Optical Network) communication system in which one optical fiber drawn from the station side device OLT is shared by a plurality of home side devices ONU has been put into practical use. The PON optical communication system is one of low-cost access methods for optical subscribers that have been applied to FTTx such as FTTH (Fiber To The Home) and FTTB (Fiber To The Building).
In the PON optical communication system, one station side is passed through a passive optical branching device (optical coupler) that splits and multiplexes the signal passively from the input signal without the need for external power supply. The device OLT and a plurality of home-side devices ONU are connected by an optical transmission line. The station-side apparatus OLT and the N-station home-side apparatus ONU are based on 1-to-N transmission connected via an optical fiber SMF and an optical coupler OC. Thereby, many home side apparatuses ONU can be allocated with respect to one station side apparatus OLT, and the whole installation cost can be held down.

  In the PON optical communication system, since the optical transmission path between the station side device OLT and the optical branching unit is shared by a plurality of home side devices ONU, the direction from the home side device ONU to the station side device OLT (hereinafter referred to as the uplink direction). ), It is necessary to take measures to avoid collision of optical signals transmitted from each home-side apparatus ONU. For this reason, the station side apparatus OLT controls the optical signal transmission timing of each home side apparatus ONU by the time division access control system.

With this time-division access control method, each home-side apparatus ONU sends out an optical signal divided at a certain time from each home-side apparatus ONU. An optical signal transmitted from each home-side apparatus ONU in this way is called a “burst optical signal”.
FIG. 15 is a diagram showing a format of a conventional PON upstream burst optical signal. The frame structure of the burst optical signal transmitted from the home side apparatus ONU to the station side apparatus OLT is shown.

  Each burst optical signal has a “burst synchronization frame portion” for bit synchronization and frame synchronization at the head of the burst optical signal, followed by a “burst effective frame portion” including one or more FEC frames. . The FEC frame is a frame in which parity data for performing FEC (Forward Error Correction) is added to information to be sent.

The burst synchronization frame portion corresponds to a “burst optical signal synchronization portion” in the claims, and is composed of a preamble (repetition of 01) and a delimiter (fixed value, 0x85B3, etc.), and an FEC frame is placed after the delimiter. It is continuously transmitted to the end of the burst optical signal.
FIG. 16 is a block diagram showing a conventional PON optical communication system from the home-side device ONU to the station-side device OLT. In this optical communication, 64B / 66B codes are used. Only one home device ONU is depicted.

  The optical transmission unit of the home device ONU receives 64-bit data from the upper layer and provides it to the 64B / 66B transmission unit. The 64B / 66B transmission unit attaches a 2-bit synchronization header (SH) every 64 bits, and sends it to the FEC encoding unit. The FEC encoding unit generates preamble (repetition of bit 01) data while the burst preamble insertion control signal is “1”, and generates one delimiter when the burst preamble insertion control signal changes from “1” to “0”. Thereafter, FEC frames are continuously generated and sent to the parallel / serial converter (P / S). The parallel / serial converter converts the parallel signal into a 1-bit serial signal and supplies it to the electrical / optical converter (E / O conversion). A burst optical signal is transmitted from the electrical / optical converter (E / O converter) to the optical fiber.

The burst preamble insertion control signal is a signal for creating this burst synchronization frame portion, and takes a value of “1” for a time corresponding to the first burst synchronization frame portion of the burst optical signal to be transmitted, and is an effective frame. This signal takes a value of time “0” corresponding to the part.
The optical receiver of the station side device OLT performs optical / electrical conversion (O / E conversion) on the burst optical signal that has entered from the optical fiber, and sends it to the serial / parallel converter (S / P). The serial / parallel converter converts the serial signal into a 66-bit parallel signal and sends it to the data decoder. The data decoding unit detects the delimiter in the burst synchronization frame unit, thereafter performs error correction for each FEC frame, and sends the error-corrected data to the 64B / 66B receiving unit. The 64B / 66B receiving unit performs 64B / 66B decoding processing and transfers 64-bit data to an upper layer.

The 64B / 66B receiving unit detects the position of the delimiter from the read 66-bit signal, and establishes frame synchronization of transmission information encoded by the 64B / 66B code.
JP 2005-184674 Japanese Patent Laid-Open No. 5-160827

However, the 64B / 66B receiver cannot receive the entire burst optical signal if delimiter detection fails, such as when the bit error rate is high. This is because there is only one delimiter for each burst optical signal, so if the detection of the delimiter at the head of the burst optical signal fails, frame synchronization is lost and frame synchronization of the FEC frame cannot be performed.
In addition, if a delimiter is erroneously detected, a frame synchronization establishment state of an erroneous FEC frame may be established, and decoding of the FEC frame may fail.

  An object of the present invention is to provide an optical receiver, a PON optical communication system, and a frame synchronization method capable of reliably establishing frame synchronization.

  The optical receiver of the present invention is configured such that burst optical signals transmitted through an optical transmission line are configured using FEC frames each including error correction parity data, and received from the optical transmission line. An error correction decoding process based on data stored in a plurality of detection buffers each storing a predetermined length of capacity from the converted electrical signal data, and an electrical / optical conversion unit that converts the optical signal into an electrical signal A frame detection unit that detects a frame boundary of data that has been successfully error-correction-decoded, and establishes frame synchronization based on the boundary, and data decoding that performs error-correction decoding of data using the FEC frame that has established synchronization Part. According to this optical receiver, burst optical signals including FEC frames are received, error correction decoding processing is performed using a plurality of detection buffers, and frame synchronization is established based on the error correction decoding success. Thus, the probability of FEC frame mis-synchronization can be reduced. In addition, the circuit scale of the synchronization circuit can be reduced.

The plurality of detection buffers preferably store each data with a shift of 1 bit.
The FEC frame includes an FEC frame in which parity data for error correction has a fixed value, and the frame detection buffer stores a capacity of the parity data, and the frame detection unit May be configured to detect frame boundaries and establish frame synchronization by executing error correction decoding on the error correction parity data. In this configuration, the length of the parity data is naturally smaller than the length of one FEC frame, and FEC frame synchronization is established with fixed-value parity data. Therefore, synchronization can be established more quickly, and the buffer capacity can be reduced. it can.

  The FEC frame includes an FEC frame in which a synchronization header has a fixed value, and the frame detection buffer stores a capacity of the synchronization header, and the frame detection unit A frame boundary may be established by detecting a header and executing error correction decoding processing to detect frame boundaries. Even in this configuration, the length of the synchronization header is naturally smaller than the length of one FEC frame, and the FEC frame synchronization is established by a fixed synchronization header, so that synchronization can be established more quickly and the buffer capacity can be reduced. be able to.

  In another optical receiver of the present invention, a burst optical signal transmitted through an optical transmission line is configured using an FEC frame, and the FEC frame includes a plurality of delimiters that are fixed values in an information field. Including an electro-optic converter that converts a burst optical signal received from the optical transmission path into an electrical signal, a delimiter boundary included in the converted electrical signal data, and the detected delimiter boundary and the boundary Data that has been successfully error-corrected decoded by performing error-correcting decoding processing based on data of the length of the information field starting from each position shifted by an integer multiple of the number of bits corresponding to the length of 1 delimiter from The frame detection unit detects the boundary of the information field based on the boundary, establishes the frame synchronization based on the boundary, and erroneously uses the FEC frame with the synchronization. A data decoder for correcting decoder in the receiver equipped with. In this configuration, since FEC frame synchronization is established by a fixed value delimiter included in the FEC frame, many bit errors occur on the medium, and even when the optical receiver fails to detect the delimiter once, Frame synchronization can be achieved by subsequent delimiters, and the probability that the entire burst optical signal cannot be received can be reduced. Further, the capacity of the buffer can be further reduced, and synchronization can be established in a short time.

  The delimiter is composed of a plurality of sub-delimiters, and the frame detection unit detects a boundary of the sub-delimiter, and detects the boundary of the sub-delimiter and each position shifted from the boundary by an integer multiple of the number of bits corresponding to one sub-delimiter. The boundary of the delimiter may be detected by performing error correction decoding processing based on the data for one delimiter to be started. In order to achieve frame synchronization, first, the boundary of the sub delimiter is detected. Then, by performing two-stage detection of detecting the delimiter, the number of bits of the sub-delimiter is naturally smaller than the number of bits of the delimiter, so that the circuit of the burst optical signal receiving unit can be simplified and the sub-delimiter The boundary detection time is shortened. Therefore, frame synchronization can be established in a shorter time than before, and the efficiency of burst optical signal transmission is improved. In addition, the circuit configuration of the burst optical signal receiver on the receiving side can be simplified.

  In the PON optical communication system of the present invention, the optical transmitter converts an electric signal into an optical signal and an FEC encoding unit that inserts an FEC frame including parity data for error correction into data to be transmitted. A photoelectric conversion unit for sending the optical signal to the optical transmission line, and the optical receiver converts the optical signal received from the optical transmission line into an electric signal, and error correction is performed on the converted electric signal. Performs the decoding process, detects the boundary of the frame that has succeeded in error correction decoding, establishes frame synchronization based on the detected boundary of the frame, and performs error correction decoding of the data using the synchronized FEC And a data decoding unit. The optical transmitter of this PON optical communication system can transmit burst optical signals composed of FEC frames, each containing error correction parity data. The optical receiver is the same as described above. Thus, it is possible to reduce the probability of failing to receive the entire burst optical signal, reduce the probability of erroneous synchronization of the FEC frame, and reduce the circuit scale of the synchronization circuit.

  Also, the frame synchronization method of the present invention converts a burst optical signal including an FEC frame including parity data for error correction received from an optical transmission path into an electrical signal, and an error is detected with respect to the converted electrical signal. Performs corrective decoding processing, detects the boundary of a frame that has been successfully error-corrected, establishes frame synchronization based on the detected frame boundary, and performs error-correction decoding of data using the FEC frame that has established frame synchronization Is the method. This frame synchronization method is a frame synchronization method performed using substantially the same configuration as the optical receiver.

  As described above, according to the present invention, frame synchronization can be reliably established and the circuit scale of the synchronization circuit can be reduced.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
FIG. 1 is a schematic diagram illustrating a configuration example of a PON optical communication system.
In the PON optical communication system, a station side device OLT provided in a station building and a home side device ONU provided in a plurality of subscribers are connected via an optical fiber SMF and an optical coupler OC.
The home-side apparatus ONU includes a network interface for connecting a terminal that enjoys optical network services, such as a personal computer installed in a subscriber's home.

The optical coupler OC is composed of a star coupler that passively branches and multiplexes a signal from an input signal without requiring an external power supply.
The optical fiber connected to the station side device OLT, the optical coupler OC, the optical coupler OC, and the home side device ONU is a single mode fiber composed of one optical fiber SMF. That is, one station side device OLT is connected to one optical coupler OC through one trunk optical fiber SMF. One optical coupler OC is connected to M second optical couplers OC (M is a number of 4 in this example) by an optical fiber SMF. The second optical coupler OC is connected to N units (N is a number of 8 or less in this example) of home-side devices ONU by branch optical fibers SMF. Therefore, a signal transmitted / received by one station-side device OLT is distributed to a maximum of 32 home-side devices ONU by 1 + M optical couplers OC. Note that the numbers of the optical couplers OC and the home-side devices ONU are merely examples.

The communication system of the present invention incorporates 10 Gigabit Ethernet (Ethernet is a registered trademark) technology into the PON optical communication system, and enables optical fiber access section communication at a baseband speed of 10.3125 Gbps. The 10GE-PON (Gigabit Ethernet-Passive Optical Network) method is used.
According to the 10GE-PON system, communication between the station side device OLT and the home side device ONU is performed in units of variable length frames. The frame structure is composed of a GE-PON header including a logical link identifier and data of 64 bytes or more. The maximum size of data is generally about 1530 bytes.

  First, a downlink frame that enters the station side apparatus OLT from the higher level network is subjected to a predetermined bridge process in the station side apparatus OLT, and a logical link to be relayed is specified. Then, it is transmitted to the optical fiber SMF as an optical signal through the station side device OLT. At this time, the station side device OLT adds a GE-PON header including a logical link identifier to the frame. The optical signal transmitted to the optical fiber SMF is branched by the optical coupler OC and transmitted to the home-side device ONU connected to the optical coupler OC. Only the home-side device ONU constituting the logical link receives a predetermined optical signal. Capture and relay frame to home network interface.

  On the other hand, the upstream optical signal includes an upstream frame from each home-side apparatus ONU. The upstream optical signal needs to be transmitted so that the optical signals from the respective home devices ONU do not compete with each other in time. For this purpose, the station side device OLT allocates a window (hereinafter simply referred to as a window) during which an upstream optical signal may be transmitted to each home side device ONU, and notifies it as a control frame. The home apparatus ONU to which the window is assigned transmits an upstream optical signal to the assigned window. This upstream optical signal is referred to as a “burst optical signal”. The burst optical signal is a finite-time optical signal sequence which is transmitted from each home-side apparatus ONU and whose light emission state is changed by a 10.3125 Gbps baseband signal.

Therefore, the competition of the upstream optical signal between each home-side apparatus ONU is avoided. Each home-side apparatus ONU, when given a certain window, may transmit frames continuously as long as it fits in that window.
The station apparatus OLT can receive a burst optical signal including a series of frame signals from each home apparatus ONU.

Note that the optical signal waveform and optical signal intensity received by the station side device OLT differ depending on the characteristics of the optical transmission line such as the characteristics of the light emitting element of the home side device ONU and the length of the optical fiber SMF. Therefore, the station side device OLT performs a predetermined process on the upstream burst optical signal, and then transmits the restored significant frame sequence to the upper network.
FIG. 2 is a diagram showing a format of a PON upstream burst optical signal. The burst optical signal is composed of a burst effective frame portion and a burst synchronization frame portion. The burst effective frame portion is composed of an FEC frame in which parity data for FEC is added to information to be sent. The burst synchronization frame portion also uses an FEC frame in which FEC is added to information to be sent, but is different from the FEC frame of the burst effective frame portion in that it is also used for frame synchronization. Therefore, FEC frames are continuously transmitted from the beginning of the burst optical signal to the end of the burst optical signal.

FIG. 3 is a block diagram showing a simplified configuration of the PON optical communication system using the 64B / 66B code from the home side apparatus ONU of the present invention to the station side apparatus OLT. Only one home device ONU is depicted.
The optical transmission unit of the home-side apparatus ONU includes a 64B / 66B transmission unit 2 that receives a burst optical signal in 64-bit units from an upper layer. The 64B / 66B transmission unit 2 attaches a 2-bit synchronization header (SH) to each 64-bit unit data constituting the burst optical signal, converts the data into 66 bits, and sends the converted data to the FEC encoding unit 3. The FEC encoding unit 3 continuously generates FEC frames based on the 66-bit data and sends them to the parallel / serial conversion unit 4 (P / S). In the parallel / serial conversion unit 4, the parallel data of a plurality of bits is converted into a serial signal of 1 bit, and the converted serial signal is converted into an optical signal in the electrical / optical conversion unit 5 (E / O conversion). , Sent to the optical fiber.

  The optical receiving unit (corresponding to the receiver of the present invention) of the station side device OLT converts the burst optical signal that has entered from the optical fiber into an electric signal by the optical / electric converting unit 6 (O / E conversion), and serial・ Send to parallel converter 7 (S / P). The serial / parallel converter 7 converts the serial signal into a 66-bit parallel signal and sends it to the data decoder 8. The data decoding unit 8 detects the FEC frame in the burst synchronization frame unit and establishes synchronization. After synchronization, error correction processing is performed for each FEC frame to read the data and send it to the 64B / 66B receiver 9. The 64B / 66B receiving unit 9 performs 64B / 66B decoding processing and transfers 64-bit data to an upper layer.

FIG. 4 is a detailed internal block diagram of the data decoding unit 8 of the optical receiving unit of the station side apparatus OLT.
The data decoding unit 8 includes an input data holding unit 81, a frame detection unit 82, and a data decoding unit 83.
The input data holding unit 81 is composed of a memory that temporarily stores a 66-bit parallel signal input from the serial / parallel conversion unit 7.

The frame detection unit 82 includes a plurality of data detection buffers for accumulating data having the number of bits (M bits) corresponding to the data detection range. The number of data detection buffers is N. These N data detection buffers are denoted by 0 to (N−1).
A specific example of the number of bits M corresponding to the data detection range and the number N of data detection buffers will be described later.

  The data decoding unit 83 performs decoding on the input data divided at the synchronized positions while performing error correction, and reads information. Here, "error correction decoding" is generated on the transmission path included in the information of the FEC frame using the FEC frame information received by the receiver and the value of the parity data and calculating based on an error correction algorithm such as Reed-Solomon. This is a process for correcting a bit error.

  FIG. 5 shows the structure of one FEC frame included in the burst synchronization frame portion. The FEC encoder 3 of the optical transmitter of the home device ONU writes the data sent from the 64B / 66B transmitter 2 in the information field, adds parity data for error correction, and transmits these as FEC frames. To do. The data entered in this information field is data (content) to be transmitted and is not fixed content. Therefore, the parity code is not fixed. The data decoding unit 8 of the optical receiving unit of the station side apparatus OLT that has received the FEC frame obtains frame synchronization by performing error correction decoding of the FEC frame, and reads the data in the synchronized information field.

FIG. 6 is a flowchart showing FEC frame synchronization processing in the data decoding unit 8. If it demonstrates also also referring FIG. 4, the flow of the signal in the data decoding part 8 will be as follows.
The 66-bit data input from the serial / parallel converter 7 is held in the input data holding unit 81 of the data decoding unit 8. The 66-bit data stored in the input data holding unit 81 has data of the number of bits (M bits) corresponding to the data detection range from the head (not necessarily the head of the FEC frame; described later). The same number of data accumulated in the data detection buffer 0 of the frame detection unit 82, shifted from the data detection range by 1 bit, is accumulated in the data detection buffer 1, and the same number of data shifted further from the data detection range is stored in the data detection buffer i. The data shifted by 1 bit is stored in a total of N data detection buffers.

  Note that there is no guarantee that the head of the FEC data is located at a fixed position of the 66-bit data stored in the input data holding unit 81. This is because the position of the FEC frame changes arbitrarily for each burst optical signal. Therefore, the top of the 66-bit data stored in the input data holding unit 81 is not necessarily the top of the FEC frame (thus, synchronization is necessary).

The number of bits M corresponding to the data detection range is the number of bits of one FEC frame, that is, the sum of the number of bits of the information frame and the parity. The number N of data detection buffers is equal to M because M bits are detected by shifting one bit at a time.
Among the data stored in each data detection buffer, there is always data that matches the information + parity pattern. The frame detection unit 82 performs error correction decoding on the data stored in each data detection buffer shifted by one bit from the head using parity data (step S1).

  The frame detection unit 82 performs error correction decoding using information + parity, identifies the boundary of data that has been error correction decoded, and notifies the data decoding unit 83 to establish FEC frame synchronization (step S2). For example, if the data stored in the data detection buffer i in FIG. 4 is data that has been successfully error-correction decoded, the position shifted by i bits from the head is the boundary of the FEC frame. There are three types of error correction decoding results: (a) no error, (b) correctable error, and (c) uncorrectable error. “Decoding succeeds” means (a) and This is the case in (b).

If synchronization is established, the data decoding unit 83 decodes data having a length of 1 FEC frame from the boundary and reads the data (step S3).
If the next 66-bit parallel signal is input to the input data holding unit 81, the input data holding unit 81 updates the accumulated data to the next 66-bit parallel signal. Since the frame synchronization is established, the data decoding unit 83 can read the 1 FEC frame portion of the data in the input data holding unit 81 and perform error correction decoding. Such a procedure can be repeated until reception of one burst optical signal is completed.

FIG. 7 shows an FEC frame when the FEC information field is fixed data and the FEC parity data is also fixed data.
In this example, since the data in the information field is fixed data, the parity data is also fixed. It is assumed that the fixed information field data and parity data are recognized in common between the home-side apparatus ONU and the station-side apparatus OLT. Accordingly, since the parity data can be specified, the parity data is detected, the error correction decoding process is executed based on the position of the parity data, and the frame position can be known and synchronized by succeeding in the decoding.

The 66-bit data input from the serial / parallel converter 7 is stored in a total of N data detection buffers with a shift of 1 bit from the beginning, but in this example, The number of bits M corresponding to the data detection range may be the number of bits of the parity frame. Since the number N of data detection buffers is detected by shifting one bit at a time, it is equal to M.
FIG. 8 is a synchronization flowchart of the FEC frame when the FEC frame shown in FIG. 7 is received by the optical receiver of the burst optical signal.

The frame detection unit 82 searches for parity data, which is fixed data, shifted by one bit from the beginning (step T1). Among the data stored in each data detection buffer, there is always data that matches the parity pattern. It is also possible to allow several bits of error as a matching condition.
If parity data is detected, the parity data is considered as parity data of the FEC frame, and FEC error correction decoding processing is executed (step T2). If the error correction decoding is successful, FEC frame synchronization is established (step T3). Thereafter, FEC frame error correction decoding processing can be performed for each FEC frame length delimited by the boundary where synchronization is established (step T4).

It is also possible to reduce the 66B synchronization header 2 bits to 1 bit and insert a fixed-length synchronization header at the beginning of the FEC frame as shown in FIG.
In this case, the FEC frame synchronization process can be performed using the periodically repeated FEC frame synchronization header.
FIG. 9 shows an FEC frame in which a synchronization header is added to the head of the information field of the FEC to obtain fixed data.

FIG. 10 is a synchronization flowchart of the FEC frame when the FEC frame shown in FIG. 9 is received by the optical receiver of the burst optical signal.
The 66-bit data input from the serial / parallel converter 7 is stored in a total of N data detection buffers with a shift of 1 bit from the beginning, as in the flow of FIG.

  In this example, the synchronization header is fixed. It is assumed that the fixed synchronization header data is recognized in common between the home apparatus ONU and the station apparatus OLT. Therefore, since the synchronization header can be specified, by detecting the synchronization header and executing error correction decoding based on the position of the synchronization header, the frame position can be known and frame synchronization can be achieved. Therefore, the bit number M corresponding to the data detection range may be the bit number of the synchronization header.

The frame detection unit 82 searches for a synchronization header that is fixed data by shifting by one bit from the beginning (step V1). Among the data stored in each data detection buffer, there is always data that matches the pattern of the synchronization header. It is also possible to allow several bits of error as a matching condition.
If a synchronization header is detected, the synchronization header is considered as a synchronization header of the FEC frame, and FEC error correction decoding processing is executed (step V2). If the error correction decoding is successful, FEC frame synchronization is established (step V3). Thereafter, error correction decoding processing of the FEC frame is performed for each FEC frame length delimited by the boundary where the synchronization is established (step V4).

Next, another embodiment of the present invention will be described.
FIG. 11 shows an FEC frame in the case where the fixed data in the information field of the FEC frame in the burst synchronization frame portion is composed of a plurality of delimiters and a synchronization header. Each delimiter is fixed data having the same length. Therefore, the information field of FEC is also fixed data, and the parity data of FEC is also fixed.

The length of the delimiter is 64 bits in this example, but is not limited to this. A 2-bit synchronization header (SH) is added to the delimiter. The sum of delimiters and synchronization bits (66 bits) corresponds to one block.
The number of delimiters to be inserted is a value obtained by subtracting the length of the parity data from the length of the FEC frame and dividing by the total number of bits of the delimiter and the synchronization bits.

The “0” and “1” patterns constituting the delimiter are predetermined, and the delimiter pattern information is commonly recognized between the home side apparatus ONU and the station side apparatus OLT.
FIG. 12 is a detailed internal block diagram of the data decoding unit 8 for processing this FEC frame.

The data decoding unit 8 includes an input data holding unit 81, a delimiter detection unit 84, a data distribution unit 85, a frame detection unit 86, and a data decoding unit 83.
The input data holding unit 81 is composed of a memory that temporarily stores a 66-bit parallel signal input from the serial / parallel conversion unit 7.
The delimiter detection unit 84 includes a plurality of delimiter detection buffers for storing data of the total number of delimiters and synchronization bits (66 bits). The number of delimiter detection buffers is the same number (66) because the total number of delimiters and synchronization bits is detected by shifting one bit at a time.

The frame detection unit 86 includes a number (n) of frame detection buffers corresponding to the number of delimiters. The storage capacity of each frame detection buffer is one information field.
FIG. 13 is a flowchart illustrating a procedure for synchronizing the FEC frame when the FEC frame illustrated in FIG. 11 is received by the optical receiver.
The 66-bit data input from the serial / parallel converter 7 is held in the input data holding unit 81. From the beginning of the data stored in the input data holding unit 81, data of the number of bits (66 bits) corresponding to the delimiter detection range is accumulated in the delimiter detection buffer 0 of the delimiter detection unit 84, and the delimiter detection range is set to 1. The same number of data shifted by bits is accumulated in the delimiter detection buffer 1, the same number of data shifted by one bit from the delimiter detection range is accumulated in the delimiter detection buffer, and a total of 66 pieces of data shifted by one bit are stored. Stored in the delimiter detection buffer.

The delimiter detection unit 84 determines whether or not the data held in the delimiter detection buffer matches the pattern of the sync header (2 bits) + delimiter (64 bits) (66-bit match comparison). It is also possible to allow several bits of error as a matching condition.
If they match, the data boundary is specified and notified to the data distributor 85 (step S2).

When receiving the notification of the delimiter boundary information from the delimiter detection unit 84, the data distribution unit 85 is an integer multiple (2) of the delimiter boundary and the number of bits of the synchronization header (2 bits) + delimiter (64 bits) from the boundary. The data of the input data holding unit 81 is divided and rearranged at the position of (times, 3 times...), And each is transferred to the frame detection unit 86.
The frame detection unit 86 distributes the divided data to each frame detection buffer. That is, of the data stored in the input data holding unit 81, one information field is distributed to the frame detection buffer 0 from the data boundary. Further, the data distribution unit 85 shifts the range by the number of bits of the synchronization header (2 bits) + delimiter (64 bits) and distributes the range to the next frame detection buffer. Such distribution is performed for all the frame detection buffers. As described above, the number of frame detection buffers is equal to the number n of delimiters in one information field.

  The frame detection unit 86 performs error correction decoding processing assuming that the head part of the data stored in each frame detection buffer is the data part of the FEC frame and the rest is the parity part of the FEC frame. The head position of the data stored in the frame detection buffer that has been successfully subjected to error correction decoding is specified as the boundary of the FEC frame, and FEC frame synchronization is established (step U4). Then, the boundary information is notified to the data decoding unit 83 (step U3).

The data decoding unit 83 performs decoding and reads information while performing error correction by dividing the input data at a synchronized position (step U5).
It is possible to detect parity data using the procedure shown in FIG. 8 in such a frame of FIG. 11, but the reason for detecting the delimiter without detecting the parity data is that the parity data of FEC is This is because it may be longer than the delimiter. In this case, it is possible to reduce the number of bits to be detected and to further increase the circuit scale of the FEC frame synchronization circuit by detecting a short delimiter and then detecting an information field, rather than detecting long parity data. It can be made smaller.

Further, as shown in FIG. 14, by configuring the delimiter with a plurality of sub delimiters, the circuit scale for detecting the delimiter can be further reduced.
Each sub delimiter is fixed data, and therefore the delimiter and the information field are also fixed data.
In this case, three stages of detection are performed: a sub delimiter, a delimiter, and an information field. The following description will be made assuming that the number of bits of the sub delimiter is 16.

In addition to the input data holding unit 81, the delimiter detecting unit 84, the data distributing unit 85, the frame detecting unit 86, and the data decoding unit 83 shown in FIG. 12, the data decoding unit 8 is a sub delimiter having a bit capacity of the number of sub delimiters. A sub-delimiter detector (not shown) having a detection buffer is provided.
The data stored in the input data holding unit 81 is stored in the sub-delimiter detection buffer from the head of the number of bits corresponding to the sub-delimiter detection range (for example, 16), and the same number of data obtained by shifting the sub-delimiter detection range by 1 bit. Is stored in the next sub-delimiter detection buffer, the same number of data with the sub-delimiter detection range further shifted by 1 bit is stored in the sub-delimiter detection buffer, and the data shifted by 1 bit is stored in a total of 16 sub-delimiter detection buffers Is done.

The sub-delimiter detection unit may store the converted electric signal data in each sub-delimiter detection buffer while shifting the data one bit at a time, and detect the boundary of the sub-delimiter by comparing each stored data pattern with the sub-delimiter pattern. it can.
When the delimiter boundary is detected, the delimiter detection unit 84 stores the delimiter boundary in the delimiter detection buffer at each sub delimiter boundary and a position that is an integer multiple of the number of bits of the sub delimiter (16 bits) from the boundary, and restores each. . Among the data stored in these delimiter detection buffers, the position of one delimiter is specified based on the data that has been successfully restored.

  If the position of the delimiter is determined, the subsequent processing is the same as described with reference to FIGS. That is, the frame detection unit 86 distributes the divided data to each frame detection buffer, distributes one information field of the data stored in the input data holding unit 81 to the frame detection buffer 0, and The number of bits of the synchronous header (2 bits) + delimiter (64 bits) is shifted and distributed to the next frame detection buffer, and such distribution is performed for all the frame detection buffers.

The frame detection unit 86 performs error correction decoding processing assuming that the head part of the data stored in each frame detection buffer is the data part of the FEC frame and the rest is the parity part of the FEC frame. The head of the data stored in the frame detection buffer that has succeeded in error correction decoding is identified as the boundary of the FEC frame, and FEC frame synchronization is established.
By performing three-stage synchronization detection including detection of such a sub-delimiter, the circuit scale of the FEC frame synchronization circuit can be further reduced.

By the way, the information to be transmitted in one burst may not be an integral multiple of the information field of the FEC frame. If the information field length of the last FEC frame in the burst is made variable, all information can be sent in one burst.
For this purpose, as shown in FIG. 17, a block number field for designating the number of 64B / 66B blocks included in the information field of the FEC frame may be provided at the head of the FEC frame.

  It is also effective to provide a parity valid flag at the beginning of the FEC frame to indicate that the parity data of the FEC frame is invalid in order to omit the FEC parity data calculation circuit of the transmitter. (See FIG. 17). In this case, if the parity data is invalid, the data decoding unit 8 of the optical receiving unit can send the value of the information field itself to the 64B / 66B receiving unit without executing the error correction decoding process using the parity data. it can.

Further, a CRC (Cyclic Redundancy Check) may be provided after the block number field and the parity valid flag (see FIG. 17). By this CRC, the data decoding unit 8 can perform error detection and error correction of the block number field and the parity valid flag itself.
As yet another example, the optical transmission unit of the home-side apparatus ONU may have a configuration in which a delimiter (delimiter for unlock) is inserted at the end of the frame of the burst optical signal to release / release block synchronization. It is valid. The optical transmission unit immediately extinguishes the optical signal intensity after transmitting the delimiter for leaving synchronization. The end of burst is clearly indicated by the delimiter for leaving synchronization.

  When the optical receiver of the station side device OLT detects the delimiter for leaving synchronization, it unlocks the synchronization established so far. After the detection of the delimiter, it is desirable that the optical receiving unit also cancels the bit error rate (BER) measurement performed after the synchronization is established. This is because even if the bit error rate is measured thereafter, the light intensity becomes weak and a large amount of errors may be measured.

  Although the embodiments of the present invention have been described above, the embodiments of the present invention are not limited to the above-described embodiments, and various modifications can be made within the scope of the present invention.

It is the schematic which shows the structural example of the PON optical communication system which connected between the control station apparatus OLT and several terminal device ONU with the optical fiber via the optical coupler. It is a frame configuration diagram of a burst optical signal transmitted from the home side apparatus ONU to the station side apparatus OLT. It is the block diagram showing the structure of the PON optical communication system from the home side apparatus ONU to the station side apparatus OLT. It is a detailed internal block diagram which shows the data decoding part of the optical receiving part of the station side apparatus OLT. It is a figure which shows the structure of one FEC frame contained in a burst synchronous frame part. It is a flowchart which shows the synchronization process of the FEC frame in a data decoding part. It is a figure which shows an FEC frame in case the parity data of FEC also becomes fixed data by making the information field of FEC into fixed data. FIG. 8 is a synchronization flowchart of the FEC frame when the FEC frame shown in FIG. 7 is received by the optical receiving unit of the burst optical signal. It is a figure which shows the FEC frame which added the synchronous header to the head of the information field of FEC, and was used as fixed data. FIG. 10 is a synchronization flowchart of the FEC frame when the FEC frame shown in FIG. 9 is received by the optical receiver of the burst optical signal. FIG. It is a figure which shows the FEC frame at the time of comprising the fixed data of the information field of the FEC frame of a burst synchronous frame part with several delimiters and a synchronous header. It is a detailed internal block diagram of the data decoding part for processing the FEC frame comprised including the delimiter. 12 is a flowchart showing a procedure for synchronizing the FEC frame when the FEC frame shown in FIG. 11 is received by the optical receiver. It is a figure which shows a FEC frame at the time of comprising a delimiter with a some sub delimiter. It is a frame block diagram of the burst optical signal transmitted from the conventional PON home-side apparatus ONU to the station-side apparatus OLT. It is a block diagram showing the PON optical communication system from the conventional home side apparatus ONU to the station side apparatus OLT. It is a frame configuration diagram in which a block number field for designating the number of 64B / 66B blocks included in the information field is installed at the head of the FEC frame.

Explanation of symbols

2 64B / 66B transmission unit 3 FEC encoding unit 4 parallel / serial conversion unit 5 electrical / optical conversion unit 6 optical / electrical conversion unit 7 serial / parallel conversion unit 8 data decoding unit 81 input data holding unit 82 frame detection unit 83 data decoding 84 Delimiter detector 85 Data distributor 86 Frame detector 9 64B / 66B receiver

Claims (8)

An optical receiver installed in a PON optical communication system for transmitting an optical signal,
The synchronization part of the burst optical signal transmitted through the optical transmission path is configured using FEC frames each including error correction parity data,
An electro-optic converter that converts the burst optical signal received from the optical transmission path into an electrical signal;
The error correction decoding process is performed based on the data stored in the plurality of detection buffers respectively storing the capacity of the predetermined length from the converted electric signal data, and the frame of the data that has been successfully error correction decoded. A frame detector that detects a boundary and establishes frame synchronization based on the boundary;
An optical receiver comprising: a data decoding unit configured to perform error correction decoding on data using an FEC frame in which synchronization is established.   The optical receiver according to claim 1, wherein the plurality of detection buffers store each data with a shift of 1 bit. The FEC frame includes an FEC frame in which parity data for error correction is a fixed value,
Each of the frame detection buffers stores a capacity of the parity data,
2. The optical receiver according to claim 1, wherein the frame detection unit detects the error correction parity data, executes error correction decoding, detects a frame boundary, and establishes frame synchronization. 3. The FEC frame includes an FEC frame whose synchronization header is a fixed value,
Each of the frame detection buffers stores a capacity of the synchronization header,
The optical receiver according to claim 1, wherein the frame detection unit detects a frame boundary by detecting the synchronization header and executing error correction decoding to establish frame synchronization. An optical receiver installed in a PON optical communication system for transmitting an optical signal,
The synchronization part of the burst optical signal transmitted through the optical transmission line is configured using the FEC frame,
The FEC frame includes a plurality of delimiters that are fixed values in an information field;
An electro-optic converter that converts the burst optical signal received from the optical transmission path into an electrical signal;
Detects delimiter boundaries included in the converted electrical signal data, and starts from the detected delimiter boundaries and each position shifted from that boundary by an integer multiple of the number of bits corresponding to the length of one delimiter. Frame that performs error correction decoding processing based on the length of data corresponding to the information field, detects the boundary of the information field based on the data that has been successfully error correction decoded, and establishes frame synchronization based on the boundary A detection unit;
An optical receiver comprising: a data decoding unit configured to perform error correction decoding on data using an FEC frame in which synchronization is established. The delimiter is composed of a plurality of sub delimiters,
The frame detection unit detects the boundary of the sub-delimiter, and based on the detected sub-delimiter boundary and data for the delimiter starting from each position shifted from the boundary by an integer multiple of the number of bits corresponding to one sub-delimiter. The optical receiver according to claim 5, wherein the delimiter boundary is detected by performing error correction decoding processing. A PON optical communication system for transmitting optical signals,
An optical transmitter includes an FEC encoding unit that inserts an FEC frame including parity data for error correction with respect to data to be transmitted, and a photoelectric unit that converts an electrical signal into an optical signal and sends it to an optical transmission line. A conversion unit,
The optical receiver converts an optical signal received from the optical transmission path into an electrical signal, and performs error correction decoding processing on the converted electrical signal to determine the boundary of the frame that has been successfully error corrected. A frame detector that detects and establishes frame synchronization based on detected frame boundaries;
A PON optical communication system comprising: a data decoding unit that performs error correction decoding of data using an FEC frame that has established synchronization. A frame synchronization method executed in a PON optical communication system for transmitting an optical signal,
A burst optical signal including an FEC frame including parity data for error correction received from an optical transmission path is converted into an electrical signal,
An error correction decoding process is performed on the converted electrical signal,
Detects the boundary of a frame that has been successfully error-correction decoded,
Establish frame synchronization based on detected frame boundaries,
A frame synchronization method for performing error correction decoding on data using an FEC frame in which frame synchronization is established.

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