JP2008059743A - Flash memory device having multi-page copyback functionality and related block replacement method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a multi-page copyback program executing method in a nonvolatile memory device. <P>SOLUTION: The nonvolatile memory device includes a memory having a plurality of memory blocks. In response to a generated multi-page copyback program command, the page of data of the memory block having a first address is replaced. It is determined whether the first address of the page of data is the same as the stored address of the page at which an error is detected. When it is determined that the first address is not the same as the stored address, the first address is incremented. The pages of data are replaced, addresses are compared, also the addresses are incremented until it is determined that the incremented address is the same as the stored address. A device and a system relating thereto are provided. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to integrated circuit memory devices, and more particularly, to non-volatile memory devices and methods.

  Generally, semiconductor memory devices for storing data are classified into volatile memory devices and nonvolatile memory devices. Volatile memory devices lose their stored data if power supply is interrupted. On the other hand, the nonvolatile memory device maintains the stored data even when the power supply is interrupted. Therefore, the nonvolatile memory device is widely used for products and the like in which power supply may be interrupted.

Nonvolatile memory devices typically include read only memory (EEPROM, commonly referred to as “flash EEPROM devices”) that can be electrically erased and programmed. Generally, a flash EEPROM device includes a first conductive type (eg, P type) semiconductor substrate, a second conductive type (eg, N type) source and drain regions that are spaced apart from each other, and between the source and drain regions. A channel region formed on the substrate, a floating gate for storing charge carriers when the device is programmed, and a control gate positioned on and above the floating gate to face the channel region. . A typical flash EEPROM integrated circuit memory device includes a column-by-column array of NAND EEPROM cells. Non-patent document 1 and non-patent document 2 describe general structures such as the array.
A schematic view and a cross-sectional view of an array having NAND EEPROM cells are disclosed in detail in Patent Document 1 by Suh et al.

  The operation of the flash memory device is generally divided into three modes, that is, a program operation, an erase operation, and a read operation. The program operation of the flash EEPROM device biases the drain region with respect to the source region with a first positive voltage, and biases the control gate with a second positive voltage higher than the first positive voltage. When no charge is stored on the control gate, an inversion layer channel of electrons and the like is formed on the substrate between the source region and the drain region by such a voltage. As widely known, a drain-to-source voltage accelerates these electrons through the channel to the drain region. Since electrons in the drain region have a sufficiently large kinetic energy, they are generally referred to as hot electrons. A high positive voltage is applied by the control gate to form an electric field in a tunneling oxide layer that separates the floating gate from the channel region. The electric field attracts thermoelectrons and accelerates the thermoelectrons toward the floating gate positioned between the control gate and the channel region by a tunneling process. Thereafter, the floating gate accumulates and captures charges. The process of charging the floating gate is a self-limiting process. The charge stored on the floating gate reduces the length of the electric field in the tunnel oxide until the moment when the thermal electrons from the drain side of the channel region cannot be accelerated any further.

  As widely known, a large amount of trapped charges (electrons, etc.) are stored on the floating gate, thereby causing an effective threshold voltage (effective voltage) of the field effect transistor including the source region, the drain region, the channel region, and the control gate. (threshold voltage: Vth) increases. When the effective threshold voltage is sufficiently increased, when a predetermined read voltage is applied to the control gate during a read operation (ie, Vth> Vread), the field effect transistor is in a non-conductive “off” state ( nonconductive “off” state) is maintained. In this state (programmed state), the EEPROM device is referred to as storing a logical value “0”. Once programmed, the EEPROM device maintains a high threshold voltage even when the power is shut off or turned off for an extended period of time.

  The erase operation of the flash EEPROM device is performed by removing the stored charge from the floating gate. For example, the erase process can be performed by grounding the control gate and applying a positive voltage (eg, 10-20 volts) to the substrate. Therefore, the flash EEPROM device requires bulk erase in many parts of the cell array. This is because the effect of applying a high substrate voltage is generally not limited to a single EEPROM cell.

  A read operation of a flash EEPROM device is generally performed by applying a predetermined read voltage Vread to a control gate through a word line that connects pages of the same EEPROM device or cell, that is, a bit line that connects columns of the same EEPROM cell. Through a positive voltage applied to the drain region. When the EEPROM device is programmed, the EEPROM device does not conduct drain current (Ids) and the bit line is maintained at a positive voltage. However, if the EEPROM device is not programmed or erased, it will cause the bit line to conduct sufficiently and drop to ground voltage GND. In this state, the EEPROM device is referred to as storing a logical value “1”. Therefore, the programmed state of the EEPROM device can be determined by monitoring the bit line voltage and current.

  Page copy operation for copying the data read from the first page of the memory cell at the first address during the read operation to the second page of the memory cell at the second address different from the first address. is required. A typical page copy operation includes reading data from the first page of memory cells in the array to a page buffer and then to a storage device external to the page buffer. Data in the storage device is restored to the page buffer, and the restored data is programmed into the second page of the memory cell using a normal program operation. However, normal page copy operations require an external storage device. In general, such an external storage device requires a long time because it must be loaded serially from the page buffer and downloaded serially to the page buffer.

  In order to solve the above problems, various page copy operations have been studied. For example, according to one conventional method, the first page data is read in a page buffer in which the inverted data is maintained. Thereafter, the inverted data is stored in the memory of the second page address. However, since the copy data of the original data from the first page is not stored in the “true” copy data but is stored as the inverted copy data, the page copy operation has a limit. is there. Therefore, if the copy data inverted by the subsequent read operation is processed as true copy data, a data error may occur.

  Patent Document 2 discloses a method for determining whether copy data is inverted copy data or true copy data. According to this method, an integrated circuit memory device having a page copy flag cell is provided. The integrated circuit memory device includes an array of memory cells and a plurality of flag cells connected to the memory cells. The plurality of flag cells have a flag indicating whether each page of the memory cell includes inverted copy data from the memory cells of other pages. The flag is a logical value indicating whether or not the corresponding page data stored in the flag EEPROM cell is true data or copy data that is page data copied from another page having another address. “1” (or logical value “0”) is configured. A page buffer is provided to maintain data read from a page of memory, data read from a corresponding flag cell, and data from an exclusive OR gate. The exclusive OR gate inverts the data output by the page buffer when the flag is set, and passes the original output data when the flag is not set. The invention is for solving the possibility that a copied page with an error is used, but still has a problem of taking a long time.

Although a memory device and method for performing the page copy operation described above have been disclosed, there remains a need for an improved memory device and method for performing a page copy operation.
US Pat. No. 5,546,341 US Pat. No. 5,996,041 B. Prince et al. Handbook "Semiconductor Memory" (John Wiley & Sons Ltd., 1991, pages 603-604, cross-sections and schematics of FIGS. 11.58 and 11.59) M.M. Momodomi et al., "An Experiential 4-Mbit CMOS EEPROM with a NAND structured Cell" (IEEE Journal of Solid State Circuits, Vol. 24, No. 5, 1238, No. 5, to 1238).

  The present invention is directed to solving the above-described problems, and its object is to provide a method, apparatus, and system for performing a multi-copyback operation.

According to the above-described embodiment for achieving the object of the present invention, a method for executing a multi-page copyback program in a non-volatile memory device including a memory having a plurality of memory blocks is provided.
The method includes replacing a data page of a memory block having a first address in response to a generated multi-page copyback program instruction, and wherein the first address of the data page includes the page of an error detected page. Determining whether the stored address is the same as the stored address, and determining that the first address is different from the stored address, incrementing the first address; And repeating the data page replacement step and the first address increase step until it is determined that the increased address and the stored address are the same.

  According to the embodiment of the present invention, the state of the replaced page can be determined. In another embodiment, the status of all replaced pages can be determined. The multi-page copyback program can be suspended and / or resumed.

  According to another embodiment of the present invention, generating the multi-page copyback program instruction includes receiving a multi-page copyback instruction from a host and a multi-page copyback received from the host. Generating at least one single page copyback instruction in response to the instruction may be included.

  In accordance with another embodiment of the present invention, a data program and / or read method for a non-volatile memory device including a memory having a plurality of memory blocks is provided. The method includes detecting a program / read error during a program / read operation of the non-volatile memory device, storing an address of one page in a memory block in which the error is detected, and multi- Receiving a page copyback program instruction; performing the multi-page copyback operation; and replacing a data page of a memory block having a first address in response to the generated multi-page copyback program instruction Determining whether the first address of the data page is the same as the stored address of the page where the error is detected, and if the first address and the stored address are not the same If determined, increasing the first address, and increasing the increased address. Until when the stored address that is the same is determined, and a step of repeating the data page replacement phase and the first address escalated.

  According to another embodiment for achieving the object of the present invention, a method for replacing a memory block including a plurality of data pages in a non-volatile memory device is provided. The method includes detecting a program / read error during a program / read operation of the non-volatile memory device and storing an address of one page among data pages of a memory block in which the program / read error is detected. In response to a program or read error, and in response to the multi-page copyback command until a stored address of the error page is reached. Replacing a data page of the memory block.

  According to another embodiment for achieving the object of the present invention, a non-volatile memory device is provided. The non-volatile memory includes a memory including at least one memory block having a plurality of data pages, and is connected to the memory, and the data page of one memory block is connected to the memory. A control unit configured to execute a multi-page copyback instruction received from a host in response to a program / read error, wherein the page in which the error has occurred has an associated error page address; The multi-page copyback command is configured to start a replacement process for at least one data page among the plurality of data pages until the page in which the error occurs arrives.

  According to an embodiment of the present invention, the control unit may further include a memory controller and an address generator connected to the memory controller. The memory controller is configured to set an error page in the address generator, the address generator is configured to set the page until the page address is the same as the error page set by the memory controller. The flag may be provided to a memory controller indicating that the memory address is reached by increasing the address.

  According to another embodiment of the present invention, the control unit may further include a program / read controller connected to the address generator and the memory controller. The program / read controller receives at least one single page copyback command from the memory controller and initiates a single page copyback operation in response to the at least one single page copyback command. Can be configured.

  According to another embodiment of the present invention, the memory controller can be configured to provide the program / read controller with the at least one single page copyback instruction.

  According to another embodiment of the present invention, the address generator receives a command from the program / read controller indicating the start of the single page copyback operation, and receives a page address in response to the command. A counter configured to increment, a register configured to store an error page address set by the memory controller, and until the incremented address and the error page address are identical to each other, A comparator configured to compare the incremented address with the error page address to provide the flag signal to the memory controller indicating that an error memory address has arrived may be included.

  According to another embodiment of the present invention, the non-volatile memory device is connected to a control unit, and data is transferred to a page of the memory block until the error page address is the same as the increased page address. A program / read circuit configured to perform a program / read operation may further be included. The control unit may further include a verification circuit connected to the program / read circuit. The verification circuit may be configured to check the state after replacing each page and provide the checked state to the program / read controller.

  According to another embodiment of the present invention, the control unit may further include a hold and resume circuit connected to the memory controller and configured to hold and / or resume a replacement operation.

  According to another embodiment for achieving the objectives of the present invention, a system is provided. The system includes an electrically coupled microprocessor, a user interface and a modem, and a non-volatile memory device electrically coupled to the microprocessor, the user interface and the modem. The nonvolatile memory device includes a memory including at least one memory block having a plurality of data pages, and a data page program or read error in one of the at least one memory block. A control unit is configured to execute a multi-page copyback instruction received from the host in response. The page in which the error has occurred has an associated error page address, and the multi-page copyback command may execute at least one of the plurality of data pages until the page in which the error has occurred is reached. It is configured to initiate a replacement process for the data page.

  According to another embodiment of the present invention, the system further includes a battery electrically connected to the microprocessor, the user interface, the modem, and the non-volatile memory device, and provided in a portable electronic device. Has been.

  According to another embodiment for achieving the objects of the present invention, a system is provided. The system includes an electrically coupled microprocessor, a user interface and a modem, and at least one memory block having a plurality of data pages electrically coupled to the microprocessor, the user interface and the modem. A non-volatile memory device including: a multi-page copy connected to the memory and received from a host in response to a program / read error of a data page in one of the at least one memory block A control unit configured to execute a back instruction is included. The page in which the error has occurred has an associated error page address, and the multi-page copyback command may execute at least one of the plurality of data pages until the page in which the error has occurred is reached. It is configured to initiate a replacement process for the data page.

  A multi-page copyback operation according to an embodiment of the present invention is performed automatically in response to a command from the control unit. In particular, the data page of the memory block having the first address is replaced in response to an automatically generated multi-page copyback program instruction. It is determined whether the first address of the data page is the same as the stored address of the page where the error was detected. If the first address is not the same as the stored address, the first address is increased. The replacement and determination step is repeated until it is determined whether the increased address is the same as the stored address. As a result, the multi-copy back operation can be performed quickly and effectively.

Hereinafter, various embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the accompanying drawings, the same components are denoted by the same reference numerals.
FIG. 1 is a block diagram of a flash memory device according to an embodiment of the present invention.
Referring to FIG. 1, a flash memory device 100 is a One NAND ^™ flash memory device provided by Samsung Electronics Co., Ltd. The flash memory device 100 includes a memory core 110 and a control unit 120. The memory core 110 includes at least one memory block MB0, MB1,..., MB (n−1). Each of the memory blocks MB0, MB1,..., MB (n−1) includes a plurality of data pages. According to the present embodiment, the memory blocks MB0, MB1,..., MB (n−1) include flash memory cells.

  The control unit 120 is connected to the memory core 110 and includes an address generator 130. The control unit 120 is configured to execute a multi-page copyback instruction according to an embodiment of the present invention. The multi-page copyback command is responsive to a data page program / read error 140 stored in any one of the memory blocks MB0, MB1,..., MB (n−1). (Not shown). Error page 140 has an error page address associated therewith. An error page address associated with the error page 140 is stored in the address generator 130. For example, a multi-page copyback command received from the host initiates a replacement process for at least one of the plurality of pages of data until the error page address is reached.

FIG. 2 is a detailed block diagram of a flash memory device according to an embodiment of the present invention.
Referring to FIG. 2, the flash memory device 200 is connected to the host 290 and includes the memory core 210 and the control unit 220 described with reference to FIG. 1. As described above in FIG. 1, the host 290 can provide a multi-page copyback instruction to the control unit 220. The control unit 220 includes a memory controller 250, an address generator 230, a program / read controller 255, a status module 260, and a verification circuit 265. As shown in FIG. 2, the memory controller 250, the address generator 230, the program / read controller 255, the status module 260, and the verification circuit 265 of the control unit 220 are individually configured. However, the present invention is not limited to this. For example, one or more components of the control unit 220 can be combined without departing from the spirit of the present invention.

  As shown in FIG. 2, the address generator 230 is connected to the memory controller 250. The memory controller 250 is configured to set an error page address in the address generator 230, and the address generator 230 has the error page in which the increased page address is set by the memory controller 250. It is configured to increase the page address until it becomes the same as the address. In this embodiment, the address generator 230 provides a flag signal to the memory controller 250 indicating that an error memory address has been reached. The address generator 230 may be generated by the memory controller 250 using any method widely known to those having ordinary skill within the scope of the present invention without departing from the spirit of the present invention (hereinafter referred to as “a person skilled in the art”). It is clear that the error memory address set in the address generator 230 represents reaching.

  The program / read controller 255 is connected to the address generator 230 and the memory controller 250 as shown in FIG. The program / read controller 255 receives at least one single-page copyback command from the memory controller 250 and starts a single-page copyback operation in response thereto. Consists of. As described above, the memory controller 250 provides the at least one single page copyback command to the program / read controller 255 in response to a multi-page copyback command received from the host 290.

Referring to FIG. 2, the memory core 210 includes one or more memory blocks 270 MB0, MB1,..., MB (n−1), and a program / read circuit 280. The program / read circuit 280 is connected to the control unit 220 and is configured to program / read data as pages of the memory block 270 until the error page address is equal to the increased page address. .
According to this embodiment, the program / read circuit 280 of the memory core 2410 may include a row selection circuit, a column selection circuit, a page buffer circuit, and a high voltage generator. Widely known.
As described above, the control unit 220 further includes a verification circuit 265. The verification circuit 265 checks the state after each page is replaced, and provides a program / readout of the memory core 210 configured to provide the checked state to the program / read controller 255 of the control unit 220. The read circuit 280 is connected.

FIG. 3 is a detailed block diagram according to an embodiment of the present invention.
Referring to FIG. 3, the address generator 330 includes a counter 315, a register 325, and a comparator 335. The counter 315 is configured to receive instructions from the program / read controller 255. The counter 315 is configured to display the start of a single page copyback operation and increase the page address in response thereto. The register 325 is configured to store an error page address set by the memory controller 250. The comparator 335 compares the page address and the error page address until the increased page address and the error page address become the same, and outputs a flag signal indicating that the error memory address has arrived to the memory controller 250. Configured to provide to.

Although the address generator 330 shown in FIG. 3 is provided to achieve an exemplary purpose, embodiments of the present invention are not limited to such a configuration. The address generator according to the embodiment of the present invention can have various configurations without departing from the spirit of the present invention.
Hereinafter, a data program and / or a read operation process of the nonvolatile memory device according to the embodiment of the present invention will be described with reference to the flowchart shown in FIG.

  As described above, the nonvolatile memory device includes a memory having a plurality of memory blocks. As shown in FIG. 4, at block 400, the process begins by determining whether a program / read error has been detected during a program / read operation of the non-volatile memory device. If no program / read error is detected at block 400, the process remains at the stage block 400 until a program / read error is detected. Conversely, if a program / read error is detected at block 400, the process proceeds to the next stage block 410. In the step block 410, the address of the page of any one block is stored (or set) in the block in which the error is detected. As described above, the memory controller 250 may be configured to set an address of an error page in the register 325 of the address generator 330. At block 420, a multi-page copyback program instruction can be generated. As described above, the multi-page copyback program command can be received from the host 290 on the memory controller 250 side. The memory controller 250 can provide the instructions to the program / read controller 255 of the control unit 250. A multi-page copyback program can be executed in response to the multi-page copyback instruction. The multi-page copyback program includes step blocks 430 to 450 of the flowchart shown in FIG.

  In particular, at block 430, a data page of a memory block having a first address can be replaced in response to the generated multi-page copyback program instruction. Block 440 increments the address in the counter, and block 450 determines whether the incremented address of the data page is the same as the stored address of the page where the error was detected. If block 450 determines that the addresses are the same, the process is aborted. On the contrary, if it is determined that the addresses are not the same, the steps 430 to 450 are repeated until it is determined that the addresses are the same in block 450.

  In this embodiment of the invention, the replacement operation includes determining the status of the replaced page as shown in the timing diagram of FIG. In another embodiment of the present invention, before the steps 430 to 450 are repeated, the status of all the replaced pages can be determined as shown in the timing diagram of FIG. In other embodiments of the present invention, after the stage block 440 is executed, the multi-page copyback program can be temporarily suspended and / or the multi-page copyback program can be resumed. The multi-page copyback program can be executed by a hold / resume circuit (to be described later).

Hereinafter, timing according to various embodiments of the present invention will be described with reference to FIGS.
As shown in FIG. 5, once the error page address is set, the multi-page copyback program 567 according to the embodiment of the present invention is executed. The portion displayed as “busy” in the timing diagram of FIG. 5 represents block replacement.
As shown in the timing diagram of FIG. 6, a state read operation can be performed across all blocks. Further, as shown in the timing chart of FIG. 8, the state reading operation can be executed after each page. In conclusion, as shown in the timing diagram of FIG. 7, a status read operation can be performed when a program / read error is detected.

FIG. 9 is a block diagram of a memory controller according to an embodiment of the present invention.
Referring to FIG. 9, the memory controller 950 includes a control logic 953, a memory buffer 951, an error correction circuit (ECC) 959, and a register 957. The control logic 953 can be provided by, for example, a state machine without departing from the spirit of the present invention.

10 to 12 are block diagrams illustrating flash memory devices according to various embodiments of the present invention. Since the block diagrams shown in FIGS. 10 to 12 are similar to the block diagram shown in FIG. 2, the same components are denoted by the same reference numerals. Therefore, only different points will be briefly described with reference to FIGS.
Referring to FIG. 10, the memory controller 1050 can be provided to the host 1090 and can be replaced with an interface 1095 in the control unit 1020. The interface 1095 may be any interface that can be operated by those skilled in the art according to embodiments of the present invention.

Referring to FIG. 11, a hold and resume circuit 1187 can be provided in the control unit 1120. The hold and resume circuit 1187 can be connected to the memory controller 1150. The hold and resume circuit 1187 can be configured to temporarily hold and / or resume the replacement operation as described with reference to the flowchart of FIG.
Referring to FIG. 12, a control unit 1220 combining the configurations of FIGS. 10 and 12 is provided to a control unit 1220 including a host 1290 and a hold and resume circuit 1287.

13 and 14 are schematic block diagrams of systems according to respective embodiments of the present invention.
As shown in FIG. 13, system 1300 includes a microprocessor 1310, a user interface 1320, a modem 1350, a non-volatile memory device 1340, and an optional battery 1330 that is electrically connected by a bus 1375.

  The user interface 1320 may be implemented by any man-machine interface widely known to those skilled in the art, for example, a keyboard, a touch screen, a voice activated circuit, and the like. The system 1300 can be embedded in a portable electronic device. Here, the terms “portable electronic device” and “portable terminal” refer to a portable radio telephone with / without a multi-line display, a data processing function and a facsimile for a portable radio telephone. And a personal mobile communication system (PCS) terminal combined with a data communication function, a wireless telephone, a wireless caller, an Internet / intranet connection, a web browser, an organizer, a calendar, and / or a global positioning system ( A portable information terminal (PDA) with integrated GPS receiver and a conventional laptop and / or palmtop including a game console, audio / video player, and wireless telephone transceiver Comprehensive with portable computers

The non-volatile memory device may include the memory and the control unit described above with reference to FIG. In particular, the memory may include one or more blocks having a plurality of data pages. The control unit may be configured to execute a multi-page copyback instruction received from the host in response to a program / read error of the one or more blocks of data pages. An error page may have an error page address associated therewith, and the multi-page copyback instruction replaces at least one of the plurality of data pages by the time the error page address is reached. Configured to start the process.
As shown in FIG. 14, the system 1400 is the same as the system 1300 shown in FIG. 13 except that the nonvolatile memory device 1465 and the control unit 1460 are provided separately.

  As described above, the present invention has been described with reference to the limited embodiments and drawings. However, the present invention is not limited to the various embodiments described above, and has ordinary knowledge in the field to which the present invention belongs. Those skilled in the art can make various modifications and variations from such description. Accordingly, the spirit of the invention should be understood by the appended claims, and their equivalent or equivalent modifications shall fall within the spirit of the invention.

1 is a block diagram of a flash memory according to an embodiment of the present invention. 1 is a detailed block diagram of a flash memory according to an embodiment of the present invention. It is a block diagram according to an embodiment of the present invention. 6 is a flowchart illustrating a multi-page copyback operation according to an embodiment of the present invention. FIG. 6 is a timing diagram illustrating a copyback operation according to an embodiment of the present invention. FIG. 6 is a timing diagram illustrating a state read operation according to an embodiment of the present invention. FIG. 10 is a timing diagram illustrating a state read operation according to another embodiment of the present invention. FIG. 10 is a timing diagram illustrating a state read operation according to another embodiment of the present invention. 2 is a block diagram of a memory controller according to an embodiment of the present invention. FIG. 1 is a block diagram of a flash memory device according to an embodiment of the present invention. FIG. 6 is a block diagram of a flash memory device according to another embodiment of the present invention. FIG. 3 is a block diagram of a flash memory device according to another embodiment of the present invention. 1 is a schematic block diagram of a system according to an embodiment of the present invention. FIG. 3 is a schematic block diagram of a system according to another embodiment of the present invention.

Explanation of symbols

100 Flash memory device 110 Memory core 120 Control unit 130 Address generator 140 Error page 230 Address generator 250 Memory controller 260 Status module 255 Program / read controller 265 Verification circuit 280 Program / read circuit 290 Host 315 Counter 325 Register 335 Compare 1187 Hold and Resume Circuit 1310 Microprocessor 1320 User Interface 1330 Battery 1350 Modem

Claims (33)

In a method for executing a multi-page copyback program in a non-volatile memory device including a memory having a plurality of memory blocks,
Replacing the data page of the memory block having the first address in response to the generated multi-page copyback program instruction;
Determining whether the first address of the data page is the same as the stored address of the page where the error was detected;
If it is determined that the first address and the stored address are different, increasing the first address;
Including a step of repeating the data page replacement step and the first address increment step until it is determined that the incremented address and the stored address are the same. Copyback program execution method.   The method of claim 1, wherein the data page replacement step is executed before the step of determining the state of the replaced page.   The multi-copyback program execution according to claim 1, wherein the step of repeating the data page replacement step and the first address incrementing step is executed before the step of determining all the replaced page states. Method.   The method of claim 1, wherein the first address incrementing step is executed before the step of suspending the multi-page copyback program.   The method of claim 4, wherein the step of suspending the multi-page copyback program is executed before the step of resuming the multi-page copyback program. Generating the multi-page copyback program instruction comprises:
Receiving a multi-page copyback command from the host;
The method of claim 1, further comprising: generating at least one single page copyback command in response to the multi-page copyback command received from the host. . In a data program and / or read method of a nonvolatile memory device including a memory having a plurality of memory blocks,
Detecting a program / read error during a program / read operation of the non-volatile memory device;
Storing the address of one page in the memory block in which the error was detected;
Receiving a multi-page copyback program instruction;
Performing the multi-page copyback operation;
Replacing the data page of the memory block having the first address in response to the generated multi-page copyback program instruction;
Determining whether the first address of the data page is the same as the stored address of the page where the error was detected;
Increasing the first address if it is determined that the first address and the stored address are not the same;
A data program comprising: repeating the data page replacement step and the first address increment step until it is determined that the incremented address and the stored address are the same; and / Or reading method.   8. The data program and / or read method according to claim 7, wherein the data page replacement step is executed before the step of determining the state of the replaced page.   8. The data program and / or read-out according to claim 7, wherein the step of repeating the data page replacement step and the first address increase step is executed before the step of determining all the replaced page states. Method.   8. The data program and / or read method according to claim 7, wherein the first address incrementing step is executed before the step of suspending the multi-page copyback program.   11. The data program and / or read method according to claim 10, wherein the step of suspending the multi-page copyback program is executed before the step of resuming the multi-page copyback program. Generating the multi-page copyback program instruction comprises:
Receiving a multi-page copyback command from the host;
8. The data program and / or read method of claim 7, comprising generating at least one single page copyback command in response to a multi-page copyback command received from the host. . In a method for replacing a memory block including a plurality of data pages in a non-volatile memory device,
Detecting a program / read error during a program / read operation of the non-volatile memory device;
Storing the address of one of the data pages of the memory block in which the program / read error is detected;
Receiving a multi-page copyback instruction in response to a program or read error;
Replacing the data page of the memory block in response to the multi-page copyback command until the stored address of the error page is reached. Replacing the data page comprises:
Replacing the data page of the memory block having the first address in response to the generated multi-page copyback program instruction;
Determining whether the first address of the data page is the same as the stored address of the page where the error was detected;
Increasing the first address if it is determined that the first address and the stored address are not the same;
The method of claim 13, further comprising: repeating the data page replacement step and the first address increment step until it is determined that the incremented address and the stored address are the same. The memory block replacement method described in 1.   The memory block of claim 13, wherein receiving the multi-page copyback command comprises receiving the multi-page copyback command from a host through communication with the non-volatile memory device. Replacement method. A memory including at least one memory block having a plurality of data pages;
A multi-page copyback command received from the host is executed in response to a program / read error of a data page in one of the at least one or more memory blocks connected to the memory. Including a control unit,
The page where the error occurred has an associated error page address;
The multi-page copyback command is configured to start a replacement process for at least one data page among the plurality of data pages until the page in which the error occurs arrives. Non-volatile memory device characterized. The control unit is
A memory controller,
An address generator connected to the memory controller;
The memory controller is configured to set an error page in the address generator;
The address generator increments the page address and provides a flag signal to the memory controller indicating that the memory address arrives until the page address is the same as the error page set by the memory controller The nonvolatile memory device according to claim 16, wherein the nonvolatile memory device is configured to do so. The control unit further includes a program / read controller connected to the address generator and the memory controller;
The program / read controller receives at least one single page copyback command from the memory controller and initiates a single page copyback operation in response to the at least one single page copyback command. The nonvolatile memory device according to claim 17, wherein the nonvolatile memory device is configured as follows.   19. The non-volatile memory device of claim 18, wherein the memory controller is configured to provide the at least one single page copyback instruction to the program / read controller. The address generator is
A counter configured to receive an instruction from the program / read controller representing the start of the single page copyback operation and to increase a page address in response to the instruction;
A register configured to store an error page address set by the memory controller;
The flag signal is sent to the memory controller indicating that an error memory address is reached by comparing the increased address with the error page address until the increased address and the error page address are the same. The non-volatile memory device of claim 18, further comprising a comparator configured to provide.   A program / read circuit configured to perform a data program / read operation on a page of the memory block until the error page address connected to the control unit is the same as the increased page address; The non-volatile memory device according to claim 16. The control unit further includes a verification circuit connected to the program / read circuit,
The non-volatile memory of claim 21, wherein the verification circuit is configured to check a state after replacing each page and to provide the checked state to a program / read controller. apparatus.   The nonvolatile memory device of claim 16, wherein the control unit further comprises a hold and resume circuit configured to hold and / or resume a replacement operation connected to the memory controller. An electrically coupled microprocessor, user interface, and modem;
A non-volatile memory device electrically coupled to the microprocessor, the user interface, and the modem;
The nonvolatile memory device is:
A memory including at least one memory block having a plurality of data pages;
A control unit configured to execute a multi-page copyback command received from a host in response to a program or read error of a data page in one of the at least one memory block. Including
The page where the error occurred has an associated error page address;
The multi-page copyback command is configured to start a replacement process for at least one data page among the plurality of data pages until the page in which the error occurs arrives. Non-volatile memory device characterized.   The system further comprises a battery electrically coupled to the microprocessor, the user interface, the modem, and the non-volatile memory device, provided in a portable electronic device. 24. The system according to 24. The control unit is
A memory controller,
An address generator connected to the memory controller;
The memory controller is configured to set an error page in the address generator;
The address generator increments the page address and provides a flag signal to the memory controller indicating that the memory address arrives until the page address is the same as the error page set by the memory controller 25. The system of claim 24, wherein the system is configured to: The control unit further includes a program / read controller connected to the address generator and the memory controller;
The program / read controller receives at least one single page copyback command from the memory controller and initiates a single page copyback operation in response to the at least one single page copyback command. 27. The system of claim 26, wherein the system is configured as follows.   28. The system of claim 27, wherein the memory controller is configured to provide the at least one single page copyback instruction to the program / read controller. The address generator is
A counter configured to receive an instruction from the program / read controller representing the start of the single page copyback operation and to increase a page address in response to the instruction;
A register configured to store an error page address set by the memory controller;
The flag signal is sent to the memory controller indicating that an error memory address is reached by comparing the increased address with the error page address until the increased address and the error page address are the same. 28. The system of claim 27, comprising a comparator configured to provide.   A program / read circuit connected to the control unit and configured to perform a data program / read operation on the page of the memory block until the error page address is the same as the increased page address; 25. The system according to claim 24. The control unit further includes a verification circuit connected to the program / read circuit,
The system of claim 30, wherein the verification circuit checks the state after replacing each page and provides the checked state to a program / read controller.   25. The system of claim 24, wherein the control unit further comprises a hold and resume circuit configured to hold and / or resume replacement operations connected to the memory controller. An electrically coupled microprocessor, user interface, and modem;
A non-volatile memory device including at least one memory block having a plurality of data pages electrically connected to the microprocessor, the user interface, and the modem;
A multi-page copyback command received from the host is executed in response to a program / read error of a data page in one of the at least one or more memory blocks connected to the memory. Including a control unit,
The page where the error occurred has an associated error page address;
The multi-page copyback command is configured to start a replacement process for at least one data page among the plurality of data pages until the page in which the error occurs arrives. Feature system.

Images