JP2008053639A - Semiconductor device and multi-layer wiring substrate - Google Patents

Semiconductor device and multi-layer wiring substrate Download PDF

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Publication number
JP2008053639A
JP2008053639A JP2006231008A JP2006231008A JP2008053639A JP 2008053639 A JP2008053639 A JP 2008053639A JP 2006231008 A JP2006231008 A JP 2006231008A JP 2006231008 A JP2006231008 A JP 2006231008A JP 2008053639 A JP2008053639 A JP 2008053639A
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JP
Japan
Prior art keywords
wiring
wiring layer
insulator
layer
semiconductor device
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Granted
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JP2006231008A
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Japanese (ja)
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JP5120913B2 (en
Inventor
Tadahiro Omi
忠弘 大見
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Tohoku University NUC
Foundation for Advancement of International Science
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Tohoku University NUC
Foundation for Advancement of International Science
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Priority to JP2006231008A priority Critical patent/JP5120913B2/en
Application filed by Tohoku University NUC, Foundation for Advancement of International Science filed Critical Tohoku University NUC
Priority to PCT/JP2007/066478 priority patent/WO2008026520A1/en
Priority to KR1020097000846A priority patent/KR101334004B1/en
Priority to US12/310,483 priority patent/US7977796B2/en
Priority to EP07806064A priority patent/EP2059103A4/en
Priority to CN2007800313659A priority patent/CN101507374B/en
Priority to TW096131781A priority patent/TWI401782B/en
Publication of JP2008053639A publication Critical patent/JP2008053639A/en
Application granted granted Critical
Publication of JP5120913B2 publication Critical patent/JP5120913B2/en
Expired - Fee Related legal-status Critical Current
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    • H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
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    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H—ELECTRICITY
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    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
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    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
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    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a multi-layer wiring substrate which can simultaneously attain a low dielectric constant and high heat transmissivity of inter layer insulation by providing a thermal via of a low dielectric constant, and to provide a semiconductor device. <P>SOLUTION: A gas or insulator whose dielectric constant is 2.5 or lower on an average is interposed between a first wiring layer 101 and second wiring layer 102 of a multi-layer wiring structure, and a desired conductive connector is located between the wiring of the first wiring layer 101 and the wiring of the second wiring layer 102, and an insulating heat transmitter whose dielectric constant is 5 or lower is positioned between the predetermined wiring of the first wiring layer 101 and the predetermined wiring of the second wiring layer 102. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は、ＩＣ、ＬＳＩ等の多層配線構造を有する半導体装置および半導体、導体、および絶縁体の少なくとも一つを含む基板上に多層配線構造を有する多層配線基板に関するものである。   The present invention relates to a semiconductor device having a multilayer wiring structure such as an IC or LSI, and a multilayer wiring substrate having a multilayer wiring structure on a substrate including at least one of a semiconductor, a conductor, and an insulator.

ＩＣやＬＳＩ等の半導体装置では、その中の各種素子の集積化に伴う配線の長さ及び面積の増加に対応するため、多層配線構造が用いられている。そして、これらの半導体装置では、更なる高集積化に対応するため、配線パターン微細化が進められ、配線断面積が小さくなる一方で、高速動作を実現するため、配線に流れる電流は増加する傾向にある。つまり、これらの半導体装置では、各配線に流れる電流の密度が増大する傾向にある。   In a semiconductor device such as an IC or LSI, a multilayer wiring structure is used in order to cope with an increase in the length and area of wiring accompanying the integration of various elements therein. In these semiconductor devices, miniaturization of the wiring pattern is promoted in order to cope with further higher integration, and the cross-sectional area of the wiring is reduced, while the current flowing through the wiring tends to increase in order to realize high-speed operation. It is in. That is, in these semiconductor devices, the density of current flowing through each wiring tends to increase.

各配線における電流密度の増加は、ジュール熱の発生量を増大させ、配線の劣化を始めとする種々の問題を招くため、配線に発生した熱を効率よく取り除く必要がある。   An increase in current density in each wiring increases the amount of Joule heat generated and causes various problems such as deterioration of the wiring. Therefore, it is necessary to efficiently remove the heat generated in the wiring.

また、この種の半導体装置の動作速度は、配線の抵抗値Ｒと配線の有する容量Ｃとの積、即ちＲＣ時定数によって大きく制限される。したがって、半導体装置の動作速度を高くするには、配線の抵抗値Ｒを低減するだけでなく、容量Ｃを低減する必要がある。   The operation speed of this type of semiconductor device is greatly limited by the product of the resistance value R of the wiring and the capacitance C of the wiring, that is, the RC time constant. Therefore, in order to increase the operating speed of the semiconductor device, it is necessary to reduce not only the resistance value R of the wiring but also the capacitance C.

上記のような問題は、個別の多層配線構造半導体チップに存在するだけでなく、半導体チップを搭載した半導体パッケージの多層配線構造にも存在するし、また、多数の半導体装置を実装した多層配線構造を有する基板（所謂プリント基板等）やその他の多層配線基板にも存在する。すなわち、いくら個別の半導体チップにおいて配線の熱を除去したり配線のＲＣを下げて動作速度を早くしても、パッケージや配線基板の多層配線構造が熱対応不備のものだったりＲＣが大きければ、全体として動作速度が遅くなり、熱による問題が回避できないからである。   The above problems exist not only in individual multi-layer wiring structure semiconductor chips, but also in multi-layer wiring structures of semiconductor packages on which semiconductor chips are mounted, and multi-layer wiring structures in which a large number of semiconductor devices are mounted. It exists also in the board | substrate (what is called a printed circuit board etc.) which has, and other multilayer wiring boards. That is, no matter how much heat is removed from individual semiconductor chips or the operation speed is increased by reducing the RC of the wiring, if the multi-layer wiring structure of the package or the wiring board is inadequate for heat or the RC is large, This is because the operation speed becomes slow as a whole, and problems due to heat cannot be avoided.

上記問題を解決すべく従来提案された多層配線構造には、層間絶縁膜として、ＳｉＯ２や、Ｓｉ３Ｎ４、あるいはポリイミド等の高分子材料を用い、層間を電気的に接続するスルーホールのみならず、層間絶縁膜に形成された貫通孔に層間絶縁膜よりも大きい熱伝導率を有する絶縁物（ＡｌＮ）を充填した熱ビアを設けることによって、層間伝熱を行うようにしたものがある（例えば、特許文献１参照）。 In the multilayer wiring structure conventionally proposed in order to solve the above problem, only a through hole for electrically connecting the layers is used by using a polymer material such as SiO 2 , Si 3 N 4 , or polyimide as an interlayer insulating film. In addition, there is one in which interlayer heat transfer is performed by providing a thermal via filled with an insulator (AlN) having a thermal conductivity larger than that of the interlayer insulating film in a through hole formed in the interlayer insulating film. (For example, refer to Patent Document 1).

また、従来提案された他の多層配線構造では、信号伝送速度をさらに上昇させるために、層間絶縁部の低誘電率化を目的として空気を層間絶縁に利用しているものがある（例えば、特許文献２参照。）。   Another conventionally proposed multilayer wiring structure uses air for interlayer insulation for the purpose of reducing the dielectric constant of the interlayer insulating portion in order to further increase the signal transmission speed (for example, patents). Reference 2).

特開平９−１２９７２５号公報Japanese Patent Laid-Open No. 9-129725 国際公開ＷＯ００／７４１３５International Publication WO00 / 74135

特許文献１および２で提案された多層配線構造では、熱ビアの材料として、熱伝導率の大きいＡｌＮ（およびＳｉ３Ｎ４）が用いられている。しかしながら、ＡｌＮは、その比誘電率が８．７（Ｓｉ３Ｎ４は７．９）と非常に大きいため、層間絶縁に低誘電率の物質を用いたとしても平均の誘電率を増加させてしまうという問題点がある。 In the multilayer wiring structures proposed in Patent Documents 1 and 2, AlN (and Si 3 N 4 ) having a high thermal conductivity is used as a material for the thermal via. However, since the relative dielectric constant of AlN is very large at 8.7 (Si 3 N 4 is 7.9), even if a low dielectric constant material is used for interlayer insulation, the average dielectric constant is increased. There is a problem that.

そこで、本発明は、低比誘電率の熱ビアを提供し、もって層間絶縁の低誘電率化と高熱伝導率化を同時に実現することができる多層配線構造を提供することを目的とする。   Therefore, an object of the present invention is to provide a thermal via having a low relative dielectric constant and to provide a multilayer wiring structure capable of simultaneously realizing a low dielectric constant and a high thermal conductivity of interlayer insulation.

本発明の他の目的は、多層配線構造の層間絶縁が低誘電率化と高熱伝導率化を同時に実現することができる多層配線基板を提供することである。   Another object of the present invention is to provide a multilayer wiring board in which interlayer insulation of a multilayer wiring structure can simultaneously realize low dielectric constant and high thermal conductivity.

また本発明の他の目的は、低誘電率化と高熱伝導率化を同時に実現することができる多層配線構造を有する半導体装置を提供することである。   Another object of the present invention is to provide a semiconductor device having a multilayer wiring structure capable of simultaneously realizing a low dielectric constant and a high thermal conductivity.

本発明の第１の要旨によれば、半導体、導体、および絶縁体の少なくとも一つを含む基板上に多層配線構造を有する多層配線基板において、前記多層配線構造中の第１の配線層とその上の第２の配線層との間に比誘電率が平均して２．５以下の気体または絶縁物が介在し、前記第１の配線層における少なくとも一つの配線と前記第２の配線層における少なくとも一つの配線との間に所望の導電接続体を設け、さらに前記第１の配線層における所定の配線と前記第２の配線層における所定の配線との間に比誘電率が５以下の絶縁物熱伝導体を設けたことを特徴とする多層配線基板が得られる。   According to a first aspect of the present invention, in a multilayer wiring board having a multilayer wiring structure on a substrate including at least one of a semiconductor, a conductor, and an insulator, the first wiring layer in the multilayer wiring structure and its A gas or an insulator having an average relative dielectric constant of 2.5 or less is interposed between the second wiring layer and the second wiring layer, and at least one wiring in the first wiring layer and the second wiring layer A desired conductive connector is provided between at least one wiring, and further, an insulation having a relative dielectric constant of 5 or less between the predetermined wiring in the first wiring layer and the predetermined wiring in the second wiring layer A multilayer wiring board provided with a physical heat conductor is obtained.

上記多層配線基板において、前記第１の配線層と前記第２の配線層との間に絶縁物が介在する場合、前記絶縁性熱伝導体の熱伝導率は該絶縁物の熱伝導率よりも大きい。   In the multilayer wiring board, when an insulator is interposed between the first wiring layer and the second wiring layer, the thermal conductivity of the insulating thermal conductor is higher than the thermal conductivity of the insulator. large.

前記第１の配線層と前記第２の配線層との間に介在する絶縁物は、炭素とフッ素とを含有する材料を含んでよい。たとえば、フロロカーボン層を主体とする絶縁層が好ましい。   The insulator interposed between the first wiring layer and the second wiring layer may include a material containing carbon and fluorine. For example, an insulating layer mainly composed of a fluorocarbon layer is preferable.

前記第１の配線層と前記第２の配線層との間に介在する絶縁物は、炭素と水素とを含有する材料を含んでよい。たとえば、ハイドロカーボン層を主体とする絶縁層や、フロロカーボン層およびハイドロカーボン層が混在する絶縁層が好ましい。
また、前記絶縁物熱伝導体は、珪素、炭素および窒素を含有する材料を含んでよく、例えば、ＳｉＣＮを含む。 The insulator interposed between the first wiring layer and the second wiring layer may include a material containing carbon and hydrogen. For example, an insulating layer mainly composed of a hydrocarbon layer or an insulating layer in which a fluorocarbon layer and a hydrocarbon layer are mixed is preferable.
The insulator thermal conductor may include a material containing silicon, carbon, and nitrogen, for example, SiCN.

また、本発明の第２の要旨によれば、複数の半導体素子が形成された基板上に多層配線構造を有する半導体装置において、前記多層配線構造中の第１の配線層とその上の第２の配線層との間に比誘電率が平均して２．５以下の気体または絶縁物が介在し、前記第１の配線層における少なくとも一つの配線と前記第２の配線層における少なくとも一つの配線との間に所望の導電接続体を設け、さらに前記第１の配線層における所定の配線と前記第２の配線層における所定の配線との間に比誘電率が５以下の絶縁物熱伝導体を設けたことを特徴とする半導体装置が得られる。   According to a second aspect of the present invention, in a semiconductor device having a multilayer wiring structure on a substrate on which a plurality of semiconductor elements are formed, the first wiring layer in the multilayer wiring structure and the second wiring thereon. A gas or an insulator having an average relative dielectric constant of 2.5 or less is interposed between the first wiring layer and at least one wiring in the second wiring layer. Insulator thermal conductor having a relative dielectric constant of 5 or less between the predetermined wiring in the first wiring layer and the predetermined wiring in the second wiring layer A semiconductor device characterized in that is provided.

上記半導体装置において、前記第１の配線層と前記第２の配線層との間に絶縁物が介在する場合、前記絶縁性熱伝導体の熱伝導率が該絶縁物の熱伝導率よりも大きい。   In the semiconductor device, when an insulator is interposed between the first wiring layer and the second wiring layer, the thermal conductivity of the insulating thermal conductor is larger than the thermal conductivity of the insulator. .

前記第１の配線層と前記第２の配線層との間に介在する絶縁物は、炭素とフッ素とを含有する材料を含んでよい。たとえば、フロロカーボン層を主体とする絶縁層が好ましい。   The insulator interposed between the first wiring layer and the second wiring layer may include a material containing carbon and fluorine. For example, an insulating layer mainly composed of a fluorocarbon layer is preferable.

前記第１の配線層と前記第２の配線層との間に介在する絶縁物は、炭素と水素とを含有する材料を含んでよい。たとえば、ハイドロカーボン層を主体とする絶縁層や、フロロカーボン層およびハイドロカーボン層が混在する絶縁層が好ましい。
また、前記絶縁物熱伝導体は、珪素、炭素および窒素を含有する材料を含んでよく、例えば、ＳｉＣＮを含む。 The insulator interposed between the first wiring layer and the second wiring layer may include a material containing carbon and hydrogen. For example, an insulating layer mainly composed of a hydrocarbon layer or an insulating layer in which a fluorocarbon layer and a hydrocarbon layer are mixed is preferable.
The insulator thermal conductor may include a material containing silicon, carbon, and nitrogen, for example, SiCN.

本発明によれば、前記第１の配線層と前記第２の配線層との間に比誘電率が平均して２．５以下の気体または絶縁物を介在させるとともに、比誘電率が５以下の絶縁物熱伝導体を用いて熱ビアを形成するようにしたことで、低誘電率でかつ高熱伝導率の多層配線構造を実現することができる。   According to the present invention, a gas or an insulator having an average dielectric constant of 2.5 or less is interposed between the first wiring layer and the second wiring layer, and the relative dielectric constant is 5 or less. By forming the thermal via using the insulating thermal conductor, a multilayer wiring structure having a low dielectric constant and a high thermal conductivity can be realized.

以下、図面を参照して本発明の実施の形態について詳細に説明する。   Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

本発明の第１の実施の形態に係る半導体装置は、半導体領域を含む基板上に第１の配線層とその上の第２の配線層とを少なくとも有している。例えば、図１に示すように、シリコン基板１００上に形成された７層の配線層１０１〜１０７と、それらの間、基板１００との間、及び放熱装置１０８との間に配された層間絶縁膜１０９〜１１６を有するものであってよい。   The semiconductor device according to the first embodiment of the present invention has at least a first wiring layer and a second wiring layer thereon on a substrate including a semiconductor region. For example, as shown in FIG. 1, seven layers of wiring layers 101 to 107 formed on a silicon substrate 100 and interlayer insulation disposed between them, the substrate 100, and the heat dissipation device 108. The film 109 to 116 may be included.

ここで、半導体装置とは、電気回路や電気素子を一つの基板上に高密度に構成したもの、すなわち、トランジスタ、抵抗体、コンデンサ等を使って集積化したものを意味し、具体的には、ＩＣやＬＳＩである。   Here, the semiconductor device means a structure in which an electric circuit or an electric element is formed on a single substrate at a high density, that is, a structure in which transistors, resistors, capacitors, etc. are integrated. IC and LSI.

基板としては、半導体素子を形成したシリコン基板のほかに、例えば、金属基板、一般の半導体基板、ガラスやプラスティックのような絶縁体基板、あるいは絶縁体膜で被覆された後さらに半導体膜で被覆された金属基板、半導体膜で被覆された絶縁体基板等が利用できる。   As a substrate, in addition to a silicon substrate on which a semiconductor element is formed, for example, a metal substrate, a general semiconductor substrate, an insulating substrate such as glass or plastic, or an insulating film, and then further covered with a semiconductor film A metal substrate, an insulator substrate coated with a semiconductor film, or the like can be used.

この基板は、導電性基板としての利用を可能にするため、少なくとも表面及び／又は裏面を構成する材料（ＳｉやＧａＡｓなどの半導体材料）の電気伝導度を１０−８（Ω・cm）−１以上とすることが望ましい。また、この基板の表面及び／又は裏面は、その上に各種素子などを作製することから、可能なかぎり平坦な面であることが好ましい。金属としては、Ｔａ，Ｔｉ，Ｗ，Ｃｏ，Ｍｏ，Ｈｆ，Ｎｉ，Ｚｒ，Ｃｒ，Ｖ，Ｐｄ，Ａｕ，Ｐｔ，Ｍｎ，Ｎｂ，Ｃｕ，Ａｇ，又はＡｌが好ましい。半導体としては、Ｓｉ，Ｇｅ，ＧａＡｓ，又はＣ（ダイアモンド）が好ましい。半導体膜で被覆された絶縁体としては、ＳｉＯ２（酸化シリコン），ＳｉＮ（窒化シリコン），ＡｌＮ（窒化アルミニウム），Ａｌ２Ｏ３（酸化アルミニウム），又はＳｉＯｘＮｙからなる混合膜が好ましい。絶縁体膜で被覆された後さらに半導体膜で被覆された金属としては、Ｔａ，Ｔｉ，Ｗ，Ｃｏ，Ｍｏ，Ｈｆ，Ｎｉ，Ｚｒ，Ｃｒ，Ｖ，Ｐｄ，Ａｕ，Ｐｔ，Ｍｎ，Ｎｂ，Ｃｕ，Ａｇ，又はＡｌが好ましい。 In order that this substrate can be used as a conductive substrate, the electrical conductivity of a material (semiconductor material such as Si or GaAs) constituting at least the front surface and / or the back surface is 10 −8 (Ω · cm) −1. It is desirable to set it above. In addition, the surface and / or the back surface of the substrate is preferably as flat as possible since various elements and the like are produced thereon. As the metal, Ta, Ti, W, Co, Mo, Hf, Ni, Zr, Cr, V, Pd, Au, Pt, Mn, Nb, Cu, Ag, or Al are preferable. As the semiconductor, Si, Ge, GaAs, or C (diamond) is preferable. As the insulator covered with the semiconductor film, a mixed film made of SiO 2 (silicon oxide), SiN (silicon nitride), AlN (aluminum nitride), Al 2 O 3 (aluminum oxide), or SiO x N y is preferable. . Examples of the metal coated with a semiconductor film after being coated with an insulator film include Ta, Ti, W, Co, Mo, Hf, Ni, Zr, Cr, V, Pd, Au, Pt, Mn, Nb, and Cu. , Ag, or Al is preferred.

第１の配線層及び第２の配線層の配線としては、金属配線やポリシリコン、ポリサイドが利用できる。この配線に用いられる金属薄膜は、半導体表面との間に酸化物のような中間層をつくらないように、高真空での金属の蒸着やスパッタ、あるいは金属の塩化物などを用いた高温中でのＣＶＤ法により作製される。   For the wiring of the first wiring layer and the second wiring layer, metal wiring, polysilicon, or polycide can be used. The metal thin film used for this wiring is a high-vacuum metal deposition or sputtering or metal chloride in high temperature so as not to form an oxide-like intermediate layer with the semiconductor surface. It is produced by the CVD method.

金属薄膜の材料としては、例えば、次に示すものが挙げられる。   Examples of the material for the metal thin film include the following.

Ｓｉ半導体装置では、Ａｌ，Ｃｒ，Ｗ，Ｍｏ，Ｃｕ，Ａｇ，Ａｕ，Ｔｉ ＷＳｉ２，ＭｏＳｉ２，ＴｉＳｉ２、又は、これらを主成分とする合金（例えば、Ｃｕ−Ｍｇ合金、Ｃｕ−Ｎｂ合金、Ｃｕ−Ａｌ合金）、若しくは、これらの材料が層状に積層された配線（例えば、Ａｌ−Ｔｉ−Ａｌ、ＴｉＮ−Ａｌ合金−ＴｉＮ、Ｗ−Ａｌ合金−Ｗ）などがある。また、ＧａＡｓ半導体装置では、Ａｕ，Ａｌ，Ｎｉ，Ｐｔ、又は、これらを主成分とする合金がある。 In a Si semiconductor device, Al, Cr, W, Mo, Cu, Ag, Au, Ti WSi 2 , MoSi 2 , TiSi 2 , or an alloy containing these as a main component (for example, Cu—Mg alloy, Cu—Nb alloy) , Cu—Al alloy), or a wiring in which these materials are laminated in layers (for example, Al—Ti—Al, TiN—Al alloy—TiN, W—Al alloy—W) or the like. In addition, in GaAs semiconductor devices, there are Au, Al, Ni, Pt, or alloys containing these as main components.

特に、以下の理由から、Ｓｉ半導体装置では、Ａｌ，Ｃｕ，Ａｇ，Ａｕ、又は、これらを主成分とする合金が重用されている。   In particular, in the Si semiconductor device, Al, Cu, Ag, Au, or an alloy containing these as a main component is heavily used for the following reasons.

（Ａ）電極材料とオーミック接触になること、
（Ｂ）絶縁膜（ＳｉＯ２，Ｓｉ３Ｎ４，Ａｌ２Ｏ３など）との密着性が良いこと、
（Ｃ）導電率が大きいこと、
（Ｄ）加工が容易で加工精度が高いこと、及び
（Ｅ）化学的・物理的、さらに電気的にも安定であること。 (A) be in ohmic contact with the electrode material;
(B) Good adhesion with an insulating film (SiO 2 , Si 3 N 4 , Al 2 O 3, etc.)
(C) high electrical conductivity;
(D) Processing is easy and processing accuracy is high. (E) Chemical, physical, and electrical stability.

また、本実施の形態に係る半導体装置は、第１の配線層と第２の配線層との間を電気的に絶縁する第１の絶縁物（層間絶縁膜１０９〜１１６）を有している。もちろん、基板と第１の配線層との間や、３以上の配線層を有する場合にそれらの配線層間にも、層間絶縁膜は設けられる。   In addition, the semiconductor device according to the present embodiment includes a first insulator (interlayer insulating films 109 to 116) that electrically insulates between the first wiring layer and the second wiring layer. . Of course, an interlayer insulating film is also provided between the substrate and the first wiring layer or between the wiring layers when there are three or more wiring layers.

第１の絶縁物は、図２に示すように、下地層２０１とその上に形成されたＣＦ（フロロカーボン）膜２０２とを有している。   As shown in FIG. 2, the first insulator has a base layer 201 and a CF (fluorocarbon) film 202 formed thereon.

下地層は、例えば、ＳｉＣＮ膜、Ｓｉ３Ｎ４膜、ＳｉＣＯ膜、ＳｉＯ２膜、ＣＨ膜、またはそれらの組み合わせからなる多層膜である。これらの比誘電率は４以下である。とくにＳｉＣＯ膜は３以下、ＣＨ膜は２．５以下である。 The underlayer is, for example, a multilayer film made of a SiCN film, a Si 3 N 4 film, a SiCO film, a SiO 2 film, a CH film, or a combination thereof. Their relative dielectric constant is 4 or less. In particular, the SiCO film is 3 or less, and the CH film is 2.5 or less.

ＣＦ膜は、例えば、反応ガスとしてフルオロカーボンガスをＸｅ又はＫｒプラズマによって分解するＣＶＤにより形成される。あるいは、フルオロカーボンガスをＡｒプラズマによって分解するＣＶＤにより形成される。あるいは、これらのＣＶＤを順次行うことにより２層構造（図２の２０２ａ及び２０２ｂ）とすることもできる。なお、Ｘｅ又はＫｒプラズマで形成したＣＦ膜よりもＡｒプラズマにより形成したＣＦ膜のほうが、その誘電率は低い。いずれにしても、その誘電率は２以下、１．７程度まで低くすることも可能である。   The CF film is formed, for example, by CVD that decomposes a fluorocarbon gas as a reactive gas with Xe or Kr plasma. Or it forms by CVD which decomposes | disassembles fluorocarbon gas with Ar plasma. Alternatively, a two-layer structure (202a and 202b in FIG. 2) can be formed by sequentially performing these CVDs. Note that the CF film formed by Ar plasma has a lower dielectric constant than the CF film formed by Xe or Kr plasma. In any case, the dielectric constant can be as low as 2 or less and as low as 1.7.

フルオロカーボンガスとしては、一般式ＣｎＦ２ｎ（但し、ｎは２〜８の整数）もしくは、ＣｎＦ２ｎ−２（ｎは２〜８の整数）で示される不飽和脂肪族フッ化物を用いることができる。特に、オクタフルオロペンチン、オクタフルオロベンタジエン、オクタフルオロシクロペンテン、オクタフルオロメチルブタジエン、オクタフルオロメチルブチン、フルオロシクロプロペンもしくはフルオロシクロプロパンを含むフッ化炭素、フルオロシクロブテンもしくはフルオロシクロブタンを含むフッ化炭素等の一般式Ｃ５Ｆ８で示されるフルオロカーボンが好ましい。 As the fluorocarbon gas, an unsaturated aliphatic fluoride represented by the general formula C n F 2n (where n is an integer of 2 to 8) or C n F 2n-2 (n is an integer of 2 to 8) is used. be able to. In particular, fluorocarbons including octafluoropentine, octafluoropentadiene, octafluorocyclopentene, octafluoromethylbutadiene, octafluoromethylbutyne, fluorocyclopropene or fluorocyclopropane, fluorocarbons including fluorocyclobutene or fluorocyclobutane. A fluorocarbon represented by the general formula C 5 F 8 is preferred.

例えば、ＣＦ膜を２層構造とする場合、Ｘｅ又はＫｒプラズマにより、第１のＣＦ膜を５〜１０ｎｍ形成し、続いて、Ａｒプラズマにより第２のＣＦ膜を２８０〜５００ｎｍ形成する。   For example, when the CF film has a two-layer structure, the first CF film is formed to 5 to 10 nm by Xe or Kr plasma, and then the second CF film is formed to 280 to 500 nm by Ar plasma.

また、ＣＦ膜の形成後、好ましくは、さらにアニールを行った後、ＡｒガスによるプラズマにＮ２ガスを導入して窒素ラジカルを生成し（Ｎ２ガスのみによりプラズマを発生させ窒素ラジカルを生成しても良い）、ＣＦ膜の表面（厚み１〜５ｎｍ、好ましくは２〜３ｎｍ）をチッ化することにより、このＣＦ膜の表面からの脱ガスを低減するようにしてもよい。これによって、膜剥がれをなくし、比誘電率を１．７〜２．２の範囲で制御することができる。 Further, after the CF film is formed, preferably, after further annealing, N 2 gas is introduced into the plasma by Ar gas to generate nitrogen radicals (the plasma is generated only by N 2 gas to generate nitrogen radicals). Alternatively, degassing from the surface of the CF film may be reduced by nitriding the surface (thickness of 1 to 5 nm, preferably 2 to 3 nm) of the CF film. As a result, film peeling can be eliminated and the relative dielectric constant can be controlled in the range of 1.7 to 2.2.

なお、アニールを行う場合は、不活性ガス雰囲気下で、好ましくは１Ｔｏｒｒ程度の減圧下で行う。   Note that annealing is performed in an inert gas atmosphere, preferably under a reduced pressure of about 1 Torr.

ＣＦ膜の代わりに、またはＣＦ膜に積層して、ＣＨ膜を用いても良い。ＣＨ膜は上記のように２．５以下の低誘電率とすることができる。ＣＨ膜はＣ２Ｈ２やＣ２Ｈ４のようなＣｘＨｙガスをＡｒ等とともに導入しプラズマ化させてＣＶＤで成膜される。 A CH film may be used instead of the CF film or laminated on the CF film. As described above, the CH film can have a low dielectric constant of 2.5 or less. The CH film is formed by CVD by introducing a C x H y gas such as C 2 H 2 or C 2 H 4 together with Ar or the like to form plasma.

さらに、層間絶縁膜は、形成したＣＦ膜および／またはＣＨ膜の上面にＳｉ３Ｎ４膜、ＳｉＣＮ膜、ＳｉＣＯ膜、ＣＨ膜、またはそれらの組み合わせからなる多層膜を形成したものであってもよい。 Further, the interlayer insulating film may be a film in which a multilayer film composed of a Si 3 N 4 film, a SiCN film, a SiCO film, a CH film, or a combination thereof is formed on the upper surface of the formed CF film and / or CH film. Good.

以上のように構成された層間絶縁膜の比誘電率は、平均して（全体として）２．５以下となるように形成される。   The interlayer dielectric film configured as described above is formed so that the relative dielectric constant is 2.5 or less on average (as a whole).

なお、ＣＦ膜の熱伝導率は、０．１３〜０．２１（Ｗ／ｍＫ）であり、ＳｉＯ２の１０．７〜６．２（Ｗ／ｍＫ）よりも２桁小さい。この熱伝導の悪さを、後述の熱ビアにより解消する。 The thermal conductivity of the CF film is 0.13 to 0.21 (W / mK), which is two orders of magnitude smaller than 10.7 to 6.2 (W / mK) of SiO 2 . This poor heat conduction is eliminated by a thermal via described later.

層間絶縁膜には、その上下に位置する配線層の配線間（例えば、第１の配線層と第２の配線層との配線間）を電気的、熱的に接続するために貫通孔（図示せず）が形成されている。この貫通孔はビアホールとも呼ばれ、一般的に、フォトエッチングと呼ばれる手法で作製できる。孔径は、上下に位置する配線の幅に基づいて決定される。この貫通孔は、電気的に配線間を接続するためのスルーホール、また熱的に配線間を接続するためのダミーホールとして利用される。   In the interlayer insulating film, through holes (see FIG. 5) are used to electrically and thermally connect between wirings of wiring layers positioned above and below (for example, between the wirings of the first wiring layer and the second wiring layer). (Not shown) is formed. This through hole is also called a via hole, and can be generally produced by a technique called photoetching. The hole diameter is determined based on the width of the wiring located above and below. This through hole is used as a through hole for electrically connecting wirings and as a dummy hole for thermally connecting wirings.

スルーホールは、層間絶縁膜に形成された貫通孔の中に導電物質を充填したものである。スルーホールは、第１の絶縁物によって電気的に分離された上下に位置する配線の間の導通をとることが役目である。したがって、スルーホールは回路形成上必要な位置に限って設けられるもので、任意の位置に設けることはできない。スルーホールは公知の方法により形成することができる。なお、スルーホールは、電気信号のみならず、熱も伝達することができる。   The through hole is a through-hole formed in the interlayer insulating film and filled with a conductive material. The through hole serves to establish conduction between the upper and lower wirings that are electrically separated by the first insulator. Therefore, the through hole is provided only at a position necessary for circuit formation, and cannot be provided at an arbitrary position. The through hole can be formed by a known method. The through-hole can transfer not only an electric signal but also heat.

ダミーホールは、層間絶縁膜に形成された貫通孔の中に第１の絶縁物よりも大きな熱伝導率を有する第２の絶縁物を充填したものである。ダミーホールは、第１の絶縁物によって電気的に分離された上下に位置する配線間において、一方の配線から他方の配線へ、第１の絶縁物よりも早く熱を伝達することができる。従って、ダミーホールを熱ビアとも呼称する。熱ビアを設けることにより、ある配線の温度が上昇した場合に、熱を迅速に他の配線へ伝達し、放熱を促して、各配線の異常な温度上昇を抑えることができる。ダミーホールは絶縁物であるため、電気信号を伝達しない。したがって、ダミーホールは、任意の場所に設けることが可能である。   The dummy hole is a through-hole formed in the interlayer insulating film filled with a second insulator having a thermal conductivity larger than that of the first insulator. The dummy hole can transfer heat from one wiring to the other wiring faster than the first insulator between the upper and lower wirings electrically separated by the first insulator. Therefore, the dummy hole is also called a thermal via. By providing a thermal via, when the temperature of a certain wiring rises, heat can be quickly transferred to other wiring, heat dissipation can be promoted, and an abnormal temperature rise of each wiring can be suppressed. Since the dummy hole is an insulator, it does not transmit an electrical signal. Therefore, the dummy hole can be provided at an arbitrary place.

第２の絶縁物としては、ＳｉＣＮが用いられる。ＳｉＣＮは、熱伝導率が約１００Ｗ／ｍＫと高く、層間絶縁膜としてＣＦ膜を用いても、十分な熱伝導を実現できる。また、ＳｉＣＮの比誘電率は５以下（４．０程度）であり、層間絶縁膜の平均の誘電率を大きく上昇させることもない。   SiCN is used as the second insulator. SiCN has a high thermal conductivity of about 100 W / mK, and sufficient thermal conduction can be realized even when a CF film is used as an interlayer insulating film. Further, the relative dielectric constant of SiCN is 5 or less (about 4.0), and the average dielectric constant of the interlayer insulating film is not greatly increased.

ＳｉＣＮは、例えば、ＳｉＨ４／Ｃ２Ｈ４／Ｎ２を用いたプラズマ処理によって形成することができる。なお、シランガス（ＳｉＨ４）／エチレン（Ｃ２Ｈ４）の代わりに、有機シランを用いることもできる。 SiCN can be formed, for example, by plasma processing using SiH 4 / C 2 H 4 / N 2 . Note that organosilane can be used instead of silane gas (SiH 4 ) / ethylene (C 2 H 4 ).

本実施の形態の半導体装置の最上層には、放熱装置１０８が設けられてもよい。放熱装置は、例えば、熱伝導率が大きな材料（例えば、Ａｇ，Ｃｕ，Ａｕ，Ａｌ，Ｔａ Ｍｏ）で作製された導電性膜やフィン構造などである。   A heat dissipation device 108 may be provided in the uppermost layer of the semiconductor device of this embodiment. The heat dissipation device is, for example, a conductive film or a fin structure made of a material having a high thermal conductivity (for example, Ag, Cu, Au, Al, TaMo).

以上の構成によれば、実質的な層間絶縁物の誘電率を小さくして高速動作を保証し、かつ、熱伝導率の高いＳｉＣＮで配線間の要所要所にダミーホールを導入することにより、配線の温度上昇を抑えて配線の信頼性を向上させることが可能となる。ＳｉＣＮの代わりに、誘電率が５以下で、熱伝導率がＣＦ膜やＣＨ膜よりも高い絶縁物を用いることができる。   According to the above configuration, by substantially reducing the dielectric constant of the interlayer insulator to ensure high-speed operation, and introducing dummy holes at necessary points between the wirings with SiCN having high thermal conductivity, It is possible to improve the reliability of the wiring by suppressing the temperature rise of the wiring. Instead of SiCN, an insulator having a dielectric constant of 5 or less and a thermal conductivity higher than that of the CF film or the CH film can be used.

次に、本発明の第２の実施の形態について説明する。   Next, a second embodiment of the present invention will be described.

図３に、本発明の第２の実施の形態に係る半導体装置の部分構成を示す。図示の半導体装置は、配線層間の層間絶縁膜が熱ビア（第１の実施の形態におけるダミーホールに相当）を除いて除去され、気体により層間絶縁が成されている多層配線構造の集積回路である。   FIG. 3 shows a partial configuration of a semiconductor device according to the second embodiment of the present invention. The semiconductor device shown in the figure is an integrated circuit having a multilayer wiring structure in which an interlayer insulating film between wiring layers is removed except for thermal vias (corresponding to dummy holes in the first embodiment), and interlayer insulation is formed by gas. is there.

詳述すると、この半導体装置は、ｐ型基板３０１、ＣＭＯＳ構成用ｎウェル３０２、ｎＭＯＳのソース領域３０３、ｎＭＯＳのドレイン領域３０４、ｎＭＯＳのゲート絶縁膜３０５、ｎＭＯＳのゲート電極３０６、ｎＭＯＳのソース電極３０７、ｎＭＯＳのドレイン電極３０８、ｐＭＯＳのドレイン領域３０９、ｐＭＯＳのソース領域３１０、ｐＭＯＳのゲート絶縁膜３１２、ｐＭＯＳのゲート電極３１１、ｐＭＯＳのソース電極３１３、ｐＭＯＳのドレイン電極３１４、素子分離領域（ＳｉＯ２等）３１５、絶縁膜（ＳｉＯ２等）３１６、裏面電極３１７、金属配線３１８、導電ビア（第１の実施の形態のスルーホールに相当）３１９、及び熱ビア３２０を含む。 More specifically, this semiconductor device includes a p-type substrate 301, a CMOS configuration n-well 302, an nMOS source region 303, an nMOS drain region 304, an nMOS gate insulating film 305, an nMOS gate electrode 306, and an nMOS source electrode. 307, nMOS drain electrode 308, pMOS drain region 309, pMOS source region 310, pMOS gate insulating film 312, pMOS gate electrode 311, pMOS source electrode 313, pMOS drain electrode 314, element isolation region (SiO 2) 2 ) 315, insulating film (SiO 2 etc.) 316, back electrode 317, metal wiring 318, conductive via (corresponding to the through hole in the first embodiment) 319, and thermal via 320.

図３において、熱ビア３２０は、図の上下方向に隣接する金属配線３１８間を接続するように示されているが、構造強度を高めるために、図の左右方向に隣接する金属配線３１８間をも接続するようにしてもよい。   In FIG. 3, the thermal via 320 is shown to connect between the metal wirings 318 adjacent in the vertical direction in the figure, but in order to increase the structural strength, the metal via 318 adjacent in the horizontal direction in the figure is connected. May also be connected.

図３の半導体装置は、金属配線としてＣｕを用いる。Ｃｕ配線は、その抵抗率を低減するため、ジャイアントグレイン構造とする。この金属配線と、気体を用いた層間絶縁により、各配線における信号遅延を１／８程度にすることができる。代表的な層間絶縁膜であるＢＰＳＧの比誘電率が４．０程度であるのに対して、気体（望ましくは、熱伝導度の大きいＨｅ）では、その比誘電率が１．０と低いからである。   The semiconductor device in FIG. 3 uses Cu as the metal wiring. The Cu wiring has a giant grain structure in order to reduce its resistivity. With this metal wiring and interlayer insulation using gas, the signal delay in each wiring can be reduced to about 1/8. Since the relative dielectric constant of BPSG, which is a typical interlayer insulating film, is about 4.0, the relative dielectric constant of gas (desirably, He having high thermal conductivity) is as low as 1.0. It is.

金属配線３１８及び導電ビア３１９は、その表面が図示しない窒化物（窒化チタン、窒化タンタル、あるいは窒化シリコン等）により覆われている。   The surfaces of the metal wiring 318 and the conductive via 319 are covered with nitride (not shown) (titanium nitride, tantalum nitride, silicon nitride, or the like).

導電ビア３１９の挿入個所は、回路設計により決定されるが、熱ビア３２０は、任意位置に挿入することが可能であり、構造的丈夫さと配線温度の上昇の程度等に基づいて挿入個所が決定される。   The insertion location of the conductive via 319 is determined by circuit design, but the thermal via 320 can be inserted at an arbitrary position, and the insertion location is determined based on the structural robustness and the degree of increase in the wiring temperature. Is done.

次に、図３の半導体装置の製造方法について説明する。   Next, a method for manufacturing the semiconductor device of FIG. 3 will be described.

この半導体装置は、層間絶縁膜としてＢＰＳＧを有する半導体装置（半完成品）として製造された後、ＢＰＳＧを除去することにより得ることができる。したがって、半完成品の製造は、従来の半導体装置と同様の方法により行われる。熱ビアと導電ビアの形成は、以下のように行われる。   This semiconductor device can be obtained by removing BPSG after being manufactured as a semiconductor device (semi-finished product) having BPSG as an interlayer insulating film. Therefore, the manufacture of the semi-finished product is performed by the same method as the conventional semiconductor device. The formation of the thermal via and the conductive via is performed as follows.

まず、熱ビアの形成方法について説明する。   First, a method for forming a thermal via will be described.

図４（ａ）に示すように、Ｃｕ（合金）配線４０１上に、Ｃｕ配線４０１の表面を安定化させる導電性窒化膜（ＴｉＮ又はＴａＮ等）４０２、薄いＳｉ３Ｎ４４０３、ＢＰＳＧ４０４、Ｓｉ３Ｎ４４０５、及びビアホール形成用パターンとしてのフォトレジスト４０６が順次形成されているものとする。なお、Ｓｉ３Ｎ４４０３、ＢＰＳＧ４０４及びＳｉ３Ｎ４４０５が、層間絶縁膜に相当する。 As shown in FIG. 4A, on the Cu (alloy) wiring 401, a conductive nitride film (TiN or TaN or the like) 402 for stabilizing the surface of the Cu wiring 401, thin Si 3 N 4 403, BPSG 404, Si It is assumed that 3 N 4 405 and a photoresist 406 as a via hole forming pattern are sequentially formed. Note that Si 3 N 4 403, BPSG 404, and Si 3 N 4 405 correspond to an interlayer insulating film.

次に、バランスド・エレクトロン・ドリフト（ＢＥＤ）マグネトロンプラズマＲＩＥ装置で、Ｃ４Ｆ８／ＣＯ／Ｏ２／Ａｒガスを用い、Ｓｉ３Ｎ４３０３、ＢＰＳＧ３０４及びＳｉ３Ｎ４３０５をエッチングすると、図４（ｂ）に示す状態となる。エッチングの最終工程（Ｓｉ３Ｎ４３０５の残りをエッチする工程）を、Ｃ４Ｆ８／ＣＯ／Ｏ２／Ｘｅ（又はＫｒ）ガスを用いて行うことにより、導電性窒化膜４０２に与える表面損傷を十分小さくすることができる。 Next, when Si 3 N 4 303, BPSG 304 and Si 3 N 4 305 are etched using a C 4 F 8 / CO / O 2 / Ar gas in a balanced electron drift (BED) magnetron plasma RIE apparatus, The state shown in FIG. The surface to be provided to the conductive nitride film 402 by performing the final step of etching (step of etching the remainder of Si 3 N 4 305) using C 4 F 8 / CO / O 2 / Xe (or Kr) gas. Damage can be reduced sufficiently.

次に、ＳｉＨ４／Ｃ２Ｈ４／Ｎ２を用いたプラズマ処理により、図４（ｃ）に示すように、ＳｉＣＮ４０７，４０８を堆積させる。なお、シランガス（ＳｉＨ４）／エチレン（Ｃ２Ｈ４）の代わりに、有機シランを用いてもよい。 Next, SiCN 407 and 408 are deposited by plasma treatment using SiH 4 / C 2 H 4 / N 2 as shown in FIG. Note that organic silane may be used instead of silane gas (SiH 4 ) / ethylene (C 2 H 4 ).

続いて、ＩＰＡ（３０％程度）／ＫＦ（１０％程度）／Ｈ２Ｏ溶液を用いて、０．５〜３ＭＨｚ程度のメガソニック超音波を照射する処理を行うと、図４（ｄ）に示すように、フォトレジスト４０６がＳｉ３Ｎ４膜４０４より剥離する。その結果、フォトレジスト４０６上に堆積したＳｉＣＮ４０８は、リフトオフにより除去される。なお、必要なら、ＣＭＰ（Chemical Mechanical Polishing）等の平坦化処理を行う。 Subsequently, when a process of irradiating megasonic ultrasonic waves of about 0.5 to 3 MHz using an IPA (about 30%) / KF (about 10%) / H 2 O solution is performed, FIG. As shown, the photoresist 406 is peeled off from the Si 3 N 4 film 404. As a result, SiCN 408 deposited on photoresist 406 is removed by lift-off. If necessary, a planarization process such as CMP (Chemical Mechanical Polishing) is performed.

以上のようにして、ＢＰＳＧ４０４中に熱ビア４０７を形成することができる。   As described above, the thermal via 407 can be formed in the BPSG 404.

配線層間が空気の場合、空気の熱伝導率は、０．０２４１（Ｗ／ｍＫ）であり、ＳｉＯ２の１０．７〜６．２（Ｗ／ｍＫ）より３桁小さい。しかしながら、ＳｉＣＮの熱伝導率は約１００（Ｗ／ｍＫ）であり、配線層間の熱伝導を十分に行うことができる。しかも、ＳｉＣＮは、比誘電率が４程度なので、層間絶縁部（空間）の平均の比誘電率を大きく増加させることもない。 When the wiring layer is air, the thermal conductivity of air is 0.0241 (W / mK), which is three orders of magnitude smaller than 10.7 to 6.2 (W / mK) of SiO 2 . However, the thermal conductivity of SiCN is about 100 (W / mK), and sufficient heat conduction can be performed between the wiring layers. Moreover, since SiC has a relative dielectric constant of about 4, it does not significantly increase the average relative dielectric constant of the interlayer insulating portion (space).

次に、導電ビア及び配線を形成する工程について説明する。導電ビア及び配線の形成には、ダマシンあるいはデュアルダマシン工程が用いられる。配線には前述の通り、Ｃｕが用いられる。導電ビアには、Ａｌ又はＡｌ合金を用いることもできるが、ここでは、配線と同じＣｕを用いる場合について説明する。   Next, a process for forming conductive vias and wiring will be described. A damascene or dual damascene process is used to form the conductive via and the wiring. As described above, Cu is used for the wiring. Al or an Al alloy can be used for the conductive via, but here, a case where Cu, which is the same as the wiring, is used will be described.

２段シャワープレートマイクロ波プラズマ装置を用い、図４（ｂ）と同様に、Ｓｉ３Ｎ４４０３、ＢＰＳＧ４０４及びＳｉ３Ｎ４４０５にビアホールを形成する。 Via holes are formed in Si 3 N 4 403, BPSG 404, and Si 3 N 4 405 in the same manner as in FIG. 4B using a two-stage shower plate microwave plasma apparatus.

次に、同装置にて、基板電極の高周波電力をゼロにするとともに、導入するガスをＨｅ／Ｏ２、Ｋｒ／Ｏ２、またはＫｒ／Ｈ２Ｏなどに切り換え、ＲＬＳＡを通してマイクロ波を印加する。これにより、Ｏ＊やＯＨ＊を大量に発生させて、表面及びビアホール側面に堆積した薄いフロロカーボン膜を除去する。 Next, in the same apparatus, the high frequency power of the substrate electrode is made zero, the gas to be introduced is switched to He / O 2 , Kr / O 2 , Kr / H 2 O or the like, and the microwave is applied through RLSA. . As a result, a large amount of O * and OH * is generated to remove the thin fluorocarbon film deposited on the surface and via hole side surfaces.

次に、Ｃｕの拡散を抑制するための窒化膜をＢＰＳＧ４０４のビアホール側面に形成するため、ＮＨ３／Ａｒ（又はＫｒ）、あるいはＮ２／Ｈ２／Ａｒ（またはＫｒ）等のガスを流し、マイクロ波により高密度プラズマを励起する。これにより、大量のＮＨ＊が発生し、図５（ａ）に示すように、ＢＰＳＧ４０４のビアホール側面の表面が５〜２０ｎｍ程度、Ｓｉ３Ｎ４４０９に変わる。 Next, a gas such as NH 3 / Ar (or Kr) or N 2 / H 2 / Ar (or Kr) is flowed in order to form a nitride film for suppressing the diffusion of Cu on the side surface of the via hole of BPSG 404. High density plasma is excited by microwaves. As a result, a large amount of NH * is generated, and the surface of the side surface of the via hole of BPSG 404 is changed to Si 3 N 4 409 by about 5 to 20 nm as shown in FIG.

この状態で、Ａｒ，Ｋｒ，Ｘｅ等の希ガスを１段目のシャワープレートから供給し、Ｃｕの供給源となるＣｕ(hgac)(tmvs)、Ｃｕ(hgac)(teovs)等をＡｒキャリアガスとともに２段目のシャワープレートから供給する。マイクロ波によるプラズマ励起は、１段目のシャワープレート直下数ｍｍの距離のところで行われ、２段目のシャワープレートは拡散プラズマ領域に設置されているため、原料ガスは過度に分解されることはない。Ａｒ＋，Ｋｒ＋，Ｘｅ＋やＡｒ＊，Ｋｒ＊，Ｘｅ＊との衝突により、励起されたりイオン化されたりするものがほとんどであり、表面吸着後イオン照射によりＣｕ膜が堆積する。ＣｕのＣＭＰやシリコンブロック表面に数μｍのダイアモンド薄膜形成を行った後、研磨用の溝パターンを設けたダイアモンド研削面による研削を行った後、臭酸（ＣＯＯＨ）２による洗浄を行うと、図５（ｂ）に示すようなＣｕ４１０が埋め込まれた導電ビアが形成される。 In this state, a rare gas such as Ar, Kr, or Xe is supplied from the first-stage shower plate, and Cu (hgac) (tmvs), Cu (hgac) (teovs), or the like serving as a Cu supply source is supplied as an Ar carrier gas. At the same time, it is supplied from the second-stage shower plate. Plasma excitation by microwaves is performed at a distance of several millimeters directly below the first stage shower plate, and the second stage shower plate is installed in the diffusion plasma region, so that the source gas is not decomposed excessively. Absent. Most of them are excited or ionized by collision with Ar + , Kr + , Xe + or Ar * , Kr * , Xe *, and a Cu film is deposited by ion irradiation after surface adsorption. After performing Cu CMP or diamond thin film formation of several μm on the silicon block surface, grinding with a diamond grinding surface provided with a groove pattern for polishing, and then cleaning with odorous acid (COOH) 2 As shown in FIG. 5B, conductive vias embedded with Cu410 are formed.

Ｃｕ４１０の周囲は、Ｓｉ３Ｎ４４０９により覆われており、ＣｕのＢＰＳＧ４０４への拡散は抑制される。 The periphery of Cu410 is covered with Si 3 N 4 409, and diffusion of Cu into BPSG 404 is suppressed.

なお、Ｃｕ４１０の表面に、ＴｉＮやＴａＮを熱ＣＶＤにより５〜１０ｎｍ程度選択堆積させておくとその酸化を防止することができる。   If TiN or TaN is selectively deposited on the surface of Cu 410 by thermal CVD to a thickness of about 5 to 10 nm, the oxidation can be prevented.

以上のようにして、層間絶縁膜としてＢＰＳＧを有し、ＢＰＳＧの所定個所に熱ビア及び導電ビアが形成された半完成品が得られる。   As described above, a semi-finished product having BPSG as an interlayer insulating film and having thermal vias and conductive vias formed at predetermined positions of BPSG is obtained.

次に、少なくとも水分量を１ｐｐｍに低減したＮ２やＡｒなどのガス中に無水のＨＦガスを１〜７％添加したガスを用いて、層間絶縁膜としてのＢＰＳＧのみを選択的に取り除く。 Next, only BPSG as an interlayer insulating film is selectively removed using a gas in which 1 to 7% of anhydrous HF gas is added to a gas such as N 2 or Ar whose water content is reduced to 1 ppm.

ＨＦ分子は、水に溶解して、ＳｉＯ２をエッチングするＨＦ２ −イオンを発生させる。それゆえ、ＢＰＳＧの除去を行う際には、ウェーハ表面に吸着している水分を少なくとも単分子層以下にまで除去しておく。例えば、水分量１ｐｐｍ以下のＮ２ガス雰囲気下でウェーハをベーキング（２００℃以上、望ましくは３００℃以上）する。その後は、ＢＰＳＧとＨＦとの反応により発生する水（Ｈ２Ｏ）がウェーハ表面に吸着しないように、ウェーハ温度を１２０〜１４０℃に維持する。 HF molecules dissolve in water, HF 2 to etch the SiO 2 - ions are generated. Therefore, when removing BPSG, the moisture adsorbed on the wafer surface is removed to at least a monomolecular layer or less. For example, the wafer is baked (200 ° C. or higher, desirably 300 ° C. or higher) in an N 2 gas atmosphere having a moisture content of 1 ppm or lower. Thereafter, the wafer temperature is maintained at 120 to 140 ° C. so that water (H 2 O) generated by the reaction between BPSG and HF is not adsorbed on the wafer surface.

ＨＦガスの濃度は、低すぎるとエッチング速度が遅くなりすぎ、高すぎるとＳｉＯ２等、ＢＰＳＧ以外の部分をエッチングし始める。 If the concentration of HF gas is too low, the etching rate becomes too slow, and if it is too high, etching begins on portions other than BPSG such as SiO 2 .

配線はＳｉ３Ｎ４，ＴａＮ，ＴｉＮなどで覆われており、これら窒化物はＨＦガスと反応しないので、配線がエッチングされることはない。 The wiring is covered with Si 3 N 4 , TaN, TiN, etc., and these nitrides do not react with HF gas, so the wiring is not etched.

以上のようにして、図３の半導体装置が製造できる。   As described above, the semiconductor device of FIG. 3 can be manufactured.

以上、実施例を半導体装置に例を取って説明したが、本発明は半導体、導体、および絶縁体の少なくとも一つを含む基板上に多層配線構造を有する多層配線基板に適用できることは言うまでもない。   Although the embodiments have been described by taking the semiconductor device as an example, it is needless to say that the present invention can be applied to a multilayer wiring substrate having a multilayer wiring structure on a substrate including at least one of a semiconductor, a conductor, and an insulator.

本発明が適用される半導体装置の概略構成を示す断面図である。It is sectional drawing which shows schematic structure of the semiconductor device to which this invention is applied. 本発明の第１の実施の形態に係る半導体装置に用いられる層間絶縁膜の構成を示す断面図である。It is sectional drawing which shows the structure of the interlayer insulation film used for the semiconductor device which concerns on the 1st Embodiment of this invention. 本発明の第２の実施の形態に係る半導体装置構成を示す部分断面図である。It is a fragmentary sectional view which shows the semiconductor device structure which concerns on the 2nd Embodiment of this invention. （ａ）乃至（ｄ）は、図３の半導体装置の熱ビアの形成方法を説明するための工程図である。(A) thru | or (d) are process drawings for demonstrating the formation method of the thermal via of the semiconductor device of FIG. （ａ）及び（ｂ）は、図３の半導体装置の導電ビアの形成方法を説明するための工程図である。(A) And (b) is process drawing for demonstrating the formation method of the conductive via of the semiconductor device of FIG.

符号の説明Explanation of symbols

１００ 基板
１０１〜１０７ 配線層
１０８ 放熱装置
１０９〜１１６ 層間絶縁膜
２０１ 下地層
２０２ ＣＦ膜
３０１ ｐ型基板
３０２ ＣＭＯＳ構成用ｎウェル
３０３ ｎＭＯＳのソース領域
３０４ ｎＭＯＳのドレイン領域
３０５ ｎＭＯＳのゲート絶縁膜
３０６ ｎＭＯＳのゲート電極
３０７ ｎＭＯＳのソース電極
３０８ ｎＭＯＳのドレイン電極
３０９ ｐＭＯＳのドレイン領域
３１０ ｐＭＯＳのソース領域
３１１ ｐＭＯＳのゲート電極
３１２ ｐＭＯＳのゲート絶縁膜
３１３ ｐＭＯＳのソース電極
３１４ ｐＭＯＳのドレイン電極
３１５ 素子分離領域（ＳｉＯ２等）
３１６ 絶縁膜（ＳｉＯ２等）
３１７ 裏面電極
３１８ 金属配線
３１９ 導電ビア
３２０ 熱ビア
４０１ Ｃｕ配線
４０２ 導電性窒化膜
４０３ Ｓｉ３Ｎ４
４０４ ＢＰＳＧ
４０５ Ｓｉ３Ｎ４
４０６ フォトレジスト
４０７，４０８ ＳｉＣＮ
４０９ Ｓｉ３Ｎ４
４１０ Ｃｕ DESCRIPTION OF SYMBOLS 100 Substrate 101-107 Wiring layer 108 Heat dissipation device 109-116 Interlayer insulating film 201 Underlayer 202 CF film 301 P-type substrate 302 n well for CMOS configuration 303 nMOS source region 304 nMOS drain region 305 nMOS gate insulating film 306 nMOS Gate electrode 307 nMOS source electrode 308 nMOS drain electrode 309 pMOS drain region 310 pMOS source region 311 pMOS gate electrode 312 pMOS gate insulating film 313 pMOS source electrode 314 pMOS drain electrode 315 element isolation region (SiO 2) 2nd etc.)
316 Insulating film (SiO 2 etc.)
317 Back electrode 318 Metal wiring 319 Conductive via 320 Thermal via 401 Cu wiring 402 Conductive nitride film 403 Si 3 N 4
404 BPSG
405 Si 3 N 4
406 Photoresist 407, 408 SiCN
409 Si 3 N 4
410 Cu

Claims (12)

半導体、導体、および絶縁体の少なくとも一つを含む基板上に多層配線構造を有する多層配線基板において、前記多層配線構造中の第１の配線層とその上の第２の配線層との間に比誘電率が平均して２．５以下の気体または絶縁物が介在し、前記第１の配線層における少なくとも一つの配線と前記第２の配線層における少なくとも一つの配線との間に所望の導電接続体を設け、さらに前記第１の配線層における所定の配線と前記第２の配線層における所定の配線との間に比誘電率が５以下の絶縁物熱伝導体を設けたことを特徴とする多層配線基板。   In a multilayer wiring board having a multilayer wiring structure on a substrate including at least one of a semiconductor, a conductor, and an insulator, between the first wiring layer in the multilayer wiring structure and the second wiring layer thereon Gas or insulator having a relative dielectric constant of 2.5 or less on average intervenes, and desired conductivity is provided between at least one wiring in the first wiring layer and at least one wiring in the second wiring layer. A connection body is provided, and an insulator thermal conductor having a relative dielectric constant of 5 or less is provided between the predetermined wiring in the first wiring layer and the predetermined wiring in the second wiring layer. Multilayer wiring board. 前記第１の配線層と前記第２の配線層との間に絶縁物が介在し、前記絶縁性熱伝導体の熱伝導率が該絶縁物の熱伝導率よりも大きいことを特徴とする請求項１に記載の多層配線基板。   An insulator is interposed between the first wiring layer and the second wiring layer, and the thermal conductivity of the insulating thermal conductor is larger than the thermal conductivity of the insulator. Item 11. A multilayer wiring board according to Item 1. 前記第１の配線層と前記第２の配線層との間に介在する絶縁物が炭素とフッ素とを含有する材料を含むことを特徴とする請求項２に記載の多層配線基板。   The multilayer wiring board according to claim 2, wherein the insulator interposed between the first wiring layer and the second wiring layer includes a material containing carbon and fluorine. 前記第１の配線層と前記第２の配線層との間に介在する絶縁物が炭素と水素とを含有する材料を含むことを特徴とする請求項２または３に記載の多層配線基板。   4. The multilayer wiring board according to claim 2, wherein the insulator interposed between the first wiring layer and the second wiring layer includes a material containing carbon and hydrogen. 5. 前記絶縁物熱伝導体が珪素、炭素および窒素を含有する材料を含むことを特徴とする請求項１〜４のいずれかに記載の多層配線基板。   5. The multilayer wiring board according to claim 1, wherein the insulator heat conductor includes a material containing silicon, carbon, and nitrogen. 前記絶縁物熱伝導体がＳｉＣＮを含むことを特徴とする請求項５に記載の多層配線基板。   The multilayer wiring board according to claim 5, wherein the insulator thermal conductor includes SiCN. 複数の半導体素子が形成された基板上に多層配線構造を有する半導体装置において、前記多層配線構造中の第１の配線層とその上の第２の配線層との間に比誘電率が平均して２．５以下の気体または絶縁物が介在し、前記第１の配線層における少なくとも一つの配線と前記第２の配線層における少なくとも一つの配線との間に所望の導電接続体を設け、さらに前記第１の配線層における所定の配線と前記第２の配線層における所定の配線との間に比誘電率が５以下の絶縁物熱伝導体を設けたことを特徴とする半導体装置。   In a semiconductor device having a multilayer wiring structure on a substrate on which a plurality of semiconductor elements are formed, the relative dielectric constant is averaged between the first wiring layer in the multilayer wiring structure and the second wiring layer thereon. A gas or an insulator of 2.5 or less is interposed, and a desired conductive connector is provided between at least one wiring in the first wiring layer and at least one wiring in the second wiring layer, and An insulating heat conductor having a relative dielectric constant of 5 or less is provided between a predetermined wiring in the first wiring layer and a predetermined wiring in the second wiring layer. 前記第１の配線層と前記第２の配線層との間に絶縁物が介在し、前記絶縁性熱伝導体の熱伝導率が該絶縁物の熱伝導率よりも大きいことを特徴とする請求項７に記載の半導体装置。   An insulator is interposed between the first wiring layer and the second wiring layer, and the thermal conductivity of the insulating thermal conductor is larger than the thermal conductivity of the insulator. Item 8. The semiconductor device according to Item 7. 前記第１の配線層と前記第２の配線層との間に介在する絶縁物が炭素とフッ素とを含有する材料を含むことを特徴とする請求項８に記載の半導体装置。   9. The semiconductor device according to claim 8, wherein the insulator interposed between the first wiring layer and the second wiring layer includes a material containing carbon and fluorine. 前記第１の配線層と前記第２の配線層との間に介在する絶縁物が炭素と水素とを含有する材料を含むことを特徴とする請求項８または９に記載の半導体装置。   10. The semiconductor device according to claim 8, wherein the insulator interposed between the first wiring layer and the second wiring layer includes a material containing carbon and hydrogen. 前記絶縁物熱伝導体が珪素、炭素および窒素を含有する材料を含むことを特徴とする請求項７〜１０のいずれかに記載の半導体装置。   The semiconductor device according to claim 7, wherein the insulator heat conductor includes a material containing silicon, carbon, and nitrogen. 前記絶縁物熱伝導体がＳｉＣＮを含むことを特徴とする請求項１１に記載の半導体装置。
The semiconductor device according to claim 11, wherein the insulator thermal conductor includes SiCN.
JP2006231008A 2006-08-28 2006-08-28 Semiconductor device and multilayer wiring board Expired - Fee Related JP5120913B2 (en)

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US12/310,483 US7977796B2 (en) 2006-08-28 2007-08-24 Semiconductor device and multilayer wiring board
EP07806064A EP2059103A4 (en) 2006-08-28 2007-08-24 Semiconductor device and multilayer wiring board
PCT/JP2007/066478 WO2008026520A1 (en) 2006-08-28 2007-08-24 Semiconductor device and multilayer wiring board
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