JP2008053578A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit which can correct accurately the variation of its manufacturing process being subjected thereto, and can suppress its circuit from becoming large-scale one. <P>SOLUTION: The semiconductor integrated circuit has a plurality of resistors connected in series with each other and interposed between first and second potentials, and dividing the voltage interposed between the first and second potentials to generate a plurality of voltages; has at least a switch circuit connected in parallel with at least a resistor of the plurality of resistors; further, has at least a fuse connected in parallel with at least another resistor of the plurality of resistors, and moreover, has each control circuit for controlling at least a switch circuit according to the control signal fed from the external to bring it into ON/OFF state. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit for generating a plurality of power supply potentials, and more particularly to a semiconductor integrated circuit including a circuit for correcting manufacturing variations.

  For example, a liquid crystal display panel is used in portable terminals such as portable telephones and PDAs (Personal Digital Assistance: personal digital assistants) that have become widespread in recent years. As one method for driving such a liquid crystal display panel, an active matrix method in which a plurality of active elements are arranged for each dot arranged in a two-dimensional matrix on the liquid crystal display panel, and the dots are driven by these active elements. Is used. As an active element, a TFT (Thin Film Transistor) is widely used.

  In order to realize multi-gradation, which is one of the standards for high image quality of a liquid crystal display panel, a gradation voltage generation circuit that generates gradation voltages corresponding to a desired number of gradations is used. Such a gradation voltage generation circuit is constituted by, for example, a plurality of voltage dividing resistors, and a reference voltage supplied from the outside is divided by the plurality of voltage dividing resistors to generate a plurality of gradation voltages. For example, in the case of 8 gradations, the gradation voltage generation circuit generates 8 types of gradation voltages. The gradation voltage generated by the gradation voltage generation circuit is impedance-converted by, for example, an operational amplifier circuit that constitutes a voltage follower circuit, and is applied to the source line of the liquid crystal display panel.

  Incidentally, as one of the characteristics of the liquid crystal display panel, there is a gradation characteristic that represents the relationship between the gradation voltage applied to the source line and the luminance of the liquid crystal display panel. The luminance of the liquid crystal display panel is not proportional to the gradation voltage, and is affected by the characteristics of the liquid crystal and the like constituting the liquid crystal display panel. Therefore, the liquid crystal display panel has, for example, a gradation characteristic peculiar to a manufacturer. Therefore, when the gradation voltage generation circuit is realized in an IC (Integrated Circuit), it is necessary to set the gradation voltage in accordance with the specifications of each liquid crystal display panel. Further, since variations in manufacturing processes occur in individual ICs, such variations may be corrected after the ICs are manufactured.

  In general, trimming is widely known as a means for correcting variations in the manufacturing process. There are various trimming techniques. For example, in order to correct the grayscale voltage in the grayscale voltage generation circuit in the IC, a trimming circuit including a plurality of voltage dividing resistors is used. In such a trimming circuit, a divided voltage value is adjusted by cutting a wiring pattern connecting a plurality of voltage dividing resistors with a laser or the like, and variations in the manufacturing process are corrected.

  The trimming circuit used in the gradation voltage generation circuit in the IC is required to be small-scale, to be able to correct with high accuracy, and to not require time for trimming. In order to satisfy such a requirement, various configurations of trimming circuits have been developed in addition to the trimming circuit configured by a plurality of voltage dividing resistors as described above.

As a related technique, the following Patent Document 1 discloses a tuning circuit that artificially generates a control signal having the same level as that of a cut or non-cut state of a fuse by a signal applied from the outside before the fuse is cut. Is disclosed. According to this tuning circuit, it is described that the result of the characteristic measurement can be obtained before the fuse blow is performed, and the fuse blow is performed based on the result, and the circuit characteristic is tuned to the optimum value. . However, Patent Document 1 does not particularly describe the problem that the tuning circuit constituted by transistors and pads becomes large-scale.
JP-A-7-130183 (first page, FIG. 2)

  Therefore, in view of the above points, an object of the present invention is to provide a semiconductor integrated circuit capable of correcting a variation in a manufacturing process with high accuracy and suppressing an increase in circuit scale. .

  In order to solve the above problems, a semiconductor integrated circuit according to one aspect of the present invention is connected in series between a first potential and a second potential, and between the first potential and the second potential. A plurality of resistors for generating a plurality of voltages, at least one switch circuit connected in parallel to at least one of the plurality of resistors, and at least another one of the plurality of resistors. And at least one fuse connected in parallel, and a control circuit that controls to turn on / off at least one switch circuit in accordance with a control signal supplied from the outside.

  Here, the plurality of resistors include a first group resistor to an Nth group resistor from the first potential side to the second potential side (N ≧ 5), and at least one switch circuit includes the first resistor A plurality of switch circuits connected in parallel to the group resistor, the Mth group resistor, and the Nth group resistor (2 <M <N−1), respectively, and at least one fuse is connected to the second group to the second group. A plurality of fuses connected in parallel to the resistance of the (M-1) group and the resistances of the (M + 1) th to (N-1) th groups may be included.

  Further, the control circuit selects one of a plurality of control signals input from the outside and a plurality of control signals generated by cutting or non-cutting the fuse inside the control circuit, and the selected plurality A selection circuit that supplies the control signal to a plurality of switch circuits may be included.

  According to the present invention, a plurality of resistors that generate a plurality of voltages by dividing a voltage between two power supply potentials, at least one switch circuit connected in parallel to at least one resistor, and at least another one Providing a semiconductor integrated circuit capable of correcting variations in the manufacturing process with high accuracy and suppressing an increase in circuit scale by providing at least one fuse connected in parallel to one resistor can do.

The best mode for carrying out the present invention will be described below in detail with reference to the drawings. In addition, the same reference number is attached | subjected to the same component and description is abbreviate | omitted.
FIG. 1 is a diagram showing a configuration of a liquid crystal module using a semiconductor integrated circuit according to an embodiment of the present invention. In FIG. 1, a gradation voltage generation circuit 100, a source driving circuit 200, a RAM (Random Access Memory) 300, a gate driving circuit 400, and a liquid crystal display panel 500 are shown. The semiconductor integrated circuit (IC) according to an embodiment of the present invention includes at least the gradation voltage generation circuit 100 and may further include one or more of the source driving circuit 200, the RAM 300, and the gate driving circuit 400. .

  The gradation voltage generation circuit 100 generates a plurality of gradation voltages and supplies these gradation voltages to the source driver circuit 200. For example, in the case of 8 gradations, the gradation voltage generation circuit 100 generates 8 types of gradation voltages. The RAM 300 temporarily stores red (R), green (G), and blue (B) image data input from an external MPU (microprocessor) or the like. The source drive circuit 200 converts image data (digital image signal) read from the RAM 300 into an analog image signal based on the gradation voltage supplied from the gradation voltage generation circuit 100, and converts the analog image signal to the liquid crystal display panel 500. Supply to multiple source lines.

  The liquid crystal display panel 500 includes the same number of TFTs arranged in a two-dimensional matrix corresponding to, for example, 720 × 132 dots. The gates of the TFTs in each row are connected to the respective gate lines, and the sources of the TFTs in each column are connected to the respective source lines. The gate driving circuit 400 supplies a high level gate signal to one sequentially selected from a plurality of gate lines of the liquid crystal display panel 500 to which an image signal is supplied.

FIG. 2 is a diagram showing a configuration of the gradation voltage generation circuit 100 shown in FIG.
The gradation voltage generation circuit 100 illustrated in FIG. 2 is supplied with power supply potentials V _DD and V _SS and outputs an operational amplifier (op-amp) 101 that outputs a stabilized power supply potential _VOUT based on the reference potential V _REF. A plurality of resistors 102 to 133 that generate a plurality of output voltages V _OUT 0 to V _OUT 7 by dividing a voltage between the potential V _OUT and the power supply potential V _SS ; a plurality of switch circuits 134 to 145; Fuses 146 to 163 and first to third simulation circuits 170a to 170c. In the present embodiment, it is assumed that the power supply potential V _DD is 5 V, the reference potential V _REF is 3 V, and the power supply potential V _SS is the ground potential (0 V).

The operational amplifier 101 is configured such that the output voltage is negatively fed back to the inverting input terminal. The resistors 102 to 133 are used as negative feedback resistors of the operational amplifier 101, and the connection point between the resistors 102 and 103 is connected to the inverting input terminal of the operational amplifier 101. The resistors 102 to 133 are connected in series from the power supply potential _VOUT to the ground potential (0 V), and the first group of resistors 103 to 106, the second group of resistors 107 to 109, and the third group of resistors 110 are connected. To 112, a fourth group of resistors 113 to 115, a fifth group of resistors 116 to 119, a sixth group of resistors 120 to 122, a seventh group of resistors 123 to 125, and an eighth group of resistors 126. -128 and a ninth group of resistors 129-132.

  Each of the switch circuits 134 to 145 is an analog switch composed of, for example, a P-channel MOS transistor and an N-channel MOS transistor connected in parallel. The switch circuits 134 to 145 are connected in parallel to the resistors 103 to 106, 116 to 119, and 129 to 132 constituting the combined resistors R1 to R3, respectively. For example, the switch circuit 134 is connected in parallel to the resistor 103. When the switch circuit 134 is turned on, both ends of the resistor 103 are short-circuited and a current flows through the switch circuit. When the switch circuit 134 is turned off, the resistor A current flows through 103. The other switch circuits 135 to 145 are the same as the switch circuit 134.

  The fuses 146 to 163 are connected in parallel to the resistors 107 to 115 and 120 to 128 constituting the combined resistors R11 to R16, respectively. For example, the fuse 146 is connected in parallel to the resistor 107, and when the fuse 146 is not cut, a current flows through the fuse 146. When the fuse 146 is cut, the fuse 146 passes through the resistor 107. Current flows. The other fuses 147 to 163 are the same as the fuse 146.

  In FIG. 2, the combined resistance R1 represents the combined resistance of the nodes 1 and 2 determined by the on / off states of the switch circuits 134 to 137. Similarly, the combined resistance R2 represents the combined resistance of the nodes 5 to 6, and the combined resistance R3 represents the combined resistance of the nodes 9 to 10. The combined resistance R11 represents a combined resistance of the nodes 2 to 3 determined by the cut states of the fuses 146 to 148. Similarly, the combined resistance R12 represents the combined resistance of the nodes 3 to 4, the combined resistance R13 represents the combined resistance of the nodes 4 to 5, and the combined resistance R14 represents the combined resistance of the nodes 6 to 7. The combined resistance R15 represents the combined resistance of the nodes 7 to 8, and the combined resistance R16 represents the combined resistance of the nodes 8 to 9.

The output voltage V _OUT 7 is output from the connection point between the resistor 106 and the resistor 107, the output voltage V _OUT 6 is output from the connection point between the resistor 109 and the resistor 110, and the output voltage is output from the connection point between the resistor 112 and the resistor 113. V _OUT 5 is output, and the output voltage V _OUT 4 is output from the connection point between the resistor 115 and the resistor 116. The output voltage V _OUT 3 is output from the connection point between the resistor 119 and the resistor 120, the output voltage V _OUT 2 is output from the connection point between the resistor 122 and the resistor 123, and the connection point between the resistor 125 and the resistor 126. The output voltage V _OUT 1 is output, and the output voltage V _OUT 0 is output from the connection point between the resistor 132 and the resistor 133. Note that, by connecting a plurality of voltage followers to the connection points of these resistors, the output voltages V _OUT 0 to V _OUT 7 may be output via the plurality of voltage followers, respectively.

  The first simulation circuit 170 a includes a selector circuit 171, pull-up resistors 172 to 175 and fuses 176 to 179 connected to the selector circuit 171. The selector circuit 171 is a general-purpose data selector or multiplexer, and is supplied with input terminals A0 and A1, B0 and B1, C0 and C1, D0 and D1, output terminals Y0 to Y3, and a selection signal SEL from the outside. Input terminal S. Control signals CTL1 to CTL4 supplied from the outside are input to input terminals A0 to D0 of the selector circuit 171 via input terminals P1 to P4, respectively.

The input terminal A1 of the selector circuit 171 is pulled up to the power supply potential V _DD via the resistor 172 and connected to the ground potential via the fuse 176. Accordingly, when the fuse 176 is not cut, the input terminal A1 is at a low level, and when the fuse 176 is cut, the input terminal A1 is at a high level. Similarly, the input terminals B1, C1, and D1 are connected to the power supply potential V _DD through the resistors 173, 174, and 175, and are connected to the ground potential through the fuses 177, 178, and 179, respectively.

  When the selection signal SEL is activated or deactivated, one of the signal input to the input terminal A0 and the signal input to the input terminal A1 is selected, and the signal input to the input terminal B0 One of the signals input to the input terminal B1 is selected, and one of the signal input to the input terminal C0 and the signal input to the input terminal C1 is selected and input to the input terminal D0. One of the signal and the signal input to the input terminal D1 is selected. The selected signal is output from the output terminals Y0 to Y3.

  Since the logic values of the signals output from each of the output terminals Y0 to Y3 of the selector circuit 171 are two levels of high level or low level, the states of the logic values of the four signals output from the output terminals Y0 to Y3 are as follows. There will be 16 ways. Corresponding to these 16 states, ON / OFF of the switch circuits 134 to 137 is set.

  In this embodiment, when the signals output from the output terminals Y0 to Y3 of the selector circuit 171 become high level, the switch circuits 134 to 137 are turned on, respectively, and when the signals output from the output terminals Y0 to Y3 become low level. The switch circuits 134 to 137 are turned off. For example, when the control signals CTL1 and CTL2 are at a high level and the control signals CTL3 and CTL4 are at a low level, the switch circuits 134 and 135 are turned on, the switch circuits 136 and 137 are turned off, and the combined resistor R1 Is the sum of the resistance values of the resistors 105 and 106.

  The configurations of the second and third simulation circuits 170b and 170c are the same as those in the first simulation circuit 170a. Control signals CTL5 to CTL8 are input to the second simulation circuit 170b from the outside via input terminals P5 to P8, and the switch circuits 138 to 141 are controlled by signals output from the second simulation circuit 170b. In addition, control signals CTL9 to CTL12 are input from the outside to the third simulation circuit 170c via the input terminals P9 to P12, and the switch circuits 142 to 145 are controlled by signals output from the third simulation circuit 170c. The

  When the selection signal SEL supplied to the selector circuit 171 of the simulation circuits 170a to 170c is activated, the input terminals A0 to D0 are validated and the input terminals A1 to D1 are invalidated. Therefore, the selector circuit 171 of the simulation circuits 170a to 170c selects the control signals CTL1 to CTL12 input via the input terminals P1 to P12.

  If the resistance values of the resistors 103 to 106 are set to be different from each other, the first simulation circuit 170a controls the switch circuits 134 to 137 in accordance with the control signals CTL1 to CTL4, so that the resistance value of the combined resistor R1 is sixteen. Can be adjusted. Similarly, the second simulation circuit 170b can adjust the resistance value of the combined resistor R2 in 16 ways by controlling the switch circuits 138 to 141 according to the control signals CTL5 to CTL8. Further, the third simulation circuit 170c can adjust the resistance value of the combined resistor R3 in 16 ways by controlling the switch circuits 142 to 145 according to the control signals CTL9 to CTL12.

FIG. 3 is a diagram showing specifications of voltage values of the output voltages V _OUT 0 to V _OUT 7 shown in FIG. Output voltages V _OUT 0 to V _OUT 7 shown in FIG. 2 are supplied as grayscale voltages to the source driver circuit 200 shown in FIG. The luminance of the liquid crystal display panel 500 is determined by the gradation voltage applied to the source line of the TFT included therein, and the relationship between the gradation voltage and the luminance of the liquid crystal display panel is not linear. It is known that it becomes a non-linear (gamma curve) corresponding to.

In FIG. 3, the solid line represents the specification of the product 1 (hereinafter referred to as “specification curve 1”), and the broken line represents the specification of the product 2 (hereinafter referred to as “specification curve 2”). According to the specifications of those products, the gradation voltage output circuit 100 is required to generate the output voltages V _OUT 0 to V _OUT 7 having the voltage value indicated by the specification curve 1 or 2.

FIG. 4 is a diagram for explaining a standard range related to the specification curve 1 shown in FIG. Variations in the manufacturing process occur in the voltage values of the output voltages V _OUT 0 to V _OUT 7, but if the variation is within the standard range between the specification upper limit value and the specification lower limit value, the IC is good. It is judged that. The standard range may vary depending on each output voltage as indicated by the arrows in FIG. 4. For example, the standard range of the output voltage V _OUT 0 is 0.3 V to 0.7 V, and the output voltage V _OUT 3 The standard range is 1.1V to 1.7V, and the standard range of the output voltage V _OUT 7 is 1.3V to 2.1V. Therefore, for example, the output voltage V _OUT 3 does not have to be 1.4 V shown on the specification curve 1 as long as it is within the range of 1.1V to 1.7V.

However, due to variations in the manufacturing process of the IC, and power supply potential _{V OUT} output from the operational amplifier 101, the output voltage _V OUT _{0 to V OUT} 7 output from each of the nodes is affected, the output voltage _{V OUT} 0 The voltage value of .about.V _OUT 7 is not necessarily within the standard range as shown in FIG. Therefore, the trimming circuit is used to correct such variations in the manufacturing process. In FIG. 2, a plurality of resistors 103 to 132, a plurality of switch circuits 134 to 145, a plurality of fuses 146 to 163, and first to third simulation circuits 170a to 170c correspond to a trimming circuit.

Hereinafter, a trimming method for correcting variations in the output voltages V _OUT 0 to V _OUT 7 shown in FIG. 2 will be described with reference to FIGS. 4 and 5. FIG. 5 is a flowchart showing a trimming method for correcting variations in the output voltages V _OUT 0 to V _OUT 7. In general, the trimming method as shown in FIG. 5 is executed by using an LSI tester. Here, it is assumed that trimming is performed according to the specification curve 1 shown in FIGS.

First, in step S10, the voltage values of the output voltages V _OUT 0, V _OUT 3 and V _OUT 7 are simulated using the first to third simulation circuits 170a to 170c. In this simulation, the selection signal SEL supplied to the selector circuit 171 is activated, and the control signals CTL1 to CTL12 are activated or deactivated so that the output voltage V _OUT when the fuses 146 to 163 are connected is used. The voltage values of 0, V _OUT 3 and V _OUT 7 are adjusted.

The values of the output voltages V _OUT 0, V _OUT 3 and V _OUT 7 when the fuses 146 to 163 are connected are different from the value of the specification curve 1 achieved after the fuse is blown. Therefore, the target center value and target range of the output voltages V _OUT 0, V _OUT 3 and V _OUT 7 when the fuses 146 to 163 are connected are the specification curve 1 and the standard range related thereto, and the transistor characteristics in the IC. And based on the design center value of the resistance value. When the transistor characteristics and resistance values are design center values, the value of the power supply potential V _OUT is uniquely calculated. Therefore, the output voltages V _OUT 0 and V _OUT when the fuses 146 to 163 are connected are used. 3, the target center value of V _OUT 7 is also uniquely calculated as shown in the following equations (1) to (3).

  In addition, when the transistor characteristics and the resistance values are design center values, it is assumed in advance which of the switches 134 to 145 is turned on and which is turned off, so that the control signals CTL1 to CTL12 are in accordance therewith. Is activated or deactivated. As a result, the values of the combined resistors R1 to R3 are determined.

In step S11, the values of the power supply potential V _OUT and the output voltages V _OUT 0, V _OUT 3 and V _OUT 7 are measured. If the output voltage values are within the target range, the control signals CTL1 to CTL12 are output. Information about the logical value is stored in the memory or the like of the LSI tester. On the other hand, if the values of the output voltages V _OUT 0, V _OUT 3 and V _OUT 7 are not within the target range, the process returns to step S10 and the control signals CTL1 to CTL12 are set so that these values approach the target center value. Change state. As shown in the equations (1) to (3), the variation in the value of the power supply potential _VOUT can be canceled by adjusting the values of the combined resistors R1 to R3. As a result, if the values of the output voltages V _OUT 0, V _OUT 3 and V _OUT 7 fall within the target range, information relating to the logic values of the control signals CTL1 to CTL12 is stored in the LSI tester memory or the like.

Alternatively, in steps S10 to S11, the values of the combined resistors R1 to R3 may be determined so that the values of the output voltages V _OUT 0, V _OUT 3 and V _OUT 7 are closest to the target center value. In any case, the fuse to be cut among the fuses 176 to 179 can be determined based on the information regarding the logical values of the control signals CTL1 to CTL12 determined in steps S10 to S11. That is, among the fuses 176 to 179 in the first to third simulation circuits 170a to 170c, the fuse of the input system corresponding to the high level control signal is cut later.

Next, in step S12, based on the values of the combined resistors R1 to R3 determined in step S10, the output voltages V _OUT 0 to V _OUT 7 are predicted when some of the fuses 146 to 163 are cut. A value is calculated. Here, the first group of fuses 146 to 148, the second group of fuses 149 to 151, the third group of fuses 152 to 154, the fourth group of fuses 155 to 157, and the fifth group of fuses 158 to 158 In each group 160, at least one fuse shall be blown. In the sixth group of fuses 161 to 163, the fuses may or may not be cut.

The predicted values of the output voltages V _OUT 0 to V _OUT 7 are expressed by the following equations (4) to (11).

  In the above formulas (4) to (11), (R11 to R16) represents the sum of the values of the combined resistors R11 to R16. Similarly, (R14 to R16) represents the sum of the values of the combined resistors R14 to R16, (R13 to R16) represents the sum of the values of the combined resistors R13 to R16, and (R12 to R16) represents the combined resistors. It represents the sum of the values of R12 to R16.

The values of the combined resistors R11 to R16 are determined so that the values of the output voltages V _OUT 0 to V _OUT 7 represented by the equations (4) to (11) are within the standard range of the specification curve 1, and accordingly The fuse to be cut is determined. For example, the fuse to be cut among the fuses 146 to 163 is selected by minimizing the error between the predicted value of the output voltages V _OUT 0 to V _OUT 7 and the target center value by the least square method or the like. .

Here, since the values of the combined resistors R1 to R3 are determined with high accuracy by the simulation in steps S10 to S11, by determining the values of the combined resistors R11 to R16 based on these values, the output voltage V _OUT An accurate value of 0 to V _OUT 7 is determined. That is, in the IC manufacturing process, transistor characteristics and resistance values vary to some extent, but the resistance ratio can be reproduced fairly accurately. In the expressions (1) to (3), the variation in the value of the power supply potential _VOUT has already been canceled by adjusting the values of the combined resistors R1 to R3. If the values of the combined resistors R11 to R16 are determined corresponding to the values of the resistors R1 to R3, the influence of variations in the IC manufacturing process can be reduced.

  Information on the fuse to be cut determined in step S12 is stored as trimming information in a memory or the like of the LSI tester together with information on the logical values of the control signals CTL1 to CTL12 determined in steps S10 to S11.

  Next, in step S13, trimming is executed based on the trimming information stored in the memory or the like of the LSI tester. In the present embodiment, the fuse is cut by a laser.

After the trimming is finished, the selection signal SEL is set to the low level, so that the input terminals A0 to D0 of the selector circuit 171 are invalidated, the input terminals A1 to D1 are validated, and the switches are switched according to the cut states of the fuses 176 to 179. On / off of the circuits 134 to 145 is set. When the values of the output voltages V _OUT 0 to V _OUT 7 are measured in this state, for example, points A to H as shown in FIG. 4 are obtained. Since the measured values of the output voltages V _OUT 0 to V _OUT 7 are within the standard range of the specification curve 1, the luminance of the liquid crystal display panel 500 shown in FIG. 1 can be within the standard range. If the measured value does not fall within the standard range of the specification curve 1, the IC may be determined as a defective product, or the values of the combined resistors R1 to R3 may be readjusted by returning to step S10 again. good.

  Note that the present invention is not only applied to semiconductor integrated circuits in the field of liquid crystal technology as described in the above embodiments, but also applied when correcting variations in the manufacturing process of semiconductor integrated circuits in other technical fields. Can do.

In general, a trimming circuit that changes the resistance value by cutting a fuse is difficult to perform trimming with high accuracy, but the circuit scale can be reduced. On the other hand, the trimming circuit that controls the switch circuit by the control signal increases the circuit scale, but can perform trimming with high accuracy. Therefore, in the present invention, in order to divide the voltage between the first potential (the power supply potential V _{OUT in} FIG. 2) and the second potential (the power supply potential V _{SS in} FIG. 2), a plurality of series connected By connecting a switch circuit in parallel to at least one of the resistors and connecting a fuse in parallel to the other resistor, trimming can be performed with high accuracy without enlarging the circuit scale. .

  In particular, when the plurality of resistors include resistors of the first group to the Nth group (N ≧ 5) from the first potential side toward the second potential side, the resistance of the first group and the Mth group ( By providing a plurality of switch circuits connected in parallel to a resistance of 2 <M <N−1) and a resistance of the Nth group, the maximum output voltage, the minimum output voltage, and the intermediate output voltage that are essential And can be adjusted with high accuracy. Further, by providing a plurality of fuses connected in parallel to the resistance of the second group to the (M-1) group and the resistance of the (M + 1) group to the (N-1) group, The output voltage can be adjusted with a small circuit scale. The voltage divided by the plurality of resistors is output from one end of each group of resistors.

1 is a diagram showing a liquid crystal module using a semiconductor integrated circuit according to an embodiment of the present invention. FIG. 2 is a diagram illustrating a configuration of a gradation voltage generation circuit 100 illustrated in FIG. 1. It shows a specification of a voltage value of the output voltage _V OUT _{0 to V OUT} 7 shown in FIG. The figure for demonstrating the standard range regarding the specification curve 1 shown in FIG. The flowchart which shows the trimming method in one Embodiment of this invention.

Explanation of symbols

  100 gradation voltage generation circuit, 101 operational amplifier, 102 to 133, 172 to 175 resistor, 134 to 145 switch circuit, 146 to 163, 176 to 179 fuse, 170a to 170c first to third simulation circuits, 171 selector circuit 200 source drive circuit, 300 RAM, 400 gate drive circuit, 500 liquid crystal display panel

Claims (3)

A plurality of resistors connected in series between the first potential and the second potential, and generating a plurality of voltages by dividing the voltage between the first potential and the second potential;
At least one switch circuit connected in parallel to at least one of the plurality of resistors;
At least one fuse connected in parallel to at least one other of the plurality of resistors;
A control circuit for controlling the at least one switch circuit to be turned on / off according to a control signal supplied from the outside;
A semiconductor integrated circuit comprising: The plurality of resistors include a first group resistor to an Nth group resistor from the first potential side to the second potential side (N ≧ 5),
The at least one switch circuit includes a plurality of switch circuits connected in parallel to a first group of resistors, an Mth group of resistors, and an Nth group of resistors (2 <M <N−1),
The at least one fuse includes a plurality of fuses connected in parallel to a resistance of the second group to the (M−1) group and a resistance of the (M + 1) group to the (N−1) group, respectively.
The semiconductor integrated circuit according to claim 1. The control circuit selects one of a plurality of control signals input from the outside and a plurality of control signals generated by cutting or non-cutting of a fuse inside the control circuit, and the selected plurality The semiconductor integrated circuit according to claim 2, further comprising: a selection circuit that supplies the control signal to the plurality of switch circuits.

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