JP2008053399A - Semiconductor structure and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor structure for controlling effectively the generating of a crack when a semiconductor layer made of different material from substrate material is formed on the substrate, and to provide a manufacturing method of the semiconductor structure. <P>SOLUTION: The semiconductor structure 10 is formed from a silicon substrate 1 of orientation (111) with diameter of 3 inches; an AlN layer 2 formed on a silicon substrate 1; an InAlN/BAlN super lattice layer 11 formed on the AlN layer 2, Al<SB>0.9-0.9u</SB>Ga<SB>0.1+0.9u</SB>N(u=0→1) layer 12 formed on the superlattice layer 11; and a GaN layer 13 having film thickness of 5 μm and made of material different from that of the silicon substrate 1, formed on the AlGaN layer 12. The super lattice layer 11 is formed from In<SB>0.2</SB>Al<SB>0.8</SB>N layers 14 with film thickness of 45 nm and B<SB>0.1</SB>Al<SB>0.9</SB>N layers 15 with film thickness of 5 nm in 30 pairs. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor structure in which a substrate and a semiconductor layer formed on the substrate are made of different materials, and a method for manufacturing the semiconductor structure.

Conventionally, a technique for forming a semiconductor layer on a substrate made of a material different from that of the semiconductor layer has attracted attention for reasons such as cost reduction of the substrate. In particular, since nitride compound semiconductors (GaN, AlN, InN, BN, and mixed crystals thereof) are difficult to produce a substrate using the same material, on a substrate made of a material different from the semiconductor layer described above. In addition, film formation is performed on a sapphire substrate or a silicon carbide substrate, which is a different material, using a technique for growing the semiconductor layer. However, since the sapphire substrate has low thermal conductivity, the sapphire substrate is not suitable for high-power electronic device applications that easily generate heat. In addition, since the manufacturer of the silicon carbide substrate is virtually monopolized, the procurement cost becomes very high. Therefore, in recent years, attempts have been made to form a nitride-based compound semiconductor layer using a silicon substrate that is inexpensive, can be stably supplied, and has a large diameter. The problem when forming a film on a silicon substrate is that the thermal expansion coefficient of silicon and the thermal expansion coefficient of a nitride compound semiconductor are different. Is added, and cracks are likely to occur. In addition, distortion resulting from the difference between the lattice constant of silicon and the lattice constant of the nitride-based compound semiconductor is easily added. In view of this, a method has been devised that suppresses the occurrence of the above-described cracks when a nitride compound semiconductor layer is formed on the silicon substrate (see Patent Document 1). The method for suppressing the occurrence of cracks is to suppress the occurrence of cracks by inserting a layer for relaxing strain between the silicon substrate and the target nitride-based compound semiconductor layer.
JP-A-5-343741

  However, in the above-described method for suppressing the occurrence of cracks, when the silicon substrate is enlarged or the thickness of the semiconductor layer made of a material different from the substrate material is increased, the amount of strain generated increases. However, there was a problem that it was not possible to sufficiently relax and the occurrence of cracks could not be suppressed.

  The present invention has been made in view of these problems, and a semiconductor structure and a semiconductor capable of effectively suppressing generation of cracks that occur when a semiconductor layer made of a material different from a substrate material is formed on the substrate. An object is to provide a method of manufacturing a structure.

  In order to achieve the above object, a semiconductor structure according to the present invention includes at least a buffer layer formed on a substrate and a semiconductor layer formed on the buffer layer with a material different from the material of the substrate. The buffer layer is made of a nitride-based semiconductor material containing In and B.

According to a second aspect of the present invention, in the semiconductor structure according to the present invention, the buffer layer includes In _w B _v Al _1-wv N (0 <w <1, 0 <v <1, w + v ≦ 1) It is characterized by comprising layers.

Further, as described in claim 3, in the semiconductor structure according to the present invention, the buffer layer is at _{least, In x Al 1-x N} (0 <x ≦ 1) layer and the _B y _{Al 1-y} N ( It is characterized by comprising a repeating structure with 0 <y ≦ 1) layers.

In addition, as described in claim 4, in the semiconductor structure according to the present invention described in claim 3, the In _x Al _1-x N layer and the B _y Al _1-y N layer have a composition gradient structure. It is characterized by having.

Further, as described in claim 5, in are in the semiconductor structure according to the present invention as set forth in claim 3, wherein the buffer layer, wherein the _{In x Al 1-x} N layer _{B y Al 1-y} N layer during the _is characterized in that it comprises _{in s B t Al 1-s} -t N (0 <s <1,0 <t <1, s + t ≦ 1) layer and.

  Further, as described in claim 6, in the semiconductor structure according to any one of claims 1 to 5, the material of the substrate is silicon.

  According to a seventh aspect of the present invention, in the semiconductor structure according to the sixth aspect of the present invention, the plane orientation of the substrate is (111) and a plane orientation equivalent thereto.

Further, as described in claim 8, in the semiconductor structure according to any one of claims 1 to 7, a uniform composition structure or a composition gradient structure is provided on one or both of the upper and lower sides of the buffer layer. It has an Al _z Ga _1-z N (0 ≦ z ≦ 1) layer.

  Further, as described in claim 9, in the semiconductor structure according to any one of claims 1 to 8, the semiconductor layer is a GaN layer having a thickness of at least 1 μm or more. It is a feature.

  According to a tenth aspect of the present invention, in the method of manufacturing a semiconductor structure according to the present invention, a buffer layer made of a nitride-based semiconductor material containing In and B is formed on a substrate, which is different from the material of the substrate A semiconductor layer is formed of the material on the buffer layer.

  According to the present invention, since the semiconductor layer made of a material different from the substrate and the buffer layer between the substrate are formed of the nitride-based semiconductor material containing In and B, the semiconductor layer is formed on the substrate. Even if the amount of generated strain increases, the generation of cracks can be effectively suppressed.

In addition, by providing an Al _z Ga _1-z N (0 ≦ z ≦ 1) layer having a uniform composition structure or a composition gradient structure on one or both of the upper and lower sides of the buffer layer, Al _z Ga _1-z N (0 ≦ z ≦ 1) The gap between the lattice constant of the layer bonded to the layer and the lattice constant of the buffer layer can be relaxed.

  Hereinafter, semiconductor stacked structures 10 to 50, which are semiconductor structures according to the first to fifth embodiments of the present invention, will be described with reference to FIGS.

(First embodiment)
A semiconductor multilayer structure 10 according to the first embodiment will be described with reference to FIG. FIG. 1 is a diagram illustrating a semiconductor multilayer structure 10 according to the first embodiment. The semiconductor multilayer structure 10 according to the first embodiment includes a silicon substrate 1 having a diameter of 3 inches and a plane orientation (111), an AlN layer 2 formed on the silicon substrate 1, and an AlN layer 2 having a uniform composition structure. InAlN / BAlN superlattice layer (hereinafter referred to as a superlattice layer) 11 which is a buffer layer formed on the substrate, and Al _z Ga _1-z N (0) having a composition gradient structure formed on the superlattice layer 11. ≦ z ≦ 1) Al _0.9-0.9u Ga _{0.1 + 0.9u} N (u = 0 → 1) layer 12 and a material different from the material of silicon substrate 1 are formed on AlGaN layer 12. The GaN layer 13 having a film thickness of 5 μm, which is a semiconductor layer. The variable u of the Al composition ratio z = 0.9−0.9u of the AlGaN layer 12 is 0 on the superlattice layer 11 side and 1 on the GaN layer 13 side. From this, the AlGaN layer 12 is well connected to the GaN layer 13. Further, the superlattice layer 11 which is a characteristic part of the present invention includes 30 layers of an In _0.2 Al _0.8 N layer 14 having a thickness of 45 nm and a B _0.1 Al _0.9 N layer 15 having a thickness of 5 nm. Formed in pairs.

Hereinafter, In _x Al _1-x N (0 <x ≦ 1) and B _y Al _1-y N (0 <y ≦ 1) will be described. Conventionally, InAlN and BAlN have not been considered to be used in a multilayer structure because good crystal quality cannot be obtained by their growth alone. InAlN and BAlN are both based on AlN and added with indium In and boron B. However, the addition of indium In and boron B exhibits completely different characteristics. In InInN to which indium In is added, indium In has an effect of reducing crystal defects, and indium In increases the tolerance of lattice distortion of InAlN as compared with AlN, so that cracks are hardly generated. Further, when the composition ratio x of indium In is increased, the lattice constant of InAlN is closer to GaN than that of AlN until the composition ratio x = 0.17 of indium In. To loosen. Further, when the composition ratio x of indium In is increased from 0.17, the lattice constant of InAlN becomes larger than that of GaN, so that the InAlN layer is subjected to compressive strain, but the composition ratio x of indium In is Since it increases, the tolerance of lattice distortion also increases. When the composition ratio x of indium In is increased to 0.4, crystal defects increase. Therefore, the composition ratio x of indium In in InAlN is desirably 0.4 or less.

  On the other hand, in BAlN to which boron B is added, the lattice constant of BAlN is smaller than that of AlN, and the growth surface is appropriately roughened. In addition, since the thermal expansion coefficient in the plane direction of BAlN is closer to that of the Si substrate than that of AlN according to the composition ratio y of boron B, the crystal growth layer and the Si substrate during the crystal growth and during the temperature drop after the growth. And cracks due to differences in thermal expansion coefficient are difficult to enter. However, when the composition ratio y of boron B is increased to 0.2, the growth proceeds locally from the hexagonal system to the cubic system. Therefore, the composition ratio y of boron B in BAlN is 0.2. The following is desirable.

The properties of the above InAlN and BAlN have a large difference compared to the conventional layers of AlN, AlGaN, etc., and the combination of two layers of InAlN and BAlN having completely different properties makes it possible to prevent lattice distortion. Excellent properties as a buffer layer. When the buffer layer is composed of the In _0.2 Al _0.8 N layer 14 and the B _0.1 Al _0.9 N layer 15 of the first embodiment, the characteristics as the buffer layer are In _0.2 Al _{0. .8 The} number of combinations of two layers of the N layer 14 and the B _0.1 Al _0.9 N layer 15 is expressed from at least 4 pairs. However, when growing the GaN layer 13 on the large-diameter silicon substrate 1 having a diameter of 3 inches, it is desirable to deposit 10 pairs or more from the strain tolerance of the buffer layer. In the first embodiment, as the buffer layer, In Superlattice layer 11 is formed in which the number of combinations of two layers of _0.2 Al _0.8 N layer 14 and B _0.1 Al _0.9 N layer 15 is 30 pairs. _The thickness of the In 0.2 _{Al 0.8} N layer 14 and the _B 0.1 _{Al 0.9} N layer _15, an In 0.2 _{Al 0.8} N layer 14 and the _B 0.1 _{Al 0.9} The N layer 15 needs to have a film thickness that does not express each property alone, and is desirably 300 nm or less. In the first embodiment, the thickness of the In _0.2 Al _0.8 N layer 14 is 45 nm, and the thickness of the B _0.1 Al _0.9 N layer 15 is 5 nm. Furthermore, in the first embodiment, when the target GaN layer 13 is deposited on the superlattice layer 11, the gap between the average lattice constant of the superlattice layer 11 and the lattice constant of the target GaN layer 13 is relaxed. In order to achieve this, an Al _0.9-0.9u Ga _{0.1 + 0.9u} N (u = 0 → 1) layer 12 is inserted between the superlattice layer 11 and the GaN layer 13. Further, in order to make the initial growth state of the superlattice layer 11 formed on the silicon substrate 1 better, the AlN layer 2 having excellent wettability and effectively acting as a nucleation layer is formed with the silicon substrate 1 and It is inserted between the lattice layers 11.

Next, a method for manufacturing the semiconductor multilayer structure 10 according to the first embodiment will be described. First, the silicon substrate 1 having a diameter of 3 inches and a plane orientation (111) is washed with an RCA method or a hydrofluoric acid solution to obtain a clean surface. Next, the cleaned silicon substrate 1 is loaded into the MOCVD apparatus, and the temperature is raised in a hydrogen atmosphere to perform thermal cleaning. After the cleaning, first, the AlN layer 2 is crystal-grown, and then the In _0.2 Al _0.8 N layer 14 and the B _0.1 Al _0.9 N layer 15 are alternately grown. Next, the Al composition ratio z = 0.9-0.9u is decreased in order from the side closer to the silicon substrate 1 in the Al _0.9-0.9u Ga _{0.1 + 0.9u} N (u = 0 → 1) layer 12. The connection with the GaN layer 13 to be grown next is improved. Finally, the target GaN layer 13 is grown by 5 μm. For the growth of these layers, a metal organic vapor phase epitaxy (MOVPE) method excellent in supply of nitrogen atoms N as a group V raw material is used.

As a result, when a 5 μm GaN layer 13 is to be deposited on a silicon substrate 1 having a diameter of 3 inches and a plane orientation (111), if there is no superlattice layer 11 as a buffer layer, the GaN layer 13 is latticed in the middle. Although it cannot withstand the strain and cracks occur, as in the first embodiment, the In _0.2 Al _0.8 N layer 14 with a film thickness of 45 nm and the B _0.1 Al _0.9 with a film thickness of 5 nm are formed. By using the superlattice layer 11 in which 30 pairs of N layers 15 are deposited, a 5 μm GaN layer 13 can be deposited without cracks. In addition, when the GaN layer 13 is measured on the upper side, that is, with the silicon substrate 1 on the lower side, the warpage of the grown silicon substrate 1 is that of the silicon substrate 1 having a diameter of 3 inches. It was 30 μm upward in the center. Further, it was confirmed by visual observation that no crack was generated.

As described above, the superlattice layer 11 used in the semiconductor multilayer structure 10 according to the first embodiment includes the In _0.2 Al _0.8 N layer 14 having a thickness of 45 nm and the B _0.1 Al having a thickness of 5 nm. _The GaN layer 13 is formed on the silicon substrate 1 by increasing the diameter of the silicon substrate 1 or increasing the film thickness of the GaN layer 13 by forming 30 pairs with the _0.9 N layer 15. Indium Al in the In _0.2 Al _0.8 N layer 14 has an effect of reducing crystal defects even when the amount of strain generated when forming the Al is increased. In _{0.2 In 0 .8} the tolerance lattice distortion N layer 14 is increased than _AlN, the boron B of B 0.1 _{Al 0.9} N layer 15, as compared to the thermal expansion coefficient of _{AlN, B} 0.1 Al _0.9 thermal expansion coefficient in the planar direction of the N layer 15 Since it is closer to the thermal expansion coefficient of the silicon substrate 1, the difference in thermal expansion coefficient between the crystal growth layer and the silicon substrate 1 is reduced during the crystal growth and during the temperature drop after the growth, thereby effectively suppressing the generation of cracks. be able to. Furthermore, in the first embodiment, an Al _0.9-0.9u Ga _{0.1 + 0.9u} N (u = 0 → 1) layer 12 having a composition gradient structure between the superlattice layer 11 and the GaN layer 13. Therefore, the gap between the average lattice constant of the superlattice layer 11 and the lattice constant of the GaN layer 13 can be relaxed. Therefore, the change in the lattice constant of the semiconductor multilayer structure 10 can be moderated, and the lattice distortion can be effectively reduced. In addition, since the AlN layer 2 which is excellent in wettability and also effectively functions as a nucleation layer is inserted between the silicon substrate 1 and the superlattice layer 11, the superlattice layer 11 formed on the silicon substrate 1 is inserted. The initial growth state can be made better.

(Second Embodiment)
Next, the semiconductor multilayer structure 20 according to the second embodiment will be described with reference to FIG. 2 focusing on differences from the semiconductor multilayer structure 10 according to the first embodiment. Further, in the semiconductor multilayer structure 20 according to the second embodiment, the same number is assigned to the same structure as the semiconductor multilayer structure 10 according to the first embodiment, and the description is omitted. The manufacturing method of the semiconductor multilayer structure 20 according to the second embodiment is the same as the manufacturing method of the semiconductor multilayer structure 10 according to the first embodiment.

FIG. 2 is a view showing a semiconductor multilayer structure 20 according to the second embodiment. The semiconductor multilayer structure 20 according to the second embodiment includes a silicon substrate 1 having a diameter of 3 inches and a plane orientation (111), an AlN layer 2 formed on the silicon substrate 1, and a buffer formed on the AlN layer 2. In _w B _v Al _1- wv N (0 <w <1, 0 <v <1, w + v ≦ 1) layer 21 and Al _z Ga _1-z N formed on the InBAlN layer 21 (0 ≦ z ≦ 1) layer 22 and AlInGaN layer 23 which is a semiconductor layer formed on AlGaN layer 22 with a material different from the material of silicon substrate 1. Here, in the second embodiment, the composition ratio w of the InBAlN layer 21 is 0.1, the composition ratio v is 0.05, and the film thickness is 5 μm. Further, since the composition ratio z = 0.3 of the AlGaN layer 22 is set, the AlGaN layer 22 has a uniform composition structure. Furthermore, the film thickness of the AlInGaN layer 23 is 1 μm. From this, also in the semiconductor multilayer structure 20 of the second embodiment, since the In _0.1 B _0.05 Al _0.85 N layer 21 is used, it is possible to obtain the same effect as that of the first embodiment. it can.

(Third embodiment)
Next, a semiconductor multilayer structure 30 according to the third embodiment will be described with reference to FIG. 3 focusing on differences from the semiconductor multilayer structure 10 according to the first embodiment. Further, regarding the semiconductor multilayer structure 30 according to the third embodiment, the same structure as that of the first embodiment is denoted by the same reference numeral, and the description thereof is omitted. The method for manufacturing the semiconductor multilayer structure 30 according to the third embodiment is the same as the method for manufacturing the semiconductor multilayer structure 10 according to the first embodiment.

FIG. 3 is a view showing a semiconductor multilayer structure 30 according to the third embodiment. The semiconductor multilayer structure 30 according to the third embodiment includes a silicon substrate 1 having a diameter of 3 inches and a plane orientation (111), an AlN layer 2 formed on the silicon substrate 1, and a buffer formed on the AlN layer 2. InAlN / InBAlN / BAlN superlattice layer 31 and Al _0.9-0.9u Ga _{0.1 + 0.9u} N (u = 0 → 1) formed on InAlN / InBAlN / BAlN superlattice layer 31 The layer 12 and the GaN layer 13 which is a semiconductor layer formed on the AlGaN layer 12 with a material different from the material of the silicon substrate 1 are formed. The variable u of the Al composition ratio z = 0.9−0.9u of the AlGaN layer 12 is 0 on the superlattice layer 11 side and 1 on the GaN layer 13 side. From this, the AlGaN layer 12 is well connected to the GaN layer 13.

Here, the InAlN / InBAlN / BAlN superlattice layer 31 which is a characteristic part of the third embodiment includes an In _x Al _1-x N (0 <x ≦ 1) layer 32 having a thickness of 20 nm and a thickness of 10 nm. of _{in s B t Al 1-s} -t N (0 <s <1,0 <t <1, s + t ≦ 1) and the layer 33, of thickness _{30nm B y Al 1-y N} (0 <y ≦ 1 a) layer 34, is formed by 50 pairs of _{in s B t Al 1-s} -t N (0 <s <1,0 <t <1, s + t ≦ 1) N layer 33 having a thickness of 10 nm. Furthermore, the composition ratio x = 0.4, y = 0.2, s = 0.2, and t = 0.1 of the InAlN / InBAlN / BAlN superlattice layer 31 are set. From this, also in the semiconductor multilayer structure 30 of the third embodiment, since the InAlN / InBAlN / BAlN superlattice layer 31 is used, the same effects as those of the first embodiment can be obtained. In the third embodiment, the In _0.2 B _0.1 Al _0.7 N layer 33 is interposed between the In _0.4 Al _0.6 N layer 32 and the B _0.2 Al _0.8 N layer 34. Therefore, the change in the lattice constant in the InAlN / InBAlN / BAlN superlattice layer 31 can be moderated. Therefore, the lattice distortion generated in the InAlN / InBAlN / BAlN superlattice layer 31 can be effectively reduced.

(Fourth embodiment)
Next, a semiconductor multilayer structure 40 according to the fourth embodiment will be described with reference to FIG. 4 focusing on differences from the semiconductor multilayer structure 10 according to the first embodiment. Further, in the semiconductor multilayer structure 40 according to the fourth embodiment, the same number is assigned to the same structure as that of the first embodiment, and the description is omitted. The method for manufacturing the semiconductor multilayer structure 40 according to the fourth embodiment is the same as the method for manufacturing the semiconductor multilayer structure 10 according to the first embodiment.

FIG. 4 is a view showing a semiconductor multilayer structure 40 according to the fourth embodiment. The semiconductor multilayer structure 40 according to the fourth embodiment includes a silicon substrate 1 having a diameter of 3 inches and a plane orientation (111), an AlN layer 2 formed on the silicon substrate 1, and a buffer formed on the AlN layer 2. An InAlN / BAlN superlattice layer 41 that is a layer, an Al _0.9-0.9u Ga _{0.1 + 0.9u} N (u = 0 → 1) layer 12 formed on the InAlN / BAlN superlattice layer 41, The GaN layer 13 is a semiconductor layer formed on the AlGaN layer 12 with a material different from that of the silicon substrate 1. Here, the InAlN / BAlN superlattice layer 41 which is a characteristic part of the fourth embodiment is composed of In _{0.01 + 0.39q} Al _0.99-0.39q N (q = 0 → 1) having a composition gradient structure. The layer 44 is formed of 100 pairs of a B _{0.01 + 0.19r} Al _0.99-0.19r N (r = 0 → 1) layer 45 having a composition gradient structure. The variable q of the In composition ratio 0.01 + 0.39q of the InAlN layer 44 and the variable r of the B composition ratio 0.01 + 0.19r of the BAlN layer 45 are 0 on the silicon substrate 1 side and 1 on the GaN layer 13 side.

From this, also in the semiconductor laminated structure 40 of 4th Embodiment, since the InAlN / BAlN superlattice layer 41 is used, the effect similar to 1st Embodiment can be acquired. In the fourth embodiment, an In _{0.01 + 0.39q} Al _0.99-0.39q N (q = 0 → 1) layer 44 having a composition gradient structure and B _{0.01 + 0.19r} having a composition gradient structure. Since the InAlN / BAlN superlattice layer 41 is formed from the Al _0.99-0.19r N (r = 0 → 1) layer 45, the change in the lattice constant in the InAlN / BAlN superlattice layer 41 is moderated. You can also Therefore, the lattice distortion generated in the InAlN / BAlN superlattice layer 41 can be effectively reduced.

(Fifth embodiment)
Next, a semiconductor multilayer structure 50 according to the fifth embodiment will be described with reference to FIG. 5 focusing on differences from the semiconductor multilayer structure 10 according to the first embodiment. Further, regarding the semiconductor multilayer structure 50 according to the fifth embodiment, the same reference numerals are given to the same structures as those in the first embodiment, and description thereof will be omitted. Note that the method for manufacturing the semiconductor multilayer structure 50 according to the fifth embodiment is the same as the method for manufacturing the semiconductor multilayer structure 10 according to the first embodiment.

FIG. 5 is a view showing a semiconductor multilayer structure 50 according to the fifth embodiment. The semiconductor multilayer structure 50 according to the fifth embodiment includes a silicon substrate 1 having a diameter of 3 inches and a plane orientation (111), an AlN layer 2 formed on the silicon substrate 1, and a buffer formed on the AlN layer 2. An InAlN / BAlN superlattice layer 51, and an Al _0.9-0.9u Ga _{0.1 + 0.9u} N (u = 0 → 1) layer 12 formed on the InAlN / BAlN superlattice layer 51, The GaN layer 53 is a semiconductor layer formed on the AlGaN layer 12 with a material different from that of the silicon substrate 1. The InAlN / BAlN superlattice layer 51 is formed by a pair of a 10 nm-thick In _0.1 Al _0.9 N layer 54 and a 3 nm-thick B _0.05 Al _0.95 N layer 55. Yes. The film thickness of the GaN layer 53 is 3 μm.

  In the fifth embodiment, as in the first embodiment, when the GaN layer 13 is on the upper side, that is, the silicon substrate 1 is on the lower side, measurement is performed with a reflective warpage measuring instrument using a laser. The warpage was 20 μm in the downward direction at the center of the silicon substrate 1 having a diameter of 3 inches. From this, the warp of the grown silicon substrate 1 can be made downward. Moreover, since the InAlN / BAlN superlattice layer 51 is used in the semiconductor multilayer structure 50 of the fifth embodiment, the same effect as that of the first embodiment can be obtained. Further, since the composition ratio x of indium In in the InAlN layer 54 of the InAlN / BAlN superlattice layer 51 approaches 0.17, the lattice constant of InAlN is closer to GaN than to AlN, and the change of the lattice constant in the semiconductor multilayer structure 50 Can be relaxed. Therefore, lattice distortion can be effectively reduced.

  The embodiment described above is an example of the implementation of the present invention, and the scope of the present invention is not limited thereto, and other various embodiments are within the scope described in the claims. It is applicable to. For example, in the manufacturing methods of the semiconductor stacked structures 10 to 50 according to the first to fifth embodiments, the metal organic vapor phase epitaxy (MOVPE) method that is excellent in supplying the nitrogen atom N of the group V material is used. However, the present invention is not limited to this, and other methods such as a crystal growth method such as a molecular beam epitaxy (MBE) method or a halogenated vapor phase epitaxy (HVPE) method can also be used.

  In the first to fifth embodiments, the silicon substrate 1 having a diameter of 3 inches and a plane orientation (111) is used. However, the present invention is not particularly limited to this, and other plane orientations such as ( 110) and (100) silicon substrates can also be used. Moreover, it is applicable also to the board | substrate of another material, for example, a sapphire substrate, a SiC substrate, a GaAs substrate, and an InP substrate.

  In the first and third to fifth embodiments, the buffer layer is formed on the silicon substrate 1 and the GaN layers 13 and 53 as semiconductor layers are formed on the buffer layer. However, other nitride-based semiconductor layers are also applicable. Similarly, in the second embodiment, the AlInGaN layer 23 is formed on the buffer layer, but other nitride-based semiconductor layers are also applicable. In addition to the nitride-based semiconductor, a semiconductor layer can be formed using GaAs, InP, ZnSe, or the like.

In the first, third to fifth _embodiments, an In x is _Al AlGaN layer 12 on the _1-x N layer is formed, not particularly limited _thereto, B y _{Al 1-} It may be formed on the _yN layer. However, in the first, third to fifth embodiments, it is desirable that the AlGaN layer 12 be formed on the In _x Al _1-x N layer. Similarly, in the first, third to fifth embodiments, the B _y Al _1-y N layer is formed on the AlN layer 2, but the present invention is not limited to this, and In _x Al _{1 -X} N layer may be formed. In the semiconductor stacked structures 10, 30 to 50 shown in the first and third to fifth embodiments, it is better that an In _x Al _1-x N layer is formed on the AlN layer 2.

Further, the buffer layers of the first, third to fifth embodiments are formed from an InAlN layer and a BAlN layer, and the buffer layer of the second embodiment is formed from In _0.1 B _0.05 Al _0.85 N. However, it is not particularly limited to this, and it may be formed from a nitride-based semiconductor material containing In and B.

  Further, the semiconductor multilayer structure 10 according to the first embodiment includes a silicon substrate 1, an AlN layer 2 formed on the silicon substrate 1, a superlattice layer 11 formed on the AlN layer 2, and a superlattice layer. 11 is formed from the AlGaN layer 12 formed on the AlGaN layer 11 and the GaN layer 13 formed on the AlGaN layer 12. However, the present invention is not limited to this, and other layers may be added. Similarly, other layers may be added to the semiconductor stacked structures 20 to 50 according to the second to fifth embodiments.

  In the first embodiment, the AlGaN layer 12 is formed on the superlattice layer 11, but the present invention is not particularly limited to this and may be omitted. However, by forming the AlGaN layer 12, the gap between the average lattice constant of the superlattice layer 11 and the lattice constant of the GaN layer 13 can be relaxed. Similarly, in the third to fifth embodiments, the AlGaN layer 12 is formed, but it may be omitted. Furthermore, although the AlGaN layer 22 is formed in the second embodiment, it may be omitted.

  In the first embodiment, the AlN layer 2 is formed on the silicon substrate 1. However, the present invention is not particularly limited to this, and the effects of the present invention can be obtained without the AlN layer 2. However, by forming the AlN layer 2, the initial growth state of the superlattice layer 11 formed on the silicon substrate 1 can be made better. Similarly, in the second to fifth embodiments, the AlN layer 2 is formed, but the effect of the present invention can be obtained without it.

In the first, third to fifth embodiments, the superlattice layer is formed on the AlN layer 2, but the present invention is not limited to this, and the space between the AlN layer 2 and the superlattice layer is not limited thereto. Alternatively, an Al _z Ga _1-z N (0 <z <1) layer may be formed. In this way, the gap between the lattice constant of the AlN layer 2 and the average lattice constant of the superlattice layer can be relaxed. Further, the same effect can be obtained by eliminating the AlN layer 2 and forming an Al _z Ga _1-z N layer between the silicon substrate 1 and the superlattice layer. In the second embodiment, the InBAlN layer 21 is formed on the AlN layer 2. However, the present invention is not limited to this, and the Al _z Ga ₁₋ is not limited to the AlN layer 2 and the InBAlN layer 21. _{A zN} layer may be formed. Further, the AlN layer 2 may be eliminated, and an Al _z Ga _1-z N (0 <z <1) layer may be formed between the silicon substrate 1 and the InBAlN layer 21.

  In the first embodiment, the composition ratio x of indium In is 0.2. However, the composition ratio x of indium In can be selected within the range of 0 <x ≦ 1. . However, in the semiconductor multilayer structure 10 shown in the first embodiment, since the crystal defects increase when the composition ratio x of indium In is 0.4 or more, the composition ratio x is preferably 0.4 or less. Similarly, the composition ratio y of boron B is set to 0.1, but the present invention is not particularly limited to this, and the composition ratio y of boron B can be selected within the range of 0 <y ≦ 1. However, in the semiconductor multilayer structure 10 shown in the first embodiment, if the composition ratio y of boron B is set to 0.2 or more, the growth proceeds locally from the hexagonal system to the cubic system. The composition ratio y is preferably 0.2 or less. Similarly, in the second to fifth embodiments, the composition ratio x of indium In can be selected in the range of 0 <x ≦ 1, and the composition ratio y of boron B can be selected in the range of 0 <y ≦ 1. However, the composition ratio x of indium In is desirably 0.4 or less, and the composition ratio of boron B is desirably 0.2 or less.

In the first embodiment, the thickness of the In _0.2 Al _0.8 N layer 14 forming the superlattice layer 11 is 45 nm, and the thickness of the B _0.1 Al _0.9 N layer 15 is 5 nm. However, the present invention is not particularly limited to this, and any thickness may be used as long as it is 300 nm or less, which is a film thickness that does not express each property of each layer independently. Similarly, each buffer layer in the second to fifth embodiments may have any thickness as long as it is 300 nm or less, which is a film thickness that does not manifest each property of the buffer layer alone.

In the fourth embodiment, a change in the composition of indium In in the In _{0.01 + 0.39q} Al _0.99-0.39q N (q = 0 → 1) layer 44 and B _{0.01 + 0.19r} Al _0. The change in the composition of boron B in the _99-0.19r N (r = 0 → 1) layer 45 has regularity, but is not limited to this, and may be irregular. In the fourth embodiment, the form of the change is linear. However, the change is not particularly limited to this, and a quadratic function change or an exponential change can be applied. Furthermore, in the fourth embodiment, from the silicon substrate 1 side toward the GaN layer 13 side, the composition ratio of indium In in the InAlN layer 44 is 0.01 + 0.39q and the composition ratio of boron B in the BAlN layer 45 is 0.01 + 0. The variables q and r are increased from the silicon substrate 1 side toward the GaN layer 13 side so that 19r increases. However, the present invention is not limited to this. You may increase it.

It is a figure which shows the semiconductor laminated structure concerning 1st Embodiment. It is a figure which shows the semiconductor laminated structure which concerns on 2nd Embodiment. It is a figure which shows the semiconductor laminated structure which concerns on 3rd Embodiment. It is a figure which shows the semiconductor laminated structure which concerns on 4th Embodiment. It is a figure which shows the semiconductor laminated structure which concerns on 5th Embodiment.

Explanation of symbols

1 silicon substrate, 2 AlN layer,
10 A semiconductor multilayer structure according to the first embodiment,
11 InAlN / BAlN superlattice layer,
12 Al _0.9-0.9u Ga _{0.1 + 0.9u} N (u = 0 → 1) layer,
13 GaN layer, 14 In _0.2 Al _0.8 N layer,
15 B _0.1 Al _0.9 N layer,
20 A semiconductor multilayer structure according to the second embodiment,
21 In _0.1 B _0.05 Al _0.85 N layer,
22 Al _0.3 Ga _0.7 N layer, 23 AlInGaN layer,
30. A semiconductor multilayer structure according to the third embodiment,
31 InAlN / InBAlN / BAlN superlattice layer,
32 In _0.4 Al _0.6 N layer, 33 In _0.2 B _0.1 Al _0.7 N layer,
34 B _0.2 Al _0.8 N layer,
40 A semiconductor multilayer structure according to the fourth embodiment,
41 InAlN / BAlN superlattice layer,
44 In _{0.01 + 0.39q} Al _0.99-0.39q N (q = 0 → 1) layer,
45 B _{0.01 + 0.19r} Al _0.99-0.19r N (r = 0 → 1) layer,
50 A semiconductor multilayer structure according to the fifth embodiment,
51 InAlN / BAlN superlattice layer, 53 GaN layer,
54 In _0.1 Al _0.9 N layer, 55 B _0.05 Al _0.95 N layer,

Claims (10)

In a semiconductor structure comprising at least a buffer layer formed on a substrate and a semiconductor layer formed on the buffer layer with a material different from the material of the substrate,
The buffer layer is made of a nitride-based semiconductor material containing In and B. 2. The semiconductor structure according to claim 1, wherein the buffer layer includes an In _w B _v Al _1-wv N (0 <w <1, 0 <v <1, w + v ≦ 1) layer. The buffer layer _is at least claims, characterized in that a repeating structure of the _{In x Al 1-x N (} 0 <x ≦ 1) layer and the _{B y Al 1-y N (} 0 <y ≦ 1) layer Item 2. The semiconductor structure according to Item 1. The semiconductor structure according to claim 3, wherein the In _x Al _1-x N layer and the B _y Al _1-y N layer have a composition gradient structure. The buffer layer, the _{an In} x _Al between _1-x N layer and the _{B y Al 1-y} N layer _{and, In s B t Al 1-} s-t N (0 <s <1,0 <t < 5. A semiconductor structure according to claim 3 or 4, characterized in that it comprises (1, s + t ≦ 1) layers.   6. The semiconductor structure according to claim 1, wherein the material of the substrate is silicon.   The semiconductor structure according to claim 6, wherein the plane orientation of the substrate is (111) and a plane orientation equivalent thereto. 8. The Al _z Ga _1-z N (0 ≦ z ≦ 1) layer having a uniform composition structure or a composition gradient structure is provided on one or both of the upper and lower sides of the buffer layer. The semiconductor structure described in 1.   The semiconductor structure according to claim 1, wherein the semiconductor layer is a GaN layer having a thickness of at least 1 μm. A buffer layer made of a nitride semiconductor material containing In and B is formed on the substrate,
A method of manufacturing a semiconductor structure, comprising forming a semiconductor layer on the buffer layer with a material different from a material of the substrate.

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