JP2008052811A - Nonvolatile semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor storage device wherein erroneous writing and erroneous erasure in a memory cell associated with minuteness of the memory cell are reduced. <P>SOLUTION: The nonvolatile semiconductor device wherein a charge storage layer and a control gate layer are layered on a channel via an insulating film and memory cells MC11 to MC1n, ..., MCm1 to MCmn each having a diffusion layer forming a current path are disposed in a matrix shape sandwiching the channel and which has bit lines BL1 to BLn connected to the diffusion layers of the plurality of memory cells MC11 to MC1n, ..., MCm1 to MCmn is provided with transistors TR1 to TRn connected to the bit lines BL1 to BLn and discharging voltage applied to the diffusion layers of the memory cells MC11 to MCmn and having a prescribed value or more. Drains of the transistors TR1 to TRn are connected to the bit lines BL1 to BLn and sources thereof are grounded. Each of the transistors TR1 to TRn has a prescribed threshold and is carried out diode-connection. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a nonvolatile semiconductor device.

  Conventionally, there is a NOR type EEPROM that can be electrically rewritten. One memory cell of a NOR type EEPROM has a MOSFET structure in which a floating gate (charge storage layer) and a control gate are stacked on a semiconductor substrate via an insulating film. In the case of an N-channel type MOSFET, the plurality of memory cells constitute a NOR type memory cell unit arranged in a matrix in which drains and gates thereof are connected to bit lines and word lines. As such a NOR type EEPROM, for example, a technical document as disclosed in Patent Document 1 is also disclosed.

  If it is a non-volatile memory cell using a channel hot electron programming system (a system in which a potential difference is applied between the source and drain, a channel current is passed to generate hot electrons and writing is performed) like the NOR type memory cell, programming is possible. The drain pulse voltage application method is used. In the NOR type memory cell, when the memory cell is miniaturized, the following two problems must be solved.

  The first problem is that when the gate length is shortened, the drain breakdown voltage decreases, while the drain voltage required for writing cannot be reduced along with the shortening of the gate length. Generally, in a floating gate type non-volatile memory cell, programming in which electrons in a Si substrate are injected into the floating gate requires energy for electrons in the substrate to cross the energy barrier of the tunnel oxide film. Become. When the channel hot electron programming method is used, in order to acquire the energy, it is necessary to apply a voltage corresponding to energy sufficient to exceed the barrier of the oxide film to the drain, approximately 3 to 4 V or more. However, the drain breakdown voltage decreases as the gate length is shortened. That is, even if the gate length is shortened, the minimum drain voltage (3 to 4 V) required for programming does not change, and only the drain breakdown voltage decreases unilaterally. Therefore, the drain voltage margin during programming cannot be secured. Problems will occur.

  Secondly, as the memory cell is miniaturized, the drain load resistance increases. As a result, the drain voltage cannot be programmed unless the drain voltage is increased to some extent, and a voltage exceeding the drain withstand voltage may be applied to the drain of the cell at the end of programming. It is a problem of producing sex. When the drain withstand voltage is exceeded, the programming threshold is lowered in the selected cell, and drain disturb occurs in the non-selected cell. In severe cases, erroneous writing and erroneous erasing occur. This is because the drain contact resistance increases as the drain contact size decreases, the bit line resistance increases as the bit line wiring width and film thickness decrease, and the column gate channel resistance increases as the cell size decreases. This is because the load resistance value on the drain side increases.

  Next, a description will be given of a mechanism in which a decrease in programming threshold and erroneous writing occur due to an increase in load resistance value as described above. In the case of a programming method that requires a channel current such as the channel hot electron programming method, a voltage drop V = (load resistance R) × (channel current I) occurs in the drain load resistance. Therefore, it is necessary to apply a voltage equal to or higher than the minimum voltage (3 to 4 V) necessary for programming to the cell drain, in other words, a programming voltage including a voltage drop of the drain load resistance. The problem here is the drain breakdown voltage of the cell when programming is completed. That is, the drain breakdown voltage of the memory cell with a shortened gate length is lowered. When the cell is programmed, electrons are injected into the floating gate, increasing the threshold and reducing the channel current. As a result, the voltage drop of the load resistance is reduced, and the drain voltage at the start of programming is applied to the drain of the cell. If the voltage exceeds the drain breakdown voltage, a hot cell is generated in the drain in the selected cell to be programmed and injected into the floating gate, so that the written threshold may be lowered.

  On the other hand, in a non-selected cell (a cell in which a pulse voltage is applied to the drain without performing programming) in which the selected cell and the bit line are common, in a case where data is held in a binary / cell system, When a voltage higher than the drain breakdown voltage is applied, hot electrons generated at the drain are injected into the floating gate. That is, the threshold value rises and erroneous writing (drain disturb) occurs. On the other hand, in a programmed cell, hot holes generated at the drain thereof are injected into the floating gate, so that erroneous erasure (drain disturb) that lowers the threshold value occurs.

Unless the above two problems are solved, it is impossible to miniaturize a memory cell of the channel hot electron programming method and of the drain pulse voltage application method.
Japanese Patent Application Laid-Open No. 07-30000

  An object of the present invention is to provide a semiconductor memory device in which erroneous writing and erroneous erasing to a memory cell due to miniaturization are reduced.

  In the nonvolatile semiconductor device according to the present invention, a memory cell having a charge accumulation layer and a control gate layer laminated on a channel via an insulating film and a diffusion layer forming a current path across the channel is arranged in a matrix. A non-volatile semiconductor device having a bit line arranged and connected to a diffusion layer of a plurality of memory cells, comprising a switching element connected to the bit line and discharging a voltage of a predetermined value or more applied to the diffusion layer. It is characterized by.

  According to the present invention, it is possible to provide a semiconductor memory device in which erroneous writing and erroneous erasing to a memory cell due to miniaturization are reduced.

  First, a conventional NOR type nonvolatile semiconductor memory cell array will be described with reference to FIGS.

  The programming method of the drain pulse application method will be described with reference to FIG. FIG. 6 is a circuit diagram of a NOR type nonvolatile semiconductor memory cell array having a floating channel structure of a conventional channel hot electron programming method. 6, the NOR type nonvolatile semiconductor memory cell array includes a plurality of memory cells MC11 to MC1n,..., MCm1 to MCmn, a plurality of word lines WL1 to WLn, and a plurality of bit lines BL1 to BLn. It is comprised by.

  Here, when programming is performed on the memory cell MC22 (selected cell S) surrounded by a dotted line, first, a word line is selected (selected word line), and a voltage of 9 to 10 V is applied. When the voltage of the word line is stabilized, a drain pulse voltage of 4 to 5 V is applied to the selected bit line (selected bit line). A programming current begins to flow between the source and drain of the applied cell, and hot electrons are generated at the drain end. Then, the hot electrons are injected into the floating gate. At this time, as shown in FIG. 6, in addition to the selected cell S (MC22), non-programmed cells MC12 and MC32 to MCm2 that are not programmed are connected to the selected bit line BL2. Normally, the current of the selected cell S (MC22) and the total current of the non-selected cells MC12, MC32 to MCm2 flow through the selected bit line BL2.

  Here, the bit line current at the time of programming will be described using a simplified diagram (FIG. 7) focusing on only the selected cell MC22. In practice, a certain amount of current also flows through the unselected cells MC12, MC32 to MCm2, but the leakage current of the unselected cells is very small and is ignored. As shown in FIG. 7, the drain load resistance R is applied to the memory cells MC11 to MC1n,..., MCm1 to MCmn. The load resistance R includes cell contact resistance, bit line array resistance, column gate channel resistance, and the like. The resistance value R increases as the miniaturization proceeds. As described above, the increase in the resistance value R due to the fineness is caused by the drain contact size reduction, the bit line wiring width and film thickness reduction, the column gate channel resistance increase, and the like.

  Next, the bit line current during programming will be described with reference to FIG. 8, the left diagram shows the relationship between the drain voltage applied to the cell and the channel current, and the right diagram shows the programming voltage threshold values of the memory cells MC11 to MC1n,..., MCm1 to MCmn. It is a figure which shows distribution. The load line Lr of the resistor R in FIG. 8 is due to the load resistor R in FIG. At the time of programming, a pulse voltage is applied to the drains of the memory cells MC11 to MC1n,..., MCm1 to MCmn, so that a channel current flows, and the bit line current increases along the static characteristics as indicated by the broken line. I will do it. When the drain load resistance R is large, a voltage drop V = (load resistance R) × (bit line current I) occurs, so that the programming current stops at the intersection A with the load resistance line. When hot electrons are generated near the drain, programming starts gradually, the threshold value decreases, and the programming current decreases to point B. Actually, some of the memory cells MC11 to MC1n,..., MCm1 to MCmn have a Vth distribution as shown in FIG. Thereafter, the current returns to 0V through the static characteristic of the broken line, and the programming ends. In this case, the maximum programming voltage is the voltage at the B 'point. In the non-miniaturized state, as shown in FIG. 8, since the drain breakdown voltage point D (punch through voltage) of the memory cell is sufficiently larger than the B ′ point, the threshold of the selected cell programming voltage due to the drain breakdown voltage. There was no particular problem with the decrease of the drain and the drain disturbance of the non-selected cells.

  When miniaturization of such a NOR type nonvolatile semiconductor memory cell is advanced, the above-described two problems occur. Next, a problem in miniaturization of a NOR type nonvolatile semiconductor memory cell will be described with reference to FIG. FIG. 9 is a diagram showing drain voltage characteristics in a miniaturized state in a conventional NOR type nonvolatile semiconductor memory cell.

  The first problem is a decrease in the drain breakdown voltage due to the shortening of the gate length. As a result, it can be seen that in FIG. 9, the voltage difference between the write start point A and the breakdown voltage point C (or point C ′) due to the decrease in the drain breakdown voltage is smaller than in FIG. That is, even if the gate length is shortened, the minimum drain voltage required for programming does not change, only the drain breakdown voltage decreases unilaterally, and a drain voltage margin during programming cannot be secured.

  The second problem is an increase in drain load resistance due to a reduction in drain contact size and a reduction in bit line wiring width and film thickness. When the cell is programmed, electrons are injected into the floating gate, increasing the threshold and reducing the programming current. As a result, since the voltage drop V due to the load resistance R decreases, the drain voltage rises from the point A, and as shown in FIG. 9, a voltage higher than the drain breakdown voltage (point C ′) (point B ′) is applied to the drain. become. In such a state, in the selected cell to be programmed, a hot hole is generated in the drain and injected into the floating gate, so that the written threshold value is lowered. On the other hand, in a non-programmed cell, if a voltage higher than the drain breakdown voltage is applied to the drain, hot electrons generated in the drain are injected into the floating gate, so that the threshold value increases and erroneous writing occurs.

  The conventional NOR type nonvolatile semiconductor memory cell array has such problems.

[First Embodiment]
Next, a NOR type nonvolatile semiconductor memory cell according to the first embodiment of the present invention will be described with reference to FIGS.

  FIG. 1A is a circuit diagram showing a partial configuration of a memory cell array in the NOR type nonvolatile semiconductor memory according to the first embodiment of the present invention. As shown in FIG. 1A, a NOR type nonvolatile semiconductor memory includes a plurality of memory cells MC11 to MC1n,..., MCm1 to MCmn, a plurality of word lines WL1 to WLn, and a plurality of bit lines BL1 to BLn. It is comprised by.

  FIG. 1B is a diagram showing a schematic configuration of each of the memory cells MC11 to MCmn. As shown in FIG. 1B, each of the memory cells MC11 to MCmn has a P-type semiconductor substrate Sub and an N + type diffusion layer Dif formed on the surface thereof. In addition, a charge storage layer (floating gate) CA is stacked on the surface of the P-type semiconductor substrate Sub between the N + type diffusion layers Dif of the memory cells MC11 to MCmn via the insulating layer In. On the storage layer CA, a control gate layer CG connected to the word lines WL1 to WLn is stacked via an insulating layer In. One N + type diffusion layer Dif functions as the source layer S, and the other N + type diffusion layer Dif functions as the drain layer D. That is, each of the memory cells MC11 to MCmn has an n-channel MOSFET structure.

  Each of these memory cells MC11 to MCmn has its drain layer D connected to bit lines BL1 to BLn, its control gate layer CG connected to word lines WL1 to WLn, and its source layer S grounded. By applying a predetermined voltage to the drain layer D and the control gate layer CG thus formed, a current path is formed between the source layer S and the drain layer D (channel) on the surface of the P-type semiconductor substrate Sub, and the channel current Then, writing is performed by channel hot electron programming.

  In particular, unlike the conventional example, the nonvolatile semiconductor memory according to the first embodiment of the present invention is provided with n-type MOS transistors TR1 to TRn for each of the bit lines BL1 to BLn. Each transistor TR1 to TRn has its drain connected to the bit lines BL1 to BLn and its source grounded. Each of the transistors TR1 to TRn has a predetermined threshold value and is diode-connected. Note that the predetermined threshold voltage of the transistors TR1 to TRn can be adjusted by the impurity concentration of the channel, the film thickness of the insulating film, or the like.

  Here, a simplified diagram focusing only on the selected cell MC22 is as shown in FIG. As shown in FIG. 2, a transistor TR2 is connected in parallel with the selected cell MC22 connected to the parasitic resistance R.

  FIG. 3 is a diagram showing drain voltage characteristics of the NOR type nonvolatile semiconductor memory cell according to the first embodiment of the present invention. Note that FIG. 3 has the same configuration as that of FIGS. 8 and 9 described above. As shown in FIG. 3, in the non-volatile semiconductor memory having the above-described circuit, the drain withstand voltage is lowered during programming due to the shortened gate length, and the write end voltage B ′ is set at the breakdown voltage value C. 'The point will be exceeded. However, according to the first embodiment of the present invention, before programming, the MOS transistors TR1 to TRn are turned on at a predetermined threshold as shown by the curve Ltr (selected cell + non-selected cell + transistor drain characteristics). A large current can be passed through the transistors TR1 to TRn to discharge the drain voltage of the memory cell. Therefore, the current flowing through the bit line intersects with the load resistance line at point E, and the drain voltage does not rise any further.

  Therefore, in the memory cell array according to the first embodiment, the rise of the drain voltage ends when the drain breakdown voltage is lower than the drain breakdown voltage, and erroneous writing and erasing due to the miniaturization of the memory cell can be reduced. In addition, since one transistor is added to one bit line, an increase in the area of the memory cell array can be suppressed.

[Second Embodiment]
Next, a semiconductor device according to the second embodiment of the present invention will be described with reference to FIG. FIG. 4 is a circuit diagram showing a partial configuration of the memory cell array in the NOR type nonvolatile semiconductor memory cell according to the second embodiment. In addition, the same code | symbol is attached | subjected to the structure similar to 1st Embodiment, and the description is abbreviate | omitted.

  As shown in FIG. 4, the memory cell array according to the second embodiment includes diode portions DI1 to DIn in which a plurality of, for example, six PN junction diodes are connected in series instead of the transistors TR1 to TRn of the first embodiment. ing. These diode portions DI1 to DIn have a function of discharging a voltage higher than a predetermined value applied to the diffusion layers of the memory cells MC11 to MCmn.

  Therefore, the memory cell array according to the second embodiment can reduce erroneous writing and erroneous erasing accompanying the miniaturization of the memory cell, as in the first embodiment. The adjustment of the threshold voltage for generating a large current in the diode parts DI1 to DIn can be controlled by the number of PN junction diodes connected in series.

[Third embodiment]
Next, a semiconductor device according to a third embodiment of the present invention will be described with reference to FIG. FIG. 5 is a circuit diagram showing a partial configuration of a memory cell array in a NOR type nonvolatile semiconductor memory cell according to the third embodiment. In addition, the same code | symbol is attached | subjected to the structure similar to 1st Embodiment, and the description is abbreviate | omitted.

  As shown in FIG. 5, the memory cell array according to the third embodiment includes transistors TR1 ′ to TRn ′ having charge storage layers (floating gates) provided instead of the transistors TR1 to TRn of the first embodiment, and the transistors Control circuits CC1 to CCn connected to the control gate layers of TR1 ′ to TRn ′ are provided. In the transistors TR1 'to TRn', the gate length of the control gate layer is designed longer than that of the memory cells MC11 to MCmn, and the concentration of the drain layer is further reduced. The transistors TR1 'to TRn' can change the threshold voltage according to the amount of charge accumulated in the charge accumulation layer.

  The control circuits CC1 to CCn have a function of reading a voltage input from the outside, generating an internal voltage based on the read voltage, and applying the internal voltage to the control gate layers of the transistors TR1 'to TRn'.

  That is, the transistors TR1 ′ to TRn ′ are in a state of conducting current based on the internal voltages from the control circuits CC1 to CCn, and have a function of discharging a voltage higher than a predetermined value applied to the diffusion layers of the memory cells MC11 to MCmn. .

Therefore, the memory cell array according to the third embodiment can reduce erroneous writing and erroneous erasure associated with the miniaturization of the memory cell array as in the first embodiment. Further, the electrons applied to the charge storage layers of the transistors TR1 ′ to TRn ′ are controlled by the voltage applied from the control circuits CC1 to CCn to the control gate layers of the transistors TR1 ′ to TRn ′, and the transistors TR1 ′ to TRn ′. The threshold voltage for generating a large current can be adjusted.

  As mentioned above, although embodiment of invention was described, this invention is not limited to these, A various change, addition, substitution, etc. are possible within the range which does not deviate from the meaning of invention. For example, in the first to third embodiments, the floating gate structure type is used for the memory cell, but it may be a MONOS type or a SONOS type.

Explanation of symbols

  MC11 to MCmn ... memory cells, WL1 to WLn ... word lines, BL1 to BLn ... bit lines, TR1 to TRn, TR1 'to TRn' ... transistors, DI1 to DIn ... diode sections, CC1 to CCn ... control circuits.

1 is a circuit diagram showing a partial configuration of a memory cell array in a NOR type nonvolatile semiconductor memory according to a first embodiment of the present invention. It is a figure which shows schematic structure of each memory cell. It is the figure which showed the relationship with transistor TR2 about the selection cell S (MC22). FIG. 4 is a diagram showing drain voltage characteristics in a state where the memory cell is miniaturized in the NOR type nonvolatile semiconductor memory cell according to the first embodiment of the present invention. FIG. 5 is a circuit diagram showing a partial configuration of a memory cell array in a NOR type nonvolatile semiconductor memory according to a second embodiment of the present invention. FIG. 5 is a circuit diagram showing a partial configuration of a memory cell array in a NOR type nonvolatile semiconductor memory according to a third embodiment of the present invention. FIG. 6 is a circuit diagram showing a partial configuration of a memory cell array in a conventional NOR type nonvolatile semiconductor memory. It is the figure which showed the relationship with the parasitic load resistance R about the selection cell S (MC22). In the conventional NOR type non-volatile semiconductor memory cell, it is a figure which shows the drain voltage characteristic when the memory cell is not miniaturized. In the conventional NOR type non-volatile semiconductor memory cell, it is a figure which shows the drain voltage characteristic in the state where the memory cell was miniaturized.

Claims (5)

A charge storage layer and a control gate layer are stacked on the channel via an insulating film, and memory cells provided with a diffusion layer that forms a current path across the channel are arranged in a matrix, and a plurality of memory cells are diffused. In a nonvolatile semiconductor device having a bit line connected to a layer,
A nonvolatile semiconductor device comprising a switching element connected to the bit line and discharging a voltage of a predetermined value or more applied to the diffusion layer.   The nonvolatile semiconductor device according to claim 1, wherein one end of the switching element is connected to the bit line and the other end is grounded.   The nonvolatile semiconductor device according to claim 2, wherein the switching element is a diode-connected transistor.   2. The nonvolatile semiconductor device according to claim 1, wherein the switching element is a plurality of diodes connected in series, the anode side being connected to the bit line and the cathode side being grounded.   The transistor is characterized in that the gate length of the control gate layer is longer than that of the memory cell, the diffusion concentration of the diffusion layer is lower than that of the memory cell, and has a charge storage region. The nonvolatile semiconductor device according to claim 2.

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